| 47th week of 2012 patent applcation highlights part 21 |
| Patent application number | Title | Published |
|---|
| 20120293173 | RF BODY COIL FOR REDUCED ACOUSTIC NOISE IN AN MR SYSTEM - An RF body coil having enhanced acoustic deadening properties for an MR scanning apparatus is disclosed. The RF body coil includes an RF support form and RF electronics affixed to the RF support form, with the RF electronics comprising a plurality of RF legs. The RF support form further includes an inner structural layer, an outer structural layer, and a middle layer sandwiched between the inner structural layer and the outer structural layer, the middle layer comprising a layer of viscoelastic material configured to increase the mechanical damping of the RF body coil so as to reduce RF body coil vibration. | 2012-11-22 |
| 20120293174 | METHOD AND APPARATUS FOR IMAGING A SUBJECT USING LOCAL SURFACE COILS - A Radio Frequency (RF) coil apparatus for generating a Magnetic Resonance (MR) image includes a body adapted to be worn by a subject being scanned, the body comprising an anterior portion, a posterior portion, and a transition portion coupled between the anterior and posterior portions, a first RF receive-only saddle coil including a first coil positioned in the anterior portion and a second coil positioned in the anterior portion, the first RF saddle coil configured to be positioned on the anterior and posterior sides of the subject. An MRI imaging system and method are also described herein. | 2012-11-22 |
| 20120293175 | LIQUID NITROGEN COOLED MRI COILS AND COIL ARRAYS - New method of cooling of MRI coil and resonators is disclosed and described. MRI coil designs showed in the disclosure are based solely on the use of copper tube elements filled with liquid nitrogen. Inside the conducting tubes at rf frequency there is no rf electric field, thus the liquid nitrogen presence inside such coils will not have any influence on MRI coil dielectric losses and on the resonant frequency modulation. Liquid nitrogen cooled coils, when in the coil noise regime, demonstrate | 2012-11-22 |
| 20120293176 | VARIABLE ROTATABLE MR COIL - A local coil for a magnetic resonance tomography system includes a plurality of coil elements. Each coil element of the plurality of coil elements has a point of application for another coil element of the plurality of coil elements. The coil element is connected to the other coil element at the point of application in a pivoting manner with respect to the coil element. | 2012-11-22 |
| 20120293177 | RECEIVER COIL ASSEMBLY WITH AIR AND FERROMAGNETIC CORED SENSORS FOR GEOPHYSICAL SURVEYING - A receiver coil assembly for performing geophysical surveys, including a hollow outer shell defining a continuous internal passage that forms a loop; a multiturn receiver air coil extending around the continuous internal passage; and a first cored coil comprising multiturn solenoid windings about a ferromagnetic core, the first cored coil having a sensing axis in a different direction than a sensing axis of the air coil. | 2012-11-22 |
| 20120293178 | AUTOMATIC ANISOTROPY, AZIMUTH AND DIP DETERMINATION FROM UPSCALED IMAGE LOG DATA - A method of determining anisotropy in a borehole is disclosed. An array of measurements along the borehole is obtained and a first depth in the borehole is selected. An arbitrary plane oriented with respect to the borehole at the first depth is designated and an anisotropy for the first depth with respect to the arbitrary plane is determined. The arbitrary plane is repositioned at the first depth and an anisotropy for different positions of the arbitrary plane at the first depth is determined. A minimum anisotropy coefficient with respect to the arbitrary plane at the first depth is identified based on anisotropy for different positions of the arbitrary plane. An anisotropy tensor for the first depth is then identified. | 2012-11-22 |
| 20120293179 | Apparatus and Method for Multi-Component Wellbore Electric Field Measurements Using Capacitive Sensors - A method and apparatus is provided for collecting reservoir data. The method includes providing one or more electromagnetic sources for generating an electromagnetic field in a reservoir and providing one or more electromagnetic sensors equipped with capacitive electrodes. The electromagnetic source is located separately from the electromagnetic sensor. The electromagnetic sensor may either be located within a well or at the surface, is capable of measuring the electromagnetic field in three dimensions, and may be isolated from the well fluids. The data collected by the electromagnetic sensors can be used to create a model of the oil reservoir, including the water saturation. | 2012-11-22 |
| 20120293180 | APPARATUS FOR MEASURING PERMITTIVITY OF ROCKS AND FAULT CLAYS USING PERMITTIVITY SENSOR - An apparatus for measuring permittivity of a sample. The apparatus includes: a sample chamber including a sealed space portion in which a sample to be measured is put; a pressure adjusting unit for varying pressure by applying water pressure to the space portion of the sample chamber; a permittivity sensor for measuring permittivity of the sample and disposed outside the sample chamber; measurement conducting wires including conductors, installed to contact the sample and connected to the permittivity sensor by using electric wires; and a data logger for storing data relating to permittivity that is measured by the permittivity sensor. | 2012-11-22 |
| 20120293181 | BIOCHEMICAL MEASURING DEVICE - The invention provides a biochemical measuring device including: a measuring unit configured to measure a base current and a peak current; a time counting unit configured to count an elapsed time from the contact of a sensor electrode to a reference solution until the start of measurement of the base current; and a control unit, wherein the control unit acquires a concentration of a specific substance using the base current value when the elapsed time is equal to or longer than a stationarizing time, and when it is shorter than the stationarizing time, acquires the concentration of the specific substance using the stationary base current value measured by the measuring unit when the elapsed time is shorter than the stationarizing time instead of the current value of the base current. | 2012-11-22 |
| 20120293182 | ELECTRICAL TEST APPARATUS FOR A PHOTOVOLTAIC COMPONENT - The present invention relates to electrical test apparatuses for photovoltaic components and methods of testing photovoltaic components. | 2012-11-22 |
| 20120293183 | METHOD AND CONTROL UNIT FOR MONITORING CABLE FAULTS ON A BROADBAND LAMBDA PROBE - A method for identifying cable faults at the terminals of a broadband lambda probe comprising a Nernst cell and a pump cell in the exhaust gas duct of an internal combustion engine. The broadband lambda probe has a reference electrode terminal RE, an internal pump electrode terminal IPE and an external pump electrode terminal APE. A pump current is applied to the broadband lambda probe and a pulsed reference pump current is applied to the broadband lambda probe. Cable faults are identified by the evaluation of potential swings in current. | 2012-11-22 |
| 20120293184 | HIGH FREQUENCY CHARACTERISTIC MEASURING DEVICE - A high frequency characteristic measuring device for measuring high frequency characteristics of a high frequency device to be measured by contacting probe needles with the high frequency device to be measured, before mounting of the high frequency device to be measured. The high frequency characteristic measuring device includes an input matching circuit substrate with an input matching circuit thereon, a first coaxial connector electrically connected to the input matching circuit substrate, and first probe needles electrically connected to the input matching circuit substrate. The high frequency characteristic measuring device further includes an output matching circuit substrate with an output matching circuit thereon, a second coaxial connector electrically connected to the output matching circuit substrate, and second probe needles electrically connected to the output matching circuit substrate. | 2012-11-22 |
| 20120293185 | DETERMINING THE CURRENT RETURN PATH INTEGRITY IN AN ELECTRIC DEVICE CONNECTED OR CONNECTABLE TO A FURTHER DEVICE - A method for determining current return path integrity in an electric device with a plurality of signal lines and supply lines. A library with at least one reference signal pattern of a near end crosstalk signal on a defined signal line arising from an input signal on another defined signal line is provided, a predetermined signal to a selected signal line of the electric device is applied, the near end crosstalk signal on at least one further signal line of the electric device is detected, said near end crosstalk signal is compared with the corresponding reference signal pattern from the library, and if there is a deviation between the near end crosstalk signal and the corresponding reference signal pattern, an information that there is any defect in the electric device is displayed. | 2012-11-22 |
| 20120293186 | METHOD, SOLVENT FORMULATION AND APPARATUS FOR THE MEASUREMENT OF THE SALT CONTENT IN PETROLEUM FLUIDS - A method and apparatus for determining the salt concentration of crude oil using a single solvent that allows for improved safety and accuracy. The apparatus can include a pair of electrodes, a solvent storage container, a power source, a temperature sensor, a computer, and a display device. The method includes introducing a volume of the crude oil and a solvent to a mixing zone and mixing them together to form a homogenized mixture. The temperature and conductivity of the homogenized mixture are measured in order to determine the salt concentration of the homogenized mixture, and subsequently, the salt concentration of the crude oil. | 2012-11-22 |
| 20120293187 | SIMPLE AND MINIMALLY INVASIVE METHODS AND SYSTEMS FOR SENSING AND COMPUTING LOAD IMPEDANCE - Systems and methods for direct load impedance computation for a two-port network are disclosed. For a two-port network connected between a first port and a second port, a method can include defining an equivalent PI network including a first equivalent network element in communication with the first port, a second equivalent network element in communication with the second port, and a third equivalent network element connected between the first port and the second port. A linear passive load can be connected to the second port of the two-port network, currents through the linear passive load, the second equivalent network element, and the third equivalent network element can be measured, and a load impedance of the linear passive load can be determined based on predetermined values of a voltage at the first port and a voltage at the second port. | 2012-11-22 |
| 20120293188 | APPARATUS AND METHOD OF USING IMPEDANCE RESONANCE SENSOR FOR THICKNESS MEASUREMENT - An apparatus for, and methods of use for, measuring film thickness on an underlying body are provided. The apparatus may include at least one Impedance Resonance (IR) sensor, which may include at least one sensing head. The at least one sensing head may include an inductor having at least one excitation coil and at least one sensing coil. The excitation coil may propagate energy to the sensing coil so that the sensing coil may generate a probing electromagnetic field. The apparatus may also include at least one power supply, at least one RF sweep generator electrically connected to the excitation coil; at least one data acquisition block electrically connected to the sensing coil; at least one calculation block; and at least one communication block. Methods of monitoring conductive, semiconductive or non-conductive film thickness, and various tools for Chemical Mechanical Polishing/Planarization (CMP), etching, deposition and stand-alone metrology are also provided. | 2012-11-22 |
| 20120293189 | NOVEL METHOD AND DEVICE FOR WHOLE-CELL BACTERIAL BIO-CAPACITOR CHIP FOR DETECTING CELLULAR STRESS INDUCED BY TOXIC CHEMICALS - The present invention is directed to methods and a bio-capacitor sensing device for the detection of toxic chemicals using bacteria. The sensing platform comprises gold interdigitated capacitor with a defined geometry, a layer of carboxy-CNTs immobilized with viable | 2012-11-22 |
| 20120293190 | CAPACITIVE SENSOR INTERFERENCE DETERMINATION - A processing system for a capacitive input device is described. The capacitive input device includes a plurality of sensor electrodes configured to detect input objects in a sensing region. The processing system configured to transmit a signal on a transmitter sensor channel of the capacitive input device. The processing system is also configured to receive the signal on a receiver sensor channel of the capacitive input device, wherein the receiver sensor channel is coupled with an amplifier. The processing system is also configured to determine if a level of interference has been received by the receiver sensor channel in conjunction with receipt of the signal. | 2012-11-22 |
| 20120293191 | HVMOS Reliability Evaluation using Bulk Resistances as Indices - A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance. | 2012-11-22 |
| 20120293192 | CHARGE READ-OUT STRUCTURE FOR A PHOTON / PARTICLE DETECTOR - A charge read-out structure for photon and particle detectors, which is capable of spatially-resolving a position of the charge. The structure comprises a resistive element defining a detection surface which is capacitively coupled to an array of electrically insulated electrodes. Each electrode in the array is capacitively coupled to an adjacent electrode in the array to form a capacitively coupled network of electrodes. Selected ones of the electrodes in the array are each coupled to an array output for connection to a respective charge measurement device. The resistive element has a resistivity sufficient to temporarily localize a charge induced on the resistive element to an area corresponding to a subset of said electrodes in the array and for a duration sufficient for signal measurement from the array of electrodes. Charge measurement devices are coupled to selected electrodes in the network such that the spatial position of a charge event in the network can be determined by comparing the outputs from each charge measurement device. | 2012-11-22 |
| 20120293193 | WATER DETECTING APPARATUS - A water detecting apparatus, which comprises: at least one close loop circuit; and a water detecting circuit, for detecting if a resistance value for the close loop circuit is a predetermined value, to determine if any water exists on the close loop circuit. | 2012-11-22 |
| 20120293194 | SENSOR - Disclosed is a sensor that can accurately detect displacement and prevents the phenomenon of a contact section between a shaft member and a sliding element receiver being shifted. The sensor comprising: a case having a through hole; a resistance substrate fixed at an inside of said case; a shaft member having a first end portion which is one end of the shaft member placed within said case and a second end portion which is other end of the shaft member exposed to an outside of said case from said through hole, said shaft member being placed at said through hole in a movable manner in an axial direction; and a sliding element receiver having a bearing end contacting with said second end portion of said shaft member, and attached with a brush sliding together with said resistance substrate, said sliding element receiver being capable of moving relatively against said resistance substrate with said shaft member. A hemispherical end face is formed at said first end portion. A hemispherical hole internally contacting with said hemispherical end face is formed at said bearing end. | 2012-11-22 |
| 20120293195 | METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUITS - Aspects of the disclosure provide a testing method. The method includes supplying a power supply from a voltage regulator to a device under test (DUT). The DUT includes an adaptive voltage scaling module configured to generate a feedback signal in response to the power supply. Further, the method includes receiving the feedback signal from the DUT to the voltage regulator to regulate the power supply based on the feedback signal from the DUT, and determining whether the DUT meets a specified performance requirement while the voltage regulator regulates the power supply provided to the DUT based on the feedback signal received from the DUT. | 2012-11-22 |
| 20120293196 | TEST KEY STRUCTURE FOR MONITORING GATE CONDUCTOR TO DEEP TRENCH MISALIGNMENT AND TESTING METHOD THEREOF - The disclosure provides a test key structure for monitoring gate conductor to deep trench misalignment and a testing method thereof. The test key structure for monitoring gate conductor to deep trench misalignment includes: a deep trench capacitor structure comprising a plurality of parallel deep trench capacitor lines and a deep trench capacitor connect; a buried strap out-diffusion adjacent to a first side of the deep trench capacitor line; a first gate conductor structure comprising a plurality of parallel first gate conductor lines and a first gate conductor connect, wherein each first gate conductor line is disposed directly over the corresponding deep trench capacitor line; and a second gate conductor structure comprising a plurality of parallel second gate conductor lines and a second gate conductor connect, wherein the first gate conductor lines are electrically connected to each other via the second gate conductor connect, and wherein the first gate conductor lines and the second gate conductor lines are parallel to each other, and the first gate conductor lines and the second gate conductor lines are arranged alternately. | 2012-11-22 |
| 20120293197 | On-Chip Leakage Current Modeling and Measurement Circuit - At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit. | 2012-11-22 |
| 20120293198 | ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN - A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to V | 2012-11-22 |
| 20120293199 | Programmable Priority Encoder - In one embodiment, a programmable priority encoder is configured to receive inputs, including an ordered list of a plurality of input request values each representing either a request or a non-request, and a starting position within the ordered list of the plurality of input request values. The programmable priority encoder is configured to generate an identification of a result position of a first input indicating said request in order from a position identified from the starting position within the ordered list. In one embodiment, the programmable priority encoder includes a hierarchal structure of logic blocks including a plurality of columns of logic blocks; wherein a first-stage column of the plurality of columns of logic blocks is configured to operate on at most N input values; and wherein the ordered list of the plurality of input request values consists of N input request values. | 2012-11-22 |
| 20120293200 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation. | 2012-11-22 |
| 20120293201 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element. | 2012-11-22 |
| 20120293202 | PROGRAMMABLE LOGIC DEVICE - An object is to provide a programmable logic device which can hold configuration data even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, and can operate with low power. A transistor in a memory portion of a programmable switch includes a material which allows a sufficient reduction in off-state current of the transistor, such as an oxide semiconductor material which is a wide bandgap semiconductor. When the semiconductor material which allows a sufficient reduction in off-state current of the transistor is used, configuration data can be held even when a power supply potential is not supplied. | 2012-11-22 |
| 20120293203 | SEMICONDUCTOR DEVICE - A programmable analog device in which data can be held even when supply of a power supply potential is stopped. The programmable circuit includes unit cells connected in parallel or in series, and each of the unit cells includes an analog element. A conduction state of each of the unit cells is changed between an on state and an off state. Each of the unit cells includes, as a switch of the unit cell, a first transistor having a sufficiently low off-state current and a second transistor, a gate electrode of the second transistor being electrically connected to a source or drain electrode of the first transistor. The conduction state of the unit cell is controlled with a potential of the gate electrode of the second transistor, which can be kept even when no power is supplied thanks to the low off-state current of the first transistor. | 2012-11-22 |
| 20120293204 | SEMICONDUCTOR DEVICE - A semiconductor device in which a transistor using an oxide semiconductor containing In, Zn, or the like for a channel region can be driven like a p-channel transistor is provided. The semiconductor device includes a transistor and an inverter, wherein an output of the inverter is input to a gate of the transistor, a channel region of the transistor includes an oxide semiconductor film containing In, Zn, or Sn, and each channel region of transistors in the inverter contains silicon. When a high voltage is input to the inverter, a low voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned off. When a low is input to the inverter, a high voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned on. | 2012-11-22 |
| 20120293205 | INTEGRATED CIRCUIT DEVICE AND METHOD OF USING COMBINATORIAL LOGIC IN A DATA PROCESSING CIRCUIT - An integrated circuit device comprising one or more data processing circuits is provided, where each data processing circuit has an input stage, a combinatorial logic stage and an output stage. The input stage is responsive to a clock signal, and receives at least a first and a second set of data signals and provides the first set of data signals to an input of the combinatorial logic stage during a first portion of a period of the clock signal, and provides the second set of data signals to the input during a second portion of the period. The output stage is responsive to the clock signal, and receives from an output of the combinatorial logic stage at least a first result signal as a function of the first set of data signals during a first portion of a subsequent period of the clock signal and receive from the output at least a second result signal as a function of the second set of data signals during a second portion of the subsequent period. | 2012-11-22 |
| 20120293206 | PROGRAMMABLE LOGIC DEVICE - An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device. | 2012-11-22 |
| 20120293207 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit in which data is held even after power is turned off is provided. Further, a novel logic circuit whose power consumption can be reduced is provided. In the logic circuit, a comparator comparing two output nodes, a charge holding portion, and an output-node-potential determining portion are electrically connected to each other. Such a structure enables data to be held in the logic circuit even after power is turned off. Further, the total number of transistors in the logic circuit can be reduced. Furthermore, the area of the logic circuit can be reduced by stacking a transistor including an oxide semiconductor and a transistor including silicon. | 2012-11-22 |
| 20120293208 | Semiconductor Device - As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a plurality of capacitors. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region. | 2012-11-22 |
| 20120293209 | LOGIC CIRCUIT - A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile. | 2012-11-22 |
| 20120293210 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced. | 2012-11-22 |
| 20120293211 | DELAY LINE OFF-STATE CONTROL WITH POWER REDUCTION - A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state. | 2012-11-22 |
| 20120293212 | LOW POWER REFERENCE CURRENT GENERATOR WITH TUNABLE TEMPERATURE SENSITIVITY - An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator. | 2012-11-22 |
| 20120293213 | FREQUENCY SYNTHESIZER - In forming a frequency synthesizer by using PLL using processing of digital signals, an A/D converting unit is not required. By the integration of a digital value that depends on a set frequency, a saw-tooth wave serving as a phase signal is generated. A frequency signal output from a voltage-controlled oscillator is input via a frequency divider to an edge detecting unit, which then detects a rising edge or a falling edge of the frequency signal to generate a rectangular-wave signal that depends on a frequency of the frequency signal. Then, a latched circuit latches a value of the saw-tooth wave in response to the rectangular-wave signal, and this value is integrated in a loop filter and the resultant is used as a control voltage of the voltage-controlled oscillator. | 2012-11-22 |
| 20120293214 | ELECTRONIC SWITCHING DEVICE - An electronic switching device comprises a first bipolar junction transistor (BJT) ( | 2012-11-22 |
| 20120293215 | DRIVING CIRCUIT HAVING CURRENT BALANCING FUNCTIONALITY - A driving circuit having current balancing functionality includes a control unit, a bias resistor, a current switch unit and plural current driving modules. The control unit is utilized for generating a control signal having at least one bit according to a control current. The bias resistor is put in use for providing a bias voltage according to a bias current. The current switch unit employs the control signal and plural bias setting currents to generate the bias current, for keeping the bias voltage within a preset voltage range. The current driving modules are used to provide plural driving currents according to the bias voltage and the control signal. Each current driving module includes a current-limit control unit which is utilized for controlling a corresponding driving current according to the control signal. | 2012-11-22 |
| 20120293216 | MEMS CAPACITIVE SENSOR BIASING CIRCUIT INCLUDING AN INTEGRATED INDUCTOR - A MEMS capacitive sensor biasing circuit. The circuit includes a high-voltage (HV) NMOS switch, an inductor, a diode, and a capacitor. The HV NMOS switch has a source coupled to ground. The inductor has a first node coupled to a drain of the HV NMOS switch, and a second node coupled to a DC power source supplying a first DC voltage. The diode has an anode coupled to the first node of the inductor and the drain of the HV NMOS switch. The capacitor has a first node coupled to a cathode of the diode, and a second node coupled to the ground. | 2012-11-22 |
| 20120293217 | FEEDFORWARD ACTIVE DECOUPLING - There are a variety of duty cycle systems, such as low noise amplifiers or LNAs, that have a large time varying current consumption, and parasitic inductances and resistance (usually from bondwires in the package) that can significantly affect supply currents. Thus, to compensate for these parasitics, a boost circuit is provided that allows for current to be supplied from a separate supply using a feedforward scheme to perform active decoupling. | 2012-11-22 |
| 20120293218 | DRIVE CIRCUIT FOR VOLTAGE-CONTROL TYPE OF SEMICONDUCTOR SWITCHING DEVICE - A charging current is supplied to the gate (control terminal) of a driven switching device during an on-state command interval, for raising the gate voltage to an on-state value. Otherwise, discharging of the gate capacitance is enabled, for decreasing the gate voltage to an off-state value. A second switching device is connected between the gate and a circuit point held at the off-state voltage value, and is maintained in an on state while the gate discharging is enabled. At a first time point, the gate voltage rises above a threshold value. At a second time point, a voltage detection circuit detects that that the gate voltage has risen above the threshold value, causing the second switching device to be set in the off state. It is ensured that the delay between the first and second time points is shorter than a minimum duration of an on-state command interval. | 2012-11-22 |
| 20120293219 | BOOTSTRAP GATE DRIVER - A bootstrap gate driver including a load indication unit, a bootstrap gate-drive unit and a drive-control unit is provided. The load indication unit is configured to generate a load indication signal in response to a state of a load. The bootstrap gate-drive unit is configured to drive a switch-transistor circuit in response to an inputted pulse-width-modulation (PWM) signal, wherein the switch-transistor circuit has a high-side driving path and a low-side driving path. The drive-control unit is coupled to the load indication unit and the bootstrap gate-drive unit, and configured to enable or disable the high-side driving path in response to the load indication signal. In the invention, the operation of the low-side driving path is not affected by enabling or disabling the high-side driving path. | 2012-11-22 |
| 20120293220 | Reset Control Device, Reset Control Method and Electronic Device - A reset control device for an electronic device having a battery for providing operating power for a system circuit is provided. The reset control device includes a signal generating unit for generating a control signal, and a control module installed in the battery and coupled to the signal generating unit for disconnecting a power supply link between the battery and the system circuit for a predetermined duration and recovering the power supply link, when the control signal conforms to a predefined rule, so as to reset the system circuit. | 2012-11-22 |
| 20120293221 | DELAY LOCK LOOP AND DELAY LOCK METHOD - A delay lock loop comprising: a first delay loop, for delaying an input signal to generate a first output signal; a second delay loop, for frequency-dividing and delaying the input signal to generate a second output signal, wherein a frequency of the first output signal is higher than which of the second output signal; a phase detector, selectively detecting phases of the input signal, and one of the first delayed output signal and the second delayed output signal, to generate a phase detecting result; and a delay control circuit, for generating a first and a second delay control signal according to the phase detecting result, wherein the first and the second delay control signals are respectively transmitted to the first delay loop and the second delay loop, to control delay amounts of the first delay loop and the second delay loop. | 2012-11-22 |
| 20120293222 | PLL CIRCUIT - A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop. | 2012-11-22 |
| 20120293223 | PHASE LOCKED LOOP AND SEMICONDUCTOR DEVICE USING THE SAME - It is an object of the present invention to provide a phase locked loop in which a voltage signal input to a voltage controlled oscillator after a return from a stand-by state becomes constant in a short time and power consumption is reduced. A transistor including a semiconductor layer formed using an oxide semiconductor material is provided between an input terminal of a voltage controlled oscillator and a capacitor of a loop filter. The transistor is turned on in a normal operation state and turned off in a stand-by state. | 2012-11-22 |
| 20120293224 | DIGITAL CLOCK REGENERATOR - A sampling unit ( | 2012-11-22 |
| 20120293225 | DUTY CORRECTION CIRCUIT - A duty correction circuit includes a clock buffer configured to buffer an input clock and generate a buffer clock, a swing level conversion block configured to generate an internal clock, which transitions to levels of a sync voltage and a power supply voltage, in response to a voltage level of the buffer clock, a duty control block configured to generate duty information and frequency information by using a high pulse width and a low pulse width of the internal clock, and a current control block configured to control a time point, at which a logic value of the buffer clock transitions, in response to the duty information and the frequency information. The current control block includes a plurality of first current paths coupled in parallel to one another in order to control the time point at which the logic value of the buffer clock transitions. | 2012-11-22 |
| 20120293226 | CLOCK AND DATA RECOVERY SYSTEM, PHASE ADJUSTING METHOD, AND PHASEDETECTOR - Disclosed is a phase discriminator, including: a first XOR gate connected to a trigger and a delay unit, a second XOR gate connected to the trigger and a latch, wherein the first XOR gate is a current mode logic XOR gate, the first XOR gate comprises a first offset current source circuit outputting a first adjustable offset circuit for controlling amplitude of the error signal output by the first XOR gate; and/or, the second XOR gate is a current mode logic XOR gate, the second XOR gate comprises a second offset current source circuit outputting a second adjustable offset circuit for controlling amplitude of reference signal output by the second XOR gate. Also disclosed are a clock and data recovery system and a phase adjustment method. The present invention can prevent introducing noise coupling to the voltage control oscillator (VCO) module. | 2012-11-22 |
| 20120293227 | CAPACITOR CONTROLLED SWITCH SYSTEM - A switch controller is provided that uses one or more capacitors to generate a slow turn on/slow turn off switch control signals to suppress audible switching noise in an audio switch. In some embodiments, an analog inverter and a capacitor are used to generate the switch control signals, while in other embodiments two capacitors are used to generate the switch control signals. To conserve power between switching states, routing logic is provided that ties the switch control signals to respective voltage rails and disables selected portions of the switch controller. | 2012-11-22 |
| 20120293228 | LEVEL CONTROL CIRCUIT, LEVEL CONTROL METHOD, AND LEVEL CONTROL SYSTEM - A level control circuit that generates output signal for level control includes: a control information storage that stores control information corresponding to a signal level, a control information circuit that outputs the output signal for level control corresponding to the signal level of a first input signal based on the control information stored in the control information storage; and an information update circuit that updates the control information of the control information storage according to the signal level of a second input signal. | 2012-11-22 |
| 20120293229 | CIRCUIT AND METHOD FOR PERFORMING ARITHMETIC OPERATIONS ON CURRENT SIGNALS - A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode. | 2012-11-22 |
| 20120293230 | RINGING SUPPRESSION CIRCUIT - An inter-line switching element formed of a MOSFET is provided between a pair of signal lines. When the level of a differential signal changes from high to low, a control circuit turns on the FET for a fixed period thereby to suppress ringing by decreasing the impedance between the signal lines when the level of the differential signal transitions, and causing the energy of the distortion of the differential signal waveform to be absorbed by the on-resistance of the FET. | 2012-11-22 |
| 20120293231 | Semiconductor Device - An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied. | 2012-11-22 |
| 20120293232 | 2-PHASE THRESHOLD DETECTOR BASED CIRCUITS - A switched capacitor circuit includes a threshold detector to generate a threshold detection signal when a difference between first and second input signals crosses a predetermined level. A coarse current source produces a coarse ramp. A series sampling capacitor samples a coarse output voltage when the threshold detector indicates a first threshold crossing. The sampling capacitor is connected in series with a fine current source producing a fine ramp. | 2012-11-22 |
| 20120293233 | Broadband Analog Radio-Frequency Components - Broadband analog radio-frequency devices can be used to create building blocks for scalable analog signal processors that operate over bandwidths of | 2012-11-22 |
| 20120293234 | PULSE SHAPER CIRCUIT WITH REDUCED ELECTROMAGNETIC EMISSION - In one embodiment, a circuit-based apparatus that operates on an input data stream includes delay-line circuitry that characterizes the input data stream, modified over time. A plurality of integrators provide a plurality of integrated signals in response to the delay-line circuitry, and a plurality of weighting amplifiers amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit combines the weighted signals. The circuit-based apparatus also includes a plurality of parallel signal-processing circuit paths that couple the weighted signals to the signal-combining circuit. By combining the weighted signals from the parallel signal-processing circuit paths, the signal-combining circuit provides a signal representative of the input data stream. | 2012-11-22 |
| 20120293235 | DOWNCONVERTER, DOWNCONVERTER IC, AND METHOD FOR CONTROLLING THE DOWNCONVERTER - A downconverter capable of being normally operated even in the case where a universal dual downconverter is made up by use of multiple downconverter circuits. The downconverter includes first and second downconverter circuits, and an amplification unit having at least a first amplifier LNA for receiving a horizontally polarized wave signal, and a second amplifier LNA for receiving a vertically polarized wave signal. If a Tone/Pola signal is a signal indicating a power-saving mode, a control circuit of the first downconverter circuit causes both a local oscillator and a frequency converter to be in a non-operating state, controlling a bias circuit such that power is supplied to the first amplifier LNA. | 2012-11-22 |
| 20120293236 | NONVOLATILE NANO-ELECTROMECHANICAL SYSTEM DEVICE - A nonvolatile nano-electromechanical system device is provided and includes a cantilever structure, including a beam having an initial shape, which is supported at one end thereof by a supporting base and a beam deflector, including a phase change material (PCM), disposed on a portion of the beam in a non-slip condition with a material of the beam, the PCM taking one of an amorphous phase or a crystalline phase and deflecting the beam from the initial shape when taking the crystalline phase. | 2012-11-22 |
| 20120293237 | HIGH-FREQUENCY SWITCH MODULE AND HIGH-FREQUENCY SWITCH APPARATUS - A high-frequency switch module includes a multi-layer substrate, and a switch circuit mounted on the multi-layer substrate. The multi-layer substrate includes a terminal through which a plurality of high-frequency signals in a plurality of frequency bands are input and output, a plurality of switch terminals, terminals to which control signals to control the switch circuit are supplied, current paths that connect the terminals to the switch circuit, and resistors that are provided on the current paths and have resistance values greater than the resistance values of the current paths. The switch circuit connects the terminal to the switch terminals corresponding to the frequency bands of high-frequency signals input and output through the terminal based on the control signals. | 2012-11-22 |
| 20120293238 | CIRCUIT USED FOR INDICATING PROCESS CORNER AND EXTREME TEMPERATURE - The present invention discloses a circuit used for indicating process corner and extreme temperature. It mainly comprises a proportional to absolute temperature (PTAT) current source, a negative to absolute temperature (NTAT) current source, a constant to absolute temperature (CTAT) current source, a corner detector, a poly detector, an extreme temperature detector. The circuit can save more power consumption without trade-off. In debug phase, the suspect sample can read out which state is and can run simulation check quickly to identify the real problem. In production phase, process indicator can easy read out at CP station. In the mean time, the large quantity of data can be easy collected and analyzed. | 2012-11-22 |
| 20120293239 | Device for Generating a Reference Current Proportional to Absolute Temperature, with Low Power Supply Voltage and Large Power Supply Rejection Rate - The device for generating a reference current proportional to absolute temperature comprises processing means connected to the terminals of a core and designed to equalize the voltages across the terminals of the core, the core being designed to then be traversed by an internal current proportional to absolute temperature, and an output module designed to deliver to an output terminal the said reference current on the basis of the said internal current; the processing means comprise a self-biased amplifier possessing at least one first stage arranged according to a folded setup and comprising first PMOS transistors arranged in a setup of the common-gate type, and a feedback stage whose input is connected to the output of the amplifier and whose output is connected to the input of the first stage as well as to at least one terminal of the core. | 2012-11-22 |
| 20120293240 | Membrane touch control panel - A membrane touch control panel includes a number of female conductors disposed on the basic layer and each having a number of electrodes electrically connected and coupled together, and each having an opening formed in each electrode, and a number of male conductors having a number of electrodes electrically connected and coupled together and received and engaged in the openings of the female electrodes respectively for forming a number of switch members, the membrane touch control panel includes a structure or configuration to be easily and quickly manufactured with greatly reduced manufacturing cost and procedures. | 2012-11-22 |
| 20120293241 | ELECTRONIC TRIMMING CIRCUIT WITH REDUCED NUMBER OF DEDICATED TRIMMING PINS - An electronic trimming circuit carries out a trimming operation on portions of an integrated device. The circuit includes N trimmable interconnected resistances, each connected in parallel to a respective shunt fuse. N trimming transistors are each connected to a respective one of the shunt fuses to force therethrough substantially the whole current flowing in the respective trimming transistor. N bias networks are each functionally connected to a control terminal of a respective one of the trimming transistors to directly bias an active junction thereof. An externally driven heating device is thermally coupled with the active junctions of the trimming transistors adapted to raise the temperature thereof. | 2012-11-22 |
| 20120293242 | Semiconductor Device - As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a first capacitor and a second capacitor. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region. | 2012-11-22 |
| 20120293243 | SEMICONDUCTOR DEVICE INCLUDING BOOSTING CIRCUIT - According to one embodiment, a semiconductor device includes the following configuration. A control circuit controls an output voltage to a predetermined voltage, based on a monitor voltage configured to monitor the output voltage. A switch circuit sets the output voltage to first and second voltages in first and second operation states, respectively. The second voltage is higher than the first voltage. A clock driver generates a clock signal that includes a voltage level of the output voltage as an amplitude thereof. A charge pump is formed by connecting unit circuits in series and at multiple stages. Each of the unit circuits includes a capacitor and a diode. The charge pump boosts an input voltage by the clock signal that is inputted to the capacitor. | 2012-11-22 |
| 20120293244 | CHARGE PUMP CIRCUITS AND METHODS - Embodiments of the present invention include charge pump circuits and methods. In one embodiment, a first charge pump receives a voltage and generates a first charge pump output voltage and current for supplying the power requirements of a circuit. A second charge pump is coupled in series with the first charge pump. The second charge pump generates a second charge pump output voltage and current for supplying different power requirements of the circuit. In one embodiment, the first charge pump provides a high current low voltage output to a first circuit and the second charge pump provides a low current high voltage output to a second circuit. Capacitors of the first charge pump may be external to an integrated circuit and capacitors of the second charge pump may be internal to the integrated circuit. | 2012-11-22 |
| 20120293245 | VOLTAGE REDUCING CIRCUIT - A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage. | 2012-11-22 |
| 20120293246 | Circuit, An Adjusting Method, and Use of a Control Loop - A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored. | 2012-11-22 |
| 20120293247 | Semiconductor Integrated Circuit Device - The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode. | 2012-11-22 |
| 20120293248 | ACTIVE AND CONFIGURABLE FILTER DEVICE - An active and configurable filter device includes a first filter with a first quality factor, a second filter with a second quality factor and a third filter with a third quality factor. The first filter defines a bandwidth and central frequency of the filter device. The second filter is connected to the first filter for using the spectrums of the first filter and second filter to define a lower bound frequency and sharpness of the bandwidth of the filter device. The third filter is connected to the second filter for using the spectrums of the first filter and third filter to define an upper bound frequency and sharpness of the bandwidth of the filter device. The first quality factor is an adjustable value in a range of 5 to 15, and the second and the third quality factors are each an adjustable value greater than 15. | 2012-11-22 |
| 20120293249 | POWER AMPLIFIER INSENSITIVE TO LOAD IMPEDANCE CHANGES - Disclosed herein is a power amplifier insensitive to load impedance changes. According to the present invention, the power amplifier comprises a power amplification circuit which amplifies an input signal, an output matching circuit connected to an output terminal of the power amplification circuit to perform impedance matching between the power amplification circuit and an antenna load, and a 4-port coupler connected between the output matching circuit and the antenna load. | 2012-11-22 |
| 20120293250 | AMPLIFIER - The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier. | 2012-11-22 |
| 20120293251 | DOHERTY POWER AMPLIFIER AND IMPLEMENTATION METHOD THEREOF - A Doherty power amplifier and an implementation method thereof are disclosed. The Doherty power amplifier includes a carrier power amplifier circuit and a peak power amplifier circuit, wherein, the peak amplifier circuit is configured with a Radio Frequency (RF) switch for controlling turn-on of peak power amplifiers in the peak amplifier circuit; and a part or all of carrier power amplifiers in the carrier power amplifier circuit use GaN devices, and a part or all of the peak power amplifiers in the peak power amplifier circuit use LDMOS devices. | 2012-11-22 |
| 20120293252 | Systems and Methods of RF Power Transmission, Modulation, and Amplification, Including Varying Weights of Control Signals - Embodiments of the present invention include a method and system for control of a multiple-input-single output (MISO) device. For example, the method includes determining a change in power output level from a first power output level to a second power output level of the MISO device. The method also includes varying one or more weights associated with respective one or more controls of the MISO device to cause the change in power output. The one or more controls can include one or more of (a) a phase control of one or more input signals to the MISO device, (b) a bias control of the MISO device, and (c) an amplitude control of the input signals to the MISO device | 2012-11-22 |
| 20120293253 | PSEUDO-ENVELOPE FOLLOWING POWER MANAGEMENT SYSTEM - Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system used to manage the power delivered to a linear RF power amplifier. | 2012-11-22 |
| 20120293254 | VARIABLE SWITCHED DC-TO-DC VOLTAGE CONVERTER - A voltage converter can be switched among two or more modes to produce an output voltage tracking a reference voltage that can be of an intermediate level between discrete levels corresponding to the modes. One or more voltages generated from a power supply voltage, such as a battery voltage, can be compared with the reference voltage to determine whether to adjust the mode. The reference voltage can be independent of the power supply voltage. | 2012-11-22 |
| 20120293255 | AMPLIFIER, TRANSMISSION DEVICE, AND AMPLIFIER CONTROL METHOD - An amplifier includes an envelope detection unit that detects an envelope of a transmission signal; a comparing unit that compares a voltage of the envelope with a reference voltage; a selecting unit that selects, in accordance with a comparison result obtained by the comparing unit, an amplifying element that amplifies the transmission signal from among a plurality of amplifying elements each having different operating power; a voltage control unit that controls, in accordance with the envelope, a voltage that is used to amplify the transmission signal in the amplifying element that is selected by the selecting unit; a current measuring unit that measures a current of a power supply that supplies the voltage that is controlled by the voltage control unit; and a reference voltage control unit that controls the reference voltage such that the current measured by the current measuring unit decreases. | 2012-11-22 |
| 20120293256 | SWITCHING AMPLIFIER - When a switching amplifier transitions into a power-off state, a switch is turned off and a power supply controller forcibly discharges a capacitor and forcibly reduces a reference potential with respect to a second power supply voltage. Since a logic power supply voltage reduces by the same amount as the reference potential, the logic power supply voltage from a viewpoint of the reference potential is fixed. A constant current circuit reduces a constant current according to the reduction in the reference potential with respect to the second power supply voltage, and reduces a first electric current and a second electric current. Before the logic power supply voltage from the viewpoint of the reference potential reduces, the first electric current and the second electric current are reduced, and an operation of a pulse generating unit can be ended in a normal state. | 2012-11-22 |
| 20120293257 | HIGH FREQUENCY POWER AMPLIFIER - A high frequency power amplifier includes: a first transistor for amplifying an input high-frequency signal; a second transistor for amplifying an output signal of the first transistor; a third transistor connected in parallel with the first transistor and for amplifying the input high-frequency signal; a first switching element connected between an output of the first transistor and an input of the second transistor; a second switching element connected between an output of the third transistor and the first switching element; third and fourth switching elements connected in series between the output of the first transistor and an output of the second transistor, and between the second switching element and the output of the second transistor; and a first capacitor connected between the third switching element and the fourth switching element. | 2012-11-22 |
| 20120293258 | INPUT COMMON MODE CIRCUIT FOR A FULLY DIFFERENTIAL AMPLIFIER - This application describes a system for minimizing the common mode voltage drift at the input of a fully differential amplifier. An impedance component is coupled to the inputs and outputs of the differential amplifier. The impedance component optimizes the common mode resistance or impedance to ground without significantly affecting the differential impedance, matches the input common mode voltage to the output common mode voltage and reduces the input common mode voltage drift in presence of leakage currents. | 2012-11-22 |
| 20120293259 | Amplifier - A configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance stage whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a common-gate low noise amplifier stage whereby the low noise amplifier circuit operates as a common-gate low noise amplifier. The second topology includes one or more internal input impedance matching components and the first topology does not include the one or more internal input impedance matching components. | 2012-11-22 |
| 20120293260 | Low-Offset Current-Sense Amplifier and Operating Method Thereof - A low-offset current-sense amplifier and an operating method thereof are disclosed. The low-offset current-sense amplifier includes a sense amplifier, a first current supply unit, a second current supply unit, and a processing unit. The first current supply unit is coupled to the sense amplifier, and includes a first transistor group and a first current output terminal. The second current supply unit is coupled to the sense amplifier, and includes a second transistor group and a second current output terminal. The processing unit controls the on/off of some transistors of the first transistor group and the second transistor group according to electric currents output from the first current output terminal and the second current output terminal, respectively. | 2012-11-22 |
| 20120293261 | Amplifier with Start-up Common Mode Feedback - An amplifier with a cascode device contains a common mode feedback circuit to ensure correct operating point in the amplifier. Common mode feedback is provided to the amplifier to maintain the common mode operating point during active operation. Additional common mode feedback is provided to the cascode devices to ensure correct start-up by forcing the node voltages to go to their desired voltage levels. | 2012-11-22 |
| 20120293262 | Amplifier - The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier. | 2012-11-22 |
| 20120293263 | OPERATIONAL AMPLIFIER - An operational amplifier may include a transimpedance input stage. The operational amplifier is capable of self-biasing its input voltage(s) including a first stage, an input source connected to the first stage, an output stage connected to the first stage via feedback resistors, and feedback current sources connected to the first stage, wherein the feedback current sources are set to generate feedback currents flowing from the output stage back to the input stage via the feedback resistors, so as to self-bias the input voltage(s) at the input stage. A method for allowing for an op-amp to self-bias its input voltage(s), including generating feedback currents flowing from the output stage back to the input stage via feedback resistors, so as to self-bias the input voltage(s) at the input stage. | 2012-11-22 |
| 20120293264 | Power Control for Linear and Class AB Power Amplifiers - Aspects of a system for improving efficiency over power control for linear and class AB power amplifiers may include a current source circuit that enables determination of a bias current level for a PA circuit within an IC die based on an amplitude of an input modulation signal. The PA circuit may enable generation of an output signal based on a differential input signal and the input modulation signal to the current source circuit. A generated bias voltage may be applied to a transformer external to the IC die, but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels may be applied to the PA circuit wherein the amplifier bias voltage levels may be derived from the generated bias voltage level and/or the determined bias current level. | 2012-11-22 |
| 20120293265 | Radio Frequency Integrated Circuit - Embodiments of the invention are concerned with configurable RFICs. In an exemplary embodiment there is provided a configurable radio-frequency integrated circuit (RFIC) including one or more configurable low noise amplifier circuits, each of said one or more configurable low noise amplifier circuits being configurable between: | 2012-11-22 |
| 20120293266 | Power Amplifiers with Improved Efficiency Over Power Control - Aspects of a system for improving efficiency over power control for linear and class AB power amplifiers may include a current source circuit that enables determination of a bias current level for a PA circuit within an IC die based on an amplitude of an input modulation signal. The PA circuit may enable generation of an output signal based on a differential input signal and the input modulation signal to the current source circuit. A generated bias voltage may be applied to a transformer external to the IC die, but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels may be applied to the PA circuit wherein the amplifier bias voltage levels may be derived from the generated bias voltage level and/or the determined bias current level. | 2012-11-22 |
| 20120293267 | LNA CIRCUIT FOR USE IN A LOW-COST RECEIVER CIRCUIT - A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal. | 2012-11-22 |
| 20120293268 | Narrowband amplifier with improved interference suppression - A radio signal is input to a first terminal and output after amplification at a second terminal. There is a third terminal which is common to both the first and the second terminal. There is an inductance interfacing the second terminal to a direct current power supply; and a radio frequency filter connected in shunt with the inductance. In an exemplary embodiment the first, second and third terminals are respective base, collector and emitter terminals of a bipolar transistor. Such a bipolar transistor is characterized in that voltage from the power supply passes to the second terminal through the inductance but not through the radio frequency filter; and the signal output passes from the second terminal through the radio frequency filter but not through the inductance. The illustrated embodiments show the radio frequency filter as a surface acoustic wave filter in direct connection with the second terminal. | 2012-11-22 |
| 20120293269 | INTEGRATED CIRCUIT FREQUENCY GENERATOR - An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles. | 2012-11-22 |
| 20120293270 | METHOD AND SYSTEM FOR TESTING OSCILLATOR CIRCUIT - An oscillator circuit generates a voltage signal. The magnitude of the voltage signal is measured and compared with predetermined upper and lower voltage signals by an internal test circuit. If the magnitude of the voltage signal is between the predetermined upper and lower voltage signals, then a pass test status signal is generated. If the magnitude of the voltage signal is not between the predetermined upper and lower voltage signals then a fail test status signal is generated. | 2012-11-22 |
| 20120293271 | Voltage tunable oscillator using bilayer graphene and a lead zirconate titanate capacitor - A voltage controlled oscillator comprising a substrate and a bilayer graphene transistor formed on the substrate. The transistor has two signal terminals and a gate terminal positioned in between the signal terminals. A voltage controlled PZT or MEMS capacitor is also formed on the substrate. The capacitor is electrically connected to the transistor gate terminal. At least one component is connected to the transistor and capacitor to form a resonant circuit. | 2012-11-22 |
| 20120293272 | Methods And Systems For Generating Millimeter-Wave Oscillations - The various embodiments of the present invention provide improved methods and circuits for generating millimeter-wave oscillations. Generating millimeter-wave oscillations may involve providing a semiconductor device comprising at least two terminals and a polar heterojunction formed from two semiconductor materials. A voltage bias may be applied to at least two terminals of the device in which the voltage enhances a two-dimensional electron gas (2DEG) layer at the polar heterojunction and produces a sharply-peaked but spatially-localized electric field within the 2DEG with a large longitudinal component, wherein the longitudinal component of the electric field serves as a nucleation site for a plurality of propagating dipole domains observable as a plurality of self-sustaining millimeter-wave oscillations. | 2012-11-22 |
