47th week of 2013 patent applcation highlights part 30 |
Patent application number | Title | Published |
20130308325 | MOUNTING ASSEMBLY FOR HANGING FIXTURE AND RELATED INSTALLATION METHOD - A mounting assembly for attaching a lighting fixture to an overhead structure. The mounting assembly includes at least a first member and a second member. The first member is configured to be coupled to the overhead structure and includes a base with an opening provided therein. The second member is configured to be coupled to the fixture and includes a body and an catch extending from the body. The catch is configured to engage the opening to pivotally connect the second member to the first member, such that the base is substantially parallel to the body. | 2013-11-21 |
20130308326 | CONTROL DEVICE FOR VEHICLE LAMP AND VEHICLE LAMP SYSTEM - There is provided a control device for controlling a vehicle lamp. The device includes: a receiver configured to receive an output value from an inclination sensor; and a controller configured to control an optical axis of the vehicle lamp based on a vehicle attitude angle that is an inclination angle of the vehicle with respect to a road surface. The controller is configured to control the optical axis in a first optical axis control mode or a second optical axis mode, wherein an optical axis angle of the optical axis is adjusted in accordance with the vehicle attitude angle in the first optical axis mode, and the second optical axis control mode is different from the first optical axis control mode. The controller controls the optical axis in the second optical axis control mode, when the vehicle attitude angle is not included in a predetermined range. | 2013-11-21 |
20130308327 | Electrical Coupling - An electrical coupling is for a vehicle and trailer assembly. The coupling is supplied with electricity and comprises a light source for illuminating an area adjacent the coupling. | 2013-11-21 |
20130308328 | Headlamp Featuring Both Low-Beam and High-Beam Outputs and Devoid of Moving Parts - A headlight produces low-beam and high-beam outputs without requiring moving parts. Low-beam LED array ( | 2013-11-21 |
20130308329 | LED LIGHT MODULE - The invention relates to an LED light module ( | 2013-11-21 |
20130308330 | LAMP UNIT - A lamp unit mounted in a vehicle includes a light source, a light source mounting portion on which the light source is mounted, and a projection lens having a front surface with a convex shape and configured to project light from the light source to the front of the lamp unit. When looking at the lamp unit from the front, the front surface of the projection lens takes a substantially round shape which is centered at an optical axis of the lamp unit in a position which lies closer to a front end portion and a substantially non-round shape at a rear end portion. The front surface changing gradually its shape from the substantially round shape to the substantially non-round shape in a region between the position and the rear end portion as it extends from the position towards the rear end portion. | 2013-11-21 |
20130308331 | ANTI-GLARE LIGHT SOURCE - An anti-glare light source includes a linear light source and a light-modulation element. The linear light source is suitable for providing light, and the light-modulation element is disposed on a propagating path of the light. The light-modulation element includes a plurality of parallel bar-shaped prisms. The bar-shaped prisms are arranged along an extension direction of the linear light source. An extension direction of each of the bar-shaped prisms is substantially perpendicular to the extension direction of the linear light source so as to converge the distribution of the light along the extension direction of the linear light source. | 2013-11-21 |
20130308332 | LASER-BASED WHITE LIGHT SOURCE - A device for generating white light is provided that includes at least one light source and at least one conversion medium. The light source emits light in the blue and/or ultraviolet spectral range. The light from the light source is generated by a laser and the light from the light source is focused by an optical system onto the conversion medium. The conversion medium converts at least part of the incident light into a different spectral range. | 2013-11-21 |
20130308333 | Semiconductor Light Source Free From Facet Reflections - A new class of optical source having a truncated waveguide is provided, where a guided section of a light generating medium is terminated at an angle at a predetermined distance away from one end facet of the waveguide, thereby leaving a section for unguided light propagation. A truncated waveguide when implemented in combination with waveguide tilt, effective front facet reflectivity is reduced significantly to eliminate unwanted facet reflections. By extending electrical pumping in the unguided propagation section, the light in the unguided path propagates to a corresponding end facet without attenuation. The reflected light propagates freely without being intercepted by the waveguide. The principles are incorporated in different types of light generating and amplifying medium including a “double-pass” gain medium for designing optical sources having significantly high output power and negligibly small spectral modulation arising from unwanted facet reflections. | 2013-11-21 |
20130308334 | LUMINESCENT DEVICE - A device for stimulable light emission that includes a fiber mat of nanofibers having an average fiber diameter in a range between 100 and 2000 nm, and includes plural stimulable particles disposed in association with the nanofibers. The stimulable particles produce secondary light emission upon receiving primary light at a wavelength λ. The average fiber diameter is comparable in size to the wavelength λ in order to provide scattering sites within the fiber mat for the primary light. Various methods for making suitable luminescent nanofiber mats include: electrospinning a polymer solution including or not including the stimulable particles and forming from the electrospun solution nanofibers having an average fiber diameter between 100 and 2000 nm. Methods, which electrospin without the stimulable particles, introduce the stimulable particles during electrospinning or after electrospinning to the fibers and therefore to the resultant fiber mat. | 2013-11-21 |
20130308335 | MODULAR OPTICAL FIBER ILLUMINATION SYSTEMS - A modular optical-fiber-based illumination system comprises a light source ( | 2013-11-21 |
20130308336 | FLAT AND THIN LED-BASED LUMINAIRE - A light emitting device is provided, comprising a light guide plate ( | 2013-11-21 |
20130308337 | BACKLIGHT MODULE - A backlight module includes a light source, a photoluminescence layer, and an optical film. The light source is used to provide a light beam. The photoluminescence layer is excited by the light beam from the light source and generates an excitation light. The optical film overlaps the photoluminescence layer along a vertical projective direction. The optical film includes a substrate and a plurality of two-dimensional symmetrical micro-structures. The two-dimensional symmetrical micro-structures are disposed on at least one surface of the substrate. The excitation light is emitted through the two-dimensional symmetrical micro-structures. | 2013-11-21 |
20130308338 | LED CUP LAMP WITH LIGHT GUIDE - The present invention discloses an LED lamp which has a light guide with a total internal reflection (TIR) surface. A light modification layer comprising either a pure component or a mixture of the component selected from a group consisted of a yellow phosphor, a red phosphor, a green phosphor, a blue phosphor, and a reflective material is optionally adopted. The light beam is modified by the light modification layer before going out of the lamp. A blue light is one of the candidates which can be adopted as the light source. | 2013-11-21 |
20130308339 | Directional backlight - Disclosed is a light guiding valve apparatus including at least one transparent stepped waveguide optical valve for providing large area collimated illumination from localized light sources, and at least one further illumination source. A stepped waveguide may be a stepped structure, where the steps include extraction features hidden to guided light, propagating in a first forward direction. Returning light propagating in a second backward direction may be refracted, diffracted, or reflected by the features to provide discrete illumination beams exiting from the top surface of the waveguide. Such controlled illumination may provide for efficient, multi-user autostereoscopic displays as well as improved 2D display functionality. Light from a separate illumination source may pass through the transparent stepped waveguide optical valve to provide at least one further additional illumination function. | 2013-11-21 |
20130308340 | ALUMINUM EXTRUSION HEAT SINK STRUCTURE AND CORRESPONDING BACKLIGHT MODULE - The present invention relates to an aluminum extrusion heat sink structure and a corresponding backlight module. The aluminum extrusion heat sink structure comprises a light source connecting portion, a back plate connecting portion and a light guide plate support portion. The manufacture cost of the aluminum extrusion heat sink structure is lower, and the heat dissipation effect is better, so as to solve the technology problem that the volume of a traditional aluminum extrusion heat sink structure is larger caused the cost of the aluminum extrusion heat sink structure and the corresponding backlight module is higher. | 2013-11-21 |
20130308341 | FLAT PANEL DISPLAY AND METHOD FOR ASSEMBLING THE FLAT PANEL DISPLAY - A front frame of a flat panel display having positioning structure allows a LCD cell to be positioned and mounted thereon along an assembly direction. A restraining frame may be further incorporated for positioning and spacing purposes for each component of the display. Optical films, a light guide component, a backlight unit, and a reflector of the flat panel display are then mounted in a row along the assembly direction on the restraining frame or the front frame, where the backlight unit and/or the reflector may be fixed to a back cover of the backlight module in advance. Finally, a speaker, wiring of the display, circuit boards, and a board cover are assembled to the front frame and the back cover. | 2013-11-21 |
20130308342 | BLACKLIGHT MODULE AND DISPLAY APPARATUS - The present invention provides a backlight module and a display apparatus. The display apparatus comprises the backlight module and a display panel. The backlight module comprises a back bezel, a light guide plate and a plurality of light sources. The back bezel includes a plurality of bezel convex portions and a plurality of corresponding bezel concave portions. The light guide plate includes a plurality of recesses, and the bezel convex portions of the back bezel are fitted into the recesses of the light guide plate. The light sources are disposed at one side of the light guide plate. The present invention can use the bezel concave portions of the back bezel to improve a heat-dissipation effect. | 2013-11-21 |
20130308343 | BACKLIGHT UNITS AND DISPLAY DEVICES INCLUDING THE SAME - A display device includes a display panel which displays an image, a backlight unit which supplies the display panel with light, an upper cover, and a lower cover. The upper and lower covers accommodate the display panel and the backlight unit. The backlight unit includes light guide plates spaced apart from each other, a light source part, an optical member and an optical diffusion member overlapping a space between the light guide plates. The optical diffusion member includes a diffusing part and a supporting part. The diffusing part faces the optical member, overlaps the space between the light guide plates, and diffuses light emitted from the light source part toward the optical member through the space between the light guide plates. The supporting part protrudes from a surface of the diffusing part which is opposite to the optical member, and is in a space between the light sources. | 2013-11-21 |
20130308344 | POWER CONVERTER AND METHOD - A power converter apparatus includes a primary bridge having a plurality of diagonally opposed primary power elements, and a secondary bridge having a plurality of diagonally opposed secondary power elements. The primary and secondary bridges are electrically coupled by a transformer. At least one control unit is configured to phase-shift switch the primary and secondary power elements, such that one or more of the primary and secondary power elements are switched off under near-zero current conditions to reduce voltage and current stresses and commutation losses within the power converter. | 2013-11-21 |
20130308345 | Variable Duty Cycle Switching With Imposed Delay - Power conversion methods, systems, articles of manufacture, and devices are provided. The power conversion may include converting between direct current and alternating current wherein switching losses associated with latent electrical charges are reduced. Current sensing may be low-side bus reference. Solid-state implementations, code implementations, and mixed implementations are provided. | 2013-11-21 |
20130308346 | ACTIVE AC SNUBBER FOR DIRECT AC/AC POWER CONVERTERS - Active AC snubbers for AC/AC converters are provided. The active snubbers are actively-controlled AC snubbers that may be used in AC/AC power converters including direct AC converters. The active snubbers provide a free-wheeling path for AC/AC converters, ensuring that the converters are tolerant of errors in measurements and timings and of faults. The desired safe commutation of the switching devices when accurate measurements of voltage and current polarities become difficult or under fault contingencies when trapped energy needs to be dispatched safely is ensured. In addition, the active AC snubber may provide equal voltage sharing among the series-connected devices and clamp output voltages. | 2013-11-21 |
20130308347 | RESONANT SWITCHING POWER SUPPLY DEVICE - A winding voltage arising in a first winding on the primary side of a transformer is detected in a winding voltage detector unit formed of a second winding, and current flowing through a resonant circuit is detected in a resonant current detector unit formed of an auxiliary capacitor and a resistor. The timing at which the polarity of the detected winding voltage is inverted is detected in a control and drive unit, and the time at which the polarity of the resonant current, whose phase is delayed with respect to that of the winding voltage, will be inverted is determined in advance. In the event that there is a switch in an on-state when the timing immediately before the inversion of the polarity of the resonant current is detected from the output of the resonant current detector unit, the control and drive unit forcibly turns off the switch. | 2013-11-21 |
20130308348 | CONVERTER - A converter includes a transformer module, a primary side circuit module, and a secondary side circuit module. The transformer module includes a magnetic core group and a winding. The winding includes a primary winding and a secondary winding, and is further installed on the magnetic core group. The primary side circuit module is coupled to the primary winding. The secondary side circuit module is coupled to the secondary winding. The primary side circuit modules or the secondary side circuit module has overlapping vertical projection area on a first plane with the winding, and the first plane is a plane in a horizontal direction of the winding. | 2013-11-21 |
20130308349 | SWITCHING REGULATOR, THE CONTROL CIRCUIT AND THE METHOD THEREOF - A switching regulator that decreases power loss and resolves thermal issues by jumping its switching frequency to a maximum frequency when its load reaches a peak load. | 2013-11-21 |
20130308350 | SYSTEMS AND METHODS FOR CONSTANT VOLTAGE MODE AND CONSTANT CURRENT MODE IN FLYBACK POWER CONVERTERS WITH PRIMARY-SIDE SENSING AND REGULATION - System and method for regulating a power converter. The system includes a first signal generator configured to receive at least an input signal and generate at least a first output signal associated with demagnetization and a second output signal associated with sampling. Additionally, the system includes a sampling component configured to receive at least the input signal and the second output signal, sample the input signal based on at least information associated with the second output signal, and generate at least a third output signal associated with one or more sampled magnitudes. Moreover, the system includes an error amplifier configured to receive at least the third output signal and a first threshold voltage and generate at least a fourth output signal with a capacitor, the capacitor being coupled to the error amplifier. | 2013-11-21 |
20130308351 | HIGH VOLTAGE INDUCTOR FILTER APPARATUS AND METHOD OF USE THEREOF - The invention comprises a high frequency inductor filter apparatus coupled with an inverter yielding high frequency harmonics and/or non-sixty Hertz output. For example, an inductor/converter apparatus is provided that uses a silicon carbide transistor to output power having a carrier frequency, modulated by a fundamental frequency, and a set of harmonic frequencies. A filter, comprising an inductor having a distributed gap core material and optional magnet wires, receives power output from the inverter/converter and processes the power by passing the fundamental frequency while reducing amplitude of the harmonic frequencies. | 2013-11-21 |
20130308352 | METHOD FOR IMPROVING PERFORMANCE OF FILTER AND POWER CONVERSION APPARATUS - A power conversion apparatus is disclosed in the present application. The power conversion apparatus comprises: a power converter comprising an energy-storage magnetic component, and a filter comprising an inductor component and a two-port network connected the energy-storage magnetic component and the inductor component, wherein a series resonance is formed by the two-port network and a mutual inductance which is formed by a coupling between the energy-storage magnetic component and the inductor component. | 2013-11-21 |
20130308353 | NEAR ZERO CURRENT-RIPPLE INVERSION OR RECTIFICATION CIRCUITS - The present invention relates to a near zero current-ripple inversion circuit including top and bottom cells, a transformer (T | 2013-11-21 |
20130308354 | POWER SUPPLY NOISE REDUCTION CIRCUIT AND POWER SUPPLY NOISE REDUCTION METHOD - To provide a power supply noise reduction circuit and a power supply noise reduction method that do not require circuit elements to be increased in size and do not cause voltage drop in a power supply voltage. A power supply noise reduction circuit | 2013-11-21 |
20130308355 | POWER CONVERTER AND MATRIX CONVERTER - The number of ICs used for a power converter is reduced. The power converter includes n power transistors each having an emitter terminal or a source terminal connected to a common line, and driver ICs. Each of the driver ICs includes n pre-drivers that drive the respective n power transistors, and a receiver circuit that is integrated monolithically with the n pre-drivers. The receiver circuit is coupled with a transmitter circuit by AC coupling, and outputs a control signal that controls the n pre-drivers in response to a signal received from the transmitter circuit. | 2013-11-21 |
20130308356 | INPUT RELAY ARCHITECTURE FOR RECTIFYING POWER CONVERTERS AND SUITABLE FOR AC OR DC SOURCE POWER - Power converter circuitry for converting power from a power source of any one of a number of power source types, and in which arcing at relays in the event of a shutdown is avoided. A shunt circuit is provided in inrush and protection circuitry of the power converter, the circuit including a power field-effect transistor and optionally a series-connected relay. The shunt circuit is controlled to divert current from the main relay in the event of a rectifier fault, allowing the main relay to be opened under reduced or zero current. The field-effect transistor of the shunt circuit can then be safely opened, allowing its series relay to be opened under zero current conditions. | 2013-11-21 |
20130308357 | THREE-LEVEL UNIT INVERTER SYSTEM - In aspects of the invention, each three-level inverter unit has an output current detector. The output from each detector is given to connection wires via a resistor, the connection wires connecting the inverter units. The voltage across the resistor is detected and the deviation, or increment, of the current value of the unit concerned from the average value is determined. The rising up edge of the ON pulses for the IGBT to be controlled is delayed, corresponding to the magnitude of the deviation. Thus, the output current is balanced between the inverter units. | 2013-11-21 |
20130308358 | POWER CONVERSION APPARATUS - According to one embodiment, a controller determines the polarity of the input voltage detected by an input voltage detector. Then, when the polarity of the input voltage is positive, the first switch is subject to pulse driving, and when the polarity of the input voltage is negative, the second switch is subject to pulse driving, where the pulse driving is carried out at an on/off timing determined on the basis of the respective detection outputs of an input voltage detector, an input current detector, an output voltage detector, and an output current detector. | 2013-11-21 |
20130308359 | SWITCHING POWER SUPPLY DEVICE - In some aspects of the invention, a zero current detecting circuit of a switching power supply device detects a gradient of the current flowing in an inductor in the OFF state of the switching element and detects the timing at which the current through the inductor becomes zero corresponding to the detected gradient of the inductor current. Specifically, the zero current detecting circuit receives a signal for controlling ON/OFF driving of the switching element and a voltage signal proportional to the current flowing through the inductor in an OFF state of the switching element. The voltage signal can be compared sequentially with first and second comparison reference voltages to control charging and discharging of a capacitor. Further, the zero current detecting circuit can detect a timing at which the charging and discharging voltage of the capacitor as the timing of zero current flowing through the inductor. | 2013-11-21 |
20130308360 | POWER FACTOR CORRECTION CIRCUIT - Provided is a power factor correction circuit capable of reducing ringing sound of a transformer produced when an overshoot protection is effected. An output voltage control circuit performs constant voltage-control such that capacitor charge voltage of an output capacitor corresponds to a first voltage value, and when the capacitor charge voltage of the output capacitor reaches a second voltage value higher than the first voltage value, an overvoltage detecting unit detects the second voltage value. Further, a current limiting unit detects a value of a switching current through a switching element, and determines a limiting value of the level of the switching current. Then, the switching current is limited to the limiting value, and when an overvoltage detecting unit detects the second voltage value, a limiting value changing unit causes the current limiting unit to change the limiting value to decrease the value of the switching current. | 2013-11-21 |
20130308361 | TRANSFORMER TAP-CHANGING CIRCUIT AND METHOD OF MAKING SAME - A transformer tap-changing circuit comprises an apparatus that includes a transformer comprising a secondary winding configured to inductively couple to a primary winding when a current is passed through the primary winding from an energy source, a first rectifier coupled to the secondary winding and configured to rectify a first AC voltage from the secondary winding into a first DC voltage, and a second rectifier coupled to the secondary winding and configured to rectify a second AC voltage from the secondary winding into a second DC voltage. The apparatus also includes a DC bus coupled to the first and second rectifiers and configured to receive the first and second DC voltages therefrom, wherein the first AC voltage is higher than the second AC voltage, and wherein the first DC voltage is higher than the second DC voltage. | 2013-11-21 |
20130308362 | SWITCHED POWER CONVERTER - The present invention relates to a switched power converter comprising a base plate on which at least one heat sink is arranged. The converter further comprises at least one power transistor arranged on a side of the at least one heat sink. Further, at least one spring element is arranged to press against the power transistor arranged on a side of the at least one heat sink and an oppositely facing side of either an adjacent heat sink or a base plate end face parallel to the at least one heat sink. | 2013-11-21 |
20130308363 | THREE DIMENSIONAL NON-VOLATILE STORAGE WITH INTERLEAVED VERTICAL SELECT DEVICES ABOVE AND BELOW VERTICAL BIT LINES - A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines. | 2013-11-21 |
20130308364 | POWER UP DETECTION SYSTEM FOR A MEMORY DEVICE - A power up detection method for a memory device and a memory device are disclosed. In a first phase, a test word is read from a read-only memory (ROM) row of a memory array of the memory device, and the test word is compared to predetermined ROM row data. If the test word matches the predetermined ROM row data, a second phase may be performed. In the second phase, first user data is read from a user-programmed row of the memory array at a first time. Second user data is read from the user-programmed row of the memory array at a second time different from the first time. The first user data is compared to the second user data. Successful power up of the memory device is determined when the first user data matches the second user data. | 2013-11-21 |
20130308365 | CIRCUIT AND METHOD FOR REDUCING WRITE DISTURB IN A NON-VOLATILE MEMORY DEVICE - An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a programming cycle, all bitlines are pre-charged to a program inhibit voltage level and held at the program inhibit voltage level with current or voltage sources coupled to each of the bitlines in a precharge operation and a following programming operation. In the programming operation, a bitline connected to a memory cell to be programmed is driven to a programming level, such as VSS, while the active precharge circuit is enabled to enable programming thereof. Because the other non-selected bitlines are held at the program inhibit voltage level, they will not be inadvertently programmed when the programming voltage is supplied by the word line. | 2013-11-21 |
20130308366 | Circuit and System of Using Junction Diode as Program Selector for One-Time Programmable Devices - Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact. | 2013-11-21 |
20130308367 | STRUCTURE AND METHOD FOR FORMING CONDUCTIVE PATH IN RESISTIVE RANDOM-ACCESS MEMORY DEVICE - An array and forming method for resistive-RAM (RRAM) devices provides for the simultaneous selection of multiple bit cells and the simultaneous forming of the RRAM resistive elements within the selected bit cells. The bit cells each include a resistive element and a transistor and are arranged vertically along vertical bit lines. The resistive elements of the bit cells are coupled to source lines that are parallel to word lines and perpendicular to the vertical bit lines. The bit lines are maintained at different biases. A high voltage is applied to one of the source lines coupled to adjacent resistive elements of bit cells disposed along more than one vertical bit line. When the associated transistors are turned on by a sufficiently high gate voltage, the desired RRAM resistive elements along one of the bit lines are formed without stressing other bit cells of the array. | 2013-11-21 |
20130308368 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs. | 2013-11-21 |
20130308369 | SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT - Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage. | 2013-11-21 |
20130308370 | MEMORY DEVICE AND SYSTEM WITH IMPROVED ERASE OPERATION - A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different. | 2013-11-21 |
20130308371 | METHOD FOR READING DATA FROM NONVOLATILE STORAGE ELEMENT, AND NONVOLATILE STORAGE DEVICE - Provided is a method for reading data from a variable resistance nonvolatile storage element, where the operation for reading data is less susceptible to a fluctuation phenomenon of resistance values in reading the data. The method includes: detecting a current value I | 2013-11-21 |
20130308372 | STORAGE DEVICE AND WRITING METHOD OF THE SAME - A storage device in which held voltage is prevented from decreasing due to feedthrough in writing data to the storage device at high voltage is provided. The storage device includes a write circuit, a bit line, a word line, a transistor, and a capacitor. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor. The other terminal of the capacitor is electrically connected to a ground. The write circuit includes an element holding write voltage and a circuit gradually decreasing voltage from the element holding write voltage. The write voltage is output from the write circuit to the word line. | 2013-11-21 |
20130308373 | Nonvolatile Latch Circuit - One embodiment of a nonvolatile latch circuit comprises a latch circuitry configurated to temporarily hold data and comprising a first output terminal, the latch circuitry is coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal, and a first nonvolatile memory element configurated to store said data and comprising a low resistance and a high resistance. The first memory element is connected in-series with a first transistor and coupled between the first output terminal and an intermediate voltage source. The resistance of the first memory element is changed by a bidirectional current running between the first output terminal and the intermediate voltage source, wherein an electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source. Other embodiments are described and shown. | 2013-11-21 |
20130308374 | CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES - A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array. | 2013-11-21 |
20130308375 | Semiconductor Integrated Circuit for Low and High Voltage Operations - A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD form a combination that is operable at the low voltage. The first circuit area uses a first portion of the combination for operating at the low voltage and the second circuit area uses a second portion of the combination for routing at the high voltage, the two metal layers in the second portion being interconnected through the IMD by via hole, for withstanding the high voltage. The first portion may comprise an array of magnetic random access memory (MRAM) devices and the second circuit area may comprise a display drive circuit. | 2013-11-21 |
20130308376 | APPARATUSES INCLUDING CURRENT COMPLIANCE CIRCUITS AND METHODS - Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form a current compliance circuit. Additional apparatus, systems, and methods are described. | 2013-11-21 |
20130308377 | Sensing Circuits And Phase Change Memory Devices Including The Same - A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current. | 2013-11-21 |
20130308378 | ELECTRIC ELEMENT - A temperature dependent electric element includes a phase change portion including at least one conductive phase change material having a predetermined phase transition temperature, a detector portion configured to detect a change in conductivity of the phase change material caused by a temperature change to a detect phase transition of the phase change material based on the detected change in conductivity of the phase change material, a temperature calibration part configured to conduct temperature calibration by adjusting a temperature at which the phase change material exhibits the phase transition detected by the detector portion based on the change in the conductivity of the phase change material to the predetermined phase transition temperature of the phase change material, and a substrate on which the phase change portion, the detector portion, and the temperature calibration part are integrally arranged. | 2013-11-21 |
20130308379 | SEMICONDUCTOR DEVICE WITH ELECTRICALLY FLOATING BODY - A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion. | 2013-11-21 |
20130308380 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND READING METHOD THEREOF - Provided are a semiconductor memory device has improved read disturbance characteristics as well as improved retention characteristics at a high temperature, and a reading method thereof. The non-volatile semiconductor memory device includes at least one bit line; and a cell string configured to be coupled with the bit line respectively, and include normal memory cells and dummy memory cells that are alternately coupled with each other, where normal data are programmed and read to and from the normal memory cells, and dummy memory cells are programmed with dummy data. | 2013-11-21 |
20130308381 | NON-VOLATILE MEMORY AND METHODS WITH SOFT-BIT READS WHILE READING HARD BITS WITH COMPENSATION FOR COUPLING - A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”. | 2013-11-21 |
20130308382 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages. | 2013-11-21 |
20130308383 | HYBRID VOLATILE AND NON-VOLATILE MEMORY DEVICE - A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice. | 2013-11-21 |
20130308384 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IMPROVING FAILURE-RELIEF EFFICIENCY - According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong. | 2013-11-21 |
20130308385 | APPARATUSES AND METHODS FOR COUPLING LOAD CURRENT TO A COMMON SOURCE - Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described. | 2013-11-21 |
20130308386 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit is configured to, during an erase operation, set a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage; set a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage, the first and second voltages being different; apply in the selected and unselected cell units a third voltage to a gate of at least one of dummy transistors in a dummy memory string; and apply a fourth voltage to a gate of another one of the dummy transistors in the dummy memory string, the fourth voltage being lower than the third voltage. | 2013-11-21 |
20130308387 | MEMORY READ APPARATUS AND METHODS - Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described. | 2013-11-21 |
20130308388 | APPARATUS AND METHOD FOR REDUCED PEAK POWER CONSUMPTION DURING COMMON OPERATION OF MULTI-NAND FLASH MEMORY DEVICES - System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption. | 2013-11-21 |
20130308389 | WORD LINE KICKING WHEN SENSING NON-VOLATILE STORAGE - Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied to one end of a selected word line during a transition from a first reference voltage to a second reference voltage. The kicking voltage may help the other end of the word line reach the second reference voltage quickly. Since the bit lines can be sensed after the selected word line has reached the target reference voltage, the time delay prior to sensing of the bit lines may be reduced. | 2013-11-21 |
20130308390 | METHOD AND APPARATUS FOR PROGRAMMING DATA IN NON-VOLATILE MEMORY DEVICE - A method and an apparatus for programming data, and a method and an apparatus for setting a data programming mode used for the same are provided. The method for programming data in a non-volatile memory device includes determining a programming mode to be used for data programming among at least two programming modes prescribing different verify voltages for cells to be programmed, based on set mode information, and programming data according to the determined programming mode. Consequently, the loss of programmed data is prevented through an SMD reflow process. | 2013-11-21 |
20130308391 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE AND NON-VOLATILE MEMORY DEVICE USING THE SAME - A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected level of the program voltage. | 2013-11-21 |
20130308392 | MEMORY DEVICE AND METHOD FOR DRIVING MEMORY DEVICE - A memory device in which one memory cell can operate in both a single-level cell mode and a multi-level cell mode includes a signal transmission path for a multi-level cell mode in which a multi-bit digital signal representing any of three or more states input to the memory circuit is converted by a D/A converter and stored in the memory cell and the stored data is read by converting a signal output from the memory cell into a multi-bit digital signal with an A/D converter and the multi-bit digital signal is output from the memory circuit, and a signal transmission path for a single-level cell mode in which a single-bit digital signal representing any of two states input to the memory circuit is directly stored in the memory cell and the signal stored in the memory cell is directly output from the memory cell. | 2013-11-21 |
20130308393 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A non-volatile memory device includes a memory cell block programmed with data, a page buffer block configured to perform a program verification operation for verifying the data on a verification target memory cell as many times as a predetermined number, and temporarily store a plurality of verification result data obtained from every program verification operation, a comparison block configured to compare the multiple verification result data, which are temporarily stored in the page buffer block, with each other to produce a comparison result, and a control block configured to determine whether a program operation is performed again on the verification target memory cell based on the comparison result. | 2013-11-21 |
20130308394 | REFRESH METHOD AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A semiconductor memory device includes an all bank select signal generation block configured to receive level signals including information on at least one bank which has been refreshed, and generate all bank select signals, in response to an all bank refresh command; and a bank block including a plurality of banks which are configured to be refreshed in response to the all bank select signals or are refreshed in response to per bank select signals which are enabled when the level signals are enabled. | 2013-11-21 |
20130308395 | DATA OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including internally generated control signals that help to ensure that buffered and amplified data from a memory cell is properly presented to a global line independent of the enable period of the internally generated enable signal EN. in the semiconductor memory device in accordance with an embodiment of the present invention, since data is outputted through the global line commonly connected to multiple banks, pre-charge signal generation units are disposed in the respective banks to prevent contention on the global line. | 2013-11-21 |
20130308396 | DRIVER FOR SEMICONDUCTOR MEMORY AND METHOD THEREOF - A driver for a semiconductor memory includes: a selection controller configured to output a target charge current select signal and a bucket charge current select signal in response to an inputted memory cell address and a target charge current value and a bucket charge current value, which are to be applied to a memory cell of the memory cell address; a current supply unit configured to supply a target charge current to the memory cell of the memory cell address in response to the target charge current select signal; and a bucket charge current supply unit configured to supply a bucket charge current to the memory cell of the memory cell address, in order to pre-charge the memory cell of the memory cell address in response to the bucket charge current select signal. | 2013-11-21 |
20130308397 | READ SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY - A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage. | 2013-11-21 |
20130308398 | MEMORY DEVICE HAVING CONTROL CIRCUITRY CONFIGURED FOR CLOCK-BASED WRITE SELF-TIME TRACKING - A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry comprises a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch. | 2013-11-21 |
20130308399 | WRITE SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY - A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell. | 2013-11-21 |
20130308400 | WRITE CONTROL DEVICE - A write control device includes a switching unit configured to selectively supply a write current in response to a driving control signal, a driving unit configured to supply a driving current to a memory cell corresponding to the write current applied through the switching unit, and an over-driving control unit coupled to an output node of the driving unit and configured to over-drive the output node in response to the driving control signal. | 2013-11-21 |
20130308401 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination. | 2013-11-21 |
20130308402 | TEST FLOW TO DETECT A LATENT LEAKY BIT OF A NON-VOLATILE MEMORY - A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level. | 2013-11-21 |
20130308403 | SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT - Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation. | 2013-11-21 |
20130308404 | CIRCUIT FOR SENSING MULTI-LEVEL CELL - A circuit for sensing a multi-level cell (MLC) comprises a first switch associated with a first read bit, a second switch associated with a second read bit, a first switch control unit to control the first switch in response to a first data bit from a counter, and a second switch control unit to control the second switch in response to a second data bit from the counter. | 2013-11-21 |
20130308405 | SEMICONDUCTOR MEMORY DEVICE CONTROLLING REFRESH CYCLE, MEMORY SYSTEM, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable. | 2013-11-21 |
20130308406 | SEMICONDUCTOR DEVICE, METHOD FOR OPERATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME - A semiconductor device includes a clock supply circuit configured to generate an internal clock by using an external clock, an internal circuit configured to operate in synchronization with the internal clock and enter a power-down mode in response to a power-down signal, and a controller configured to control an entry of the clock supply circuit into the power-down mode in response to a locking signal, which represents that the clock supply circuit has been locked, and the power-down signal. | 2013-11-21 |
20130308407 | CONTROLLING A VOLTAGE LEVEL OF AN ACCESS SIGNAL TO REDUCE ACCESS DISTURBS IN SEMICONDUCTOR MEMORIES - A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level. | 2013-11-21 |
20130308408 | INPUT BUFFER - An input buffer includes a first buffer circuit to amplify a difference between a first input signal and a second input signal; a second buffer circuit formed of a replica circuit of the first buffer circuit to generate a common mode output signal in response to the first input signal; and a detector to compare the common mode output signal with a reference output signal and to control the first and second buffer circuits according to the comparison result such that a level of the common mode output signal coincides with a level of the reference output signal. | 2013-11-21 |
20130308409 | INTEGRATED CIRCUIT DEVICE, POWER MANAGEMENT MODULE AND METHOD FOR PROVIDING POWER MANAGEMENT - An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at least one memory sub-module is redundant, and place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant. | 2013-11-21 |
20130308410 | HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY - Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example. | 2013-11-21 |
20130308411 | SLURRY DISTRIBUTOR, SYSTEM, AND METHOD FOR USING SAME - A slurry distributor includes a feed conduit and a distribution conduit in fluid communication therewith. The feed conduit includes an entry segment with a feed inlet and a feed entry outlet in fluid communication therewith and extending along a first feed flow axis. The feed conduit includes a shaped duct having a bulb portion in fluid communication with the feed entry outlet. The feed conduit includes a transition segment in fluid communication with the bulb portion and extending along a second feed flow axis in non-parallel relationship with the first feed flow axis. The bulb portion has an area of expansion with a cross-sectional flow area that is greater than a cross-sectional flow area of an adjacent area upstream from the area of expansion. The shaped duct has a convex interior surface in confronting relationship with the feed entry outlet of the entry segment. | 2013-11-21 |
20130308412 | DEVICE FOR THE CONTINUOUS TREATMENT OF AT LEAST ONE RAW MATERIAL, TREATMENT INSTALLATION AND USE OF SUCH A DEVICE - The continuous treatment device ( | 2013-11-21 |
20130308413 | MEANS AND METHOD FOR STIRRING LIQUIDS IN LONG THIN CONTAINERS - Provided is a thermostat with reduced temperature difference within the tank when a solution is being heat-treated. Stirring guides ( | 2013-11-21 |
20130308414 | Automatic Flow Control in Mixing Fracturing Gel - A system for mixing fracturing gel includes a dry gel mixing chamber having a bladed impeller carried to rotate in the mixing chamber. The mixing chamber has a dry gel inlet and hydrating fluid inlet. A valve is fluidically coupled to the hydrating fluid inlet to automatically maintain a specified flow condition of hydrating fluid into the mixing chamber over multiple different values of the flow condition to the hydrating fluid inlet. | 2013-11-21 |
20130308415 | VALVE SWITCH MODULATION FOR REDUCING ERRORS DUE TO OSCILLATIONS OF THE INLET FLUID OF A PUMP SYSTEM - Described is a method of reducing liquid composition errors in a low-pressure mixing pump system. Packets representing the switching intervals of each component of the desired fluid mixture are provided to an intake of the mixing pump system. For each packet, a switching time associated with at least one of the components in the packet is modulated. Modulated switching times are based on time offsets that are specifically selected according to the undesirable frequency characteristic of an intake response of the mixing pump system. The average of the volumes contributed by the packets thus modulated is equal to a component volume that achieves a desired proportion of the component in the output flow of the mixing pump system. Modulated switching times enable the reduction or elimination of composition error in the output flow of the mixing pump system. | 2013-11-21 |
20130308416 | SYSTEM FOR USE IN BONE CEMENT PREPARATION AND DELIVERY - A system for use in combining two part preparations, such as bone cement, can include a chamber for intermixing liquid and powder components, a container, a vacuum channel, and a filter. The mixing chamber can be configured to hold a non-liquid, polymer powder component of a bone cement. The container can be configured to hold a liquid component of the bone cement. The vacuum channel can direct a partial vacuum to draw the liquid component from the container into the non-liquid component in the mixing chamber to intermix the components and to thereby provide a settable bone cement. | 2013-11-21 |
20130308417 | BLENDER CONTAINER AND COVER - A container ( | 2013-11-21 |
20130308418 | MIXING OF THE CONTENT OF A FLEXIBLE CONTAINER FOR BIOPHARMACEUTICAL USE - A receptacle ( | 2013-11-21 |
20130308419 | ULTRASONIC NON-DESTRUCTIVE EVALUATION METHODS FOR FRICTION-WELDED BLISKS - The disclosed embodiments generally relate to non-destructive evaluation methods. More particularly, the disclosed embodiments relate to ultrasonic non-destructive evaluation methods for the evaluation of friction welded bladed discs (“blisks”). In an embodiment, a method for non-destructive evaluation of a bladed disc structure includes identifying a region of interest on the bladed disc structure; positioning an ultrasonic transducer and receiver in the region of interest; scanning the region of interest using the ultrasonic transducer and receiver to produce a scan image; and comparing the scan image against a reference image to determine the presence of an anomaly in the region of interest. | 2013-11-21 |
20130308420 | METHOD AND APPARATUS FOR PRE-STACK DEGHOSTING OF SEISMIC DATA - A method for deghosting seismic data collected with a seismic system, the seismic data being related to a subsurface of a body of water. The method includes receiving the seismic data recorded by detectors distributed along a variable-depth profile; calculating migrated (d | 2013-11-21 |
20130308421 | SEISMIC CABLE WITH ADJUSTABLE BUOYANCY - A method and apparatus for a seismic cable is described. In one embodiment, a method for performing a seismic survey in a water column is described. The method comprises providing a length of flexible cable from a cable storage device disposed on a vessel to a cable handling device adjacent the cable storage device. The flexible cable comprises a specific gravity that is greater than a specific gravity of water in the water column. The method further comprises routing the flexible cable to pass adjacent a workstation disposed on the vessel, deploying a free end of the flexible cable into the water column, attaching at least one of a plurality of seismic sensor units to the cable as the cable passes the workstation, and controlling the motion of the vessel and the rotational speed of the cable handling device to allow the flexible cable to rest on the bottom of the water column. | 2013-11-21 |
20130308422 | CONSTANT ENERGY DISPLACEMENTS - An electric sweep type seismic vibrator source of the type used in seismic prospecting for hydrocarbons is provided. In one example, the source uses an engine and generator combination to create electric power for all systems on the source such as driving a frame of linear electric motors that direct a rod or piston to contact the ground in a recurring fashion along with driving the source from location to location through a survey area. A foot is arranged on the bottom end of the rod or piston for contact with the ground and by engaging the grid of motors to push down against the ground in a rapid progression, acoustic energy is created and delivered into the ground for geophones to sense and record. | 2013-11-21 |
20130308423 | ROBUST STACKED SLIP-SWEEP METHOD AND SYSTEM - A method for processing seismic data including contiguous-sweep records corresponding to rotated sweep segments includes attenuating harmonics and generating stacked traces, each stacked trace being a weighted sum of traces corresponding to same location in the subsurface, based on seismic data from different seismic receivers, following plural shots at plural locations. | 2013-11-21 |
20130308424 | Method of Generating and Characterizing a Seismic Signal in a Drill Bit - A method, apparatus and system for estimating a parameter of interest downhole is disclosed. An acoustic source signal is generated at a drill bit downhole. The generated acoustic source signal is received at a source sensor at the drill bit. A character of the generated acoustic source signal is determined from the received signal at the source sensor. The characterized source signal is used to estimate the downhole parameter of interest. | 2013-11-21 |