47th week of 2008 patent applcation highlights part 63 |
Patent application number | Title | Published |
20080288650 | Method for the Energy-Saving and Timely Transmission of Event Messages - A method and a system-on-a-chip for the guaranteed and energy-saving transmission of event messages is provided in a distributed computer system consisting of a plurality of node computers, which are interconnected by a time-controlled communications system. The node computers establish a common time base of known precision and periodically exchange messages at a prior defined points in time. A guaranteed event message is sent in a sporadic time-controlled message (SZN). The sporadic time-controlled message transports the guaranteed event message and is sent only if the content of this sporadic time-controlled message has been changed since the last time it was sent. The receiver stores the content of an incoming sporadic time-controlled message in a queue until the receiving process has read this content exactly once in a consuming manner. | 2008-11-20 |
20080288651 | Consistent Policy Control of Objects in a Service Oriented Architecture - A method for the consistent control of policies assigned to objects of a service oriented architecture is disclosed. Each policy may include one or more assertions, and the method may include identifying one or more operational dependencies between at least two SOA objects, analyzing the assigned policies of the at least two SOA objects to determine any inconsistency, and issuing a warning to a user if an inconsistency has been determined. | 2008-11-20 |
20080288652 | NETWORK CORE ACCESS ARCHITECTURE - The proposed architecture is integrated in a generic System on Chip (SoC) and can include or consist of an expanded network interface and an infrastructure for accessing Intellectual Property (IP) cores in the system. The architecture enables the system on chip to communicate with a user workstation connected to a communication network. The invention can be used as a simplified network interface for data exchange, which does not require embedded processors and respective software. The invention can be used to temporarily replace the normal data input and output of an IP core with stimuli and responses used for a variety of purposes. | 2008-11-20 |
20080288653 | Computerized, Copy-Detection and Discrimination Apparatus and Method - An engine identifying segments or portions of one source material or source file common to or found in another source material or file. The engine may receive a first data stream in binary form as well as a second stream in binary form. The engine may include a data stream processor or pre-processor programed to translate the first and second data streams to generate respective first and second processed data streams. The commonality between the first and second processed data streams may be greater than the commonality between the first and second data streams themselves. Also, a comparator may be programmed to compare the first and second process data streams and identify binary segments found in both the first and second processed data streams. | 2008-11-20 |
20080288654 | Node and method to provide and keep real-time up-to-date data in a distributed hash table - A node and method are provided that create a finger table at the node, subscribe to changes in a network address of at least one other node included in the finger table, receive at least one notification including an identifier and a network address of the at least one other node, and update the finger table with a new network address of the at least one other node received in the at least one notification. The node and method also create a reverse finger table at a node, receive subscriptions to changes in a network address of the node from another node, store the network address of the other node in the reverse finger table, and when the network address of the node changes, send a notification of a new network address from the node to the other node in the reverse finger table. | 2008-11-20 |
20080288655 | Subscription Propagation in a High Performance Highly Available Content based Publish Subscribe System - The present invention is directed to a publish/subscribe system containing a plurality of brokers, a plurality of subscribers and plurality of brokers including publisher connecting brokers, intermediate brokers and subscriber connecting brokers. Subscriptions are introduced into the system by the subscribers through associated subscription brokers. New subscriptions are aggregated, assigned a virtual start time and propagated through the system toward the publishers. Each broker maintains subscription information in the form of a directed acyclic graph and a broker vector. Messages are published through the system by the publishers through their associated publisher connecting brokers. Each message is assigned a message vector associating subscriptions to that message. The published messages are routed through the brokers toward the subscribers in accordance with comparisons of message brokers and vector brokers conducted at each broker. | 2008-11-20 |
20080288656 | SYSTEM, METHOD AND PROGRAM PRODUCT TO ROUTE MESSAGE PACKETS - A system, method and computer program for routing a response packet in a session along a path similar to a request packet's outbound path that includes a firewall and a first router. The firewall receives the request packet and forwards the request packet to the first router. Upon receipt of the request packet, the firewall and first router broadcast session information to their respective sets of directly connected devices. A second router receives the response packet. After determining that the second router was not in the outbound path according to the second router's session table, the second router forwards the response packet to the device (i.e., the firewall or the first router) that is most upstream in the outbound path among the outbound path devices that are available and connected to the second router. | 2008-11-20 |
20080288657 | Information delivery system, reregistration message sending method, node device, and recording medium recording node processing program - In an information delivery system including a plurality of node devices mutually communicable through a network,
| 2008-11-20 |
20080288658 | SYSTEMS AND METHODS OF NETWORK OPERATION AND INFORMATION PROCESSING, INCLUDING USE OF UNIQUE/ANONYMOUS IDENTIFIERS THROUGHOUT ALL STAGES OF INFORMATION PROCESSING AND DELIVERY - Systems and methods are disclosed for network operation and information processing involving engaging users of a network. In one exemplary embodiment, there is provided a method of engaging users of a public-access network. Moreover, the method includes associating a processing component with the public-access network; transmitting a request for authorization to use the public-access network, including transmission of a specific identifier associated with the user; transmitting first data including data determined by processing software as a function of the specific identifier; and opening up a connection to the network for the user. In one or more further embodiments, the specific identifier may include or be a function of a processing component ID or the MAC address of a device associated with the user. Other exemplary embodiments may include building profiles of users who access the network based on information collected. | 2008-11-20 |
20080288659 | MAINTAINING CONSISTENCY WITHIN A FEDERATION INFRASTRUCTURE - The present invention extends to methods, systems, and computer program products for a joining node to join a ring of nodes within a rendezvous federation. Embodiments include detecting a neighborhood of nodes on the ring of nodes. The joining node indicates its intent to take id-space ownership for a portion of the id-space between the joining node and a selected immediately adjacent node. The joining node indicates an intent to monitor the selected node. The joining node receives three indications, the first indicating acceptance of the joining node's intent to take id-space ownership for a portion of the id-space between the joining node and the selected node, the second indicating acceptance of the joining node's intent to monitor the selected node, the third indicating the first selected node's intent to monitor the joining node. The joining node indicates acceptance of the selected node's intent to monitor the joining node. | 2008-11-20 |
20080288660 | SERIAL PORT INITIALIZATION IN STORAGE SYSTEM CONTROLLERS - A boot menu is provided for manual setting of serial port parameters. A serial console mode menu allows an operator to set serial port parameter values. After the user selects the serial port parameters, when the controller continues with the boot process, the serial port is initialized with the newly selected parameters. A mechanism is also provided for manual setting of serial port parameters through an administrative management window at the host. In addition, an adaptive baud rate negotiation mechanism using the Universal Asynchronous Receiver Transmitter (UART) registers in the serial port is provided. The adaptive baud rate negotiation is based on the return characters received from a break character from the serial console. The mechanism uses a look-up table for the baud rate versus the bit pattern that is received. The mechanism then sets the baud rate based on the look-up table values. | 2008-11-20 |
20080288661 | METHOD AND SYSTEM TO MAP VIRTUAL I/O DEVICES AND RESOURCES TO A STANDARD I/O BUS - A method and system to map virtual I/O devices and resources to a standard I/O bus is provided. The system, in one example embodiment, comprises a virtual device detector, a resource allocator, and an activation module. The virtual device detector may be configured to detect an indication of a virtual Peripheral Component Interconnect Express (PCIe) device having an associated template. The resource allocator may allocate, based on the template, a plurality of resources required for the virtual PCIe device from a pool of available resources. The activation module may generate a set of entries in a resource mapping table, the set of entries corresponding to the allocated resources and defining the virtual PCIe device. | 2008-11-20 |
20080288662 | Identification address configuration circuit and method without use of dedicated address pins - An identification address of a sensor interface device is configured in response to the order of connection of first (DXP | 2008-11-20 |
20080288663 | METHOD AND SYSTEM FOR HANDLING ERRORS - In accordance with a specific aspect of the present disclosure, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized and written to an output buffer location. | 2008-11-20 |
20080288664 | SWITCHING APPARATUS AND METHOD FOR LINK INITIALIZATION IN A SHARED I/O ENVIRONMENT - An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality of I/O ports is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains. The link is initialized in a manner that is transparent to the plurality of operating system domains. | 2008-11-20 |
20080288665 | Service Access Method And Apparatus - The invention may be embodied as a method of selecting a service and inputting information to that service. In one such method, an input device having keys is provided. When such a key is pressed and released quickly, the user indicates a desire to enter a symbol on the key in order to enter symbols of an entry string. In addition, one or more of the keys may also be used to identify a service and also supply that service with the entry string. For example, by pressing and holding such a key, the entry string may be delimited and then sent to a service corresponding to the pressed key. In this manner, a single key press may be used to both delimit an entry string and also send the entry string to the service. The service may use the delimited entry string to retrieve information, which is then supplied to the input device. | 2008-11-20 |
20080288666 | Embedded System Development Platform - A modular development platform is described which enables creation of reliable, compact, physically robust and power efficient embedded device prototypes. The platform consists of a base module which holds the processor and one or more peripheral modules each having a peripheral device and an interface element. The modules can be electrically and physically connected together. The base module communicates with peripheral modules using packets of data with an addressing portion which identifies the peripheral module that is the intended recipient of the data packet. | 2008-11-20 |
20080288667 | Numerical controller with function to add display screens - A numerical controller having a function to add display screens. The numerical controller comprises a display unit, a memory device stored with a display software which causes the display unit to display a standard display screen, and a detachable external memory device stored with additional display screen data to be displayed as an additional display screen on the display unit. The display software has functions to determine whether or not the external memory device is attached to the numerical controller, determine whether or not the external memory device is stored with the additional display screen data, and select and display the standard display screen and/or the additional display screen on the display unit based on results of the determination. | 2008-11-20 |
20080288668 | COMMUNICATION METHOD - The disclosure relates to a method and system for communication between modular devices for measurement, closed-loop and open-loop control. It is proposed that the communication-carrying bus physics and the USB protocol be used for data transmission between modules. | 2008-11-20 |
20080288669 | MEMORY CARD ADAPTER AND METHOD FOR STORING DATA ON MEMORY CARD - An adapter for storing data includes a male connector, a first slot, a second slot, a switch circuit, and a controller. The male connector is used for connecting to an electronic device. The first slot is used for connecting a first memory card. The second slot is used for connecting a second memory card. The switch circuit is used for selectively connecting the male connector with the first slot and the second slot. The controller is used for detecting states of the first memory card and the second memory card and controlling the switch circuit to connect the male connector with one of the first slot and the second slot based on detected states. | 2008-11-20 |
20080288670 | USE OF VIRTUAL TARGETS FOR PREPARING AND SERVICING REQUESTS FOR SERVER-FREE DATA TRANSFER OPERATIONS - A system and method are disclosed for utilizing virtual targets and abstract copy orders in preparing and servicing requests for server-free data transfer operations in a data storage network. The abstract copy orders represent data transfers between virtual targets and real devices. They allow source target copy orders to be prepared separately from destination target copy orders. The abstract copy orders may then be converted into concrete copy orders involving only real device targets for execution by a data mover that implements the server free data transfer operations. | 2008-11-20 |
20080288671 | Virtualization by multipath management software for a plurality of storage volumes - A path management method for a computer system which includes first and second storage controllers and a host computer, the first controller providing a first volume to the host computer, the second controller providing a second volume to the host computer, the host computer including one or more task application units and a path management unit, the path management method including: setting, by the path management unit, a plurality of first paths and a plurality of second paths; providing, by the path management unit, the first and second volumes as third volume to the task application unit; and transmitting, by the path management unit, through the first path write request for writing data in the third volume which is issued from the task application unit. | 2008-11-20 |
20080288672 | INFORMATION PROCESSING SYSTEM, INFORMATION TERMINAL AND SERVER APPARATUS - An information processing system includes an information terminal, and a server apparatus connected with the information terminal in a data communicable manner. The server apparatus includes a screen data generation unit configured to generate screen data of a screen to be displayed on an operation screen of the information terminal in response to one of data transmitted from the information terminal and internal processing of the server apparatus and to transmit the screen data to the information terminal. The information terminal includes an operation input unit configured to perform an operation input regarding the information terminal, an operation screen control unit configured to update display content on the operation screen of the information terminal on the basis of the screen data to be transmitted from the server apparatus, and a storage unit configured to store the display content displayed on the operation screen in response to a first operation input. | 2008-11-20 |
20080288673 | System-on-Chip Apparatus with Time Shareable Memory and Method for Operating Such an Apparatus - The invention relates to a system-on-chip apparatus ( | 2008-11-20 |
20080288674 | Storage system and storage device - A storage system includes: a plurality of data input and output parts through; a data storing part that stores the data inputted and outputted through the plurality of data input and output parts; a range information storing part that stores range information; first control part controlling the data storing part to read and write the data in accordance with the stored range information, and that rewrites the stored range information to predetermined range information in a case where a prescribed signal is inputted from the data input and output part; and a plurality of second control parts that are provided correspondingly to the plurality of data input and output parts to input and output the data, and that input the prescribed signal to the data input and output parts in a prescribed case. | 2008-11-20 |
20080288675 | HOST DEVICE, INFORMATION PROCESSOR, ELECTRONIC APPARATUS, PROGRAM, AND METHOD FOR CONTROLLING READING - A host device for controlling a storage device controller to access a storage device includes: a command issue controller controlling an issue of a command for allowing the storage device controller to access the storage device; a response detector for detecting a reception of a response from the storage device corresponding to the command; and a buffer data controller controlling reading and writing of a buffer of the storage device controller. The buffer stores one of reading data and writing data of the storage device. The buffer data controller controls one of the reading and the writing at least once in a predetermined data size unit corresponding to the command after the command issue controller issues the command. | 2008-11-20 |
20080288676 | DUAL PORT USB INTERFACE - A dual port interface is disclosed comprising a host port and a peripheral port. The host port and the peripheral port are defined using predetermined signals. In a preferred embodiment the dual port interface is used in a network comprising one or more dual port USB (DPUSB) connections. By use of the DPUSB interface, both one-to-one and one-to-many network topologies can be created. Use of the DPUSB interface also provides the opportunity of new types of devices such as memory cards and cables that will greatly increase the ease of use of many intelligent electronic devices such as cameras and PDAs. | 2008-11-20 |
20080288677 | KVM switch system with a simplified external controller - A KVM switch system with external control functionality is described. A KVM switch is able to be controlled from an external device. The external device can either include a single button dedicated to controlling the desktop KVM switch or indicate a state of the KVM switch. The external device can be connected to the desktop KVM switch through a plurality of communication media. The external device can be small in size and attached to an object on a user's desktop. | 2008-11-20 |
20080288678 | STORAGE SYSTEM - Data transfer is performed to and from a host computer using a first block as the minimum unit. Data transfer is performed to and from a storage area using a second block as the minimum unit. A second block set of the storage area stores data obtained from performing data conversion processes that change the size of the data itself, with a first block set as the unit. Here a correspondence relationship is generated between the first block set and the second block set. In response to a read request from the host computer, a second block set, which corresponds to the first block set that includes the first block that is requested, is read, a reverse-conversion process is performed, and the data is sent to the host computer. | 2008-11-20 |
20080288679 | Resetting a Hypertransport Link in a Blade Server - Methods, apparatus, and computer program products are described for resetting a HyperTransport link in a blade server, including reassigning, by a blade management module, a gate signal from enabling a transceiver to signaling a HyperTransport link reset; sending, by the blade management module to a reset sync module on an out-of-band bus, the gate signal; and in response to the gate signal, sending, by the reset sync module to the blade processor, HyperTransport reset signals. The HyperTransport link includes a bidirectional, serial/parallel, high-bandwidth, low-latency, point to point data communications link. The blade server includes the blade processor, the reset sync module, and the baseboard management controller. The blade server is installed in the blade center. The blade center includes the blade management module. The blade management module is coupled to the baseboard management controller by the blade communication bus. | 2008-11-20 |
20080288680 | COMMUNICATION ARRANGEMENT - The disclosure relates to an arrangement and method for communication between modular devices for measurement, closed-loop and open-loop control which are connected to one another via a backplane. It is proposed that two modules of the device in each case be connected to one another via a serial point-to-point connection. Modules with a coupling element are connected to a plurality of other modules. | 2008-11-20 |
20080288681 | Devices with multiple functions, and methods for switching functions thereof - Devices with multiple functions and methods for switching functions thereof are provided. The device comprises a plurality of hardware components, a plurality of functional modules, an input device, and a processing module. Each functional module corresponds to one of the functional connecting configurations for the hardware components. The processing module executes one of the functional modules and drives the hardware components according to the functional connecting configuration corresponding to the executed functional module. The processing module determines whether to generate a switch command according to an input command received by the input device. When the switch command is generated, the processing module directly terminates the functional module being currently executed and adjusts to execute another functional module, and drives the hardware components according to the functional connecting configuration corresponding to the functional module to be executed. | 2008-11-20 |
20080288682 | Database Contention and Deadlock Detection and Reduction Within Application Servers - A method in a data processing system for detecting and reducing database contention and deadlock caused from within an application server. A determination is made as to whether a set of parameters in a statistical model indicates contention. If the set of parameters in the statistical model indicates contention, an application server administrator is notified of the contention and the number of threads in an application server pool is reduced. If the set of parameters in the statistical model indicates contention is reduced, the number of threads in the application server pool is increased. | 2008-11-20 |
20080288683 | Method and system for managing a plurality of I/O interfaces with an array of multicore processor resources in a semiconductor chip - The present invention relates to a method and system for managing I/O interfaces with an array of multicore processor resources in a semiconductor chip. The I/O interfaces are connected to the processor resources through an I/O shim. An I/O interface sends a dataframe to the I/O shim. The I/O interface packetizes data to form the dataframe, based on an I/O protocol. The dataframe includes a header and the data. The I/O shim identifies a command corresponding to the dataframe by using one or more of the processor resources. The command includes a set of tasks. Subsequently, the set of tasks is executed on the data. | 2008-11-20 |
20080288684 | DESIGN STRUCTURE FOR AN ADDRESS TRANSLATION DEVICE - An design structure to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The design structure includes an apparatus, which includes a detection module to detect an incoming address on the I2C bus, a translation module to translate the incoming address to an outgoing address, and a communication module to communicate data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, address conflicts between commonly addressed slave devices can be avoided while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts. | 2008-11-20 |
20080288685 | SHARED SIMULTANEOUSLY-CONNECTED DRIVES - Local drive presence is provided for local and remote drives by maintaining a plurality of uninterrupted protocol connections between a plurality of I/O controllers and a plurality of device interfaces through which peripheral bus commands are transmitted. Preferably, the I/O controllers are each housed in a separate server blade and provide each blade with access to the local and remote drives. At each of the device interfaces, rather than attaching an actual storage device, peripheral bus commands received at the device interfaces are serialized and conditionally passed or suppressed to and from the shared drive which is shared amongst the plurality of uninterrupted protocol connections. Preferably, the plurality of uninterrupted protocol connections is maintained such that the shared drives can be simultaneously shared. In one embodiment, the local drives are provided in a media tray which is shared amongst a plurality blades. | 2008-11-20 |
20080288686 | MAIN DEVICE REDUNDANCY CONFIGURATION AND MAIN DEVICE REPLACING METHOD - A networking system architecture includes a plurality of main devices, one of the main devices acts as a master main device, and the other main devices act as slave main devices. If the master main device malfunctions, one of the slave main devices substitutes for the master main device to act as a new master main device. Priorities are set to the main devices, respectively If a current master main device malfunctions, the current master main device may be replaced by a new master main device having the highest priority among the other main devices. | 2008-11-20 |
20080288687 | INFORMATION PROCESSING DEVICE AND PROCESSOR - A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range. | 2008-11-20 |
20080288688 | Bus system and method of arbitrating the same - A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one transfer mode selection circuit. The at least one bus master device may generate a burst cycle control signal, a transfer start signal and a bus control request signal for requesting control of the bus, and may be activated in response to a bus control grant signal, so as to exchange data via the bus. The bus arbiter may generate the bus control grant signal in response to the bus control request signal and provide the bus control grant signal to the bus master device. The at least one transfer mode selection circuit may convert a burst mode into a single mode to generate a selection signal, when the bus control grant signal is deactivated before a burst mode operation is completed. | 2008-11-20 |
20080288689 | Opportunistic granting arbitration scheme for fixed priority grant counter based arbiter - In one embodiment, an arbiter may provide for opportunistic granting of one or more grants to a requestor that has no available fixed grants remaining in a given arbitration round. In one embodiment, a method may detect that a target resource to be accessed by a requestor with a valid grant count is unavailable during an arbitration round, and opportunistically grant an access grant to another requestor to access a different target resource for a slot of the round. Other embodiments are described and claimed. | 2008-11-20 |
20080288690 | Image processing controller and image forming apparatus - An image processing controller performs transmission and processing of image data by connecting an engine and a CPU connected via a chipset. A first controller controls communication with the chipset via a first PCI-Express I/F. A second controller controls communication with the engine when it is connected via a second PCI-Express I/F. A third controller controls communication with the engine when it is connected via a PCI I/F. The first controller receives, on behalf of the engine, an access from the CPU to the engine and inhibits a reference by the CPU to a resource connected to the image processing controller. | 2008-11-20 |
20080288691 | METHOD AND APPARATUS OF LOCK TRANSACTIONS PROCESSING IN SINGLE OR MULTI-CORE PROCESSOR - The present invention relates to a method and apparatus of lock transactions processing in a single or multi-core processor. An embodiment of the present invention is a processor with one or more processing cores, an address arbitrator, where one or more processing cores are configured to submit a lock transaction request to the address arbitrator corresponding to a specific instruction in response to the execution of the specific instruction. The lock transaction request includes a lock variable address asserted on an address bus. The processor further includes a lock controller for performing lock transaction processing in response to the lock transaction request, and notifying processing result to the processing core from which the lock transaction request was sent. The processor further includes a switching device, coupled to the address arbitrator and the lock controller, for identifying the lock transaction request and notifying the lock transaction request to the lock controller. | 2008-11-20 |
20080288692 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MICROCOMPUTER - It is intended to improve the efficiency of request retransmission. A high-speed serial interface block is provided which enables split-transaction communication performed through the issuing of a response from a completer to a request issued by a requester. The high-speed serial interface block mentioned above is provided with a reception butter for retrieving received data and with a control unit for causing execution of a process which is performed in the case where there is no response from the completer mentioned above within a predetermined time when the reception buffer mentioned above has overflown. When the reception buffer mentioned above has overflown, a process of issuing a time out even within a prescribed time for time-out determination is allowed to improve the efficiency of request retransmission. | 2008-11-20 |
20080288693 | Parallel Processing Device and Exclusive Control Method - To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P | 2008-11-20 |
20080288694 | METHOD FOR DYNAMICALLY ARRANGING INTERRUPT PINS - A method for dynamically arranging interrupt pins is provided, which is suitable for arranging a plurality of interrupt pins of a control chip. In this method, a number of interrupts sent from each of a plurality of device paths in a unit time is detected. The device paths are sorted according to the interrupt numbers thereof. Then, from the one in the head of the sequence, the devices paths are arranged to the interrupt pins. Herein, when arranging a device path, an interrupt checking number required to check the device path sending the interrupt every time an interrupt is produced in each of the interrupt pins is calculated. Then, when arranging the next device path, the device path is arranged to the interrupt pin with the least interrupt checking number. | 2008-11-20 |
20080288695 | DYNAMIC CREATION OF LOW-LEVEL INTERFACES - In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions. | 2008-11-20 |
20080288696 | DEVICE WITH A PROCESSOR AND A PERIPHERAL UNIT AND METHOD FOR GENERATING AN ACKNOWLEDGMENT SIGNAL - A device is provided that includes a processor, a peripheral unit, and a first logic, and to a method for generating an acknowledgment signal. The processor is clocked by a processor clock signal, which runs asynchronously to the peripheral clock signal, by which the peripheral unit is clocked. The peripheral unit sends an interrupt request synchronously to the peripheral clock signal to the processor, which thereupon is woken up from its idle state, to process the interrupt request in its working state. After the processing or during the processing of the interrupt request, the processor generates an acknowledgment signal synchronous to the processor clock signal. The first logic generates an acknowledgment signal, which is synchronous to the peripheral clock signal and by which the peripheral unit is informed about the processed interrupt request, from the acknowledgment signal synchronous to the processor clock signal. | 2008-11-20 |
20080288697 | Memory module having a cover pivotally coupled thereto - A storage device has a memory module and a cover pivotally coupled to a housing of the memory module. In one such storage device, the memory module and cover can pivot with respect to each other to configure the storage device in a first configuration or in each of one or more second configurations. In the first configuration, the cover substantially encloses a connector of the memory module that extends from the housing. In one or more second configurations, the connector is entirely exposed. For one embodiment, opposing light-transmission elements may pass through the cover and extend into an interior of the housing. | 2008-11-20 |
20080288698 | CARD READER CONTROLLING APPARATUS BASED ON SECURE DIGITAL PROTOCOL - The proposed invention discloses a card reader controlling apparatus based on Secure Digital (SD) protocol, which comprises a high-speed bus interface, at least one SD host, at least one SD connection interface and SDIO connection interface (SD/SDIO interface), at least one bridge, and at least one other specific memory card connecting interface. The card reader controlling apparatus according to the proposed invention is capable of directly accessing data from/to an input/output device compatible with the SDIO connection interface (e.g. an SD card) or one other specific memory card via the high-speed bus interface. Thus, multiple format conversions performed by other peripheral bus interfaces (such as an USB interface) as the prior art can be by-passed or eliminated. | 2008-11-20 |
20080288699 | METHOD FOR CONTROLLING THE EXECUTION OF AN APPLET FOR AN IC CARD - A method for controlling the execution of an applet for an IC Card including a java card platform, includes a phase for downloading the applet inside the IC Card, a phase for executing the applet through the java card platform and a phase for storing an identification platform number inside a memory portion of the IC Card. The phase for executing the applet has a first step for detecting the identification platform number to perform the phase for executing the applet with or without restrictions, respectively if the identification platform number is not or is detected by the step for detecting. The applet is a java card applet or a SIM toolkit applet. | 2008-11-20 |
20080288700 | Removable computer with mass storage - The present invention provides a detachable add-on card unit to a host system that combines mass storage capability and a processor on the same card. The card can receive data from the host, process the data, and store it in processed form, as well as the reverse process of retrieving stored data, processing it, and supplying it to the host. The non-volatile mass storage memory may contain program storage as well as card system data and user data. The end user of the card can program applications into the program storage. The combination of mass storage and a processor also adds to the capabilities of the on-card processor, allowing the card to store and execute programs. The present invention is able to provide a programmable add-on card unit to a host system. A number of applications can be stored in the card's mass storage and loaded as needed by the on-card micro-controller. | 2008-11-20 |
20080288701 | Method for protecting a connection interface in a computer-docking assembly - A method for protecting a connection interface in a computer-docking assembly comprising rotating at least partially a computer-support assembly about an arm assembly while moving the computer-support assembly toward a connection interface of the base station and while the arm assembly is at least partially rotating about the base station. The method for protecting additionally comprises aligning generally the computer-support assembly with the connection interface of the base station to posture the computer-support assembly in proximity to the interface connection of the base station for protecting the interface connection. A method for engaging a portable computer including moving away from a base station at least one engager member bound to a computer-support assembly. The base station and the computer-support assembly are rotatably connected to an arm assembly. The method for engaging additionally includes moving the computer-support assembly away from the base station while rotating about the arm assembly, and positioning the computer-support assembly in a posture for receiving a portable computer. The method for engaging further additionally includes disposing a portable computer in the computer-support assembly, and contacting at least one surface of the portable computer. | 2008-11-20 |
20080288702 | METHOD AND SYSTEM FOR DOCKING A LAPTOP WITH ETHERNET A/V BRIDGING TO GUARANTEE SERVICES - Methods and systems for docking a laptop with Ethernet A/V bridging to guarantee services are disclosed and may include interfacing a portable computing device with a docking station using an Ethernet interface, and utilizing audio/video (AV) bridging for communicating data between the portable computing device and one or more devices coupled to the docking station. AV bridging may be utilized based on latency requirements of the data communication. The interfacing may include directly coupling an Ethernet port of the docking station to an Ethernet port of the portable computing device. Alternatively, the interfacing may include coupling an Ethernet port of the docking station to an Ethernet port of the portable computing device via an Ethernet cable. The portable computing device may be powered via the Ethernet interface, and may utilize power over Ethernet protocol. The docking station may include a passive or active docking station. | 2008-11-20 |
20080288703 | Method and Apparatus of Providing Power to an External Attachment Device via a Computing Device - A method and apparatus of providing power to an external Serial Advanced Technology Attachment (SATA) device via a computing device are described here. One embodiment includes, transmitting data to a plurality of devices via at least one port of a first type of a computing device, and providing power to the plurality of devices via at least one port of a second type of the computing device; wherein the plurality of devices comprises one or more of a disk controller and an external Serial Advanced Technology Attachment device. The at least one port of the first type of the computing device is an external Serial Advanced Technology Attachment port and the at least one port of the second type of the computing device is a Universal Serial Bus port. In one embodiment, the disk controller comprises at least one parallel advanced technology attachment port. | 2008-11-20 |
20080288704 | METHOD AND SYSTEM FOR UNIVERSAL SERIAL BUS (USB) OVER A/V BRIDGING AND A/V BRIDGING EXTENSIONS - Aspects of a system for universal serial bus (USB) over ANV bridging and ANV bridging extensions may include a LAN subsystem that enables reception of signals from a peripheral device coupled to a computing device via a USB interface. The LAN subsystem may enable the generation of payload data based on the received signals. The LAN subsystem may enable transmission of the generated payload data via a network based on a traffic class designation. The generated payload data may be encapsulated within an outgoing PDU, which may include an Ethernet frame and/or an IP packet. The outgoing encapsulating PDU may contain the traffic class designation. The LAN subsystem may also generate a time stamp for the encapsulating PDU. The LAN subsystem may enable indication that the outgoing encapsulating PDU encapsulates the generated payload data based on one or more data type identifiers, which include an EtherType and an EtherTypeSubType. | 2008-11-20 |
20080288705 | Wireless Peripheral Interconnect Bus - A wireless peripheral interconnect bus that enables the transferring of data at a high rate over wireless medium. The bus further enables the wireless connection of peripheral components to a computing device, thereby providing a distributed computing device. The bus implements a layered protocol to provide a reliable link over the wireless medium. The wireless peripheral interconnect bus may be implemented as at least one of a peripheral component interconnect PCI Express™ (PCIe) bus, a PCIe second generation, or a PCIe third generation. | 2008-11-20 |
20080288706 | MODULAR AUTOMATION DEVICE - The disclosure relates to a device, arrangement and method for communication between modular devices for measurement, closed-loop control and open-loop control, which are connected to one another via a backplane. It is proposed that two modules of the device in each case be connected to one another via a serial point-to-point connection. Modules with a coupling element are connected to a plurality of other modules. | 2008-11-20 |
20080288707 | METHOD FOR CONTROLLING THE ACTIVE DATA INTERFACE WHEN MULTIPLE INTERFACES ARE AVAILABLE - Systems and methods are provided for controlling which of multiple data interfaces in an electronic device is used for communication with another electronic device so as to minimize disruption of the user experience. In one embodiment, a switch may be provided that is configured to maintain the data stream through a presently used data interface even when other data interfaces become physically connected or available for data transfer. Benefits of unused, but nevertheless connected data interfaces may be received by the electronic device without initiating a transfer of the communication duties between interfaces. | 2008-11-20 |
20080288708 | MULTIPLE VIRTUAL USB DEVICES WITH VIRTUAL HUB IMPLEMENTED USING ONE USB DEVICE CONTROLLER - A USB device using one USB device controller to simulate multiple virtual USB devices with a virtual USB hub is described. The USB device controller is assigned a USB address and communicates with the USB host under the control of an MCU and its firmware. The USB device also includes a CPLD (or FPGA or ASIC) and an analog switch for filtering the USB packets from the host and replacing the address in the packet by a fixed address before sending the packet to the USB device controller. The address in the original packet is stored in the CPLD and accessible by the MCU. The MCU controls the USB device controller to simulate one or more USB hubs and multiple USB devices. | 2008-11-20 |
20080288709 | Wide area network connection platform - Embodiments of the invention relate to a wide area network platform for use in conjunction with multiple distinct bus applications. The wide area network platform may include a hardware module for connection with system hardware, the hardware module including a universal serial bus interface and a wide area network interface. The hardware module is operable with multiple distinct bus applications. The platform may further include a universal device driver for interfacing with an operating system and with the system hardware and operating transparently through the multiple distinct bus applications. | 2008-11-20 |
20080288710 | Semiconductor Memory Device and Its Control Method - A card information storage part ( | 2008-11-20 |
20080288711 | Multimedia Platform - A device comprising a multimedia platform with a plurality of memories and a method of sharing a non-volatile memory. The multimedia platform in accordance with an embodiment of the present invention can have a non-volatile memory, a multimedia processor setting a route in accordance with a route selection signal received from the main processor such that the main processor accesses the non-volatile memory or the display unit, a first volatile memory which is a temporary memory device of the main processor, and a second volatile memory which is a temporary memory of the multimedia processor. With the present invention, the portable terminal can be made smaller by putting a memory chip and a multimedia platform in a single chip by use of the POP (package on package) technology. | 2008-11-20 |
20080288712 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 2008-11-20 |
20080288713 | FLASH-AWARE STORAGE OPTIMIZED FOR MOBILE AND EMBEDDED DBMS ON NAND FLASH MEMORY - Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates. | 2008-11-20 |
20080288714 | FILE STORAGE IN A COMPUTER SYSTEM WITH DIVERSE STORAGE MEDIA - A method for storing data in a computer having a magnetic hard disk drive (HDD) and an electronic solid-state drive (SSD). The method includes configuring the computer so that the HDD and the SSD are each independently accessible by an operating system of the computer. A plurality of files is received for storage by the computer. A predicted use profile of the computer is defined. A respective one of the HDD and the SDD is selected for the storage of each of the files responsively to the predicted use profile. | 2008-11-20 |
20080288715 | Memory Page Size Auto Detection - Methods and apparatuses are presented for memory page size auto detection. A method for automatically determining a page size of a memory device includes receiving page size extents of the memory device, determining a bus width of the memory device, detecting a number of pages having an automatic detection marker, and determining the page size of the memory device based upon the detected number of pages and the received page size extents. An apparatus for automatically determining page size detection includes logic for performing the above presented method. | 2008-11-20 |
20080288716 | STORAGE DEVICE - A storage device includes: a binary flash memory that has a first storage area and a capacity of storing two values per each cell; a multivalued flash memory that has a second storage area and a capacity of storing at least three values per each cell; and a controller configured to arrange the first storage area ahead of the second storage area, logically combine the first storage area with the second storage area to form a single combined storage area, and perform data reading and data writing from and into the combined storage area. Data management information is stored in a head of the combined storage area according to a predetermined file system. The storage device of this arrangement has the advantages of both an SLC flash memory and an MLC flash memory. | 2008-11-20 |
20080288717 | SINGLE SECTOR WRITE OPERATION IN FLASH MEMORY - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages. When updating data previously written to one of the plurality of logical addresses, the controller is configured to write the updated data to a second physical page which is mapped to the logical address. Each of the logical addresses may be associated with a pointer field, which is for storing a pointer value indicating the invalidity of a physical page and/or the location of another physical page. | 2008-11-20 |
20080288718 | METHOD AND APPARATUS FOR MANAGING MEMORY FOR DYNAMIC PROMOTION OF VIRTUAL MEMORY PAGE SIZES - A computer implemented method, apparatus, and computer usable program code for managing real memory. In response to a request for a page to be moved into real memory, a contiguous range of real memory is reserved for the page corresponding to a contiguous virtual memory range to form a reservation within a plurality of reservations for the real memory. This reservation enables efficient promotion of pages to a larger page size. The page only occupies a portion of the contiguous range of real memory for the reservation. In response to a need for real memory, a selected reservation is released within the plurality of reservations based on an age of the selected reservation within the plurality of reservations. | 2008-11-20 |
20080288719 | Memory Tracing in an Emulation Environment - A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory are captured in a second Random Access Memory. After the capturing, the contents of the second Random Access Memory are copied to a visibility system. During the copying, the user design may modify the data in the first Random Access Memory while the captured contents within the second Random Access Memory remain unmodifiable so that the captured contents are not compromised. In another aspect, different size memories are in the emulator to emulate the user model. Larger memories have their ports monitored to reconstruct the contents of the memories, while smaller memories are captured in a snapshot RAM. Together the two different modes of tracing memory are used to provide visibility to the user of the entire user memory. | 2008-11-20 |
20080288720 | MULTI-WAFER 3D CAM CELL - A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. | 2008-11-20 |
20080288721 | TRANSPOSING OF BITS IN INPUT DATA TO FORM A COMPARAND WITHIN A CONTENT ADDRESSABLE MEMORY - An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a comparand for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data. | 2008-11-20 |
20080288722 | Method for Optimization of the Management of a Server Cache Which May be Consulted by Client Terminals with Differing Characteristics - A method is provided for optimisation of the management of a server cache for dynamic pages, which may be consulted by client terminals with differing characteristics which requires the provision of discrete versions of a dynamic page in the cache. When a terminal requests a dynamic page, a verification step—for the presence of at least one version of the dynamic page in the cache is carried out, such that if the verification is positive the following complementary steps are carried out: procurement of a set of characteristics specific to the type of client terminal, determination of a subset of necessary characteristics from amongst the specific characteristics for the reproduction of the dynamic page on a client terminal, search, among the version(s) of the dynamic page in the cache for a suitable version using the subset of necessary characteristics and allocation of the suitable version to the client terminal. | 2008-11-20 |
20080288723 | STORAGE DEVICE AND STORAGE DEVICE DATA LIFE CYCLE CONTROL METHOD - A storage device including a control part which performs control by extracting a life tag specifying a retention term during which the data is to be retained in the second volume having the quicker access time than the first volume, the control part managing the retention term of the corresponding data as specified by the life tag, and an elapsed term which has elapsed since the corresponding data was stored. A storage part manages update segment control information, and when the elapsed term of certain data exceeds the retention term of the certain data, the storage part nullifies the certain data in the second volume. | 2008-11-20 |
20080288724 | METHOD AND APPARATUS FOR CACHE TRANSACTIONS IN A DATA PROCESSING SYSTEM - A plurality of new snoop transaction types are described. Some include address information in the requests, and others include cache entry information in the requests. Some responses include tag address information, and some do not. Some provide tag address content on the data bus lines during the data portion of the transaction. These new snoop transaction types are very helpful during debug of a data processing system. | 2008-11-20 |
20080288725 | METHOD AND APPARATUS FOR CACHE TRANSACTIONS IN A DATA PROCESSING SYSTEM - A plurality of new snoop transaction types are described. Some include address information in the requests, and others include cache entry information in the requests. Some responses include tag address information, and some do not. Some provide tag address content on the data bus lines during the data portion of the transaction. These new snoop transaction types are very helpful during debug of a data processing system. | 2008-11-20 |
20080288726 | Transactional Memory System with Fast Processing of Common Conflicts - A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and performs fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. A transaction program employs a plurality of Set Associative Transaction Tables, one for each microprocessor, and Load and Store Summary Tables in memory for fast processing of common conflict. | 2008-11-20 |
20080288727 | Computing System with Optimized Support for Transactional Memory - A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection, of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. | 2008-11-20 |
20080288728 | MULTICORE WIRELESS AND MEDIA SIGNAL PROCESSOR (MSP) - A media signal processor (MSP) architecture is disclosed in this invention To address the shortcomings of conventional high performance processing units, the MSP architecture is designed using a new concept in parallel processing—“Same Instruction Different Operation” (SIDO) and “Same Instruction Multiple Data” (SIMD) architectures. The scalable nature of the architecture makes it possible to add multiple cores to match the processing needs of any type of data processing application. With multiple MSPs working in parallel, multiple data streams can be processed in either parallel or in a sequentially pipelined manner, using a software-based control mechanism. | 2008-11-20 |
20080288729 | METHODS AND APPARATUS FOR PREDICTIVE DOCUMENT RENDERING - A system receives a document having a predefined format to be rendered on the computer system. The document is comprised of a plurality of objects. The system identifies at least one correlation between at least two objects within the plurality of objects, and assigns a weight to the correlation. The system determines a logical relationship between at least two objects within the plurality of objects. The logical relationship is determined according to the weight of at least one correlation. The logical relationship is associated with an order in which at least one object is rendered on the computer system. | 2008-11-20 |
20080288730 | Transactional Memory System Which Employs Thread Assists Using Address History Tables - A computing system uses specialized “Set Associative Transaction Tables” and additional “Summary Transaction Tables” to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table and processes memory transactions with a Transaction Table in memory for parallel processing of multiple threads of execution by support of which an application need not be aware. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. | 2008-11-20 |
20080288731 | Request arbitration device and memory controller - A bus arbiter receives requests of initiators, and internally includes a page hit/miss determining unit with permissible determining function, a bank open/close determining unit with permissible determining function, and an LRU unit with permissible determining function. Regarding the priority of the request arbitration on the requests, the bank priority on the SDRAM is determined in the order of page hit, bank open, and LRU. Furthermore, each determining unit internally includes a permissible time determining unit, and processes, at top priority, the request of the initiator which the corresponding permissible time is below the count threshold value in the priority processing of the determining unit. | 2008-11-20 |
20080288732 | METHOD AND APPARATUS FOR MOVING CONTENTS USING COPY AND MOVEMENT CONTROL INFORMATION - A method and apparatus for moving contents using copy and movement control information are discussed. According to an embodiment, the method includes transmitting, by a first device, a copy of a content using a copying operation to a second device based on copy and movement control information; updating, in the first device, the copy and movement control information based on the copying operation; determining, by the first device, whether or not the content is to be moved based on the copy and movement control information, the copy and movement control information indicating whether or not the content is to be moved; and moving, by the first device, the content to a third device based on the determination result. | 2008-11-20 |
20080288733 | METHOD FOR CONTROLLING STORAGE DEVICE CONTROLLER, STORAGE DEVICE CONTROLLER, AND PROGRAM - Disclosed herein is a method for controlling a storage device controller connected to a storage device provided with a plurality of storage volumes for storing data respectively and an information processing apparatus for requesting an input/output of data so as to receive an input/output request from the information processing apparatus and execute an input/output processing of the data for each of the plurality of storage volumes. The method brings one (primary) of the plurality of storage volumes into correspondence with another (secondary) in which a copy of data is to be written when the data is written in the primary volume so as to form a pair group consisting of a plurality of pairs, each having such a primary volume and such a secondary volume. | 2008-11-20 |
20080288734 | Mail processing computer automatic recovery system and method - An improved method and system to return a mail processing control computer back into operation after a hard drive failure. A first phase is a back-up process for the primary drive of the mail processing computer. A second phase is the recovery process when a primary hard drive failure occurs. The back-up process includes copying the primary drive to be protected to a spare backup drive. The data copied to the backup drive reflects data of the primary drive at a particular point in time. Once the backup drive is installed, the machine returns to normal operation. In the course of normal operation, incremental changes to the primary hard drive are recorded to a backup computer. When there is a failure of the primary drive, a new primary drive is installed in its place. An image of the backup drive is then copied to the new primary drive, thereby causing the new primary drive to reflect the original primary drive at the particular point in time. Next, the incremental changes recorded in the backup computer are updated to the primary drive from the backup computer. | 2008-11-20 |
20080288735 | Data Protection for Non-Volatile Semiconductor Memory Using Block Protection Flags - Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch. | 2008-11-20 |
20080288736 | SYSTEMS AND METHODS FOR CHANGING PARAMETERS OF A CONTROLLER - Systems and methods for modifying a parameter value of a controller are described. In one embodiment, the method includes verifying a local presence at the controller, modifying a parameter value at a remote device, confirming the identity of the remote device, and storing the modified parameter value in the controller. | 2008-11-20 |
20080288737 | Optimizing Memory Accesses for Network Applications Using Indexed Register Files - A processing device includes an optimizer to migrate objects from an external memory of a network processing to local memory device to registers connected to a processor. The optimizer further aligns and eliminates redundant unitialization code of the objects. | 2008-11-20 |
20080288738 | SYSTEMS AND METHODS OF DATA STORAGE MANAGEMENT, SUCH AS PRE-ALLOCATION OF STORAGE SPACE - A system and method for pre-allocating space on a storage medium is described. In some cases, the system receives two or more data items to be stored on a storage medium, pre-allocates a single, contiguous block of space on the medium, and stores the two or more data items within the single, contiguous block of space. | 2008-11-20 |
20080288739 | SCALABLE PERFORMANCE-BASED VOLUME ALLOCATION IN LARGE STORAGE CONTROLLER COLLECTIONS - A scalable, performance-based, volume allocation technique that can be applied in large storage controller collections is disclosed. A global resource tree of multiple nodes representing interconnected components of a storage system is analyzed to yield gap values for each node (e.g., a bottom-up estimation). The gap value for each node is an estimate of the amount in GB of the new workload that can be allocated in the subtree of that node without exceeding the performance and space bounds at any of the nodes in that subtree. The gap values of the global resource tree are further analyzed to generate an ordered allocation list of the volumes of the storage system (e.g., a top-down selection). The volumes may be applied to a storage workload in the order of the allocation list and the gap values and list are updated. | 2008-11-20 |
20080288740 | Method and Device for Generating an Identification Data Block for a Data Carrier - The invention relates to a method for generating an identification data block (ID) for a data carrier ( | 2008-11-20 |
20080288741 | Data Access Tracing - A moving window history of at least one previous data address accessed by a processor is maintained, the at least one previous data address in the history each being associated with an index. A difference between a current data address and one of the at least one previous data address in the history is determined. The difference and the index associated with the one of the at least one previous data address in the history are provided as a representation of the current address. | 2008-11-20 |
20080288742 | METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING PAGE SIZE IN A VIRTUAL MEMORY RANGE - The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for adjusting a page size for a virtual memory range. The process identifies a set of pages in the virtual memory range that reside on a primary memory to form a page occupancy. Each of the set of pages has a first page size. The process changes the first page size to a second page size in response to a comparison of the page occupancy to a threshold value indicating that the first page size should be adjusted. | 2008-11-20 |
20080288743 | APPARATUS AND METHOD OF MANAGING MAPPING TABLE OF NON-VOLATILE MEMORY - An apparatus and method for managing a mapping table of a non-volatile memory are provided. The apparatus includes a non-volatile memory having memory cells, each of which stores data bits in a plurality of pages included in a block according to a plurality of states, each of which has at least two bits, an operating time measuring unit measuring a write operation time on each of the plurality of pages included in the block, and a mapping table generating unit dividing the pages into a plurality of groups according to the measured write operation time and generating a mapping table by using the divided groups. | 2008-11-20 |
20080288744 | DETECTING MEMORY-HAZARD CONFLICTS DURING VECTOR PROCESSING - A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when memory operations are performed in parallel using at least a portion of the vectors, and tracking positions in at least one of the vectors of any detected conflict between the memory addresses. Next, the processor executes the instructions for detecting the conflict between the memory addresses and tracking the positions. | 2008-11-20 |
20080288745 | GENERATING PREDICATE VALUES DURING VECTOR PROCESSING - A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more predicate values corresponding to any detected conflict between the memory addresses, where a given predicate value indicates elements in at least the portion of the vector that can be processed in parallel. Next, the processor executes the instructions for detecting the conflict between the memory addresses and generating the one or more predicate values. | 2008-11-20 |
20080288746 | Executing Multiple Instructions Multiple Data ('MIMD') Programs on a Single Instruction Multiple Data ('SIMD') Machine - Executing MIMD programs on a SIMD machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the compute nodes initially configured exclusively for SIMD operations, the SIMD machine further comprising a data communications network, the network comprising synchronous data communications links among the compute nodes, including establishing one or more SIMD partitions, booting one or more SIMD partitions in MIMD mode; establishing a MIMD partition; executing by launcher programs a plurality of MIMD programs on two or more of the compute nodes of the MIMD partition; and re-executing a launcher program by an operating system on a compute node in the MIMD partition upon termination of the MIMD program executed by the launcher program. | 2008-11-20 |
20080288747 | Executing Multiple Instructions Multiple Data ('MIMD') Programs on a Single Instruction Multiple Data ('SIMD') Machine - Executing MIMD programs on a SIMD machine, including establishing SIMD partitions on the SIMD machine; booting SIMD partitions in MIMD mode; executing MIMD programs on the compute nodes of a first SIMD partition booted in MIMD mode; re-executing a launcher program by an operating system on a compute node in the first SIMD partition booted in MIMD mode upon termination of the MIMD program executed by the launcher program; determining by a scheduler that the first SIMD partition booted in MIMD mode is required to establish a new SIMD partition large enough to run a SIMD program that is scheduled for execution; moving by the scheduler data processing operations from the first SIMD partition booted in MIMD mode to the second SIMD partition booted in MIMD mode; and establishing by the scheduler the new SIMD partition. | 2008-11-20 |
20080288748 | Dynamic core switching - A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled. | 2008-11-20 |
20080288749 | READ-COPY UPDATE GRACE PERIOD DETECTION WITHOUT ATOMIC INSTRUCTIONS THAT GRACEFULLY HANDLES LARGE NUMBERS OF PROCESSORS - A method, system and computer program product for avoiding unnecessary grace period token processing while detecting a grace period without atomic instructions in a read-copy update subsystem or other processing environment that requires deferring removal of a shared data element until pre-existing references to the data element are removed. Detection of the grace period includes establishing a token to be circulated between processing entities sharing access to the data element. A grace period elapses whenever the token makes a round trip through the processing entities. A distributed indicator associated with each processing entity indicates whether there is a need to perform removal processing on any shared data element. The distributed indicator is processed at each processing entity before the latter engages in token processing. Token processing is performed only when warranted by the distributed indicator. In this way, unnecessary token processing can be avoided when the distributed indicator does not warrant such processing. | 2008-11-20 |