47th week of 2008 patent applcation highlights part 21 |
Patent application number | Title | Published |
20080284444 | Method for on-line measurement of battery internal resistance, current operational module, and on-line measurement instrument for battery internal resistance - A method and a current operational module for on-line measurement of battery internal resistance and an on-line measurement instrument for battery internal resistance have high measurement accuracy and strong anti-interference ability. The on-line measurement instrument for battery internal resistance comprises a current work module, a voltage measurement module, an analog to digital conversion module, a signal generation module, a centre processing module, an Input/Output module, and a power supply module used for on-line measurement of battery internal resistance. | 2008-11-20 |
20080284445 | POTENTIAL MEASUREMENT APPARATUS AND IMAGE FORMING APPARATUS - A potential measurement apparatus is provided which can suitably maintain the oscillation state of an oscillator including a detection electrode and stably measure the potential of a measurement object. The potential measurement apparatus includes a bearing part, an elastic supporting part supported by the bearing part, an oscillator movably supported by the elastic supporting part, detection electrodes installed in the oscillator, a drive mechanism driving the oscillator and a signal detection unit. The signal detection unit is connected to the detection electrodes to detect electrical signals appearing in the detected electrodes. A stress detecting element for generating an electric signal according to the stress of the elastic suspension part | 2008-11-20 |
20080284446 | Determination of Field Distribution - A method for determining field intensity for a particle on a substrate, the method comprising providing an incident wave, determining an electric vector of the field and a magnetic vector of the field inside and outside of the particle, and determining additional scattered fields inside and outside of the particle due to reflection of the incident wave from the substrate. | 2008-11-20 |
20080284447 | Method for determining location of phase-to earth fault - A method and apparatus for determining a location of a phase-to-earth fault on a three-phase electric line ( | 2008-11-20 |
20080284448 | TEST APPARATUS AND PIN ELECTRONICS CARD - Provided is a test apparatus that tests a DUT, which includes a driver that outputs a test signal to the DUT, a first transmission path that electrically connects the driver and the DUT, a first FET switch provided on the first transmission path to connect or disconnect the driver and the DUT to or from each other, and a capacitance compensator that detects an output signal from the DUT, and charges or discharges a capacitive component of the first FET switch based on the detected output signal. | 2008-11-20 |
20080284449 | Power converters with component stress monitoring for fault prediction - A power converter includes a controller and at least one circuit component. The controller is configured for monitoring stress on the circuit component during operation of the power converter and estimating a remaining life of the circuit component based on the monitored stress. | 2008-11-20 |
20080284450 | Arc wave generator for testing an arc-fault circuit interrupter - Provided is an arc wave generator for testing an arc fault circuit interrupter (AFCI) for use in a test system for testing whether or not an arc fault circuit interrupter (AFCI) is operating normally, in which a false arc is generated for use in testing the arc fault circuit interrupter (AFCI). The arc wave generator includes a rectifier which receives a commercial power source as an input source and rectifies alternating-current voltage of the commercial power source to generate a rectified signal. A drop resistor drops the voltage of the rectified signal to generate a voltage-dropped signal. A mono-stable multivibrator adjusts a voltage level and a pulse width of the voltage-dropped signal and generates a pulse signal which is used to generate a false arc for testing the arc fault circuit interrupter (AFCI). Thus, a false arc is generated with a simple circuit to accurately test the actions of the arc fault circuit interrupter (AFCI). | 2008-11-20 |
20080284451 | Device, method and system for estimating the termination to a wired transmission-line based on determination of characteristic impedance - A system and method for measuring a characteristic impedance of a transmission-line comprises transmitting energy to the line, and shortly after measuring the voltage/current involved and thus measuring the equivalent impedance. The measured characteristic impedance may then be used in order to determine the termination value required to minimize reflections. In another embodiment, the proper termination is set or measured by adjusting the termination value to achieve maximum power dissipation in the terminating device. The equivalent characteristic impedance measurement may be used to count the number of metallic conductors connected to a single connection point. This abstract is not intended to limit or construe the scope of the claims. | 2008-11-20 |
20080284452 | SEMICONDUCTOR DEVICE AND METHOD OF MEASURING SHEET RESISITANCE OF LOWER LAYER CONDUCTIVE PATTERN THEREOF - Contact holes (openings) ( | 2008-11-20 |
20080284453 | IC TEST VECTOR GENERATOR FOR SYNCHRONIZED PHYSICAL PROBING - Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times. | 2008-11-20 |
20080284454 | Test interface with a mixed signal processing device - The present invention relates to a test interface to which a mixed signal processing circuit is integrated, and more particularly to a test interface of a probe card or a DUT card to which a mixed signal processing circuit is integrated, and the mixed signal processing circuit is integrated to pin electronic channels of a tester and the operation process of the mixed signal processing circuit is integrated to the system software of the tester. | 2008-11-20 |
20080284455 | PROBE APPARATUS - A probe apparatus includes a load port for mounting therein a carrier having therein a plurality of substrates; a plurality of probe apparatus main bodies, each having a probe card having probes on its bottom surface; a substrate transfer mechanism for transferring the substrates between the load port and the probe apparatus main bodies, the substrate transfer mechanism being rotatable about a vertical axis and movable up and down. The substrate transfer mechanism has at least three substrates capable of moving back and forth independently. Further, at least two wafers are received from the carrier by the substrate transfer mechanism, and then are sequentially loaded into the probe apparatus main bodies. The prove apparatus a high throughput increasing a wafer transfer efficiency. | 2008-11-20 |
20080284456 | Test Apparatus of Semiconductor Devices - A test apparatus of a semiconductor device is provided. A signal pin can be electrically connected to a connector and can have a region for electrically connecting to a semiconductor device. The signal pin can be inserted into the connector, and the region of the signal pin for electrically connecting to a semiconductor device can be located on a portion of the signal pin that is not inserted into the connector. | 2008-11-20 |
20080284457 | METHOD AND APPARATUS FOR CONTROL OF A POSITIONING DEVICE - In a device and a method for positioning an object, a drive of a movement device is controlled. To this end, a visual joystick is actuated, as a result of which a moveable actuator is moved, at least linearly by means of a display of a control unit of the movement device, into a position, in which a direction of movement, which can be implemented with the drive, is displayed symbolically. The drive for the movement of the object in the displayed direction of movement is initiated by means of a switching function of the actuator. | 2008-11-20 |
20080284458 | Method for Forming Connection Pin, Probe, Connection Pin, Probe Card and Method for Manufacturing Probe Card - A prove which can be easily formed, is not limited in a mounting position and number, and capable of sufficiently securing a space allowing a contact to move is provided. | 2008-11-20 |
20080284459 | Testing Using Independently Controllable Voltage Islands - A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test. | 2008-11-20 |
20080284460 | METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION - A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures. | 2008-11-20 |
20080284461 | ACTIVE CANCELLATION MATRIX FOR PROCESS PARAMETER MEASUREMENTS - An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage. | 2008-11-20 |
20080284462 | MECHANICAL STRESS CHARACTERIZATION IN SEMICONDUCTOR DEVICE - Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer. | 2008-11-20 |
20080284463 | PROGRAMMABLE CIRCUIT HAVING A CARBON NANOTUBE - A semiconductor device comprising a programming circuit that includes an active device on or in a substrate and a programmable electronic component on the substrate. The programmable electronic component includes at least one carbon nanotube having a segment with an adjusted diameter. The programmable electronic component has a value that depends upon the adjusted diameter. The programming circuit also includes interconnects that couple the active device to the programmable electronic component. The active device is configured to control a current transmitted to the programmable electronic component. | 2008-11-20 |
20080284464 | TIME BASED DRIVER OUTPUT TRANSITION (SLEW) RATE COMPENSATION - Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate. | 2008-11-20 |
20080284465 | On-die system and method for controlling termination impedance of memory device data bus terminals - A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor. | 2008-11-20 |
20080284466 | Driver Circuit - A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential. | 2008-11-20 |
20080284467 | On die termination circuit and method for calibrating the same - On die termination circuit and method for calibrating the same includes a external resistor connected to a first node, a plurality of calibration resistors connected to a second node, the plurality of calibration resistors being turned on/off in response to a calibration code set, a current mirror configured to mirror currents of the first node and the second node and a code generator configured to generate a calibration code set according to the mirrored currents. In accordance with a method for calibrating an on die termination circuit of the present invention, the method includes a step of mirroring a current of a first node connected to an external resistor and a current of a second node connected to a plurality of calibration resistors and a step of generating a calibration code set according to the mirrored currents. | 2008-11-20 |
20080284468 | METHOD AND APPARATUS FOR CONTROLLING A COMMUNICATION SIGNAL BY MONITORING ONE OR MORE VOLTAGE SOURCES - An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage. | 2008-11-20 |
20080284469 | REDUCED POWER CONSUMPTION LIMITED-SWITCH DYNAMIC LOGIC (LSDL) CIRCUIT - An limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers. | 2008-11-20 |
20080284470 | Direct Digital Synthesizer and Nuclear Magnetic Resonance Instrument Using the Same - A DDS (direct digital synthesizer) remarkably increased in the number of frequencies which can be output while maintaining the phase coherency, and an NMR instrument using such a DDS are provided. A DDS including phase accumulators and a phase-to-amplitude modulator is provided with a plurality of phase accumulators operating with fixed phase implements which are equal to powers of 2, a controller for outputting each bit of a frequency tuning word as control data, a plurality of switches for outputting an output of an associated one of the phase accumulators when an associated one of the control data supplied from the controller is 1 and outputting 0 when the associated one of the control data is 0, and an adder for adding up outputs of the switches. | 2008-11-20 |
20080284471 | Current load driving circuit - A current load driving circuit for driving a current load, including: a first current mirror circuit that outputs a current; and a second current mirror circuit that receives the current outputted from the first current mirror circuit as an input current and then amplifies the input current to drive the current load. The whole of the first current mirror circuit and the second current mirror circuit is divided into an input circuit and an output circuit; and the divided position is provided on a voltage route of the first current mirror circuit or a voltage route of the second current mirror circuit. | 2008-11-20 |
20080284472 | APPARATUS FOR ADJUSTING BANDWIDTH AND CENTRAL FREQUENCY OF OSCILLATING SIGNAL GENERATED FROM CHAOTIC SIGNAL AND METHOD FOR GENERATING SIGNAL THEREOF - A communication apparatus and a method for generating a signal thereof are provided. The communication apparatus adjusts a bandwidth or central frequency of an oscillating signal which is generated from a chaotic signal to be used in the modulation, or adjusts both the bandwidth and the central frequency. Accordingly, it is possible to transform the oscillating signal generated from the chaotic signal more diversely and thus to modulate an information signal more diversely and more adaptively. | 2008-11-20 |
20080284473 | PHASE SYNCHRONOUS CIRCUIT - An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. Further, when a plurality of phase comparators are disposed, in both cases where comparing phases all at once and comparing phases one after another, it is possible to complete the phase synchronization within a short time by making a delay amount variable. | 2008-11-20 |
20080284474 | Techniques for integrated circuit clock management - A clock generator ( | 2008-11-20 |
20080284475 | Semiconductor device having delay locked loop and method for driving the same - A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal. | 2008-11-20 |
20080284476 | Techniques for integrated circuit clock management using pulse skipping - A processor ( | 2008-11-20 |
20080284477 | ON-CHIP JITTER MEASUREMENT CIRCUIT - An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay. | 2008-11-20 |
20080284478 | DUTY CORRECTION CIRCUIT OF DIGITAL TYPE FOR OPTIMAL LAYOUT AREA AND CURRENT CONSUMPTION - The present invention relates to a duty correction circuit that corrects a distorted duty of a clock signal using a delay unit and a delay controller, thereby reducing the layout area and current consumption. The duty correction circuit includes a repeater that generates a clock signal having the same phase as that of an input clock signal with a distorted duty, and a clock signal having an inverted phase of the phase; a delay line delaying the phase of the clock signal having the inverted phase and generating a feedback clock signal; a phase comparator comparing the phase of the clock signal having the same phase with the phase of the feedback clock signal and generating a delay control signal according to the phase difference between the phases of the clock signal having he same phase and the feedback clock signal; a delay controller controlling the amount of delay of the delay line according to the delay control signal; and a phase mixer performing half-phase blending on the clock signal having the same phase and the feedback clock signal and outputting a clock signal having a corrected duty. | 2008-11-20 |
20080284479 | METHOD OF FORMING A PWM CONTROLLER AND STRUCTURE THEREFOR - In one embodiment, a PWM controller is configured to form a drive signal that has an operating frequency that varies around a center by a percentage of the center frequency. | 2008-11-20 |
20080284480 | SCAN FLIP-FLOP WITH INTERNAL LATENCY FOR SCAN INPUT - A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits. | 2008-11-20 |
20080284481 | Cross-point latch and method of operating the same - Provided is a cross-point latch and a method of operating the cross-point latch. The cross-point latch includes a signal line, two control lines crossing the signal line, and unipolar switches disposed at crossing points between the signal line and the control lines. | 2008-11-20 |
20080284482 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit for an inverter device, comprising a pulse generator for generating a pulse signal upon receiving the input signal for controlling the high-voltage switching device of the inverter device, a driver circuit for driving the high-voltage switching device, and a signal transfer circuit for transferring the pulse signal generated by the pulse generator to the driver circuit, wherein a wide band-gap semiconductor device is used in the signal transfer circuit | 2008-11-20 |
20080284483 | Clock distribution circuit and test method - A clock distribution circuit having plural stages of buffers disposed along branch paths for dividing up a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, includes in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, a selector for receiving an output of an adjacent buffer located upstream in terms of chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the at least one buffer by a first input and a second input respectively, selecting one of the first input and the second input based on a select control signal, and supplying the selected input to the one buffer. | 2008-11-20 |
20080284484 | CLOCK SWITCH FOR GENERATION OF MULTI-FREQUENCY CLOCK SIGNAL - An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases. | 2008-11-20 |
20080284485 | Method for determining a switch-on threshold and electronic circuit arrangement for carrying out the method - An electronic circuit arrangement is disclosed for converting an input voltage signal having a first voltage level into an output signal having a second voltage level. An input unit is provided for inputting the input voltage signal at the first voltage level, while an output unit is arranged for outputting the output signal at the output of the electronic circuit arrangement. A threshold value comparison unit serves for comparing the first voltage level of the input signal with a switch-on threshold value. The circuit arrangement furthermore contains an input impedance changeover unit for changing over an input impedance of the circuit arrangement from a low value to a high value after a predetermined delay duration after the first voltage level of the input voltage signal exceeded the switch-on threshold value. | 2008-11-20 |
20080284486 | INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR DEVICE AND METHOD FOR GENERATING INTERNAL VOLTAGE - An internal voltage generator of a semiconductor device consumes relatively small amount of driving current and generates a stable internal voltage with relatively small voltage level variation. The semiconductor device includes an oscillator configured to generate an oscillation signal in response to an input signal, wherein the oscillation signal oscillates with a first period and oscillates with a second period longer than the first period during a predetermined latter section, and an internal circuit configured to perform a predetermined operation in response to the oscillation signal. | 2008-11-20 |
20080284487 | Passive Mixer And High Q RF Filter Using A Passive Mixer - A passive mixer include a switching architecture configured to generate differential in-phase (I) and differential quadrature-phase (Q) signals using differential components of the in-phase (I) and quadrature-phase (Q) signals operating on transitions of an approximate 25% duty cycle signal. | 2008-11-20 |
20080284488 | Mixer Circuit - A subharmonic mixer circuit having an input stage ( | 2008-11-20 |
20080284489 | TRANSCONDUCTOR AND MIXER WITH HIGH LINEARITY - A transconductor. The transconductor comprises first and second active device networks. The first active device network has a first node and a second node and comprises a first MOS transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. The second active device network has a first node and a second node respectively connected to the first and second nodes of the first active device network and comprises a second MOS transistor and a voltage drop generator. The second MOS transistor has a gate and a source respectively connected to the gate and the source of the first MOS transistor. The voltage drop generator is coupled between a drain of the second MOS transistor and the second nodes of the first and second active device networks and generates a voltage drop across the same. | 2008-11-20 |
20080284490 | Compensated operational amplifier and active RC filter including such an amplifier - A method of compensating a monolithic integrated operational amplifier against process and temperature variations, such that the operational amplifier is suitable for use in an active filter, the method comprising a providing an amplifier having a first stage and an output stage, wherein the output stage drives an RC load, and wherein a compensation capacitor at an output of the first stage is selected so as to scale with the capacitance C of the RC load, and a transconductance of the first stage is a function of the resistance R of the RC load. | 2008-11-20 |
20080284491 | Integrated Circuit, Electronic Device and Integrated Circuit Control Method - An integrated circuit ( | 2008-11-20 |
20080284492 | Voltage Switch Circuit of Semiconductor Device - Disclosed is a voltage switch circuit of a semiconductor device. The subject voltage switch circuit can be used to apply voltage to a semiconductor memory device control circuit. The voltage switch circuit according to an embodiment includes five transistors and a capacitor. An output terminal of the subject circuit outputs VSS when VDD is applied to an input terminal, and outputs a boosted operating voltage when VSS is applied to the input terminal. | 2008-11-20 |
20080284493 | Proportional to absolute temperature current generation circuit having higher temperature coefficient, display device including the same, and method thereof - A proportional to absolute temperature (PTAT) current generation circuit may include a current mirror unit and/or a level control unit. The current mirror unit may be connected between a first power supply voltage, a first node, and/or a second node. The level control unit may be connected between the first node, the second node, and/or a second power supply voltage. The level control unit may be configured to control a level of an output current of the current mirror unit based on a voltage level of the first node and a voltage level of the second node. The level control unit may include a first transistor connected between the first node and the second power supply voltage, at least one second transistor connected between the second node and a third node, the at least one second transistor configured to operate in a weak inversion region, and/or a third transistor connected between the third node and the second power supply voltage. | 2008-11-20 |
20080284494 | FUSE DEVICE, METHOD FOR WRITING DATA, METHOD FOR READING DATA, AND METHOD FOR WRITING AND READING DATA - A fuse device includes a plurality of serially connected fuse elements whose number is n (n is an integer of two or more), a power source connected to one end of a first fuse element that is a top of the n serially connected fuse elements, and a plurality of program control transistors. Each of the program control transistors is connected to each of nodes between the fuse elements, and to an end of the n-th fuse element, respectively. | 2008-11-20 |
20080284495 | MOS CAPACITOR WITH LARGE CONSTANT VALUE - A capacitor circuit includes a first capacitor having a positive terminal coupled to a first node and a negative terminal coupled to a second node, a second capacitor having a negative terminal coupled to the first node and a positive terminal coupled to the second node, a third capacitor having a positive terminal coupled to the first node and a negative terminal coupled to a third node, a fourth capacitor having a negative terminal coupled to the first node, and a positive terminal coupled to the third node, a first voltage drop generator coupled between the second node and a fourth node for providing a first voltage drop between the second node and the fourth node, and a second voltage drop generator coupled between the fourth node and the third node for providing a second voltage drop between the fourth node and the third node. | 2008-11-20 |
20080284496 | INTERNAL VOLTAGE GENERATION CIRCUIT FOR SEMICONDUCTOR DEVICE AND METHOD FOR GENERATING INTERNAL VOLTAGE THEREIN - An internal voltage generation circuit of a semiconductor device includes: a voltage detecting unit configured to detect a voltage level of an internal voltage output terminal to output a voltage detection signal; an oscillating unit configured to generate a first oscillation signal having a predefined frequency in response to the voltage detection signal; and a pumping unit configured to perform a charge pumping operation in response to the first oscillation signal and the voltage detection signal to output an internal voltage to the internal voltage output terminal, a period of the charge pumping operation being limited within an activation period of the voltage detection signal. | 2008-11-20 |
20080284497 | VOLTAGE GENERATOR THAT PREVENTS LATCH-UP - A voltage generator that prevents latch-up includes: a charge pump circuit that is controlled by first through third enable signals, boosts an internal power voltage generated from an external power voltage, and generates first through fourth voltages; a detector that detects the first through third voltages and generates first through third flag signals that go logic high when the first through third voltages reach predetermined respective voltage levels and maintain logic low when the voltages do not reach the predetermined respective voltage levels; and a charge pump controller that receives the first through third flag signals, and generates the first through third enable signals to have the first through fourth voltages sequentially generated. The voltage generator can prevent latch-up that may occur in a boosting mode or in a normal operation mode. | 2008-11-20 |
20080284498 | Type of Charge Pump Apparatus and Power Source Circuit - This invention discloses charge pump apparati, where a charge pump apparatus, including a positive charge pump circuit and a negative charge pump circuit, providing multiple positive and negative voltages, comprises: a capacitor set shared by said positive charge pump circuit and said negative charge pump circuit; multiple electronic switches connected to said capacitor set and a plurality of voltage sources; multiple output capacitors connected to selected ones of said multiple electronic switches and one or more output terminals; and a non-overlapping time sequence that controls the on and off states of said multiple electronic switches; wherein under the control of said non-overlapping time sequence, corresponding electronic switches are turned on and off to control the output of the positive and negative voltages provided by said output capacitors to generate output voltages that are pre-determined multiples of the one or more input voltages. With this invention, coupling capacitors are shared during the processes of charging and discharging, and operate at alternating intervals through time sequence-control. As a result, both positive and negative output voltages can be simultaneously adjusted to provide different boost levels. The charge pump is both low in cost and has a design that is simple and easy to produce. | 2008-11-20 |
20080284499 | N-STAGE EXPONENTIAL CHARGE PUMPS, CHARGING STAGE THEREOF AND METHODS OF OPERATION THEREOF - An exponential charge pump uses a number of identical or similar charging stages, each having a first and second capacitor. During a first clock phase, the first capacitor of each stage is charged by the second capacitor of the preceding stage, and, during a complementary second clock phase, the positive plate of the first capacitor of each stage is pushed to an increased voltage by the first capacitor of the preceding stage and charges the second capacitor of the next stage to the increased voltage at the same time. A similar mechanism occurs to the second capacitors in each stage, but with complementary timing. The increased voltage of the first capacitor of the last stage is pumped to an output capacitor during the second clock phase, and the increased voltage of the second capacitor of the last stage is pumped to an output capacitor during the first clock phase. | 2008-11-20 |
20080284500 | LOAD-DRIVE CONTROLLER - In a load-drive controller, a first comparing unit compares a load current supplied from an H bridge circuit and a desired setting current; a PWM control unit generates a control signal to control the load current; a gate driver drives and controls output transistors of the H bridge circuit based on the control signal, and a load current monitoring unit determines which is larger a level shift equivalent value of the setting current or a peak hold equivalent value of the load current, and the PWM control unit controls increase or decrease of the load current based on a comparison result of the first comparing unit and on a determination result of the load current monitoring unit, so that the load current quickly reaches the setting current of a micro step drive during decrease of the setting current. | 2008-11-20 |
20080284501 | REFERENCE BIAS CIRCUIT FOR COMPENSATING FOR PROCESS VARIATION - A reference bias circuit is provided. The reference bias circuit includes a voltage detector, an operational amplifier, a compensation circuit, and a reference current generator. The voltage detector detects a first input voltage and a second input voltage of the operational amplifier based on a voltage of a first node and a voltage of a second node. The voltage of the first and second nodes varies with temperature, which changes the first input voltage and the second input voltage and thus changes the output voltage of the operational amplifier. The compensation circuit compensates for the variation of the voltage of the first and second nodes caused by temperature and/or process variation, thereby preventing the variation of a reference current generated by the reference current generator based on the output voltage of the operational amplifier. | 2008-11-20 |
20080284502 | CURRENT BIASING CIRCUIT - A current biasing circuit is provided, which is designed to suppress reference current drift caused by temperature variation with a low overall temperature coefficient of a constant-voltage circuit and at least one resistor. The constant-voltage circuit comprises a diode and/or a diode-connected transistor. This current biasing circuit is based on a current mirror architecture, is easy to implement, and is a relatively temperature-independent current source. | 2008-11-20 |
20080284503 | Charge Pump Start up Circuit and Method Thereof - The present invention discloses a charge pump start up circuit comprising: a start up transistor having one end which is electrically connected with a voltage supply source, and another end which is electrically connected to a voltage node; and a charge pump circuit having an input which is electrically connected with the voltage node, and an output which is electrically with the gate of the start up transistor. | 2008-11-20 |
20080284504 | SEMICONDUCTOR INTEGRATED CIRCUIT - This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET. | 2008-11-20 |
20080284505 | Filter Circuit for Wireless Applications and Noise Reduction Method - An object of the present invention is to provide a filter circuit which improves NF of a Gm-C filter. The filter circuit comprises a filter comprising at least one first operational transconductance amplifier whose mutual conductance varies depending on a first control signal and a first capacitor, a second operational transconductance amplifier whose mutual conductance is controlled by the first control signal, a third operational transconductance amplifier whose mutual conductance is controlled by a second control signal, and a second capacitor connected to output terminals of the first and second operational transconductance amplifiers and input terminals of the filter. | 2008-11-20 |
20080284506 | System and method for controlling an electromagnetic field generator - A system for driving an electromagnetic field generator. In one aspect, the system may include a plurality of transistors arranged in an H-bridge configuration, the H-bridge having first and second output terminals, first and second switching inputs, and a power input. The system may further include a control transistor coupling the power input to a power supply, and a diode having a cathode coupled to the power input and an anode coupled to ground. The first and second output terminals may be coupled to the electromagnetic field generator and the first and second switching inputs may receive switching signals based on an output of the electromagnetic field generator. | 2008-11-20 |
20080284507 | Autozeroing current feedback instrumentation amplifier - An embodiment is directed to an instrumentation amplifier. The instrumentation amplifier includes an output stage for generating an output voltage, a low-frequency path coupled with the output stage, and a high-frequency path coupled with the output stage. The high-frequency path dominates the low-frequency path at frequencies above a particular frequency, and the low-frequency path dominates the high-frequency path at frequencies below the particular frequency. The low-frequency path includes an input stage for sensing a differential input and generating an intermediate current based thereon, a feedback stage coupled with the input and output stages, the feedback stage for generating a feedback current based on the output voltage, and an auto-zeroing circuit coupled with the input, feedback, and output stages, the auto-zeroing circuit for generating a nulling current. The nulling current compensates for errors in the intermediate and feedback currents resulting from input offsets in the input and feedback stages. | 2008-11-20 |
20080284508 | OUTPUT CIRCUITS WITH CLASS D AMPLIFIER - Output circuits using pulse width modulation (PWM) and/or pulse density modulation (PDM) are described. In one aspect, a PWM output circuit includes a PWM modulator that operates based on a square wave signal instead of a sawtooth or triangular wave signal. In another aspect, a PDM output circuit includes a PDM modulator that uses variable reference voltages to reduce variations in switching frequency. In yet another aspect, a dual-mode output circuit supports both PWM and PDM and includes a pulse modulator and a class D amplifier. The pulse modulator performs PWM on an input signal if a PWM mode is selected and performs PDM on the input signal if a PDM mode is selected. The class D amplifier receives a driver signal from the pulse modulator and generates an output signal. | 2008-11-20 |
20080284509 | N-WAY DOHERTY DISTRIBUTED POWER AMPLIFIER - A power amplifier using N-way Doherty structure for extending the efficiency region over the high peak-to-average power ratio of the multiplexing modulated signals such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. In an embodiment, the present invention uses a dual-feed distributed structure to an N-way Doherty amplifier to improve the isolation between at least one main amplifier and at least one peaking amplifier and, and also to improve both gain and efficiency performance at high output back-off power. Hybrid couplers can be used at either or both of the input and output. In at least some implementations, circuit space is also conserved due to the integration of amplification, power splitting and combining. | 2008-11-20 |
20080284510 | ERROR DRIVEN RF POWER AMPLIFIER CONTROL WITH INCREASED EFFICIENCY - A power amplifier controller for adjusting a supply voltage to a power amplifier. The power amplifier controller adjusts the supply voltage so that distortion in an RF output signal corresponds to a predetermined limit. An amplitude error signal is generated by the power amplifier controller which represents a difference between an RF output signal and an attenuated RF output signal. The AC components of the amplitude error signal are processed to generate a deviation signal that represents the distortion in the RF output signal. The supply voltage to the power amplifier is increased when the deviation signal exceeds a distortion level control signal, and decreased when the deviation signal drops below the distortion level control signal. | 2008-11-20 |
20080284511 | Device Comprising a Switching Amplifier and a Load | 2008-11-20 |
20080284512 | POWER AMPLIFIER CIRCUITRY AND METHOD - A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals. | 2008-11-20 |
20080284513 | FULLY DIFFERENTIAL AMPLIFIER - A fully differential amplifier includes: an N-stage amplifier including first to Nth amplifier stages, where N is a positive integer greater than or equal to 2, the first to Nth amplifier stages being cascaded in sequence so as to generate a pair of differential output voltages; a common mode feedback circuit coupled to the N-stage amplifier, detecting a common mode level of the differential output voltages, and controlling the first amplifier stage according to the common mode level detected thereby; and a common mode frequency compensation circuit including a pair of capacitors, each having a first terminal coupled to the N-stage amplifier to receive a respective one of the differential output voltages, and a second terminal coupled to a common mode node of the first to (N-1)th amplifier stages of the N-stage amplifier. | 2008-11-20 |
20080284514 | DIFFERENTIAL AMPLIFIER WITH MULTIPLE SIGNAL GAINS AND WIDE DYNAMIC RANGE - A circuit and method for amplifying a differential input signal over a wide dynamic range using multiple signal gains such that, over a predetermined range of values of the differential input signal, a ratio of the differential output signal to the differential input signal varies in relation to a continuous combination of the multiple signal gains. | 2008-11-20 |
20080284515 | CIRCUITS FOR QUIESCENT CURRENT CONTROL - A circuit capable of quiescent current control, the circuit comprising a first operational transconductance amplifier (OTA) including a first output terminal, a first transistor including a first gate coupled to the first output terminal of the first OTA, a second OTA including a second output terminal, a second transistor including a second gate coupled to the second output terminal of the second OTA, a resistive load including a first terminal coupled to the first output terminal and the first gate, and a second terminal coupled to the second terminal and the second gate, a first current source capable of providing a first current flowing toward the first terminal of the resistive load, and a second current source capable of providing a second current flowing away from the second terminal of the resistive load. | 2008-11-20 |
20080284516 | Monolithic Lna Support Ic - A low noise amplifier (LNA) comprises: a plurality of FETs (F | 2008-11-20 |
20080284517 | Variable Gain Amplifier - A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages ( | 2008-11-20 |
20080284518 | OVERDRIVE CONTROL SYSTEM - An overdrive control system includes a voltage controlled current source to deliver a compensation current, and being between a first voltage reference and an internal node, which is connected to an output terminal. The voltage controlled current source has a control terminal connected to an output terminal of an adding block, which has a positive input connected to an input terminal. At least one clamping block is between the output terminal and a second voltage reference, and is connected to a negative input of the adding block. The voltage controlled current source delivers its compensation current to the output terminal when a voltage signal on the input terminal has an higher value than a voltage signal on the output terminal, and forces an output voltage signal to follow an input voltage signal to an extent that depends on a clamping voltage provided by the clamping block. | 2008-11-20 |
20080284519 | APPARATUS AND METHOD FOR POWER ADDED EFFICIENCY OPTIMIZATION OF HIGH AMPLIFICATION APPLICATIONS - A power added efficiency optimizer apparatus is provided for measuring and monitoring input and output power of an amplifying device, and adjusting the load impedance seen by the amplifying device so that power added efficiency is maintained at optimum levels. A power added efficiency optimizing device includes a variable load impedance that can be controlled, at least one power detection device located after the load, a difference forming apparatus, and at least one coupling device. The power added efficiency optimizing device provides an ability to maintain an amplifier at peak efficiency in a dynamic way and in the presence of changing electromagnetic load conditions. | 2008-11-20 |
20080284520 | System And Method For Power Detection In A Power Amplifier - A system for detecting power output of a power amplifier includes a first power detector configured to detect a forward power output of a power amplifier, the first power detector configured to provide a first power detector output, and a second power detector configured to receive a collector parameter signal and detect a collector parameter therefrom, the second power detector also configured to provide a second power detector output. | 2008-11-20 |
20080284521 | Electronic Signal Processor - An electronic signal processor for processing signals includes a complex first filter, one or more gain stages and a second filter. The first filter is characterized by a frequency response curve that includes multiple corner frequencies, with some corner frequencies being user selectable. The first filter also has at least two user-preset gain levels which may be alternately selected by a switch. Lower frequency signals are processed by the first filter with at least 12 db/octave slope, and preferably with 18 db/octave slope to minimize intermodulation distortion products by subsequent amplification in the gain stages. A second filter provides further filtering and amplitude control. The signal processor is particularly suited for processing audio frequency signals. Related methods include filtering the input signal with an input filter of the second or third order high pass type, amplifying the filtered signal and further filtering the amplified signal with a low pass filter, which may be of the second order type. | 2008-11-20 |
20080284522 | LINEAR TRANSIMPEDANCE AMPLIFIER WITH MULTIPLEXED GAIN STAGE - A linear transimpedance amplifier includes a forward transimpedance circuit that receives an input signal from an optical device. The forward transimpedance circuit generates a linear output signal. The forward transimpedance circuit includes a first gain path and a second gain path, the first gain path configured to amplify the input signal when the first gain path is at a lower input impedance relative to the second gain path and the second gain path configured to amplify the input signal when the second gain path is at a lower input impedance relative to the first gain path. A feedback circuit includes a first circuit that detects a low frequency component of the output signal. The feedback circuit further includes a second circuit that is driven by the low frequency component of the output signal and is connected with the forward transimpedance circuit such that the second circuit uses an average optical device current to at least partially control when the input signal is amplified by the first gain path and when the input signal is amplified by the second gain path. | 2008-11-20 |
20080284523 | OSCILLATOR DEVICE, OPTICAL DEFLECTOR AND IMAGE FORMING APPARATUS USING THE OPTICAL DEFLECTOR - An oscillator device includes an oscillation system having an oscillator and an elastic supporting member, a detecting member for detecting oscillation amplitude of the oscillator, a driving member for driving the oscillator, and a control unit for generating a driving signal for driving the oscillator and for supplying the driving signal to the driving member, wherein the control unit reciprocally sweeps a driving frequency of the driving signal so that a resonance frequency of the oscillation system is included within a frequency range swept, wherein the control unit determines a resonance frequency based on at least two frequencies with which an oscillation amplitude value obtainable by the reciprocal sweeping reaches a maximum, and wherein the control unit generates the driving signal based on the determined resonance frequency. | 2008-11-20 |
20080284524 | Phase Locked Loop Circuit Having Regulator - Embodiments of present invention provide a circuit including a voltage regulator, a phase frequency detector, a charge pump, a low pass filter a control-voltage generating circuit and a voltage controlled oscillator. In a first mode of operation the voltage controlled oscillator produces an output clock in accordance with a control voltage produced from the control-voltage generating circuit and the output voltage of the voltage regulator. In a second mode of operation, the voltage controlled oscillator produces an output clock in accordance with a control voltage from the low pass filter and the output voltage of the voltage regulator. | 2008-11-20 |
20080284525 | Noise canceling technique for frequency synthesizer - A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes an input terminal and an output terminal, a loop filter, a digital phase detector, and an analog phase detector. The digital phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output coupled to the loop filter, the digital phase detector configured to operate at a first phase comparison frequency. The analog phase detector included a first input coupled to the input terminal, a second input coupled to the output terminal, and an output alternating current (AC) coupled to the loop filter, the analog phase detector configured to operate at a second phase comparison frequency. The first phase comparison frequency is different from the second phase comparison frequency. | 2008-11-20 |
20080284526 | TUNING CIRCUIT AND METHOD - A tuning circuit and a method for setting its tuning voltage. The tuning circuit has a phase frequency detector coupled to a loop filter which is coupled to a voltage controlled oscillator. An output terminal of the voltage controlled oscillator is coupled to an input terminal of the phase frequency detector to form a feedback loop. A state machine is coupled between the phase frequency detector and the voltage controlled oscillator. A switch is coupled between an output terminal of the state machine and the input terminal to the loop filter or between the output terminal of the state machine and the input terminal of the voltage controlled oscillator. Alternatively, a comparator is coupled between an input terminal of the state machine and the output terminal to the loop filter or between the input terminal of the state machine and the output terminal of the phase frequency detector. | 2008-11-20 |
20080284527 | PHASE LOCKED LOOP AND METHOD FOR OPERATING THE SAME - A phase locked loop can reduce a locking time, thereby efficiently reducing power in a locking operation. The phase locked loop includes a phase detector, a control voltage generator, a voltage controlled oscillator and a start-up driver. The phase detector detects a phase difference between a reference clock and a feedback clock to generate a detection signal corresponding to the detected phase difference. The control voltage generator generates a control voltage having a voltage level corresponding to the detection signal. The voltage controlled oscillator generates an internal clock having a frequency corresponding to a voltage level of the control voltage. The start-up driver drives a control voltage terminal to a predefined start-up level in response to a start-up level multiplex signal corresponding to a frequency of the reference clock prior to activation of the voltage controlled oscillator. | 2008-11-20 |
20080284528 | RESONATOR, OSCILLATOR, AND COMMUNICATION APPARATUS - Disclosed is a resonator including a plurality of resonator elements each including at least oscillation parts and lower electrodes with an intervening space therebetween, in which the plurality of resonator elements are disposed in a closed system and the oscillation parts of the plurality of resonator elements are continuously formed in an integrated manner. | 2008-11-20 |
20080284529 | METHOD AND APPARATUS OF A RING OSCILLATOR FOR PHASE LOCKED LOOP (PLL) - The present invention relates to a ring oscillator including a delay stage, the delay stage includes a differential pair of input transistor, a variable resistive load coupled to the transistor, a differential output between the variable resistive load and the corresponding input transistor, a variable current source coupled to the differential pair of transistors for variably setting a bias current through the differential pair of transistors, and an input coupled to the variable resistive load and the variable current source for receiving an configuration signal, wherein the variable resistive load and the variable current source are changed in response to the configuration signal, wherein the bias current of the variable current source increases and the variable resistive load decreases, and vice versa. | 2008-11-20 |
20080284530 | PHASE NOISE MINIMIZED PHASE/FREQUENCY-LOCKED VOLTAGE-CONTROLLED OSCILLATOR CIRCUIT - A phase noise minimization circuit is disclosed, to be used in a voltage-controlled oscillator (VCO) circuit embedded in a feedback system. The phase noise minimization circuit includes a noise power meter to analyze the control voltage fed into the VCO by the feedback system and determine its voltage noise power. Since the VCO is controlled by the feedback system, the control voltage noise power is also an indication of the VCO phase noise power for frequencies offset within the bandwidth of the feedback system. The VCO has several parameters that can be adjusted to affect its phase noise. A minimization algorithm generates the optimum set of parameters that minimize the control voltage noise power (and thus the VCO phase noise power), and sends them to the oscillator. The phase noise minimization circuit may be used in a variety of applications, particularly in phase-locked loop and frequency-locked loop VCOs. | 2008-11-20 |
20080284531 | FRACTIONAL-N SYNTHESIZED CHIRP GENERATOR - A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time. | 2008-11-20 |
20080284532 | VOLTAGE- AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT - An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor. | 2008-11-20 |
20080284533 | ELECTRICAL OSCILLATOR CIRCUIT AND AN INTEGRATED CIRCUIT - An electrical oscillator circuit comprising: a resonator comprised in the first subcircuit; and an active device comprised in the second subcircuit connected to energize the resonator to provide an oscillating electrical signal transmitted as a differential signal via electrical conductors to the second subcircuit. The oscillator is characterized in that the second subcircuit comprises means for receiving the differential signal transmitted via the electrical conductors and converting the differential signal to a single-ended signal with reference to the signal ground reference of the second subcircuit. Thereby a noise robust oscillator signal is provided with the use of very few components. Particularly suitable for oscillators embodied in an integrated circuit with the resonator mounted on a printed circuit board, PCB. And an integrated circuit. | 2008-11-20 |
20080284534 | OSCILLATOR - An oscillator is provided that includes a plurality of excitation units for providing an excitation signal and a tank as an oscillation generating unit for generating an oscillation signal in response to the excitation signal, whereby the tank has terminals for providing the oscillator signal, whereby each excitation unit has at least one inductor, whereby the tank is coupled magnetically to the at least one inductor of each excitation unit, and whereby the excitation signal can be transmitted between the excitation units and the tank by means of the magnetic coupling. | 2008-11-20 |
20080284535 | Two-level mounting board and crystal oscillator using the same - The present invention relates to a two-level mounting board in which a second substrate is supported horizontally by a metal pin above a first substrate having a mounting electrode on an outer base surface, the free, lower end of the metal pin is inserted in a hole provided in the surface of the first substrate, and the metal pin is affixed by solder to an annular electrode land provided on the surface of the first substrate to form an outer periphery of the hole, wherein part of the ring of the annular electrode land is cut away to open the same. This provides a two-level mounting board in which metal pins can be connected reliably to the first substrate to support the second substrate horizontally, and a crystal oscillator using the same. | 2008-11-20 |
20080284536 | Dual Mode Power Amplifier - A dual mode power amplifier can include a linear gain section and a non-linear gain section configured together as a polar amplifier. The dual mode power amplifier may be used to transmit GFSK, 4-DPSK, and 8-DPSK modulated data. In one mode, both non-linear and linear gain sections may be used to transmit 4-DPSK and 8-DPSK modulated data. Alternatively, in another mode, the linear gain section may be bypassed while the non-linear gain section may be used to transmit GFSK modulated data. By selecting the operating mode, the dual mode power amplifier may be advantageously configured to use relatively less power while supporting GFSK, 4-DPSK, and 8-DPSK modulation schemes. | 2008-11-20 |
20080284537 | Impedance Matching Network, and Plasma Processing Apparatus Using Such Impedance Matching Network - Provided is an impedance matching network having: an amplitude-adjusting variable capacitor and a phase-adjusting variable capacitor that are positioned between an input terminal and an output terminal, matching being achieved by adjustment of values of the variable capacitors; a first capacitor connected in series to one of the variable capacitors; a first switch connected in parallel to the one of the variable capacitors; and a unit operable to a) keep the first switch to an ON state while the input terminal does not receive RF power, and b) bring the first switch to an OFF state immediately after an initial start-up of a load connected to the output terminal after the input terminal has started to receive RF power. | 2008-11-20 |
20080284538 | PRINTED CIRCUIT BOARD - A printed circuit board includes a signal layer, a first reference plane layer, and a second reference plane layer. At least one transmission line is arranged on the signal layer. The transmission line includes a main transmission line, and two branch transmission lines connected to an end of the main transmission line. The first reference plane layer is disposed below the signal layer for the main transmission line. The second reference plane layer is disposed below the first reference plane layer for the branch transmission lines, to increase impedance of the two branch transmission lines. | 2008-11-20 |
20080284539 | HIGH FREQUENCY CIRCUIT, SEMICONDUCTOR DEVICE, AND HIGH FREQUENCY POWER AMPLIFICATION DEVICE - A small, high performance, multifunctional high frequency circuit that is multiband and multimode compatible reduces loss from a switch formed on the output side of a final stage amplification unit. The final stage amplification unit power amplifies an input signal and outputs an amplified signal. A first matching circuit impedance converts the amplified signal input thereto at a first input impedance, and outputs a first impedance-converted signal at a first output impedance. A control unit that generates a control signal denoting signal path selection information. A switch unit selects one of at least two signal paths based on the control signal, passes the first impedance-converted signal at an on impedance through the selected path, and outputs the pass signal. A second matching circuit impedance converts a pass signal input thereto at a second input impedance, and outputs a second impedance-converted signal at a second output. | 2008-11-20 |
20080284540 | ANTENNA DUPLEXER - An antenna duplexer is provided, which can be built with a smaller size and lower height than ever without compromising out-of-band attenuation characteristic and isolation characteristic between a transmit terminal and a receive terminal. The antenna duplexer includes a transmit filter provided between an antenna terminal and the transmit terminal, and a receive filter provided between the antenna terminal and the receive terminal. The filters are enclosed by a package, in which a ground pattern for the receive filter is separated from other ground patterns. | 2008-11-20 |
20080284541 | Bulk acoustic device and method for fabricating - A method for fabricating a bulk acoustic wave (BAW) device comprising providing a growth substrate and growing an Group-III nitride epitaxial layer on the growth substrate. A first electrode is deposited on the epitaxial layer. A carrier substrate is provided and the growth substrate, epitaxial layer and first electrode combination is flip-chip mounted on the carrier substrate. The growth substrate is removed and a second electrode is deposited on the epitaxial layer with the epitaxial layer sandwiched between the first and second electrodes. A bulk acoustic wave (BAW) device comprises first and second metal electrodes and a Group-III nitride epitaxial layer sandwiched between the first and second electrodes. A carrier substrate is included, with the first and second electrodes and epitaxial layer on the carrier substrate. | 2008-11-20 |
20080284542 | FILM BULK ACOUSTIC RESONATOR - A film bulk acoustic resonator includes: a substrate; a lower electrode held on the substrate with at least a portion thereof being in a hollow state; a piezoelectric film provided on the lower electrode; and an upper electrode provided on the piezoelectric film. At least one of the lower electrode and the upper electrode is primarily composed of copper (Cu) and further contains a first element having a negatively larger free energy of oxide formation (ΔG) than copper. At least one of the lower electrode and the upper electrode is primarily composed of copper (Cu) and further contains a second element having smaller surface energy than copper. | 2008-11-20 |
20080284543 | PIEZOELECTRIC THIN-FILM RESONATOR AND FILTER - A piezoelectric thin-film resonator includes: a lower electrode that is formed on a substrate; a piezoelectric film that is formed on the substrate and the lower electrode; an upper electrode that is formed on the piezoelectric film, with a portion of the piezoelectric film being interposed between the lower electrode and the upper electrode facing each other; and an additional film that is formed on the substrate on at least a part of the outer periphery of the lower electrode at the portion at which the lower electrode and the upper electrode face each other, with the additional film being laid along the lower electrode. | 2008-11-20 |