47th week of 2008 patent applcation highlights part 15 |
Patent application number | Title | Published |
20080283841 | TFT SUBSTRATE AND MANUFACTURING METHOD, AND DISPLAY DEVICE WITH THE SAME - In forming a TFT and a storage capacitance element, whereas sharing with each other the conductive film and the insulation film, which are components of the TFT and the storage capacitance element, contributes to improving production efficiency, it is difficult to obtain a storage capacitance element that is optimized independently of the TFT. A TFT substrate provided with a TFT and a storage-capacitance element according to the present invention is characterized in that the storage-capacitance element is obtained that includes an electrically conductive film and an insulation film each being different from those used in the TFT. Furthermore, in order to form such a structure, a method of manufacturing the TFT substrate is provided that achieves both flexibility in design and efficiency in production without need for addition of any photolithography processes. | 2008-11-20 |
20080283842 | METHOD FOR MAKING SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS OBTAINED BY THE METHOD, METHOD FOR MAKING THIN FILM TRANSISTOR SUBSTRATE AND THIN FILM TRANSISTOR SUBSTRATE OBTAINED BY THE METHOD, AND METHOD FOR MAKING DISPLAY APPARATUS AND DISPLAY APPARATUS OBTAINED BY THE METHOD - A method for making a semiconductor apparatus including the steps of: forming a laminate structure of an insulating film made of a metal oxide and a semiconductor thin film on a substrate; forming a light absorption layer on top of the laminate structure; and irradiating an energy beam of a wavelength capable of being absorbed by the light absorption layer on the light absorption layer and simultaneously crystallizing the insulating film and the semiconductor thin film by means of heat generated in the light absorption layer. | 2008-11-20 |
20080283843 | DISPLAY DEVICE AND ELECTRONIC DEVICE USING THIN-FILM TRANSISTORS FORMED ON SEMICONDUCTOR THIN FILMS WHICH ARE CRYSTALLIZED ON INSULATING SUBSTRATES - A method of receiving video data, a control signal, etc. via a non-contact transmission path is adopted, and a receiving circuit for receiving and amplifying a signal is formed on the same insulating substrate as a display device. Thus, there are provided a thin-film transistor which is formed in a semiconductor thin film that is formed on the insulating substrate and crystallized in a predetermined direction, and an inductor for forming an inductive-coupling circuit, which is formed by using an electrically conductive thin film provided on the insulating substrate. The direction of movement of carriers flowing in the thin-film transistor is parallel to the direction of crystallization of the semiconductor thin film, and the inductor and the thin-film transistor are integrated so as to be electrically coupled directly or indirectly. | 2008-11-20 |
20080283844 | Method for manufacturing a field effect transistor having a field plate - An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal. | 2008-11-20 |
20080283845 | Silicon carbide semiconductor device having high channel mobility and method for manufacturing the same - A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path. The channel area and the gate insulating film have an interface therebetween. The interface includes a dangling bond, which is terminated by a hydrogen atom or a hydroxyl. The interface has a hydrogen concentration equal to or larger than 2.6×10 | 2008-11-20 |
20080283846 | METHOD FOR GROWING SEMICONDUCTOR LAYER, METHOD FOR PRODUCING SEMICONDUCTOR LIGHT-EMITTING ELEMENT, SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND ELECTRONIC DEVICE - Disclosed herein is a method for growing a semiconductor layer which includes the step of growing a semiconductor layer of hexagonal crystal structure having the (11-22) or (10-13) plane direction on the (1-100) plane of a substrate of hexagonal crystal structure. | 2008-11-20 |
20080283847 | Integrated circuit package provided with cooperatively arranged illumination and sensing capabilities - An integrated circuit package includes an angled one-piece substrate having a light source fixed to one area and a sensor die fixed to a second area, such that the light source is directed to illuminate the field of view of the sensor die when a surface of interest is imaged. The integrated circuit package is well suited for generating navigation information regarding movement relative to a surface. In one method of forming the integrated circuit package, the single-piece substrate is originally a generally flat lead frame to which the sensor die and light source are attached. After the components have been connected, the lead frame is bent to provide the desired light source-to-sensor angle. In an alternative method, the lead frame is pre-bent. For either method, optics may be connected to the integrated circuit package, thereby providing a module that includes the optics, the light source, the sensor and the packaging body. | 2008-11-20 |
20080283848 | Semiconductor device and method for manufacturing the same - A plurality of rectangle semiconductor substrates are attached to a single mother glass substrate. A pixel structure is determined so that even if a gap or a an overlapping portion is generated in a boundary between a plurality of semiconductor substrates, a single-crystal semiconductor layer does not overlap with the gap or the overlapping portion. Two TFTs are located in a first unit cell including the first light emitting element, four TFTs are located in a second unit cell including the second light emitting element, and no TFT is located in a third unit cell including the third light emitting element. A boundary line is between the third unit cell and a fourth unit cell. | 2008-11-20 |
20080283849 | LED DEVICE AND METHOD BY WHICH IT IS PRODUCED - A LED device formed of LED chips bonded to an exoergic member by the LED chips being bonded to an Au—Sn alloy layer formed on an upper surface of the exoergic member with columnar crystals being formed within the Au—Sn alloy layer extending in a direction perpendicular to the upper surface of the exoergic member. The method of producing the LED device forms an Sn film directly on the upper surface of the exoergic member, an Au film on a lower surface of the LED chips, mounts the LED chips with the Au film thereon onto the Sn film formed on the upper surface of the exoergic member, and the exoergic member with LED chips mounted thereon is heated in an atmosphere in which a forming gas flows, so that the LED chips are bonded to the exoergic member. | 2008-11-20 |
20080283850 | Reflective Positive Electrode and Gallium Nitride-Based Compound Semiconductor Light-Emitting Device Using the Same - It is an object of the present invention to provide a gallium nitride-based compound semiconductor light-emitting device which has a highly reflective positive electrode that has high reverse voltage and excellent reliability with low contact resistance to the p-type gallium nitride-based compound semiconductor layer. | 2008-11-20 |
20080283851 | GaN Substrate, and Epitaxial Substrate and Semiconductor Light-Emitting Device Employing the Substrate - GaN substrate ( | 2008-11-20 |
20080283852 | Light-emitting device and a method for producing the same - A light-emitting device and a method to from the device are is described. The device described herein may realize the transversely single mode operation by the buried mesa configuration even when the active layer contains aluminum. The method provides a step to form the mesa on a semiconductor substrate with an average dislocation density of 500 to 5000 cm | 2008-11-20 |
20080283853 | Light-Emitting Diode, Light-Emitting Diode Substrate and Production Method of Light-Emitting Diode - The light-emitting diode is a light-emitting diode including a light-converting material substrate and a semiconductor layer formed on the light-converting material substrate, wherein the light-converting material substrate includes a solidified body in which at least two or more oxide phases selected from a simple oxide and a complex oxide are formed continuously and three-dimensionally entangled with each other, at least one oxide phase in the solidified body comprises a metal element capable of emitting fluorescence, and the semiconductor layer includes a plurality of compound semiconductor layers and has at least a light-emitting layer capable of emitting visible light. A light-emitting diode substrate forms a semiconductor, ensuring that the crystal-structure matching with a semiconductor for the formation of a light-emitting diode is good, a good semiconductor layer with less defects can be formed, good-efficiency light emission can be obtained from a light-emitting layer formed in the semiconductor layer, uniform florescence can be emitted by light from the light-emitting layer in the semiconductor layer, and light can be efficiently out put; and a color unevenness-free light-emitting diode using the substrate. | 2008-11-20 |
20080283854 | LIGHT EMITTING DIODE DEVICE LAYER STRUCTURE USING AN INDIUM GALLIUM NITRIDE CONTACT LAYER - A light emitting diode device layer structure including a p-type contact layer that contains at least some indium (In), wherein the p-type contact layer is a not-intentionally doped strained nitride contact layer. | 2008-11-20 |
20080283855 | Optoelectronic Thin-Film Chip - An optoelectronic thin-film chip is specified, comprising at least one radiation-emitting region ( | 2008-11-20 |
20080283856 | Light-emitting diode module and the manufacturing thereof - A method for manufacturing a light-emitting diode (LED) module is provided. Plural LED package structures are formed on a substrate first. A space is located between two adjacent LED package structures. A Lens laminated plate is subsequently bonded to the LED package structures. The lens laminated plate includes plural lenses, and each lens is located right above a LED of each LED package structure. Finally, plural LED modules are formed by cutting the substrate along the space. A LED module structure is also disclosed. | 2008-11-20 |
20080283857 | Novel phosphor for white light-emitting diodes and fabrication of the same - The present invention provides a light-emitting diode-converted phosphor compound having the following chemical formula: | 2008-11-20 |
20080283858 | LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING SAME - A light-emitting diode includes: a light-emitting structure, a transparent electrically conductive thick film, a first electrical contact and a second electrical contact. The light-emitting structure includes a first-type cladding layer, a second-type cladding layer, and an active layer sandwiched between the first-type cladding layer and the second-type cladding layer. The transparent electrically conductive thick film is formed on the first-type cladding layer. The first electrical contact is located on the transparent electrically conductive thick film. The second electrical contact is located on the second-type cladding layer. The transparent electrically conductive thick film is made from a metal-doped metal oxide. | 2008-11-20 |
20080283859 | LIGHT-EMITTING DIODE APPARATUS AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) apparatus includes an epitaxial multilayer, a micro/nano rugged layer and an anti-reflection layer. The epitaxial multilayer has a first semiconductor layer, an active layer and a second semiconductor layer in sequence. The micro/nano rugged layer is disposed on the first semiconductor layer of the epitaxial multilayer. The anti-reflection layer is disposed on the micro/nano rugged layer. In addition, a manufacturing method of the LED apparatus is also disclosed. | 2008-11-20 |
20080283860 | Light emitting device - A light emitting device includes an emission portion, an optical control portion for reflecting or refracting light emitted from the emission portion in a predetermined direction, a light guiding member including a light input surface to which the reflected or refracted light is inputted, a refection region formed on a surface thereof for reflecting the inputted light, and a light output surface for externally outputting the reflected light from the refection region, a reflection portion, on which the emission portion is mounted and which covers externally the refection region, for dissipating heat generated from the emission portion and for reflecting light passing through the refection region in a direction of the light output surface, and a space formed between the light guiding member and the reflection portion. | 2008-11-20 |
20080283861 | Power light emitting die package with reflecting lens and the method of making the same - A light emitting die package and a method of manufacturing the die package are disclosed. The die package includes a leadframe, at least one light emitting device (LED), a molded body, and a lens. The leadframe includes a plurality of leads and has a top side and a bottom side. A portion of the leadframe defines a mounting pad. The LED device is mounted on the mounting pad. The molded body is integrated with portions of the leadframe and defines an opening on the top side of the leadframe, the opening surrounding the mounting pad. The molded body further includes latches on the bottom side of the leadframe. The lens is coupled to the molded body. A composite lens is used as both reflector and imaging tool to collect and direct light emitted by LED(s) for desired spectral and luminous performance. | 2008-11-20 |
20080283862 | Side-emission type semiconductor light-emitting device and manufacturing method thereof - A side-emission type semiconductor light-emitting device | 2008-11-20 |
20080283863 | TRANSPARENT ELECTRODE - In order to emit a light from an electrode side, in semiconductor light emitting devices such as LED and the like, and liquid crystal, the electrode is formed of a transparent material so as to transmit a light through the transparent electrode and exit the light. A ZnO, which constitutes a material for the transparent electrode, is subject to erosion by acid and alkali, thus, as the case may cause loss of a reliability of the electrode under the influence of ion-containing moisture. In order to solve such a problem, this invention has as its aim a transparent electrode film provided with stability capable of preventing any degradation under the influence of any ion-containing moisture, while being kept acid-proof and alkali-proof. In order to accomplish the above-mentioned aim, this invention provides a transparent electrode made up of a ZnO as its main material, wherein its surface is covered with a Mg-doped ZnO film. | 2008-11-20 |
20080283864 | Single Crystal Phosphor Light Conversion Structures for Light Emitting Devices - Solid state light emitting devices include a solid state light emitting die and a light conversion structure. The light conversion structure may include a single crystal phosphor and may be on a light emitting surface of the solid state light emitting die. The light conversion structure may be attached to the light emitting surface of the solid state light emitting die via an adhesive layer. The light conversion structure may also be directly on a light emitting surface of the solid state light emitting die. Related methods are also disclosed. | 2008-11-20 |
20080283865 | III-Nitride Compound Semiconductor Light Emitting Device - The present invention relates a III-nitride compound semiconductor light emitting device in which a first layer composed of a carbon-containing compound layer, such as an n-type or p-type silicon carbide (SiC), silicon carbon nitride (SiCN) or carbon nitride layer (CN) layer, is formed on the p-type III-nitride semiconductor layer of the existing III-nitride semiconductor light emitting device, and a second layer composed of a III-nitride semiconductor layer with a given thickness is formed on the first layer. | 2008-11-20 |
20080283866 | Nitride semiconductor light-emitting device and method for producing same - In a method for producing a nitride semiconductor light-emitting device according to the present invention, first, a nitride semiconductor substrate having groove portions formed is prepared. An underlying layer comprising nitride semiconductor is formed on the nitride semiconductor substrate including the side walls of the groove portions, in such a manner that the underlying layer has a crystal surface in each of the groove portions and the crystal surface is tilted at an angle of from 53.5° to 63.4° with respect to the surface of the substrate. Over the underlying layer, a light-emitting-device structure composed of a lower cladding layer containing Al, an active layer, and an upper cladding layer containing Al is formed. According to the present invention, thickness nonuniformity and lack of surface flatness, which occur when accumulating a layer with light-emitting-device structure of nitride semiconductor over the nitride semiconductor substrate, are alleviated while inhibiting occurrence of cracking. | 2008-11-20 |
20080283867 | SEMICONDUCTOR DEVICE - A fourth semiconductor region of a first conduction type is provided in a partial region of a third semiconductor region of a second conduction type. This configuration enhances the blocking voltage at the time when the sheet carrier concentration of a fifth semiconductor region is enhanced. | 2008-11-20 |
20080283868 | Semiconductor Device - A semiconductor device includes a first layer having a first conductivity type, a second layer having a second conductivity type, a third layer having the second conductivity type, one or more first zones having the first conductivity type and located within the second layer, wherein each one of the one or more first zones is adjacent to the third layer, and one or more second zones having the second conductivity type and located within the second layer, wherein each one of the one or more second zones is adjacent to one or more of the one or more first zones. | 2008-11-20 |
20080283869 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - A method for manufacturing a semiconductor light emitting device, which is capable of providing high characteristic homogeneity and reproducibility, is disclosed. The disclosed method includes forming a buffer layer over a substrate, selectively growing a nitride crystal layer on the buffer layer, forming a nitride semiconductor layer having a multilayer structure over the nitride crystal layer, forming a first electrode on the nitride semiconductor layer, attaching an auxiliary substrate to the first electrode, separating the substrate from the nitride crystal layer, forming a second electrode on the nitride crystal layer exposed in accordance with the separation of the substrate, and removing the auxiliary substrate from the first electrode. | 2008-11-20 |
20080283870 | FIELD-EFFECT SEMICONDUCTOR DEVICE - A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on the main semiconductor region. Between these electrodes, with spacings therefrom, an insulator is provided with is made from a material capable of developing a stress to reduce carrier concentration in neighboring part of the two-dimensional electron gas layer, creating a discontinuity in this layer. A gate electrode overlies the insulator via a piezoelectric layer which is made from a material capable of developing, in response to a voltage applied to the gate electrode, a stress for canceling out the stress developed by the insulator. Thus the device is physically held off by the action of the insulator while no voltage is being impressed to the gate electrode and, upon voltage application thereto, piezoelectrically turns on by the action of the piezoelectric layer. The turn-on resistance of the device is relatively low as the insulator occupies only part of the source-drain spacing. | 2008-11-20 |
20080283871 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to the standard cell, the standard cell has: a p-type MOS transistor having first diffused regions and a first gate electrode; an n-type MOS transistor having second diffused regions and a second gate electrode with STI disposed for device isolation between the n-type MOS transistor and the p-type MOS transistor substantially in parallel with the first borderlines; dummy p-type MOS transistors having third gate electrodes disposed on the second borderlines so as to be adjacent to the first diffused regions of the p-type MOS transistor, the third gate electrodes being connected to power supply wiring so as to turn off the dummy p-type MOS transistors; and dummy n-type MOS transistors having fourth gate electrodes disposed on the second borderlines so as to be adjacent to the second diffused regions of the n-type MOS transistor, the fourth gate electrodes being connected to ground wiring so as to turn off the dummy n-type MOS transistors. | 2008-11-20 |
20080283872 | Variable path wiring cell, semiconductor integrated circuit designing method thereof, and forming method of variable path wiring cell - Provided are a first wiring layer where each of the first, second internally present wirings can be selectively connected to the first and the second externally extended wirings, and a second wiring layer that has substantially the same structure as that of the first wiring layer. There is further provided an interlayer contact layer which arbitrarily connects one of the first and the second internally present wirings on the first wiring layer to one of the first, second internally present wirings on the second wiring layer, and connects the remainder of the first and the second internally present wirings on the first wiring layer to the remainder of the first and the second internally present wirings on the second wiring layer. | 2008-11-20 |
20080283873 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via. | 2008-11-20 |
20080283874 | Field-Effect Transistors - The present invention provides a field-effect transistor and method for the fabrication of a field-effect transistor by deposition on a substrate ( | 2008-11-20 |
20080283875 | FIELD EFFECT TRANSISTOR, BIOSENSOR PROVIDED WITH IT, AND DETECTING METHOD - A high-sensitivity field effect transistor using as a channel ultrafine fiber elements such as carbon nanotube, and a biosensor using it. The field effect transistor comprises a substrate, a source electrode and a drain electrode arranged on the substrate, a channel for electrically connecting the source electrode with the drain electrode, and a gate electrode causing polarization due to the movement of free electrons in the substrate. For example, the substrate has a support substrate consisting of semiconductor or metal, a first insulating film formed on a first surface of the support substrate, and a second insulating film formed on a second surface of the support substrate, the source electrode, the drain electrode, and the channel arranged on the first insulating film, the gate electrode disposed on the second insulating film. | 2008-11-20 |
20080283876 | Noise detection circuit - Noise occurring in a circuit is more accurately detected. A low-pass filter ( | 2008-11-20 |
20080283877 | Strained-channel transistor device - Semiconductor device comprising at least:
| 2008-11-20 |
20080283878 | Method and Apparatus for Monitoring Endcap Pullback - Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders. | 2008-11-20 |
20080283879 | TRANSISTOR HAVING GATE DIELECTRIC LAYER OF PARTIAL THICKNESS DIFFERENCE AND METHOD OF FABRICATING THE SAME - A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates. | 2008-11-20 |
20080283880 | CMOS PIXEL SENSOR WITH DEPLETED PHOTOCOLLECTORS AND A DEPLETED COMMON NODE - An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output. | 2008-11-20 |
20080283881 | Image Sensor and Method for Manufacturing the Same - An image sensor according to one embodiment of the present invention includes a semiconductor substrate having a CMOS circuit formed therein; an interlayer dielectric layer formed on the semiconductor substrate and including a trench formed therein; a metal wiring and a first conductive layer formed within the trench of the interlayer dielectric layer; an intrinsic layer formed on the semiconductor substrate including the first conductive layer and the interlayer dielectric layer; and a second conductive layer formed on the intrinsic layer. | 2008-11-20 |
20080283882 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a compound semiconductor substrate; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially formed on the compound semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being a compound semiconductor; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The carrier density in the channel layer is inversely proportional to the third power of depth into the channel layer from a top surface of the channel layer, the channel layer has a uniform sheet carrier density, and the top surface of the channel layer has a dopant concentration in a range from 5.0×10 | 2008-11-20 |
20080283883 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same are provided. The image sensor can include transistor circuitry on a substrate, and a photodiode arranged above the transistor circuitry. The photodiode can include carbon nanotubes and a conductive polymer layer on the carbon nanotubes. A transparent conducting electrode can be provided on the carbon nanotubes. | 2008-11-20 |
20080283884 | CMOS IMAGE DEVICE WITH POLYSILICON CONTACT STUDS - A CMOS image device comprises a pixel array region including a photo diode region, a floating diffusion region, and at least one MOS transistor having a gate and a junction region, a CMOS logic region disposed around the pixel array region, the CMOS logic region including a plurality of nMOS transistors and pMOS transistors, and contact studs formed on the floating diffusion region and the junction region in the pixel array region, the contact studs comprising impurity-doped polysilicon layers. | 2008-11-20 |
20080283885 | Small pixel for CMOS image sensors with vertically integrated set and reset diodes - A pixel of an image sensor, the pixel includes a floating diffusion node to sense photo-generated charge, a reset diode to reset the floating diffusion node in response to a reset signal, and a set diode to set the floating diffusion node. | 2008-11-20 |
20080283886 | Small pixel for image sensors with JFET and vertically integrated reset diode - A pixel and a pixel array of an image sensor device of the present invention have small pixel sizes by resetting sensed charge using a diode built vertically above a substrate. The pixel and the pixel array also have low noise performance by using a JFET as a source follower transistor for sensing charge. The pixel includes a floating diffusion node configured to sense photo-generated charge, a reset diode configured to reset the floating diffusion node in response to a reset signal, and a junction field effect transistor configured to output a signal having an output voltage level corresponding to a charge level of the floating diffusion node. | 2008-11-20 |
20080283887 | CMOS Image Sensor - A method of fabricating a CMOS image sensor is disclosed, by which image sensor characteristics are enhanced. In one aspect, the method includes forming a plurality of photodiodes in the photodiode region of a semiconductor substrate; stacking a first insulating layer over the semiconductor substrate including the photodiodes; forming a metal pad on the insulating layer in the pad region of the substrate; forming a second insulating layer over the semiconductor substrate including the metal pad; selectively etching exposed portions of the second insulating layer, using a mask, to form simultaneously a pad opening in the pad region and a trench in the photodiode region; selectively etching portions of the second insulating layer and the first insulating layer under the trench; and forming a slope on lateral sides of at least the second insulating layer. | 2008-11-20 |
20080283888 | SPIN TRANSISTOR, PROGRAMMABLE LOGIC CIRCUIT, AND MAGNETIC MEMORY - A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers. | 2008-11-20 |
20080283889 | SEMICONDUCTOR DEVICE - The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between first and second potentials. Lower electrodes of the first and third capacitive elements are respectively formed by a common conductor pattern and coupled to the first potential. Lower electrodes of the second and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and coupled to the second potential. Upper electrodes of the first and second capacitive elements are respectively formed by a common conductor pattern and brought to a floating potential. Upper electrodes of the third and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and brought to a floating potential, but not coupled to the upper electrodes of the first and second capacitive elements by a conductor. | 2008-11-20 |
20080283890 | DEEP TRENCH INTER-WELL ISOLATION STRUCTURE - A deep trench is formed in a semiconductor substrate. The deep trench may comprise a pair of parallel substantially vertical sidewalls having a constant separation distance. A set of outer substantially vertical sidewalls may have a closed shape in a horizontal cross-section. At least one dielectric layer is formed in the deep trench. The deep trench is filled with at least one conductive trench fill material to form a conductive deep trench fill region. A shallow trench isolation structure is formed directly on the deep trench to encapsulate the conductive deep trench fill region therebeneath. The stack of the deep trench and the shallow trench isolation structure form a deep trench inter-well isolation structure that provides electrical isolation of devices on one side of the stack from devices on the other side. | 2008-11-20 |
20080283891 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure comprises a first wafer and a second wafer, between which a glue layer can be used for combination. The first wafer comprises a first semiconductor cell structure, and a surface of the first wafer comprises conductive pads electrically connected to the first semiconductor cell structure. The second wafer comprises a second semiconductor cell structure and is bonded to the surface of the first wafer having the conductive pads. The first and second semiconductor cell structures are electrically connected through the conductive pads, and the conductive pads are formed around each die of the first wafer. The density of the first semiconductor cell structure in the first wafer is larger than the density of the second semiconductor cell structure in the second wafer. | 2008-11-20 |
20080283892 | Cylinder-Type Capacitor and Storage Device, and Method(s) for Fabricating the Same - A one cylinder storage device and a method for fabricating a capacitor are disclosed, realizing simplified fabrication by overexposure with a mask having a plurality of holes, in which the method includes forming a contact hole in an insulating layer on a semiconductor substrate; forming a conductive layer on the insulating layer to fill the contact hole; forming a photoresist layer on the conductive layer; forming a photoresist layer pattern by overexposure and generating a side lobe phenomenon; forming a cylindrical lower electrode by patterning the conductive layer using the photoresist layer pattern as a mask; and forming a dielectric layer and an upper electrode covering the lower electrode. | 2008-11-20 |
20080283893 | ILLUMINATING EFFICIENCY-INCREASABLE AND LIGHT-ERASABLE EMBEDDED MEMORY STRUCTURE AND FABRICATING METHOD THEREOF - An illuminating efficiency-increasable and light-erasable embedded memory structure including a substrate, a memory device, many dielectric layers, many cap layers and at least three metal layers is described. The substrate includes a memory region and a core circuit region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have a first opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively. The metal layers are disposed in the dielectric layers in the core circuit region. | 2008-11-20 |
20080283894 | Forming floating body RAM using bulk silicon substrate - A method for forming Z-RAM cells and the resulting semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate; a dielectric layer on the semiconductor substrate; an opening in the dielectric layer, wherein the semiconductor substrate is exposed through the opening; a semiconductor strip on the dielectric layer and adjacent the opening; a gate dielectric over a surface of the semiconductor strip; a gate electrode over the gate dielectric; and a source/drain region in the semiconductor strip and adjacent the gate electrode. | 2008-11-20 |
20080283895 | Memory structure and fabricating method thereof - A memory structure including a substrate, dielectric patterns, spacer patterns, a first dielectric layer, a conductor pattern, a second dielectric layer and doped regions is described. The dielectric patterns are disposed on the substrate. The spacer patterns are disposed on each sidewall of each of the dielectric patterns respectively. The first dielectric layer is disposed between the spacer patterns and the substrate. The conductor pattern is disposed on the substrate and covers the spacer patterns. The second dielectric layer is disposed between the spacer patterns and the conductor pattern. The doped regions are disposed in the substrate under each of the dielectric patterns respectively. | 2008-11-20 |
20080283896 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH TWIN-WELL - A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well. | 2008-11-20 |
20080283897 | FLASH MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a flash memory device and a method for fabricating thereof. The device comprises a gate stack layer of a gate dielectric layer and a gate polysilicon layer formed on a substrate, a stack layer comprising a floating polysilicon layer and gate spacer formed on the sidewall of the gate stack layer. A metal layer is formed on the gate stack layer and is utilized in place of a portion of the gate polysilicon layer. Because the metal layer has relatively high conductivity and is electrically connected to a metal plug later formed, current velocity of the device is increased to improve performance. | 2008-11-20 |
20080283898 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction. | 2008-11-20 |
20080283899 | CONDUCTIVE SPACERS EXTENDED FLOATING GATES - A method for manufacturing on a substrate ( | 2008-11-20 |
20080283900 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a method of manufacturing a semiconductor device, which includes exposing a photoresist using an exposing mask provided with a light-shielding pattern having two or more narrow width portions, developing the photoresist to form a plurality of stripe-shaped resist patterns, selectively etching a first conductive film using the resist pattern as a mask, forming an intermediate insulating film on the first conductive film, forming a second conductive film on the intermediate insulating film, and forming, by patterning the first conductive film, the intermediate insulating film, and the second conductive film, a flash memory cell and a structure constructed by forming a lower conductor pattern, a segment of the intermediate insulating film, and a dummy gate electrode in this stacking order. | 2008-11-20 |
20080283901 | NONVOLATILE MEMORY WITH MULTIPLE BITS PER CELL - A dual-gate memory cell includes a first memory device and a second memory device each having a gate electrode and a charge storage gate dielectric layer. The first and second memory devices share a channel region and source and drain regions. Such a memory cell is read by sensing the charge in one of the dielectric layers by applying a first voltage in the gate electrode associated with the dielectric layer sensed, and applying a second voltage substantially different than the first voltage in the other dielectric layer. | 2008-11-20 |
20080283902 | Non-volatile memory device and method of manufacturing the same - A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components. | 2008-11-20 |
20080283903 | Transistor With Quantum Dots in Its Tunnelling Layer - According to an example embodiment there is a semiconductor component, which is arranged in a semiconductor body, with at least one source zone and with at least one drain zone which in each case is a first conductivity type, with at least one body zone of a second conductivity type arranged in each case between source zone and drain zone, and with at least one gate electrode insulated with an insulating layer relative to the semiconductor body. The insulating layer is a consolidated, preferably sintered, layer containing quantum dots. | 2008-11-20 |
20080283904 | TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME - A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a gate stacked on the gate oxide layer. A charge storage spacer stack is disposed at either side of the gate. The charge storage spacer stack includes a bottom charge storage layer and an upper spacer layer. An insulating layer is disposed between the charge storage spacer stack and the gate. A liner is disposed underneath the bottom charge storage layer. A source/drain region is disposed at one side of the bottom charge storage layer within the substrate. | 2008-11-20 |
20080283905 | Nonvolatile memory devices and methods of fabricating the same - Provided are nonvolatile memory devices and methods of fabricating the same which may prevent or reduce deterioration of device characteristics and deterioration of a breakdown voltage. The nonvolatile memory device may include a semiconductor substrate, a charge-trap insulation layer on the semiconductor substrate and having a first region and second regions having a lower density of charge-trap sites than the first region, and a gate electrode on the charge-trap insulation layer, wherein the first region is overlapped by the gate electrode and the second regions are outside of the first region. | 2008-11-20 |
20080283906 | SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS - A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder. | 2008-11-20 |
20080283907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided with first and second silicon pillars formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surfaces of the first and second silicon pillars via a gate insulation film, first and second diffusion layers provided on a lower part and an upper part of the first silicon pillar, respectively, a cap insulation film covering an upper part of the second silicon pillar, a gate contact connected to the gate electrode, and a protection insulation film in contact with the upper surfaces of the first and second silicon pillars. The gate contact is connected to an upper region of the gate electrode provided at the periphery of the cap insulation film. An opening is formed on the protection insulation film provided at the side of the first silicon pillar. | 2008-11-20 |
20080283908 | LATERAL DMOS DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - A lateral DMOS device having a structure that prevents breakdown of a semiconductor device while enhancing the breakdown voltage property. The lateral DMOS device can include a body diode region having a second conduction type well region formed in a first conduction type semiconductor substrate, the second conduction type well region including a first conduction type body region and a drain region each formed in the second conduction type well region, a first conduction type impurity region formed in the first conduction type body region, a source region formed in the first conduction type body region, and a gate insulating film and a gate electrode formed on the first conduction type semiconductor substrate, wherein the first conduction type body region and the second conduction type well region compose a body diode; and a protective diode region in which the first conduction type impurity region is formed at a prescribed interval, wherein the first conduction type body region and the second conduction type well region compose a protective diode. | 2008-11-20 |
20080283909 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate electrode buried in the trench via the gate insulating film, and a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region. c≧d is satisfied, where d is a depth from an upper surface of the first-conductivity-type source region to a lower end of the gate electrode, and c is a depth from an upper surface of the first-conductivity-type source region to a lower surface of the second-conductivity-type base region. | 2008-11-20 |
20080283910 | INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate. | 2008-11-20 |
20080283911 | High-voltage semiconductor device and method for manufacturing the same - A high-voltage semiconductor device and a method for manufacturing the same are disclosed. The disclosed high-voltage semiconductor device includes a semiconductor substrate, a first N type well in the semiconductor substrate, a first P type well in the first N type well, second N type wells in the first N type well along a periphery of the first P type well, a gate insulating film and a gate electrode on the first P type well, and first heavily-doped N type impurity regions in the first P type well at opposite sides of the gate electrode. | 2008-11-20 |
20080283912 | Semiconductor device having super junction structure and method of manufacturing the same - A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column layer, a plurality of source regions disposed at a surface portion of the channel-forming layer, and gate electrodes penetrate through the channel-forming layer. The PN column layer includes first columns having a first conductivity type and second columns having a second conductivity type which are alternately arranged in such a manner that the first columns contact the second columns on (111)-oriented surfaces, respectively. The gate electrodes are adjacent to the source regions, respectively, and each of the gate electrodes has side surfaces that cross the contact surfaces of the first columns and the second columns in a plane of the silicon substrate. | 2008-11-20 |
20080283913 | Semiconductor device - A semiconductor device includes a semiconductor substrate and a super junction structure on the substrate. The super junction structure is constructed with p-type and n-type column regions that are alternately arranged. A p-type channel layer is formed to a surface of the super junction structure. A trench gate structure is formed to the n-type column region. An n+-type source region is formed to a surface of the channel layer near the trench structure. A p+-type region is formed to the surface of the channel layer between adjacent n+-type source regions. A p-type body region is formed in the channel layer between adjacent trench gate structures and in contact with the p+-type region. Avalanche current is caused to flow from the body region to a source electrode via the p+-type region without passing through the n+-type source region. | 2008-11-20 |
20080283914 | Semiconductor device and method for manufacturing the same - An impurity buried layer constructed by two buried regions formed by impurities of identical type exist, a buried region formed by an impurity having a slow diffusion speed is provided on the entire surface of a transistor formation region, and a buried region formed by an impurity having a fast diffusion speed is provided inwardly from beneath the inside end of an isolation insulating film serving as a region on which an electric field concentrates partially. | 2008-11-20 |
20080283915 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a high voltage semiconductor device and a method of manufacturing the same. The high voltage semiconductor device includes: a semiconductor substrate; a first high voltage N-type well formed on the semiconductor substrate; a first high voltage P-type well formed inside the first high voltage N-type well; a second high voltage N-type well formed to surround the first high voltage P-type well inside the first high voltage N-type well; a gate dielectric layer and a gate electrode formed to be stacked on the upper of the first high voltage P-type well; and a first N-type high-concentration impurity region formed at both sides of the gate electrode in the first high voltage P-type well, wherein the concentration of the upper region of the first high voltage N-type well is lower than that of the lower region thereof, based on a portion formed with the first high voltage P-type well. Therefore, the present invention can apply bulk bias, simplify a process, improve punch through breakdown voltage in the P-type well formed inside a low-concentration deep N-type well, reduce field of a high-concentration N-type impurity region, and reduce resistance. | 2008-11-20 |
20080283916 | Semiconductor substrate, semiconductor device and manufacturing method thereof - It is an object to provide a method for manufacturing a semiconductor substrate in which contamination of a semiconductor layer due to an impurity is prevented and the bonding strength between a support substrate and the semiconductor layer can be increased. An oxide film containing first halogen is formed on a surface of a semiconductor substrate, and the semiconductor substrate is irradiated with ions of second halogen, whereby a separation layer is formed and the second halogen is contained in a semiconductor substrate. Then, heat treatment is performed in a state in which the semiconductor substrate and the support substrate are superposed with an insulating surface containing hydrogen interposed therebetween, whereby part of the semiconductor substrate is separated along the separation layer, so that a semiconductor layer containing the second halogen is provided over the support substrate. | 2008-11-20 |
20080283917 | METHODS FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING A MANDREL AND SEMICONDUCTOR STRUCTURES FORMED THEREBY - Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon of the body. The mandrel may be composed of porous silicon and the body may be fabricated using either a semiconductor-on-insulator substrate or a bulk substrate. The body may be used to fabricate a fin body of a fin-type field effect transistor. | 2008-11-20 |
20080283918 | Ultra Thin Channel (UTC) MOSFET Structure Formed on BOX Regions Having Different Depths and Different Thicknesses Beneath the UTC and SourceDrain Regions and Method of Manufacture Thereof - A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX | 2008-11-20 |
20080283919 | SINGLE AND DOUBLE-GATE PSEUDO-FET DEVICES FOR SEMICONDUCTOR MATERIALS EVALUATION - Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface. | 2008-11-20 |
20080283920 | HYBRID ORIENTED SUBSTRATES AND CRYSTAL IMPRINTING METHODS FOR FORMING SUCH HYBRID ORIENTED SUBSTRATES - A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided. | 2008-11-20 |
20080283921 | DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF - A dual-gate device includes an active layer between a first gate structure and a second gate structure. Each gate structure is isolated from the active layer by a dielectric layer and is located above a semiconductor or channel region in the active layer defined by spaced-apart diffusion regions formed by implanting antimony ions. The antimony-doped diffusion regions are particularly suitable in the dual-gate device because it can be implanted and activated at a temperature less than 900° C. and show little movement of the implanted antimony ions even after numerous thermal steps in the manufacturing process. As a result, dual-gate devices with well-controlled channel lengths may be achieved. | 2008-11-20 |
20080283922 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first conductivity type well formed on a semiconductor substrate, and a first transistor and a second transistor formed on the well. The first transistor has first pocket regions containing a first conductivity type impurity and first source/drain regions containing a second conductivity type impurity, and the second transistor has second pocket regions containing a first conductivity type impurity and second source/drain regions containing a second conductivity type impurity, and executes an analog function. A concentration of the first conductivity type impurity contained in the source-side and the drain-side second pocket regions is lower than a concentration of the first conductivity type impurity included in the first pocket regions. | 2008-11-20 |
20080283923 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost. | 2008-11-20 |
20080283924 | Semiconductor device and method for fabricating the same - The semiconductor device comprises a silicon wafer | 2008-11-20 |
20080283925 | Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement - In a first embodiment, a multi-fin component arrangement has a plurality of multi-fin component partial arrangements. Each of the multi-fin component partial arrangements has a plurality of electronic components, which electronic components have a multi-fin structure. At least one multi-fin component partial arrangement has at least one dummy structure, which at least one dummy structure is formed between at least two of the electronic components formed in the at least one multi-fin component partial arrangement. The dummy structure is formed in such a way that electrical characteristics of the electronic components formed in the multi-fin component partial arrangements are adapted to one another. | 2008-11-20 |
20080283926 | METHOD FOR INTEGRATING SILICON GERMANIUM AND CARBON DOPED SILICON WITHIN A STRAINED CMOS FLOW - The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate having a PMOS device region and NMOS device region. Thereafter, a first gate structure and a second gate structure are formed over the PMOS device region and the NMOS device region, respectively. Additionally, recessed epitaxial SiGe regions may be formed in the substrate on opposing sides of the first gate structure. Moreover, first source/drain regions may be formed on opposing sides of the first gate structure and second source/drain regions on opposing sides of the second gate structure. The first source/drain regions and second source/drain regions may then be annealed to form activated first source/drain regions and activated second source/drain regions, respectively. Additionally, recessed epitaxial carbon doped silicon regions may be formed in the substrate on opposing sides of the second gate structure after annealing. | 2008-11-20 |
20080283927 | Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit - System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment comprises manufacturing an integrated circuit, comprising forming a trench in an integrated circuit substrate, forming a cavity within the integrated circuit substrate, wherein the cavity is linked to the trench, depositing a dielectric layer within the cavity, and depositing polycrystalline silicon over the dielectric layer, wherein an inherent stress is induced in the polycrystalline silicon that grows on the dielectric layer. The dielectric layer may be, for example, silicon aluminum oxynitride (SiAlON), mullite (3Al | 2008-11-20 |
20080283928 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film formed on a first active region, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film formed on a second active region and made of an insulating material different from that of the first gate insulating film, and a second gate electrode formed on the second gate insulating film. Upper regions of the first gate electrode and the second gate electrode are electrically connected to each other on the isolation region located between the first active region and the second active region, and lower regions thereof are separated from each other with a sidewall insulating film made of the same insulating material as that of the first gate insulating film being interposed therebetween. | 2008-11-20 |
20080283929 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a p channel MOS transistor and an n channel MOS transistor each having a gate electrode made of metal on a gate insulating film made of oxide whose relative dielectric constant is higher than that of silicon oxide, threshold voltage thereof is reduced. A gate insulating film of a p channel MOS transistor and an n channel MOS transistor is made of hafnium oxide, a gate electrode of the p channel MOS transistor is made of ruthenium, and a gate electrode of the n channel MOS transistor is made of alloy containing ruthenium as a base material and hafnium. | 2008-11-20 |
20080283930 | EXTENDED DEPTH INTER-WELL ISOLATION STRUCTURE - By depositing and forming a spacer out of a semiconductor material layer or a dielectric material layer on the edges of an inter-well isolation area while forming a plug over an intra-well isolation area, a narrow intra-well isolation trench having a normal depth is formed in the intra-well isolation area, while a wider inter-well isolation trench having an extended portion is formed in the inter-well isolation area. The extended portion of the inter-well isolation trench provides enhanced inter-well isolation due to the presence of the extended portion beneath the normal depth. The extended portion of the inter-well isolation trench enables reduction of the width of the intra-well isolation trench structure relative to prior art inter-well isolation structures having a normal depth. | 2008-11-20 |
20080283931 | OTP memory cell, OTP memory, and method of manufacturing OTP memory cell - An OTP memory cell according to the present invention includes: a semiconductor substrate including a lower electrode forming region having a lower electrode formed therein, a diffusion layer forming region having a source and a drain formed therein, a first trench-type insulating region, and a second trench-type insulating region; an upper electrode being in contact with the first trench-type insulating region and formed on the lower electrode with the first insulating film interposed therebetween; and a gate electrode being in contact with the second trench-type insulating region and formed on a channel region with the second insulating film interposed therebetween, in which a shape of at least a part of an end of the lower electrode forming region in contact with the first insulating film is sharper than a shape of an end of the channel region in contact with the second insulating film. | 2008-11-20 |
20080283932 | Semiconductor Device Manufactured Using a Gate Silicidation Involving a Disposable Chemical/Mechanical Polishing Stop Layer - In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto. The bulk oxide layer and the CMP stop layer are removed with a CMP process to expose the top of gate electrodes and are removed from over the source/drain areas with a wet etch. The CMP stop layer has a CMP removal rate that is less than a CMP removal rate of the bulk oxide layer and has a wet etch removal rate that is greater than a wet etch removal rate of the blocking layer. | 2008-11-20 |
20080283933 | Oxygen-rich layers underlying BPSG - An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio. | 2008-11-20 |
20080283934 | SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD - A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance. | 2008-11-20 |
20080283935 | TRENCH ISOLATION STRUCTURE AND METHOD OF MANUFACTURE THEREFOR - The disclosure provides a trench isolation structure, a semiconductor device, and a method for manufacturing a semiconductor device. The semiconductor device, in one embodiment, includes a substrate having a first device region and a second device region, wherein the first device region includes a first gate structure and first source/drain regions and the second device region includes a second gate structure and second source/drain regions. The semiconductor device further includes a trench isolation structure configured to isolate the first device region from the second device region, the trench isolation structure comprising: 1) an isolation trench located within the substrate, wherein the isolation trench includes an opening portion and a bulbous portion, and further wherein a maximum width of the opening portion is less than a maximum width of the bulbous portion, and 2) dielectric material substantially filling the isolation trench. | 2008-11-20 |
20080283936 | SILICON GERMANIUM FLOW WITH RAISED SOURCE/DRAIN REGIONS IN THE NMOS - Provided is a method for manufacturing a semiconductor device that includes a substrate having a PMOS device region and NMOS device region. A first gate structure including a first hardmask and a second gate structure including a second hardmask are formed in the region and region, respectively. Epitaxial SiGe regions are created in the substrate proximate the first gate structure, the first hardmask protecting the first gate structure from the SiGe. First source/drain regions are formed proximate the first gate structure, at least a portion of each of the first source/drain regions located within one of the SiGe regions. Additionally, a raised portion is grown above the substrate proximate the second gate structure, the portion forming at least a part of second source/drain regions located on opposing sides of the second gate structure. Additionally, the first and second hardmasks protect the first and second gate structures from the growing. | 2008-11-20 |
20080283937 | Semiconductor Device and Method for Fabricating the Same - Provided are a semiconductor device and a method for fabricating the same. The semiconductor device can include a transistor structure, including a gate dielectric on a substrate, a gate electrode on the gate dielectric, a spacer at sidewalls of the gate electrode, and source/drain regions in the substrate; and an interlayer dielectric on the transistor structure where an air gap is provided in a region between the spacer, the interlayer dielectric, and the source/drain region of the substrate. | 2008-11-20 |
20080283938 | Semiconductor device and method for manufacturing the same - Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device may include a substrate having a plurality of isolation areas formed therein, the isolation areas defining an active region, a gate electrode formed on the active region, spacers formed on sides of the gate electrode, a source region formed in the substrate at a side of the spacer formed at a first side of the gate electrode, a drain region formed in the substrate at a side of the spacer formed on a second side of the gate electrode, and lightly doped drain regions formed in the substrate below the spacer. | 2008-11-20 |
20080283939 | DIELECTRIC-MODULATED FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - The present invention relates to a Field-Effect Transistor (FET) and, more particularly, to a Dielectric-Modulated Field-Effect Transistor (DMFET) and a method of fabricating the same. A DMFET according to an embodiment of the present invention comprises a substrate in which a source and a drain are formed, wherein the source and the drain are spaced apart from each other, a gate formed on a region between the source and the drain, of the substrate, wherein at least part of the gate is spaced apart from the substrate, biomolecules formed below a region spaced apart from the substrate, of the gate, and a linker for combining the gate and the biomolecules. | 2008-11-20 |
20080283940 | LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS - A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO | 2008-11-20 |