46th week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100289078 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In order to further improve a driving performance without increasing an element area in a lateral MOS having a high driving performance, in which a gate width is increased per unit area by forming a plurality of trenches horizontally with respect to a gate length direction, the semiconductor device includes: a well region which is formed of a high resistance first conductivity type semiconductor at a predetermined depth from a surface of a semiconductor substrate; a plurality of trenches which extend from a surface to a midway depth in the well region; a gate insulating film which is formed on surfaces of concave and convex portions formed by the trenches; a gate electrode embedded inside the trenches; a gate electrode film which is formed on the surface of the substrate in contact with the gate electrode embedded inside the trenches in regions of the concave and convex portions, the regions excluding vicinities of both ends of the trenches; another gate electrode film which is embedded inside the trenches in the vicinities of the both ends of the trenches in contact with the gate electrode film so that a surface of the another gate electrode film is located at a position deeper than the surface of the semiconductor substrate; and a source region and a drain region which are formed as two low resistance second conductivity type semiconductor layers formed from a part of the semiconductor surface, the part being out of contact with the another gate electrode film, so as to be shallower than the depth of the well region. | 2010-11-18 |
20100289079 | HIGH-VOLTAGE SOI MOS DEVICE STRUCTURE AND METHOD OF FABRICATION - Structures and methods for integrating a thick oxide high-voltage metal-oxide-semiconductor (MOS) device into a thin oxide silicon-on-insulator (SOI). A method of forming a semiconductor structure includes forming first source and drain regions of a first device below a buried oxide layer of a silicon-on-insulator (SOI) wafer, forming a gate of the first device in a layer of semiconductor material above the buried oxide layer; and forming second source and drain regions of a second device in the layer of semiconductor material above the buried oxide layer. | 2010-11-18 |
20100289080 | SEMICONDUCTOR DEVICE COMPRISING METAL GATES AND A SILICON CONTAINING RESISTOR FORMED ON AN ISOLATION STRUCTURE - In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure. | 2010-11-18 |
20100289081 | REDUCED SILICON THICKNESS OF N-CHANNEL TRANSISTORS IN SOI CMOS DEVICES - In sophisticated SOI devices, the thickness of the active semiconductor layer in the N-channel transistor may be reduced compared to the P-channel transistor for a given transistor configuration, thereby obtaining a significant increase in performance of the N-channel transistor without negatively affecting performance of the P-channel transistor. | 2010-11-18 |
20100289082 | ISOLATION WITH OFFSET DEEP WELL IMPLANTS - A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate. | 2010-11-18 |
20100289083 | MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMATION IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE - In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced. | 2010-11-18 |
20100289084 | SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor. | 2010-11-18 |
20100289085 | Asymmetric Semiconductor Devices and Method of Fabricating - A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the inventive asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the inventive asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high k gate dielectric, while in other embodiments, in which the first and second conductive spacers are comprised of different conductive materials, the base of the second conductive spacer is in direct contact with the threshold adjusting material. | 2010-11-18 |
20100289086 | Source/Drain Strained Layers - A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer. | 2010-11-18 |
20100289087 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor substrate with an active element formed in the semiconductor substrate, an element isolating insulating film formed around the active element and semiconductor substrate, a polysilicon resistance element formed over the element isolating insulating film with terminal areas and a resistance portion formed between the terminal areas, the polysilicon resistance element having plural reticulations which have the same shapes and the same size. | 2010-11-18 |
20100289088 | THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER - An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above. | 2010-11-18 |
20100289089 | ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION - Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. | 2010-11-18 |
20100289090 | ENHANCING UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING STI STRUCTURES AFTER THE GROWTH PROCESS - When forming sophisticated gate electrode structures of transistor elements of different type, the threshold adjusting channel semiconductor alloy may be provided prior to forming isolation structures, thereby achieving superior uniformity of the threshold adjusting material. Consequently, threshold variability on a local and global scale of P-channel transistors may be significantly reduced. | 2010-11-18 |
20100289091 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided with an SRAM cell unit. The SRAM cell unit is provided with a data storing section composed of a pair of drive transistors and a pair of load transistors; a data write section composed of a pair of access transistors; and a data read section composed of an access transistor and a drive transistor. Each of the transistors is provided with a semiconductor layer protruding from a base plane; a gate electrode extending on the both facing side planes over the semiconductor layer from above; a gate insulating film between a gate electrode and a semiconductor layer; and a source/drain region. Each semiconductor layer is arranged to have its longitudinal direction along a first direction. In the adjacent SRAM cell units in the first direction, all the corresponding transistors have the semiconductor layer of one transistor on a center line which is along the first direction of the semiconductor layer of the other transistor. | 2010-11-18 |
20100289092 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 2010-11-18 |
20100289093 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface. | 2010-11-18 |
20100289094 | ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY AN IN SITU ETCH PROCESS - When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack. | 2010-11-18 |
20100289095 | SEMICONDUCTOR DEVICE - The semiconductor device comprises a semiconductor chip defining a first face and a second face opposite to the first face, the semiconductor chip comprising at least one contact element on the first face of the semiconductor chip, an encapsulating body encapsulating the semiconductor chip, the encapsulating body having a first face and a second face opposite to the first face, a redistribution layer extending over the semiconductor chip and the first face of the encapsulating body and containing a metallization layer comprising contact areas connected with the contact elements of the semiconductor chip, and an array of external contact elements located on the second phase of the encapsulating body. | 2010-11-18 |
20100289096 | VIBRATING NANO-SCALE OR MICRO-SCALE ELECTROMECHANICAL COMPONENT WITH ENHANCED DETECTION LEVEL - A vibrating nano-scale or micro-scale electromechanical component including a vibrating mechanical element that cooperates with at least one detection electrode. The detection electrode is flexible and is configured to vibrate in phase opposition relative to the vibrating mechanical element. Such a component may find, for example, application to resonators or motion sensors. | 2010-11-18 |
20100289097 | Integrated Microphone - A method of forming a microphone having a variable capacitance first deposits high temperature deposition material on a die. The high temperature material ultimately forms structure that contributes to the variable capacitance. The method then forms circuitry on the die after depositing the deposition material. The circuitry is configured to detect the variable capacitance. | 2010-11-18 |
20100289098 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) device on a structure that includes a bottom cap layer and a bottom metal-filled trench having a normal axis, the magnetic tunnel junction device including a bottom electrode, magnetic tunnel junction layers, a magnetic tunnel junction seal layer, a top electrode, and a logic cap layer, the magnetic tunnel junction device having an MTJ axis that is offset from the normal axis. | 2010-11-18 |
20100289099 | INTEGRATION OF VACUUM MICROELECTRONIC DEVICE WITH INTEGRATED CIRCUIT - A device includes an integrated circuit (IC) and at least one ultra-small resonant structure formed on said IC. At least the ultra-small resonant structure portion of the device is vacuum packaged. The ultra-small resonant structure portion of the device may be grounded or connected to a known electrical potential. The ultra-small resonant structure may be electrically connected to the underlying IC, or not. | 2010-11-18 |
20100289100 | SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE, AND ELECTRONIC APPARATUS - Disclosed herein is a solid-state image pickup device including a solid-state image pickup element operable to produce an electric charge according to the amount of light received, a lens disposed on the upper side of a pixel of the solid-state image pickup element, a protective film which covers the upper side of the lens and a surface of which is flattened, and a surface film which is formed at the surface of the protective film and which is higher in hydrophilicity than the inside of the protective film. | 2010-11-18 |
20100289101 | IMAGE SENSOR - An image sensor including an array of pixels, wherein each pixel includes, in a vertical stack: a central photosensitive area; a stack of interconnects on top of the periphery of the photosensitive area, extending upwards up to a first height; a filtering layer on top of the photosensitive area, extending upwards from a height lower than the first height; and a microlens overlying the filtering layer in vertical projection, the optical axis of this microlens being such that the light rays received by the pixel reach the photosensitive area, substantially at its center. | 2010-11-18 |
20100289102 | METHOD OF MAKING DEEP JUNCTION FOR ELECTRICAL CROSSTALK REDUCTION OF AN IMAGE SENSOR - The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of sensor elements configured to receive light directed towards the back surface; and an aluminum doped feature formed in the substrate and disposed horizontally between two adjacent elements of the plurality of sensor elements and vertically between the back surface and the plurality of sensor elements. | 2010-11-18 |
20100289103 | PIN Photodiode and Light Reception Device - Among photodiodes used in an optical system for applying light to the entire chip, the conventional PIN photodiode has a problem that light should be applied only to a light reception surface in order to prevent degradation of light response and that positioning of the optical system is difficult. Moreover, in the mesa type PIN photodiode not requiring positioning of an optical system, disconnection failure is often caused by the mesa step. The present invention is made to solve the aforementioned problems, and its object is to provide a PIN photodiode having an improved light response and causing less disconnection failure of metal wiring and a light reception device using the PIN photodiode. The PIN photodiode of the present invention has a structure that the light reception surface is surrounded by a groove of a predetermined depth. | 2010-11-18 |
20100289104 | PHOTOSENSOR PACKAGE - A photosensor package includes a substrate assembly, a photosensor chip mounted at the substrate assembly, a solder ball to electrically connect the photosensor chip, the substrate assembly and a printed circuit board, and a passive device mounted at the substrate assembly. | 2010-11-18 |
20100289105 | Edge Illuminated Photodiodes - This invention comprises plurality of edge illuminated photodiodes. More specifically, the photodiodes of the present invention comprise novel structures designed to minimize reductions in responsivity due to edge surface recombination and improve quantum efficiency. The novel structures include, but are not limited to, angled facets, textured surface regions, and appropriately doped edge regions. | 2010-11-18 |
20100289106 | PHOTODIODE WITH INTERFACIAL CHARGE CONTROL AND ASSOCIATED PROCESS - A photodiode includes a first doped layer and a second doped layer that share a common face. A deep isolation trench has a face contiguous with the first and second doped layers. A conducting layer is in contact with a free face of the second doped layer. A protective layer is provided at an interface with the first doped layer and second doped layer. This protective layer is capable of generating a layer of negative charge at the interface. The protective layer may further be positioned within the second doped layer to form an intermediate protective structure. | 2010-11-18 |
20100289107 | PHOTODIODE WITH INTERFACIAL CHARGE CONTROL BY IMPLANTATION AND ASSOCIATED PROCESS - A photodiode includes a first doped layer and a second doped layer adjacent to the first doped layer and sharing a common face. A deep isolation trench is provided adjacent the photodiode having a face contiguous with the first doped layer and the second doped layer. A free face of the second doped layer is in contact with a conducting layer. A protective layer capable of generating a layer of negative charge is provided at the interface between, on one side, the first doped layer and the second doped layer and, on the other side, the deep isolation trench. | 2010-11-18 |
20100289108 | Silicon dioxide cantilever support and method for silicon etched structures - A semiconductor device includes a semiconductor layer ( | 2010-11-18 |
20100289109 | SCHOTTKY DIODES CONTAINING HIGH BARRIER METAL ISLANDS IN A LOW BARRIER METAL LAYER AND METHODS OF FORMING THE SAME - Fabrication of a Schottky diodes may include providing a Schottky contact layer containing a low barrier metal layer with spaced apart high barrier metal islands therein on a first surface of a substrate. A diode contact is formed on a second surface of the substrate that is opposite to the first surface. Formation of the Schottky contact layer may include providing a liquid mixture of a high barrier metal and a low barrier metal on the first surface of the substrate. Temperature and/or relative concentrations of the high and low barrier metals in the liquid mixture may be controlled to cause regions of the high barrier metal to solidify within the liquid mixture and agglomerate to form the spaced apart high barrier metal islands while inhibiting solidification of the low barrier metal. The temperature and relative concentrations may then be controlled to cause the low barrier metal to solidify and form the low barrier metal layer containing the high barrier metal islands. | 2010-11-18 |
20100289110 | SEMICONDUCTOR DEVICE - A semiconductor device using one or more guard rings includes a p-type guard ring region surrounding a pn junction region, an insulating film covering the p-type guard ring region, one or more conductive films electrically connected with the p-type guard ring region through one or more contact holes made in the insulating film, and a semi-insulating film covering the insulating film and the conductive films. Thus, a desired breakdown voltage characteristic can be ensured even if a foreign matter or the like adheres to a surface of the conductive films. | 2010-11-18 |
20100289111 | System and Method for Designing Cell Rows - A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row. | 2010-11-18 |
20100289112 | METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER - A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic. | 2010-11-18 |
20100289113 | FABRICATION PROCESS OF A HYBRID SEMICONDUCTOR SUBSTRATE - The present invention relates to a method for manufacturing a hybrid semiconductor substrate comprising the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby avoiding higher number of process steps involved in the manufacturing process of hybrid semiconductor substrate. | 2010-11-18 |
20100289114 | SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU DOPED SEMICONDUCTOR MATERIAL - The PN junction of a substrate diode in a sophisticated SOI device may be formed on the basis of an embedded in situ doped semiconductor material, thereby providing superior diode characteristics. For example, a silicon/germanium semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material. | 2010-11-18 |
20100289115 | SOI SUBSTRATE AND METHOD FOR MANUFACTURING SOI SUBSTRATE - An oxide film having a thickness “t | 2010-11-18 |
20100289116 | Selective Epitaxial Growth of Semiconductor Materials with Reduced Defects - A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material. | 2010-11-18 |
20100289117 | SHALLOW TRENCH ISOLATION STRUCTURE INCLUDING SECOND LINER COVERING CORNER OF TRENCH AND FIRST LINER - A STI structure disposed in a trench of a substrate is provided. The STI structure includes a first liner, a second liner and an insulation layer. The first liner is disposed on sidewalls of the trench, and a top of the first liner is lower than a surface of the substrate. The second liner covers the trench and the first liner. The second liner and the first liner may constitute with different materials. The insulation layer is disposed on the second liner to fill up the trench. | 2010-11-18 |
20100289118 | SEMICONDUCTOR DEVICE - A semiconductor device has an inductor. The inductor has a first metal interconnection layer formed in the insulation film to extend in a first direction which is parallel to a substrate face of the semiconductor substrate, and connected electrically at a first end part thereof to the first terminal; a first via interconnection formed in the insulation film to extend in a second direction perpendicular to the substrate face, and connected at a top part thereof to a second end part of the first metal interconnection layer; and a second metal interconnection layer formed in the insulation film to extend in the first direction under the first metal interconnection layer, facing to the first metal interconnection layer, insulated from the first metal interconnection layer by the insulation film, connected at a first end part thereof to a bottom part of the first via interconnection, and connected electrically at a second end part thereof to the second terminal. | 2010-11-18 |
20100289119 | INTEGRATED CAPACITOR - According to the preferred embodiment, an integrated capacitor having a key-shaped structure is provided. The integrated capacitor comprises a first pair of key-shaped metal patterns and a second pair of key-shaped metal patterns. The first pair of key-shaped metal patterns engages with the second pair of key-shaped metal patterns, and a dielectric layer is situated therebetween. | 2010-11-18 |
20100289120 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In a semiconductor device comprising a capacitive element, an area of the capacitive element is reduced without impairing performance, and further, without addition of an extra step in a manufacturing process. A first capacitor is formed between an active region of a semiconductor substrate provided through a first capacitive insulating film and a lower electrode comprised of a conductor film in the same layer as a select gate electrode of a select, a second capacitor is formed between the lower electrode, and an upper electrode comprised of a conductor film in the same layer as a memory gate electrode of a memory, provided through the second capacitive insulating film in the same layer as the insulating films of a multi-layer structure, including a charge storage layer, and a stacking-type capacitive element is comprised of the first capacitor and the second capacitor, wherein a planar shape of the lower electrode is a grid-like shape having a plurality of lengths of linear conductor films each having a first width, formed along a first direction with a first interval provided therebetween, and a plurality of lengths of linear conductor films each having a second width, formed along a second direction (the direction intersecting the first direction) with a second interval provided therebetween. | 2010-11-18 |
20100289121 | Chip-Level Access Control via Radioisotope Doping - A mechanism for changing the doping profile of semiconductor devices over time using radioisotope dopants is disclosed. This mechanism can be used to activate or deactivate a device based on the change in doping profile over time. The disclosure contains several possible dopants for common semiconductor substrates and discusses several simple devices which could be used to actuate a circuit. The disclosure further discloses a means for determining the optimal doping profile to achieve a transition in bulk electrical properties of a semiconductor at a specific time. | 2010-11-18 |
20100289122 | III-V NITRIDE SUBSTRATE BOULE AND METHOD OF MAKING AND USING THE SAME - A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 10 | 2010-11-18 |
20100289123 | METHOD FOR MAKING A SEMI-CONDUCTING SUBSTRATE LOCATED ON AN INSULATION LAYER - A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer. | 2010-11-18 |
20100289124 | Printable Semiconductor Structures and Related Methods of Making and Assembling - The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices. | 2010-11-18 |
20100289125 | ENHANCED ELECTROMIGRATION PERFORMANCE OF COPPER LINES IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY SURFACE ALLOYING - In sophisticated semiconductor devices, the electromigration performance of copper metal lines at the top interface thereof may be enhanced by forming a copper alloy that is locally restricted to the interface. To this end, an appropriate alloy-forming species, such as aluminum, may be provided on the basis of a non-masked deposition process and may be subsequently removed by a non-masked etch process, wherein the characteristic of the resulting alloy may be adjusted during an intermediate heat treatment. | 2010-11-18 |
20100289126 | Semiconductor Device and Method of Forming a 3D Inductor from Prefabricated Pillar Frame - A semiconductor device is made by mounting a semiconductor die over a carrier. A ferromagnetic inductor core is formed over the carrier. A prefabricated pillar frame is formed over the carrier, semiconductor die, and inductor core. An encapsulant is deposited over the semiconductor die and inductor core. A portion of the pillar frame is removed. A remaining portion of the pillar frame provides an interconnect pillar and inductor pillars around the inductor core. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors. In another embodiment, a shielding layer is formed over the semiconductor die. A capacitor or resistor is formed within the first or second interconnect structures. | 2010-11-18 |
20100289127 | SEMICONDUCTOR DEVICE - A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead. | 2010-11-18 |
20100289128 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND TRANSPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: conductively bonding a first surface of a transposer to an inner end of a lead separate from the transposer; conductively bonding a die to the first surface of the transposer; and encapsulating the inner end with a mold compound having a bottom mold surface that is exposed and is coplanar with a surface of the transposer opposite the first surface. | 2010-11-18 |
20100289129 | COPPER PLATE BONDING FOR HIGH PERFORMANCE SEMICONDUCTOR PACKAGING - A bonding plate forms high-performance, low-resistance interconnections between integrated circuit die and an electronic package lead frame. The bonding plate is made from copper, aluminum, or metalized silicon and is processed using standard semiconductor fabrication techniques to apply solder bumps and, optionally, copper pillars. The bonding plates are singulated from a wafer and applied to the die package using standard pick-and-place and solder reflow equipment and processes. This achieves high performance interconnect at low cost without the need for specialized tooling. | 2010-11-18 |
20100289130 | Method and Apparatus for Vertical Stacking of Integrated Circuit Chips - A method and apparatus for constructing a packaged integrated circuit stack | 2010-11-18 |
20100289131 | Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure - A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die. | 2010-11-18 |
20100289132 | SUBSTRATE HAVING EMBEDDED SINGLE PATTERNED METAL LAYER, AND PACKAGE APPLIED WITH THE SAME, AND METHODS OF MANUFACTURING OF THE SUBSTRATE AND PACKAGE - A substrate having single patterned metal layer applied in a package is provided. The substrate includes a first patterned dielectric layer, a patterned metal layer and a second patterned dielectric layer, wherein the patterned metal layer is embedded in the first patterned dielectric layer. Also, the top surfaces of the patterned metal layer and the first patterned dielectric layer lie in the same plane. At least part of the patterned metal layer are exposed from the holes formed on the lower surface of the first patterned dielectric layer, so as to form plural first contact pads for electrical connection downwardly. The second patterned dielectric layer, formed above the patterned metal layer and the first patterned dielectric layer, at least exposes part of the patterned metal layer to form plural second contact pads at the top surface of the patterned metal layer for electrical connection upwardly. | 2010-11-18 |
20100289133 | Stackable Package Having Embedded Interposer and Method for Making the Same - The present invention relates to a stackable package having an embedded interposer and a method for making the same. The package includes a substrate, a chip, a first embedded interposer, a circuit layer and a solder mask. The substrate has an upper surface, a bottom surface and at least one connecting pad. The connecting pad is disposed adjacent to the upper surface. The chip is disposed adjacent to the upper surface of the substrate, and is electrically connected to the substrate. The first embedded interposer encapsulates the upper surface of the substrate and the chip. The to first embedded interposer includes at least one plating through hole. The plating through hole penetrates through the first embedded interposer, and is connected to the connecting pad of the substrate. The circuit layer is disposed adjacent to the first embedded interposer, and the plating through hole is connected to the circuit layer. The circuit layer includes at least one pad. The solder mask is disposed adjacent to the circuit layer, and exposes the pad. Therefore, the package has more pads for inputting/outputting, more flexibility for stacking a top package, and a reduced total thickness. | 2010-11-18 |
20100289134 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH REINFORCED ENCAPSULANT HAVING EMBEDDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling stacking interconnects on the component side; and forming an integrated circuit receptacle, for receiving an integrated circuit device, by molding a reinforced encapsulant on the component side and exposing a portion of the stacking interconnects. | 2010-11-18 |
20100289135 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is disclosed. One embodiment provides at least one semiconductor chip including contact elements on a first surface of the chip. An encapsulation layer covers the semiconductor chip. A metallization layer is applied above the first surface of the chip and the encapsulation layer. The metallization layer includes contact areas connected with the contact elements of the chip. External pins are connected with the contact areas. | 2010-11-18 |
20100289136 | SEMICONDUCTOR PACKAGE - A semiconductor package comprises a semiconductor chip, through electrodes and cooling parts. The semiconductor chip has bonding pads on an upper surface thereof. The through-electrodes are formed in the semiconductor chip. The cooling parts are formed in the semiconductor chip and on the upper surface of the semiconductor chip in order to dissipate heat. | 2010-11-18 |
20100289137 | HEAT SINK PACKAGE - Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. | 2010-11-18 |
20100289138 | SUBSTRATE STRUCTURE FOR FLIP-CHIP INTERCONNECT DEVICE - An integrated circuit (IC) and a method of forming the device are provided. The device includes a substrate and a metal trace formed on the substrate, the metal trace including a bond area and a routing area. The routing area includes a rough surface for promoting adhesion to underfill of a flip-chip die. The flip-chip die can include a bump bond connected to the bond area of the metal trace. The underfill is between the substrate and an active surface of the flip-chip die, the rough surface of the routing area adhering to the underfill in the absence of a photo resist on the routing area of the metal trace. | 2010-11-18 |
20100289139 | HARDWIRED SWITCH OF DIE STACK AND OPERATING METHOD OF HARDWIRED SWITCH - A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided. | 2010-11-18 |
20100289140 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor device, and a wiring board where the semiconductor device is mounted. The semiconductor device includes a semiconductor substrate, a piercing electrode configured to pierce the semiconductor substrate and electrically connect the wiring board and the semiconductor device, and a ring-shaped concave part provided so as to surround the piercing electrode, the ring-shaped concave part being configured to open to a wiring board side of the semiconductor substrate. | 2010-11-18 |
20100289141 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that has a large number of external connection terminals. The package substrate includes a slot, the external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The bonding finger arrangement includes a first bonding finger array, which is located at a close distance from the each longer side of the slot, and a second bonding finger array, which is located at a distance farther than the distance of the first bonding finger array from the each longer side of the slot. The central section of the bonding finger area includes at least the second bonding finger array, and the end sections of the bonding finger area includes the first bonding finger array. | 2010-11-18 |
20100289142 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an interconnect to the substrate; encapsulating the interconnect with an encapsulation leaving a portion of the interconnect not encapsulated; attaching a joint to the interconnect and simultaneously creating a coined-surface of the interconnect contacting the joint; and attaching an integrated circuit to the substrate. | 2010-11-18 |
20100289143 | METHOD FOR PRODUCING LOW-k FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - Hydrophobicity of a low dielectric constant film comprising a porous silica film is improved by applying a raw material for forming a porous silica film onto a substrate, and performing vapor-phase transport treatment to expose the substrate to an atmosphere of organic amine vapor to which no water is added. Simultaneously, reduction in a dielectric constant, reduction in leakage current, and improvement in mechanical strength are attained by controlling a pore diameter in a predetermined range. | 2010-11-18 |
20100289144 | 3D INTEGRATION STRUCTURE AND METHOD USING BONDED METAL PLANES - A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer. | 2010-11-18 |
20100289145 | WAFER CHIP SCALE PACKAGE WITH CENTER CONDUCTIVE MASS - A method and structure for an unencapsulated wafer section such as a wafer chip scale package (WCSP) includes a plurality of interconnect terminals and a pad metallization structure on an active surface of a WCSP chip. An area of the pad metallization structure is larger than an area of one of the interconnect terminals and, in an embodiment, larger than an area of two interconnect terminals. A plurality of conductive interconnects are attached to the plurality of interconnect terminals. The conductive interconnects are placed in contact with first lands of a supporting substrate, which can be a printed circuit board. Subsequently, a conductive mass is electrically coupled with a second land of the receiving substrate, with the second land being connected to at least one via of the supporting substrate which can, in turn, be connected to a plane of the supporting substrate. Improved thermal characteristics can result. | 2010-11-18 |
20100289146 | Electronic System and Method for Manufacturing a Three-Dimensional Electronic System - A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a contact pad at a first main side of the first substrate; providing a second substrate with a main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area and the contact pad. | 2010-11-18 |
20100289147 | SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER - A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die. | 2010-11-18 |
20100289148 | SEMICONDUCTOR POWER MODULE - Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown. | 2010-11-18 |
20100289149 | SEMICONDUCTOR COMPONENT AND ASSUMBLY WITH PROJECTING ELECTRODE - A semiconductor component has a substrate and a projecting electrode on the substrate. The projecting electrode is configured suitably for electrically and mechanically connecting the semiconductor component to an external substrate. Furthermore, the projecting electrode is formed by a one-dimensional or two-dimensional array of projecting sub-electrodes, which are separated from each other by an electrically insulating fluid beginning from a substrate surface. The semiconductor component has an improved projecting-electrode. It provides the projecting electrode with a sub-structure, which achieves sufficient flexibility without introducing much constructive complexity and processing complexity during fabrication. | 2010-11-18 |
20100289150 | Semiconductor device, designing method for semiconductor device, computer-readable medium, and manufacturing method for semiconductor device - A designing method for a semiconductor device includes: determining a placement of metal wirings to be connected to contact holes and a placement of through-holes for preparing the contact holes. The determining step includes: specifying areas in one of the metal wirings to be exposed by the through-holes, specifying a capacitance of the metal wirings, and determining the placement of the metal wirings such that damage to the areas is suppressed in a case where electric charges accumulated in the capacitance are transferred from one of the metal wirings to a polar solvent through the areas. | 2010-11-18 |
20100289151 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lower-layer wire, an upper-layer wire including a wire portion and a first wide portion whose wire width is greater than the wire portion, and a contact formation portion in which a contact portion for connecting the lower-layer wire and the first wide portion with each other is provided. The contact formation portion has a planar shape of which a length L1 in a direction parallel to a wire width direction of the first wide portion is greater than a length L2 in a direction parallel to a wire length direction of the first wide portion. | 2010-11-18 |
20100289152 | Strip conductor structure for minimizing thermomechanocal loads - A semiconductor chip device including a surface on which at least one electrical contact surface is provided. A foil from an electrically insulating material is applied, especially by vacuum, to the surface and rests closely to the surface and adheres to the surface. The foil, in the area of the contact surface, is provided with a window in which the contact surface is devoid of the foil and is contacted across a large area to at least one layer from an electroconductive material. In at least one embodiment, the layer from the electroconductive material is part of a flexible contact for electrically connecting the contact surface to at least one external connecting conductor. | 2010-11-18 |
20100289153 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip is provided comprising a semiconductor substrate on which an integrated circuit is formed. The semiconductor chip, which is provided on the semiconductor substrate in an area array, further comprises a plurality of electrodes electrically coupled with the inside of the semiconductor substrate, wherein the electrodes are arranged into a plurality of first groups respectively lined along a plurality of paralleling first straight lines and, further, into a plurality of second groups respectively lined along a plurality of second straight lines which extend so as to intersect with the first straight lines. | 2010-11-18 |
20100289154 | METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING - A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element. | 2010-11-18 |
20100289155 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. The semiconductor device includes a semiconductor substrate and a penetration electrode penetrating the semiconductor substrate. A cavity part is formed in the semiconductor substrate to isolate the penetration electrode from the semiconductor substrate. A connection terminal is provided at a position where the connection terminal does not overlap the penetration electrode in a plan view. The connection terminal electrically connects the semiconductor device to the wiring board. | 2010-11-18 |
20100289156 | SEMICONDUCTOR DEVICE - According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area. | 2010-11-18 |
20100289157 | CIRCUIT BOARD HAVING BYPASS PAD - An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided. | 2010-11-18 |
20100289158 | ADHESIVE FILM, DICING DIE BONDING FILM AND SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to an adhesive film, a dicing die bonding film and a semiconductor device. More specifically, the adhesive film of the present invention is characterized by comprising a base film and an adhesive layer and having a yield strength of 20 to 50 gf and a slope of tensile elastic region of 30 to 80 gf/mm at a thickness of 5 to 50 μm. In the present adhesive film, the yield strength and the slope of tensile elastic region are controlled so that the incidence of burrs may be predicted and controlled depending on thickness of an adhesive layer. The dicing die bonding film, and the semiconductor device comprising the same have lower incidence of burrs and an excellent workability and reliability. | 2010-11-18 |
20100289159 | Semiconductor Die Collet and Method - Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the collet using a vacuum force. A pushing force is also exerted on the die adjacent to the applied vacuum force. The pushing force opposes flexion of the die in the direction of the vacuum force. In further steps, the die is placed on a die pad, and die attach adhesive is interposed between the die and the die pad. A preferred method includes applying a pushing force to bow the central region of the die toward the die pad. In a preferred apparatus of the invention, a collet has a body including a bearing surface for receiving a die and a vacuum for holding it. A chamber encompassed by the bearing surface is adapted for applying the force of expelled gas against a die borne on the bearing surface. The collet is configured for holding a die surface against the bearing surface and for simultaneously pushing outward on the center region of the die so held. | 2010-11-18 |
20100289160 | LENS SUPPORT AND WIREBOND PROTECTOR - A wirebond protector has an elongated shape that corresponds to the elongated array of wirebonds along the edge of a microelectronic device that connect a semiconductor die to electrical conductors on a substrate. In making the microelectronic device with wirebond protection, wirebonds are first formed in the conventional manner The wirebond protector is then attached to the device in an orientation in which it extends along the array of wirebonds to at least partially cover the wirebonds. | 2010-11-18 |
20100289161 | MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF SHAPED ARTICLE - There is provided a method of manufacturing a shaped article having a plurality of lens sections arranged one-dimensionally or two-dimensionally and a substrate section connecting the lens sections, the lens sections and the substrate section being integrally made of a resin material. The resin material is cured between a transfer surface of a first mold, which is fit to one side surface of the shaped article, and a transfer surface of a second mold which is fit to an opposite side surface of the shaped article. A space between the transfer surface of the first mold and the transfer surface of the second mold is narrowed in accordance with contraction of the resin material caused by the curing, and the transfer surface of the first mold and the transfer surface of the second mold are kept in tight contact with the resin material. | 2010-11-18 |
20100289162 | METHOD FOR MANUFACTURING OPTICAL WAVEGUIDE - A method for manufacturing an optical waveguide includes the steps of: A) forming a liquid-state resin mass by adding dropwise a liquid-state resin on an under-cladding layer; B) forming a liquid-state resin layer to cover cores by pressing a mold on the liquid-state resin mass and applying the liquid-state resin to be expanded on the under-cladding layer; and C) curing the liquid-state resin layer and then releasing the mold, wherein the liquid-state resin added dropwise has a viscosity of 500 to 2,000 mPa·s and the rate at which the liquid-state resin is applied to be expanded is 10 to 50 mm/s. | 2010-11-18 |
20100289163 | OPTICAL PART MANUFACTURING METHOD, MOLD MANUFACTURING METHOD, OPTICAL PART MANUFACTURING APPARATUS, AND MOLD MANUFACTURING APPARATUS - The present invention provides an optical part manufacturing method and an optical part manufacturing apparatus capable of manufacturing optical parts, whereby aligning an optical part with a bonded member and bonding the optical part and the bonded member can be accomplished successively, and a mold manufacturing method and a mold manufacturing apparatus capable of manufacturing a mold that is used to mold optical parts as above. A molding apparatus | 2010-11-18 |
20100289164 | ENCAPSULATION COMPOSITIONS AND PROCESS FOR PREPARING THE SAME - Encapsulation compositions in which an encapsulate (A) is encapsulated in a matrix (B) may be prepared by: | 2010-11-18 |
20100289165 | Granulation Process and Apparatus - A granulation process wherein a liquid is sprayed into a prilling tower ( | 2010-11-18 |
20100289166 | DROP PELLETIZING DEVICE AND METHOD FOR THE OPERATION THEREOF - A drop pelletizing device and method for producing pellets from a low-viscosity plastic melt are provided. The drop pelletizing device can include a die plate with holes, in which the plastic melt can be subjected to a harmonic pressure oscillation such that the plastic melt emerging from the holes forms individual pellet droplets, a pressure vessel, in which prevails an overpressure above the ambient pressure, a discharge device adapted to discharge the individual pellet droplets from the pressure vessel and to reduce the overpressure, a separator adapted to separate the individual pellet droplets from the coolant; and at least one circulating device adapted to agitate the coolant to separated and unclump the individual pellet droplets in the coolant and for producing turbulence within the coolant. | 2010-11-18 |
20100289167 | APPARATUS FOR PRODUCING POROUS BODY AND METHOD FOR PRODUCING POROUS BODY - An apparatus for producing a porous body that forms an expandable slurry containing at least inorganic powder, a foaming agent, and a binder into a sheet, causes the expandable slurry sheet to be foamed and baked, and thereby produces the porous body, the apparatus includes: a mixer preparing the expandable slurry by containing inorganic powder, a foaming agent, and a binder; a die-coater that has a discharge opening which discharges the expandable slurry provided from the mixer to an external thereof so as to shape the expandable slurry into a sheet; and a carrier sheet arranged so as to face the discharge opening of the die-coater with a gap interposed therebetween, and feeding the expandable slurry discharged from the discharge opening, wherein a flow path of the expandable slurry from inside the mixer to the discharge opening of the die-coater is hermetically sealed from an outside. | 2010-11-18 |
20100289168 | METHOD FOR MANUFACTURING FLEXIBLE AIR-CATHODE PLATE - A manufacturing method for a flexible air-cathode plate has steps of: mixing carbon powder and polytetrafluoroethylene solution to obtain a mixture; dehydrating the mixture by centrifuge to remove excess water; pressing the mixture to form a plate having a thickness of about 0.2 to 0.3 mm; cutting the plate into at least two plates; and mounting a collector grid between two plates of at least two plates and hot pressing them to obtain the flexible air-cathode plate. Since the flexible air-cathode plate can be curved, the flexible air-cathode plate can be used for a water battery. | 2010-11-18 |
20100289169 | Apparatus and method for dry forming a uniform non-woven fibrous web - An apparatus and method is disclosed for dry forming a uniform non-woven fibrous web. The apparatus includes a transport duct, a spreading member and a discharge member connected in series. The discharge member has a flexible plate and a plurality of screws which act upon the flexible plate to deflect its inner surface and provide further control of the basis weight of the to be formed fibrous web. The apparatus also has a forming zone located below the discharge member. The method combines a plurality of individual fibers with a pressurized gaseous stream and routes this stream through the apparatus to form the uniform non-woven fibrous web. | 2010-11-18 |
20100289170 | Apparatus and Method for Pelletizing Wax and Wax-Like Materials - An apparatus and method for the pelletization of waxes, wax-like and other materials having a sharp melt point include a vessel for forming the wax into a hot molten material. A heat exchanger then cools the molten wax to a temperature just above its melt temperature. The cooled liquid wax is fed to an extruder which further reduces the temperature and mixes the liquid wax into a thoroughly mixed extrudable solid wax. The solid wax is then extruded through die orifices of a die plate into a cutting chamber, and a rotary cutter cooperating with the die face of the die plate cuts the extruded solid wax strands into pellets. The die plate, cutting chamber and rotary cutter can have the same structure as an underwater pelletizer, but operating without water or liquid as a dry face pelletizer. The thus formed wax pellets drop out of the cutting chamber by gravity through an opening in the bottom thereof. | 2010-11-18 |
20100289171 | Apparatuses and Methods for Processing Doses of Flowable Material - An apparatus comprises an extruding device ( | 2010-11-18 |
20100289172 | PROCESS FOR PREPARING ETHYLENE-VINYL ALCOHOL COPOLYMER COMPOSITION, AND PROCESS FOR PRODUCING ETHYLENE-VINYL ALCOHOL COPOLYMER PELLETS - An ethylene-vinyl alcohol copolymer alcohol solution comprising an ethylene-vinyl alcohol copolymer and an alcohol having a carbon number of not greater than 4 is brought into contact with an aqueous solution of at least one additive selected from a carboxylic compound, a boron compound and a phosphoric compound to replace a part or all of the alcohol with water, whereby an ethylene-vinyl alcohol copolymer composition containing the additive is prepared. This preparation process makes it possible to efficiently replace the alcohol in the ethylene-vinyl alcohol copolymer alcohol solution with water, and homogeneously incorporate the thermal stabilizer in the composition. | 2010-11-18 |
20100289173 | METHOD AND ASSEMBLY FOR EXTRUDING A RUBBER COMPOUND - The invention relates to the extrusion of tire components with a large change of gauge across their cross-sectional area. It is provided a method and an assembly for extruding such a tire component with an extruder feeding a flow channel with a downstream die opening, whereby a deflector is provided in the flow channel upstream the die opening such that a flow of rubber is slowed down in front of broad portions of the cross-sectional area of the downstream die, avoiding distortion or bending of the extruded tire component. | 2010-11-18 |
20100289174 | METHOD FOR REMOVING DILUENT FROM A POLYMER EXTRUDATE, AND ITS APPLICATIONS - The invention relates to a method for removing a process solvent (P-sol) from a polymer extrudate, especially in connection with a process for producing a microporous membrane. The method involves contacting the extrudate with chlorinated hydrocarbon (CHC) and hydrofluoroether (HFE) in a first stage; contacting the extrudate from the first stage with HFE in a second stage; combining the first and second waste streams and then separating the P-sol from the combined streams to make an HFE-CHC stream; cooling the HFE-CHC stream to make an HFE-rich phase and a CHC-rich phase; and conducting the CHC-rich phase and/or the HFE-rich phase to step (A). | 2010-11-18 |
20100289175 | Procedure for Extrusion of Plastic Material and Extruder - The invention relates to a method for extruding plastic material using a screw-type extruder (S), wherein a first pressure (P | 2010-11-18 |
20100289176 | METHOD FOR MAKING MOLD - A method for making a mold, the method includes steps of: providing a substrate and a retaining member, the retaining member being made of polytetrafluoroethylene, and being ring-shaped; engaging the substrate with the retaining member; disposing viscous liquid polydimethyl siloxane containing material on the substrate within the retaining member; rotating the retaining member and the substrate to cause the polydimethyl siloxane containing material to spread out on the substrate and form a polydimethyl siloxane containing layer; press-molding the polydimethyl siloxane containing layer using a stamper to form one or more molding portions on the polydimethyl siloxane containing layer; solidifying the polydimethyl siloxane containing layer with the one or more molding portions; separating the stamper from the polydimethyl siloxane containing layer; and separating the substrate from the retaining member to obtain a mold. | 2010-11-18 |
20100289177 | Method for the production of shaped cellulose bodies - The present invention relates to a process for the production of cellulosic moulded bodies according to the amine-oxide process, comprising the following steps:
| 2010-11-18 |