46th week of 2011 patent applcation highlights part 59 |
Patent application number | Title | Published |
20110283008 | Video Class Room - A method, system, and computer program product for providing full two-way interaction among participants at a large number of locations. A method for providing presentation services may comprise receiving an audio stream and a plurality of video streams of a presentation, wherein at least some of the plurality of transmitted video streams have different frame rates, resolutions, or both, receiving an audio stream and a video stream of each of a plurality of participants to the presentation, selectively transmitting the audio stream and the plurality of video streams of the presentation and the audio stream and the video stream of each of the plurality of participants to a presentation location and to each of the plurality of participants. | 2011-11-17 |
20110283009 | NETWORK STREAMING OF A VIDEO STREAM OVER MULTIPLE COMMUNICATION CHANNELS - The present disclosure is directed to streaming a video from a sending endpoint to a receiving endpoint. Both of the sending endpoint and the receiving endpoint have multiple communication channels connecting the sending endpoint and the receiving endpoint to one or more networks, respectively, and the streaming video includes a plurality of intra-frame coded frames and a plurality of inter-frame coded frames. The sending endpoint sends different ones of the plurality of intra-frame coded frames and different ones of high priority inter-frame coded frames to the receiving endpoint over more than one of the multiple communication channels having a connection-oriented protocol. In addition, the sending endpoint sends different ones of non-high priority inter-frame coded frames to the receiving endpoint over more than one of the multiple communication channels having a connectionless-oriented protocol. | 2011-11-17 |
20110283010 | Method and system for validating interactive multimedia applications for use in enhanced or interactive television systems - Disclosed herein are embodiments of a computerized system and method of validating an application contained within a multimedia transport stream. Such embodiments can include the steps of, or structure for, reading data from a multimedia transport stream by a computer, the data representing an application that presents viewable content when executed by a display device and comprises a reference to an identifier of an external resource utilized by the application during execution; and prior to delivery of the multimedia transport stream to a display device, modifying the multimedia transport stream by the computer such that the external resource is not requested by the display device. In some embodiments, the transport stream is modified in response to the computer determining that the external resource is not available. | 2011-11-17 |
20110283011 | System, Apparatus for Content Delivery for Internet Traffic and Methods Thereof - In one embodiment, a method of serving media includes receiving user profiles from a layer3 node in an access network, and receiving a request to serve media content to a user equipment. The user profiles include information relating to user account and/or network characteristics of the user equipment. The method further includes using an user equipment information from the user profiles, assigning a first media server from a hierarchical set of media servers to serve the user equipment if the media content to be served is cacheable. The hierarchical set of media servers include a plurality of first type of media servers deployed in a plurality of layer2 (L2) access networks. The user equipment is coupled to a content delivery network through a layer2 access network of the plurality of layer2 access networks. | 2011-11-17 |
20110283012 | Adaptive Bitrate Management for Streaming Media Over Packet Networks - A method including providing pseudo-streaming media data to a terminal; receiving a transport control protocol (TCP) acknowledgement from the terminal; estimating one or more network conditions of a network based at least in part on the TCP acknowledgement; determining an optimal session bitrate based on the estimated one or more network conditions; and providing pseudo-streaming media data to the terminal based on the optimal session bitrate. | 2011-11-17 |
20110283013 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR STATELESS LOAD BALANCING OF NETWORK TRAFFIC FLOWS - Methods, systems, and computer readable media for performing stateless load balancing of network traffic flows are disclosed. According to one aspect, the subject matter described herein includes a method for performing stateless load balancing of network traffic flows. The method occurs at a layer 3 packet forwarding and layer 2 switching device. The method includes responding to address resolution protocol (ARP) requests from clients, the ARP requests including a virtual IP (VIP) address shared by the device and a plurality of servers coupled to the device, with the medium access control (MAC) address of the device. The method also includes receiving, from the clients, packets addressed to the VIP address and having the MAC address of the device. The method further includes load sharing the packets among the servers using a layer 3 forwarding operation that appears to the clients as a layer 2 switching operation. | 2011-11-17 |
20110283014 | Distribution of Multimedia Content over a Network - Performing transmission of data over network using at least a first and second rate adaptation algorithm. The transmission of data may use a plurality of buffers. It may be determined that a number of available buffers of the plurality of buffers is below a first threshold. Accordingly, data may be transmitted according to the second rate adaptation algorithm which provides increased flowrate. During the transmission of the data, it may be determined that the number of available buffers of the plurality of buffers exceeds a second threshold. Accordingly, data may be transmitted according to the first rate adaptation algorithm that provides increased throughput. | 2011-11-17 |
20110283015 | ADAPTIVE BITRATE MANAGEMENT FOR STREAMING MEDIA OVER PACKET NETWORKS - A method including receiving a receiver report from a terminal; estimating one or more network conditions of a media network based at least in part on the receiver report; determining an optimal session bitrate based on the estimated one or more network conditions; and providing media data to the terminal based on the optimal session bitrate. | 2011-11-17 |
20110283016 | LOAD DISTRIBUTION SYSTEM, LOAD DISTRIBUTION METHOD, APPARATUSES CONSTITUTING LOAD DISTRIBUTION SYSTEM, AND PROGRAM - A load distribution system that can further reduce load on a single apparatus and a network and that can distribute load for each process. The load distribution system of the present invention comprises: at least one packet forwarding apparatus comprising a packet forwarding unit that forwards a packet by using a forwarding rule sent from a flow control apparatus and a flow end check unit that detects a flow end; a load distribution apparatus that determines a load distribution destination from among a plurality of service provider servers by referring to a flow end notification sent from the flow control apparatus; and a flow control apparatus comprising a flow route setting unit that determines a forwarding route for a flow using a service provider server determined by the load distribution apparatus and notifies a packet forwarding apparatus on the forwarding route of a forwarding rule realizing the forwarding route and a flow end determination unit that notifies the load distribution apparatus of a flow end, based on flow end information detected by the packet forwarding apparatus. | 2011-11-17 |
20110283017 | Interconnecting Members of a Virtual Network - Computerized methods, systems, and computer-readable media are provided for establishing and managing a virtual network (V-net) and virtual machine (VM) switches that enable protected and isolated interconnections between members of the V-net. The V-net members include an originating network adapter that generates data packets addressed to a destination network adapter. Upon detecting data-packet generation, a source-side VM switch accesses a forwarding table associated with the V-net, ascertains a destination-side, VM-switch locator that corresponds to an identifier of the destination network adapter, and modifies the data packets to include the identifier. The forwarding table represents a mapping between the members of the V-net and VM switches located on respective nodes within the data center. In operation, the mapping enforces communication policies that govern data-packet traffic. Upon receiving the data packets, the destination-side VM switch restores the data packets and forwards them to the destination network adapter. | 2011-11-17 |
20110283018 | Method and apparatus for correlating nameserver IPv6 and IPv4 addresses - A method of correlating nameserver addresses is implemented in a multi-tier name server hierarchy comprising a first level authority for a domain, and one or more second level authorities to which the first level authority delegates with respect to a particular sub-domain associated with the domain. Preferably, the first level authority is IPv4-based and at least one second level authority is IPv6-based. The first level authority responds to a request issued by a client caching nameserver (a “CCNS”) and returns an answer that includes both IPv4 and IPv6 authorities for the domain. The CCNS is located at an IPv4 source address that is passed along to the first level authority with the CCNS request. According to a feature of this disclosure, the first level authority encodes the CCNS IPv4 source address in the IPv6 destination address of at least one IPv6 authority. Then, when the CCNS then makes a follow-on IPv6 request (with respect to the sub-domain) directed to the IPv6 authority, the IPv6 authority knows both the IPv6 address of the CCNS (by virtue of having received it in association with the request) as well as its IPv4 address (by virtue of the encoding). The IPv6 authority maintains the IPv4-IPv6 correlation. Over time (i.e., as other CCNSs make requests), the IPv6 authority builds up a database of these CCNS IPv6-IPv4 associations. | 2011-11-17 |
20110283019 | WEB-ENABLED MAINFRAME - According to one embodiment, a data sources interface of a mainframe receives a transaction request from a user terminal communicating through a network. The transaction request is formatted in a web-based format. A data sources function is called to instruct a mainframe application to perform the requested transaction, and the instruction to the mainframe is formatted in the native format of the mainframe. A transaction result formatted in the native format of the mainframe is received from the mainframe application. The transaction result is modified according to the web-based format to yield a data source, and the data source is sent to the user terminal. | 2011-11-17 |
20110283020 | METHOD AND SYSTEM FOR PHYSICAL LAYER AGGREGATION - Aspects of a method and system for physical layer aggregation are provided. A first portion of one or more circuits of a network device may be operable to implement media access control (MAC) functions, a second portion of the one or more circuits may be operable to perform physical layer aggregation, and a third portion of the one or more circuits may be operable to perform physical layer functions for communicating over a plurality of physical links. The first portion of the one or more circuits may be operable to encapsulate data into a packet comprising a preamble and convey the packet to the second portion of the one or more circuits. The second portion of the one or more circuits may be operable to fragment the packet into a plurality of fragment payloads and convey each of the fragment payloads to the third portion of the one or more circuits, wherein at least one of the plurality of fragment payloads comprises at least a portion of the preamble. The third portion of the one or more circuits may be operable to add a header to the fragment payloads to generate a corresponding plurality of fragments, and send the plurality of fragments over one or more of the plurality of physical links. | 2011-11-17 |
20110283021 | SYSTEMS AND METHODS FOR TRANSFORMATION OF LOGICAL DATA OBJECTS FOR STORAGE - Systems and methods for encrypting a plaintext logical data object for storage in a storage device operable with at least one storage protocol, creating, reading, writing, optimization and restoring thereof. Encrypting the plaintext logical data object comprises creating in the storage device an encrypted logical data object comprising a header and one or more allocated encrypted sections with predefined size; encrypting one or more sequentially obtained chunks of plaintext data corresponding to the plaintext logical data object thus giving rise to the encrypted data chunks; and sequentially accommodating the processed data chunks into said encrypted sections in accordance with an order said chunks received, wherein said encrypted sections serve as atomic elements of encryption/decryption operations during input/output transactions on the logical data object. | 2011-11-17 |
20110283022 | PROCEDES ET DISPOSITIFS DE SYNCHRONISATION, DANS UN RESEAU DE COMMUNICATION, POUR APPLICATIONS DE TYPE VENTE AUX ENCHERES EN TEMPS REEL - A synchronization method and device for implementing auction sale applications in a communication network using a server and at least one customer terminal. When receiving ( | 2011-11-17 |
20110283023 | METHODS AND SYSTEMS TO DYNAMICALLY MANAGE PERFORMANCE STATES IN A DATA PROCESSING SYSTEM - Data processing systems which operate in different modes, including a mode which supports providing an output of images through a port on the systems. In one embodiment, a data processing system includes a processing system, a cellular telephone transceiver, and a port which is configured to provide, as an output from the handheld data processing system, data representing movie video images. Methods and machine readable media are also described. | 2011-11-17 |
20110283024 | ELECTRONIC DEVICE WITH CARD INTERFACE - When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode. | 2011-11-17 |
20110283025 | MULTI-LEVEL PORT EXPANSION FOR PORT MULTIPLIERS - A port multiplier dynamically determines and reports its identity based on a number of supported downstream port connections. The number of supported downstream port connections can dynamically change. The port multiplier identifies devices connected to its downstream ports, whether storage devices or other port multipliers. Based on a total number of downstream ports, the port multiplier reports its identity upstream. The upstream reporting can be to another port multiplier, or the host device if directly connected to the host device. The port multiplier receives storage address space allocation from upstream based on its reported identity, and allocates the storage address space to its downstream ports. | 2011-11-17 |
20110283026 | METHOD AND APPARATUS FOR HBA MIGRATION - In one implementation, a system includes multiple SCSI nodes configured to perform a SCSI target function. Each of the multiple SCSI nodes includes a host bus adaptor configured to connect the SCSI node with a Fibre Channel fabric. The host bus adaptor being assigned a world wide name and a network address. The system further includes a host configured to perform a SCSI initiator function. The world wide name assigned to a source host bus adaptor associated with one SCSI node is relocated to a target host bus adaptor associated with another SCSI node. After that, the network address associated with the source host bus adaptor is relocated to the target host bus adaptor. In one implementation, the system determines whether or not a network address assigned to a source host bus adaptor associated with one of the multiple SCSI nodes is shared with at least one other service. If so, the system determined whether the shared network address can be relocated to a target host bus adaptor associated with another one of the multiple of SCSI nodes. If the latter determination is in affirmative, the world wide name and network address are relocated. | 2011-11-17 |
20110283027 | Automation Appliance and Method for Accelerated Processing of Selected Process Data - An automation appliance ( | 2011-11-17 |
20110283028 | IMPLEMENTING NETWORK MANAGER QUARANTINE MODE - A method and circuit for implementing a network manager quarantine mode in an interconnect system, and a design structure on which the subject circuit resides are provided. A respective network manager on a source interconnect chip and a destination interconnect chip sends end-to-end (ETE) heartbeats on each path between the source and destination interconnect chips. Each network manager maintains a heartbeat table with counters to track each path to each destination interconnect chip. When a first network manager of a first interconnect chip detects a change from at least one valid path to no working paths for a second interconnect chip of the interconnect chips, the quarantine mode is established for a programmable quarantine time interval and all paths are prevented from advertising good heartbeats during the quarantine time interval. | 2011-11-17 |
20110283029 | IMPLEMENTING ELECTRONIC CHIP IDENTIFICATION (ECID) EXCHANGE FOR NETWORK SECURITY - A method and circuit for implementing electronic chip identification (ECID) exchange for network security in an interconnect system, and a design structure on which the subject circuit resides are provided. Each interconnect chip includes an ECID for the interconnect chip, each ECID is unique and is permanently stored on each interconnect chip. Each interconnect chip sends predefined exchange identification (EXID) messages including the ECID across links to other interconnect chips in the interconnect system. Each interconnect chip compares a received EXID with a system list for the interconnect system to verify validity of the sending interconnect chip. | 2011-11-17 |
20110283030 | METHOD AND SYSTEM FOR MANAGING PULSE-WIDTH MODULATION - A host computer and a method for managing pulse-width modulation (PWM) include detecting a signal of a powerGD port. The management system further includes confirming a first state according to a first signal of the powerGD port. The management system further includes enabling the PWM port if the first state is in a power-on state, and disabling the PWM port if the first state is a power-off state. | 2011-11-17 |
20110283031 | SYSTEM ON CHIP AND OPERATING METHOD THEREOF - A system on chip comprises a bus electrically connected with a master intellectual property (IP) block, a slave IP block, and a default slave IP block. An IP block control part is configured to generate a control signal for activating or inactivating the slave IP block. When a call signal on the slave IP block is received from the master IP block, the bus is configured to transfer the received call signal to either one of the slave IP block and the default slave IP block according to the received call signal and the control signal. | 2011-11-17 |
20110283032 | ARBITRATION DEVICE - An arbitration device including: a first measuring circuit to measure a first period; a second measuring circuit to measure a second period; a second selection circuit to select and output the first period or the second period according to a first selection signal; a first control circuit to output the first selection signal according to the first period and the second period; a third selection circuit to select a third data or either the first data or the second data according to a second selection signal; a third measuring circuit to measure a third period; a fourth measuring circuit to measure a fourth period; and a second control circuit to output the second selection signal according to either the selected first period or the selected second period and the third period and the fourth period. | 2011-11-17 |
20110283033 | COMPUTER SYSTEM - A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor. | 2011-11-17 |
20110283034 | SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE AND SYSTEM EACH INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip includes a redistribution interconnect that is implemented by shorting bumps, and a semiconductor package and a system each including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a passivation film disposed on the semiconductor substrate, and a plurality of pseudo bumps disposed on the passivation film. Each pseudo bump is directly connected to adjacent pseudo bumps to form at least one redistribution interconnect. | 2011-11-17 |
20110283035 | Hybrid Storage System With Control Module Embedded Solid-State Memory - A hybrid control module includes a host interface control module configured to transfer data to and from a host interface. A first embedded multi-media card (eMMC) interface is configured to (i) connect to a second eMMC interface of a control module embedded solid-state memory (SSM) and (ii) transfer the data between the hybrid control module and the control module embedded SSM. A buffer management module is (i) in communication with the host interface control module, the first eMMC interface and a disk access control module and (ii) configured to buffer the data in volatile memory. The data is received by the buffer management module and from at least one of the host interface control module, the first eMMC interface, or the disk access control module. | 2011-11-17 |
20110283036 | Multi-Pass System and Method Supporting Multiple Streams of Video - Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data. | 2011-11-17 |
20110283037 | INFORMATION PROCESSING APPARATUS AND DATA TRANSFER METHOD - An object is to provide an information processing apparatus capable of improving the availability as a system while improving the reliability of a data transfer path and a data transfer method. An information processing apparatus has a data transfer path branching in a tree structure, from a root node to a plurality of nodes while communicably coupling therebetween and transmitting serial data between the root node and the plurality of nodes, including two internode data transfer paths provided between at least a pair of nodes of the plurality of nodes, through which serial data transfer is performed; and a routing processing unit provided to each terminal nodes that are the nodes on both ends of the internode data transfer path, transfers the return data from the transmission destination node to the transmission source node by using the same internode data transfer path as the internode data transfer path used for data transfer to the transmission destination node, when each of the terminal nodes transfers data received from any of another nodes being a transmission source to any of the nodes being a transmission destination via the other terminal node. | 2011-11-17 |
20110283038 | Information processing system, information processing device, control method for information processing device, and computer-readable recording medium - An information processing system including plural information processing devices multi-dimensionally connected with one another, where each of the information processing devices includes first and second receiving storage devices to store data allocated to first and second virtual channels in respective data transmitting and receiving directions, a virtual channel control unit to compare a position in a dimension of a destination information processing device with a position in the same dimension of an own information processing device, and if the comparison result indicates that the position of the own information processing device matches a position one information processing device before the position of the destination information processing device, change one of the first and the second virtual channels to the other one, and a data storage unit to store the allocated data in a corresponding one of the first and second storage devices. | 2011-11-17 |
20110283039 | SEMICONDUCTOR DEVICE - To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller. | 2011-11-17 |
20110283040 | Multiple Page Size Segment Encoding - An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field. | 2011-11-17 |
20110283041 | CACHE MEMORY AND CONTROL METHOD THEREOF - A cache memory comprises a data array that stores a cashed block; a first address array that stores an address of the cached block; a second address array that stores an address of a first block to be removed from the data array when a cache miss occurs; and a control unit that transmits to a processor the first block stored in the data array as a cache hit block, when the address stored in the second address array results in a cache hit during a period before a second block which has caused the cache miss is read from a memory and written into the data array. | 2011-11-17 |
20110283042 | Transaction splitting apparatus and method - A transaction splitting apparatus and method are provided in which neighboring sub-transactions accessing a predetermined bank in each memory may access different banks. The transaction splitting apparatus includes a first processing unit to split a transaction into at least one sub-transaction, the transaction accessing a first bank among a plurality of banks comprised in a memory, and a second processing unit to translate an address of the at least one sub-transaction, to interleave the at least one sub-transaction using the plurality of banks. | 2011-11-17 |
20110283043 | LARGE CAPACITY SOLID-STATE STORAGE DEVICES AND METHODS THEREFOR - Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks. | 2011-11-17 |
20110283044 | DEVICE AND METHOD FOR RELIABLE DATA STORAGE - A data storage device comprising at least one non-volatile storage medium having a plurality of data blocks, and a controller configured to allocate at least one of the data blocks for a writing operation based at least in part on data integrities of the data blocks. | 2011-11-17 |
20110283045 | EVENT PROCESSING IN A FLASH MEMORY-BASED OBJECT STORE - Approaches for processing an event in an objects store, such as an MySQL database management system or a memcached caching system, that are maintained on one or more solid state devices. A plurality of threads may be instantiated. Each of the threads may be configured to retrieve items from a queue of items. Each item in the queue of items may be associated with a particular event occurring within the object store. Each event is a message that indicates an activity requiring work has occurred within the object store. When a particular thread retrieves an item from the queue of items, the particular thread processes the particular event associated with the item retrieved by the particular thread. In this way, event handling in object stores such as MySQL and memcached may be performed more efficiently on a solid state device. | 2011-11-17 |
20110283046 | STORAGE DEVICE - The present invention aims to improve the performance of accessing flash memory used as a storage medium in a storage device. In the storage device in accordance with the present invention, a storage controller, before accessing the flash memory, queries a flash controller as to whether the flash memory is accessible (see FIG. | 2011-11-17 |
20110283047 | HYBRID STORAGE SYSTEM FOR A MULTI-LEVEL RAID ARCHITECTURE - Embodiments of the present invention provide a hybrid storage system for a multi-level RAID architecture. Specifically, embodiments of this invention provide a hybrid RAID controller coupled to a system control board. Coupled to the hybrid RAID controller are a DDR RAID controller and a HDD/Flash RAID controller. A set of DDR RAID control blocks are coupled to the DDR RAID controller, each of the set of DDR RAID control blocks include a set of DDR memory disks. Further, a set of HDD RAID control blocks are coupled to the HDD/Flash RAID controller, each of the set of HDD RAID control blocks include a set of HDD/Flash SSD Units. | 2011-11-17 |
20110283048 | STRUCTURED MAPPING SYSTEM FOR A MEMORY DEVICE - This disclosure is related to systems and methods for a structured mapping system for a memory device, such as a solid state data storage device. In one example, a data storage device may include a multi-level address mapping system. The multi-level address mapping system may be implemented completely independent of a host computer and a host computer operating system. Also, the multi-level mapping system may be stored to allow each level, or subsets of each level, to be re-written independently of the other levels or the other subsets. | 2011-11-17 |
20110283049 | SYSTEM AND METHOD FOR MANAGING GARBAGE COLLECTION IN SOLID-STATE MEMORY - Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection to maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. When garbage collection is performed, the controller selects a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. The pools facilitate the optimal or near-optimal selection of garbage collection candidate blocks in an efficient manner and the data structure of the pools can be implemented with bitmasks, which take minimal space in memory. | 2011-11-17 |
20110283050 | MEMORY BUFFER HAVING ACCESSIBLE INFORMATION AFTER A PROGRAM-FAIL - Subject matter disclosed herein relates to a memory device, and a method of operating same, including a memory buffer to maintain information to be available after a failure to program the information to a memory array. | 2011-11-17 |
20110283051 | MOVING EXECUTABLE CODE FROM A FIRST REGION OF A NON-VOLATILE MEMORY TO A SECOND REGION OF THE NON-VOLATILE MEMORY - A data storage device includes a controller and a non-volatile memory coupled to the controller. The non-volatile memory includes executable boot code that is executable by a processor associated with the data storage device. The controller is configured to read a first portion of the executable boot code from a first region of the non-volatile memory, and in response to detecting a condition, move a second portion of the executable boot code in a second region of the non-volatile memory to a third region of the non-volatile memory. | 2011-11-17 |
20110283052 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - The object of the present invention is to efficiently perform access to a physical block corresponding to a logical block often designated by an access request. To realize it, predetermined number of pieces of logical block information each for access to a physical block corresponding to logical block, until then, designated by an access request is held. In holding the predetermined pieces of logical block information, a piece of logical block information having high priority precede a piece of logical block information having low priority in priority order. In management of the priority order, priority of a piece of logical block information corresponding to a logical block often designated by an access request becomes high. When an access request is received, if logical block information corresponding to the logical block designated by the access request is held, access to the physical block corresponding to the designated logical block is performed based on the held logical block information. | 2011-11-17 |
20110283053 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory device that stores information includes: a flash memory that is managed by a predetermined file system having a parameter dependent on the semiconductor memory device; a rewrite frequency storage unit that stores a rewrite frequency of the flash memory; an ID detection unit that detects whether or not first identification information associated with the rewrite frequency is stored in the flash memory as the parameter; and a control unit that, when the ID detection unit detects that the first identification information is stored, reflects the rewrite frequency stored in the rewrite frequency storage unit, on a storage area corresponding to the first identification information. | 2011-11-17 |
20110283054 | NONVOLATILE MEMORY - For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series. | 2011-11-17 |
20110283055 | Exclusive-Option Chips and Methods with All-Options-Active Test Mode - A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles. | 2011-11-17 |
20110283056 | INFORMATION MANAGEMENT APPARATUS AND INFORMATION MANAGING METHOD - An information management apparatus for managing data includes a rewritable nonvolatile memory, and a memory controller configured to control inputting information into and outputting information from the nonvolatile memory. The memory controller overwrites a data, which includes a first validity check information, a first data body, a second validity check information, a second data body having the same data as the first data body and a third validity check information arranged in this order, in a designated address area in the nonvolatile memory when the memory controller performs a writing control in which the memory controller writes data in the nonvolatile memory. | 2011-11-17 |
20110283057 | Microcontroller Programmable System on a Chip - Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks. | 2011-11-17 |
20110283058 | STORAGE APPARATUS AND METHOD OF MANAGING DATA STORAGE AREA - To extend endurance and reduce bit cost, a method and a storage apparatus are provided, which storage apparatus includes a controller and a semiconductor storage media that includes a first storage device and a second storage device having an upper limit of an erase count of data smaller than the first storage device. Area conversion information includes correspondence of a first address to be specified as a data storage destination and a second address of an area in which data is to be stored. A rewrite frequency of stored data is recorded for each area. The controller selects an area corresponding to the first address, determines whether or not the rewrite frequency of the selected area is equal to or larger than a first threshold value, when the rewrite frequency is equal to or larger than the threshold value, selects an area to be provided by the first storage device, and when the rewrite frequency is smaller than the threshold value, selects an area to be provided by the second storage device and maps the address of the selected area to the first address. | 2011-11-17 |
20110283059 | TECHNIQUES FOR ACCELERATING COMPUTATIONS USING FIELD PROGRAMMABLE GATE ARRAY PROCESSORS - Various embodiments are disclosed for accelerating computations using field programmable gate arrays (FPGA). Various tree traversal techniques, architectures, and hardware implementations are disclosed. Various disclosed embodiments comprise hybrid architectures comprising a central processing unit (CPU), a graphics processor unit (GPU), a field programmable gate array (FPGA), and variations or combinations thereof, to implement raytracing techniques. Additional disclosed embodiments comprise depth-breadth search tree tracing techniques, blocking tree branch traversal techniques to avoid data explosion, compact data structure representations for ray and node representations, and multiplexed processing of multiple rays in a programming element (PE) to leverage pipeline bubble. | 2011-11-17 |
20110283060 | Maintenance Operations in a DRAM - A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order. | 2011-11-17 |
20110283061 | UPDATING CAM ARRAYS USING PREFIX LENGTH DISTRIBUTION PREDICTION - A method and apparatus for ordering a plurality (P) of entries having various prefix lengths for storage in a number (T) of available storage locations in a content addressable memory (CAM) array according to the prefix lengths is disclosed. Initially, a first number (N) of the entries of selected and used to generate a distribution graph of their prefix lengths. Then, for each unique prefix length, a corresponding subset of the T storage locations in the CAM array are allocated according to a predicted prefix length distribution indicated by the distribution graph. Then, all of the entries are stored in the corresponding allocated storage locations according to prefix length. | 2011-11-17 |
20110283062 | STORAGE APPARATUS AND DATA RETAINING METHOD FOR STORAGE APPARATUS - To enable reduction of the data capacity while inhibiting degradation of read performance. | 2011-11-17 |
20110283063 | DISK ARRAY DEVICE, A DISK ARRAY DEVICE CONTROL METHOD AND A DISK ARRAY DEVICE CONTROL PROGRAM - A disk array device includes a control unit which sends and receives a command and data to/from a host device, and in case a first disk device which constitutes RAID is stopped, controls so that data which is to be written from the host device to the stopped first disk device is written to a second disk device different from the first disk device. | 2011-11-17 |
20110283064 | STORAGE APPARATUS AND DATA STORAGE METHOD USING THE SAME - A storage apparatus comprises a disk device and a disk adapter for controlling the disk device. The disk adapter controls the disk device and forms a data volume and a pool volume, creates a data block for parity data, compresses write data and the created parity data, and stores a number of compressed data blocks equal to or less than a predetermined number and stores compressed parity data that are within a predetermined size in storage areas in an actual volume, and stores the remaining compressed data blocks of a number greater than the predetermined number and compressed parity data that exceed the predetermined size in storage areas in the pool volume corresponding to a virtual volume. | 2011-11-17 |
20110283065 | Information Processing Apparatus and Driver - According to one embodiment, an information processing apparatus includes a memory includes a buffer area, a first storage, a second storage and a driver. The buffer area is reserved in order to transfer data between the driver and a host system that requests for data writing and data reading. The driver is configured to write data into the second storage and read data from the second storage using the first external storage as a cache for the second storage. The driver is further configured to reserve a cache area in the memory, between a buffer area and the first external storage, and between a buffer area and the second storage. | 2011-11-17 |
20110283066 | Information Processing Apparatus and Driver - According to one embodiment, an information processing apparatus includes a memory includes a buffer area, a first storage, a second storage and a driver. The buffer area is reserved in order to transfer data between the driver and a host system that requests for data writing and data reading. The driver is configured to write data into the second storage and read data from the second storage in units of predetermined blocks using the first storage as a cache for the second storage. The driver is further configured to reserve a cache area in the memory, between the buffer area and the first external storage, and between the buffer area and the second storage. The driver is further configured to manage the cache area in units of the predetermined blocks. | 2011-11-17 |
20110283067 | Target Memory Hierarchy Specification in a Multi-Core Computer Processing System - Target memory hierarchy specification in a multi-core computer processing system is provided including a system for implementing prefetch instructions. The system includes a first core processor, a dedicated cache corresponding to the first core processor, and a second core processor. The second core processor includes instructions for executing a prefetch instruction that specifies a memory location and the dedicated local cache corresponding to the first core processor. Executing the prefetch instruction includes retrieving data from the memory location and storing the retrieved data on the dedicated local cache corresponding to the first core processor. | 2011-11-17 |
20110283068 | MEMORY ACCESS APPARATUS AND METHOD - A memory access apparatus is coupled to a memory unit and includes a header access circuit and a payload access circuit. The header access circuit includes a header fetching unit used to fetch a header descriptor in the memory unit, and the payload access circuit includes a payload fetching unit used to fetch a payload descriptor in the memory unit. The header access circuit and the payload access circuit perform fetching with respect to the memory unit in a non-sequenced manner. | 2011-11-17 |
20110283069 | METHOD FOR ESTIMATING CAPACITY USAGE STATUS OF STORAGE UNIT, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - The present invention provides a method for estimating a capacity usage status of a storage unit, where the storage unit includes a plurality of sectors. The method includes: estimating capacity usage statuses of a portion of sectors; and utilizing a controller to estimate the capacity usage status of the storage unit according to the estimated capacity usage statuses of the portion of sectors in a situation of not estimating capacity usage statuses of all of the sectors of the storage unit. | 2011-11-17 |
20110283070 | Method to Separate and Persist Static and Dynamic Portions of a Control Application - The subject matter disclosed herein describes a method of allocating and persisting memory in an industrial controller without requiring a battery backup or a large capacitive storage system. Each data object is identified as static or dynamic. Static objects are further classified by whether frequent access of that data object is required. Each of the data objects is stored in non-volatile memory. The dynamic data objects and static data objects requiring frequent access are stored in volatile memory. A record of static data objects is maintained in non-volatile memory and a record of dynamic data objects is maintained in volatile memory. Upon power loss, the present value of each dynamic data object is copied to non-volatile memory. When power is restored, the values of both the dynamic data objects and the static data objects that require frequent access at run-time are copied from non-volatile memory to volatile memory. | 2011-11-17 |
20110283071 | Dynamically Configurable Memory System - In a digital system with a processor coupled to a paged memory system, the memory system may be dynamically configured using a memory compaction manager in order to allow portions of the memory to be placed in a low power mode. As applications are executed by the processor, program instructions are copied from a non-volatile memory coupled to the processor into pages of the paged memory system under control of an operating system. Pages in the paged memory system that are not being used by the processor are periodically identified. The paged memory system is compacted by copying pages that are being used by the processor from a second region of the paged memory into a first region of the paged memory. The second region may be placed in a low power mode when it contains no pages that are being used by the processor. | 2011-11-17 |
20110283072 | Backup System and Backup Method - When detecting the completion of remote copying of a primary volume to a secondary volume, a host compute splits a copy pair into the primary volume and the secondary volume and has the secondary volume store a snapshot of the primary volume. A backup server recognizes the secondary volume. | 2011-11-17 |
20110283073 | SYSTEM AND METHOD FOR PERFORMING AUXILIARY STORAGE OPERATIONS - Systems and methods for protecting data in a tiered storage system are provided. The storage system comprises a management server, a media management component connected to the management server, a plurality of storage media connected to the media management component, and a data source connected to the media management component. Source data is copied from a source to a buffer to produce intermediate data. The intermediate data is copied to both a first and second medium to produce a primary and auxiliary copy, respectively. An auxiliary copy may be made from another auxiliary copy. An auxiliary copy may also be made from a primary copy right before the primary copy is pruned. | 2011-11-17 |
20110283074 | Backup management method in a remote copy environment - Provided is a computer system which is capable of backup operation with a minimum count of volumes in a remote copy environment when a disaster or the like causes a storage system to stop working normally. The computer system has a host computer, a first storage system, a second storage system, and a management computer. The first storage system contains a data volume which stores data requested by an application to be written. The second storage system contains a mirrored volume to which data stored in the data volume is copied. The computer system is characterized by being configured to receive an input of a policy about backup processing executed in backup volumes and set a configuration of the first storage system and a configuration of the second storage system under the received policy. | 2011-11-17 |
20110283075 | METHOD AND SYSTEM FOR DYNAMIC STORAGE TIERING USING ALLOCATE-ON-WRITE SNAPSHOTS - A method for dynamic storage tiering may comprise: detecting a storage hot-spot located in a first storage pool; and creating a first point-in-time copy of a virtual volume including the storage hot-spot located in the first storage pool in a second storage pool according to the detecting. | 2011-11-17 |
20110283076 | SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster. | 2011-11-17 |
20110283077 | PRESERVING AN EXISTING VOLUME MAP IN RE-INITIALIZING A DATA STORAGE VOLUME - A method, system and computer-program product for re-initializing a storage volume with an previously created volume map being preserved to allow access to previously stored data sets. The invention includes creating a new volume map in an unused volume area where the new volume map has pointers to new data sets. One of the new data sets contains the previously created volume map that points to previously created data sets. Each volume map is referenced by a volume label and includes a VTOC and an optional VTOC index. The pointers in the VTOC are data set control block (DSCB) records. | 2011-11-17 |
20110283078 | STORAGE APPARATUS TO WHICH THIN PROVISIONING IS APPLIED - At least two virtual volumes of a plurality of virtual volumes are associated with at least one pool. At least two pools of the plurality of pools are associated with each of virtual volumes. At least two pools that are associated with each of virtual volumes have a priority level. A storage control apparatus receives a write command and the write target data from a host apparatus. When a virtual area of a write destination specified by the write command is an unallocated virtual area, the storage control apparatus selects one pool based on the priority level of the pools that are associated with a virtual volume of a write destination specified by the write command. The storage control apparatus allocates an unallocated physical area in the selected pool to a virtual area of a write destination, and writes the write target data to the allocated physical area. | 2011-11-17 |
20110283079 | DATA PROCESSING DEVICE APPLYING FOR STORAGE DEVICE, DATA ACCESSING SYSTEM AND RELATED METHOD - A data processing device applying for a storage device includes: a first interface circuit coupled to the storage device; a processing circuit coupled to the first interface circuit for reading a control code from a divided storage area in the storage device, and executing the control code to generate a storage capacity of the storage device; and a second interface circuit coupled to the processing circuit for feeding the storage capacity back to an operating system such that the operating system regards the storage capacity as a usable capacity of the storage device. | 2011-11-17 |
20110283080 | APPARATUS AND METHOD FOR MANAGING MEMORY - Provided is a memory management method, and an apparatus to perform the method, which achieves a shortened user waiting time in consideration of system performance. The method includes acquiring a deallocation unit used to deallocate an allocated memory area according to at least one attribute, and deallocating the allocated memory area using the deallocation unit. | 2011-11-17 |
20110283081 | STAGGERED PROGRAMMING FOR RESISTIVE MEMORIES - Subject matter disclosed herein relates to a memory device and method of programming same. | 2011-11-17 |
20110283082 | Scalable, Concurrent Resizing Of Hash Tables - A system, method and computer program product for resizing a hash table while supporting hash table scalability and concurrency. The hash table has one or more hash buckets each containing one or more items that are chained together in a linked list. Each item in the hash table is processed to determine if the item requires relocation from a first bucket associated with a first table size to second bucket associated with a second table size. If the item requires relocation, it is linked to the second bucket without moving or copying the item in memory. The item is unlinked from the first bucket after waiting until there is no current hash table reader whose search of the hash table could be affected by the unlinking, again without moving or copying the item in memory. | 2011-11-17 |
20110283083 | Configuring Surrogate Memory Accessing Agents Using Non-Priviledged Processes - Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address. | 2011-11-17 |
20110283084 | DATA STORAGE DEVICES HAVING IP CAPABLE PARTITIONS - Apparatuses, methods, and systems related to IP-addressable partitions are disclosed. In some embodiments an IP address is used to uniquely identify a selected subset of partitions. Other embodiments may be described and claimed. | 2011-11-17 |
20110283085 | SYSTEM AND METHOD FOR END-TO-END DATA INTEGRITY IN A NETWORK FILE SYSTEM - A computer readable storage medium, embodying instructions executable by a computer to perform a method, the method including: validating a memory write of data segments using a first number of leaf hashes of a first hash tree, where each of the first number of leaf hashes is associated with one of the data segments of a first block size, generating interior node hashes based on the first number of leaf hashes, where each of the interior node hashes is associated with a second block size, generating a first root hash using the interior node hashes, where the first root hash is associated with a remote procedure call size, transmitting the first root rash and the data segments to a network file system, where the transmission is performed using the remote procedure call size, and validating the transmission of the data segments using the first root hash. | 2011-11-17 |
20110283086 | STREAMING PHYSICS COLLISION DETECTION IN MULTITHREADED RENDERING SOFTWARE PIPELINE - A circuit arrangement, program product and method stream level of detail components between hardware threads in a multithreaded circuit arrangement to perform physics collision detection. Typically, a master hardware thread, e.g., a component loader hardware thread, is used to retrieve level of detail data for an object from a memory and stream the data to one or more slave hardware threads, e.g., collision detection hardware threads, to perform the actual collision detection. Because the slave hardware threads receive the level of detail data from the master thread, typically the slave hardware threads are not required to load the data from the memory, thereby reducing memory bandwidth requirements and accelerating performance. | 2011-11-17 |
20110283087 | IMAGE FORMING APPARATUS, IMAGE FORMING METHOD, AND COMPUTER READABLE MEDIUM STORING CONTROL PROGRAM THEREFOR - A first processing unit is implemented by executing a first application program by using an internal computer in an environment where a first operating system is operating. The first processing unit performs a first process or an external service call in accordance with instruction information describing a process to be executed. A second processing unit is implemented by executing a second application program by using the internal computer or an additional computer connected to the internal computer in an environment where a second operating system is operating. The second processing unit performs a second process when instructed by an external service call to execute the second process. When the instruction information includes information specifying the second process as the process to be executed, a transfer unit updates the information included in the instruction information, and transfers the updated instruction information to the first processing unit. | 2011-11-17 |
20110283088 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus includes a connecting unit that distributes the plurality of processing modules over the stages, and connects the plurality of processing modules such that a plurality of partial data are processed in parallel. The data processing apparatus detects, with respect to at least a part of the stages, a ratio of an amount of data for which processing in the subsequent stage has been executed, as a passage rate, acquires a processing time for a data amount to be processed in each stage, for which the passage rate was detected, based on the passage rate, and determines the number of processing modules distributed to each stage based on the data amount. | 2011-11-17 |
20110283089 | MODULARIZED MICRO PROCESSOR DESIGN - A method and system of modularized design for a microprocessor are disclosed. Embodiments disclose modularization techniques, whereby the overall design of the execution unit of the processor is split into different functional modules. The modules are configured to function independent of each other. The microprocessor comprises different components such as a cache logic ( | 2011-11-17 |
20110283090 | Instruction Addressing Using Register Address Sequence Detection - A circuit arrangement and method support efficient indexing into large register files by utilizing register address sequence detection, wherein register addresses to be used by an instruction are produced by concatenating a portion of the address that is contained in the instruction with another portion that is speculatively produced by sequence detection logic. The portion of the correct full address that is not contained in the instruction is stored in a software accessible special purpose register. If the end of a particular sequence of addresses is detected by the sequence detection logic, the invention speculatively assumes that the next address in the sequence will be used. Since only a portion of the full addresses are stored in the instruction, they occupy less instruction space than the full address widths. An instruction may include at least one address portion that identifies a register address. | 2011-11-17 |
20110283091 | PARALLELIZING SEQUENTIAL FRAMEWORKS USING TRANSACTIONS - Various technologies and techniques are disclosed for transforming a sequential loop into a parallel loop for use with a transactional memory system. Open ended and/or closed ended sequential loops can be transformed to parallel loops. For example, a section of code containing an original sequential loop is analyzed to determine a fixed number of iterations for the original sequential loop. The original sequential loop is transformed into a parallel loop that can generate transactions in an amount up to the fixed number of iterations. As another example, an open ended sequential loop can be transformed into a parallel loop that generates a separate transaction containing a respective work item for each iteration of a speculation pipeline. The parallel loop is then executed using the transactional memory system, with at least some of the separate transactions being executed on different threads. | 2011-11-17 |
20110283092 | GETFIRST AND ASSIGNLAST INSTRUCTIONS FOR PROCESSING VECTORS - The described embodiments comprise a processor that executes vector instructions. In the described embodiments, while executing program code, the processor receives a vector instruction that indicates an input vector that includes N elements, wherein receiving the vector instruction comprises optionally receiving a predicate vector that includes N elements. The processor then executes the vector instruction. When executing the vector instruction, if the predicate vector is received, based on active elements in the predicate vector, otherwise, if the predicate vector is not received, based on an assumed predicate vector for which each element is active, the processor sets a value in a scalar register equal to a predetermined element of the input vector. In the described embodiments, the vector instruction can be a GetFirst, an AssignLast1P, or an AssignLast2P instruction. | 2011-11-17 |
20110283093 | MINIMIZING PROGRAM EXECUTION TIME FOR PARALLEL PROCESSING - According to one embodiment, an information processing apparatus comprises a storage storing program modules and parallel execution control description describing relationships of the program modules, a conversion module extracting a part relating to the program module from the parallel execution control description, and creating graph data structure creation information including preceding and succeeding information of the program module, an adding module extracting graph data structure creation information to which the input data is given, creating a node, and adding the created node to a formerly created graph data structure, and an execution module subjecting the graph data structure to at least one of first search and second search with a restricted breadth, selecting one node from nodes stored in the node memory, and executing a program module corresponding to the selected node. | 2011-11-17 |
20110283094 | Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit - A semiconductor device is capable of being coupled to a first debugger and a second debugger, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupled to the first chip. The first chip includes a first processing unit that executes a first instruction group, and a first debug control unit capable of being coupled to the first debugger to control a communication with the first debugger, and the second chip includes a memory that stores a first data and the program including the first instruction group and a second instruction group, the first data is generated based on a second data inputted from the second debugger, a second processing unit that executes the second instruction group, a second debug control unit capable of being coupled to the second debugger to control a communication with the second debugger, and the first debug control unit controls permission or prohibition of a connection configuration to the first debugger based on the second data and a third data inputted from the first debugger. | 2011-11-17 |
20110283095 | Hardware Assist Thread for Increasing Code Parallelism - Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread. | 2011-11-17 |
20110283096 | REGISTER FILE SUPPORTING TRANSACTIONAL PROCESSING - A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency. Responsive to the processor processing a second instruction in a transactional code section to obtain as an execution result a second register value of the logical register, the mapper moves a first register value of the logical register to the second level register file, places the second register value in the first level register file, marks the second register value as speculative, and replaces a first mapping for the logical register with a second mapping. Responsive to unsuccessful termination of the transactional code section, the mapper designates the second register value in the first level register file as invalid so that the first register value in the second level register file becomes the working value. | 2011-11-17 |
20110283097 | IMAGING PROCESS - A user-friendly system, method, and program product for installing an image on a computer, the method comprising: booting the computer ( | 2011-11-17 |
20110283098 | ELECTRONIC DEVICE WITH OVERLAPPED BOOT TASK FETCHES AND BOOT TASK EXECUTION - In accordance with at least some embodiments, a system includes a first processor and a second processor. The system also includes a boot task storage medium that can only be accessed by one processor at a time. A boot process of the system has a first stage and a second stage. During the first stage, the first processor fetches and executes boot tasks without assistance from the second processor. During the second stage, boot task execution performed by first processor overlaps with at least one boot task fetch performed by the second processor. | 2011-11-17 |
20110283099 | Private Aggregation of Distributed Time-Series Data - Techniques are described herein for privately aggregating distributed time-series data. A requestor provides a query sequence to users. Each user evaluates the query sequence on the user's time-series data to determine an answer sequence. Each user transforms its answer sequence to another domain, adds noise, and encrypts it for further processing by the requestor. The requestor combines these encrypted sequences in accordance with a homomorphic encryption technique to provide an encrypted summation sequence. The requestor provides the encrypted summation sequence to at least some of the users, who may in turn provide respective decryption shares to the requestor. The requestor combines the decryption shares in an effort to decrypt the encrypted summation sequence. Decrypting the encrypted summation sequence provides a summation of the encrypted sequences from the users, which may be transformed back to the original domain to estimate a summation of the answer sequences of the users. | 2011-11-17 |
20110283100 | Determination and Display of LUN Encryption Paths - A management station which manages the encryption devices in a SAN to set up encrypted LUNs. In setting up the encryption, the source and target ports are identified, along with the target LUN. LUN serial numbers used to identify unique LUNs. As paths to a given LUN are defined, the management station compares the path to existing paths and provides an indication if there is a mismatch in the encryption policies or keys being applied to the LUN over the various paths. This allows the administrator to readily identify when there is a problem with the paths to an encrypted LUN and then take steps to cure the problem. By determining the paths and then comparing them, the management station greatly simplifies setting up multipath I/O to an encrypted LUN or access by multiple hosts to an encrypted LUN. | 2011-11-17 |
20110283101 | System to Enable Detecting Attacks Within Encrypted Traffic - A system and method for detecting network attacks within encrypted network traffic received by a protected network includes a decryption module and an adaptor module. This system and method can be inserted and used with multiple types of operating systems. | 2011-11-17 |
20110283102 | METHOD AND SYSTEM FOR SUPPORTING WATERMARK EMBEDDING IN MULTIMEDIA SYSTEM-ON-CHIPS - A secure server may be utilized to support watermark embedding in multimedia system-on-chips, by generating an encrypted and signed watermarking signal for use in each particular system-on-chip. The encrypted and signed watermarking signal is generated based on a unique per-chip ID associated with the particular system-on-chip. The watermarking signal may be signed by the secure server utilizing a random number generated in and/or provided by the particular system-on-chip. The watermarking signal may be encrypted by the secure server based on a secret encryption key associated with the particular system-on-chip. The secret encryption key may be determined based on the unique per-chip ID associated with the particular system-on-chip. The secure server may store information, received from various system-on-chips, for use during generation of watermarking signals. The information received from each system-on-chip may comprise corresponding unique per-chip ID and/or a random number associated with each particular system-on-chip. | 2011-11-17 |
20110283103 | ONE TIME PASSWORDS WITH IPSEC AND IKE VERSION 1 AUTHENTICATION - A system adapted to condition access to a network over an IPsec session to clients providing a proper one-time-password, even though the network access control uses IKEv1, which does not support one-time-passwords. An authentication service receives from a client an access request including the one-time-password, and provides the one-time-password to a service that checks the password. The one-time-password service returns a cookie when the password is successfully validated and the client is properly authenticated. The cookie is passed on to the client computer, which uses the cookie as part of a request for a certificate. A certificate authority generates a certificate if a request for a certificate is received from an authenticated client, which in turn may be used to form the IPsec session for access to the network. | 2011-11-17 |
20110283104 | Domain Access System - A domain access system may include a connection package for a remote device. The connection package may be installed and used to connect to a domain without having to be physically attached to the domain. The connection package may include a domain identifier and a machine name, as well as certificates used to authenticate the device to the domain, group policies, and other components and configuration information. An installation program may configure the remote device with the various components and certificates so that the remote device may connect to the domain. | 2011-11-17 |
20110283105 | METHOD OF DISTRIBUTING A DECRYPTION KEY IN FIXED-CONTENT DATA - Secondary content in encrypted for distribution to client terminals by selecting at least a portion of raw encrypted audio-video data (REAVD) that is provided on a media article as an encryption key, encrypting secondary content using the encryption key, and storing encrypted secondary content at a remotely located host. The media article can then be used for providing access to the encrypted secondary content to client terminals by receiving encrypted secondary content at a client terminal, extracting a decryption key from a media article encoded with REAVD, the decryption key being determined by at least a portion of the REAVD, using the decryption key to decrypt the secondary content, and outputting the decrypted secondary content from the client terminal. | 2011-11-17 |
20110283106 | METHOD FOR REALIZING AUTHENTICATION CENTER AND AUTHENTICATION SYSTEM - A method for realizing an authentication center (AC) and an authentication system are disclosed. The method comprises: a UE sends an authentication request to an AC and applies for temporary authentication information, the AC assigns a first authentication random code to the UE, then the UE calculates a first response code and sends it to the AC, the AC assigns the temporary authentication information to the UE after authentication and authorization; the UE sends a login request to the application system (AS) which assigns a second authentication random code to the UE, and the UE uses it and the temporary authentication information to calculate a second response code, and sends this code to the AS; the AS sends the second response code to the AC for authentication and authorization; the AC returns the authentication result to the AS which in turn returns the authentication result to the UE. | 2011-11-17 |
20110283107 | METHOD FOR ESTABLISHING A SECURED COMMUNICATION WITHOUT PRELIMINARY INFORMATION SHARE - The invention relates to a method for generating a session key between two communicating electronic devices not requiring any prerecorded information in one of the two devices and enabling the authentication of one of said devices. The method uses a close collaboration between a symmetrical algorithm and an asymmetrical algorithm. | 2011-11-17 |