46th week of 2011 patent applcation highlights part 15 |
Patent application number | Title | Published |
20110278602 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device includes a substrate having an element mounting area in a principal surface thereof. The light emitting device also includes at least one light emitting element mounted in the element mounting area of the substrate. The light emitting device also includes a heat transfer member provided on the substrate. The heat transfer member has a thermal conductivity different from thermal conductivity of the substrate so as to form uneven thermal resistance distribution in the element mounting area. Thermal resistance in a heat radiation path through the substrate for release of heat emitted from the light emitting element changes with the mounting position of the light emitting element. | 2011-11-17 |
20110278603 | ORGANIC EL DISPLAY AND METHOD FOR MANUFACTURING SAME - Disclosed is a method for manufacturing an organic EL display, which comprises: a step of preparing an organic EL panel that comprises a substrate and organic EL elements arranged as a matrix on the substrate, wherein each organic EL element has a pixel electrode arranged on the substrate, an organic layer arranged on the pixel electrode, a transparent counter electrode arranged on the organic layer, a protective layer arranged on the transparent counter electrode, and a color filter arranged on the protective layer, and a defect portion present in the organic layer in each organic EL element is detected; a step of destroying a region of the transparent counter electrode positioned above the defect portion by irradiating the region with laser light through the color filter; and a step wherein a region of the color filter positioned above the defect portion is removed. | 2011-11-17 |
20110278604 | DISPLAY APPARATUS - A display apparatus displays a character or a graphic formed by a first light-emitting element group (first group) and a background of the character or the graphic formed by a second light-emitting element group (second group) on a display unit. The ratio of the electric current flowing through the light-emitting elements (elements) in the second group to the elements in the first group with respect to the elements of a same color as the elements whose electric current per unit light-emitting area is the largest among the elements of different colors when the display unit displays white, is closer to 1 than the ratio of the electric current flowing through each of the elements in the second group to the elements in the first group with respect to the elements of different colors from the elements whose electric current per unit light-emitting area is the largest when the display unit displays white. | 2011-11-17 |
20110278605 | LIGHT EMITTING DEVICE AND ILLUMINATION DEVICE - A light emitting device is a light emitting device using light emitting elements and includes: a substrate; a resin frame provided circularly on the substrate; a resin wall provided on the substrate so as to partition an area surrounded by the resin frame into 2 zones; light-emitting sections (a first light-emitting section: blue LEDs+red fluorescent material, a second light-emitting section: blue LEDs+yellow fluorescent material) provided in the respective zones, each of which light-emitting sections includes at least one light emitting element; and first and second anode electrodes and a cathode electrode provided so that each of the light-emitting sections receives current via a corresponding anode electrode and the cathode electrode, the light-emitting sections emitting respective pieces of light each having at least one color, which respective pieces of light have different colors from each other, the first and second anode electrodes being electrically connected to the first and second light-emitting sections, respectively. With the arrangement, which can increase an integration degree, it is possible to achieve a high color rendering property and an excellent color mixing property, to easily adjust a chromaticity, and to easily generate light with a desired chromaticity. | 2011-11-17 |
20110278606 | LED LIGHT EMITTING DEVICE - In order to provide an LED light emitting device that can easily control a color temperature of white light, the LED light emitting device is provided with a plurality of types of light emitting parts that: respectively have LED elements that emit ultraviolet radiation or violet color visible light, and phosphors that absorb the ultraviolet radiation or violet color visible light to emit colored light; and emit the colored light, wherein: the colored light emitted by the plurality of types of light emitting parts become white light when all mixed with each other; the LED elements of the plurality of types of light emitting parts are all the same ones, and mounted on a single base material; and two or more light emitting parts overlap with each other in their parts. | 2011-11-17 |
20110278607 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes first and second insulating substrates facing to each other, and a liquid crystal sandwiched between the first and second substrates. A plurality of gate lines are formed at the first substrate to transmit scanning signals, and data lines cross over the gate lines to transmit picture signals. Pads are connected to the gate and data lines. Pixels are demarcated by the gate lines and the data lines, and collectively form a display area. The gate lines demarcate the pixels into rows, and the data lines demarcate the pixels into columns. A black matrix defines each pixel, and a pixel electrode is formed at the pixel. A storage capacitor line is formed at the first substrate parallel to the gate line, and overlapped with the pixel electrodes at the first pixel row. Storage capacitors are formed between the pixel electrodes and the previous gate lines as well as between the pixel electrodes and the storage capacitor line. A gate-off voltage or a common electrode voltage is applied to the storage capacitor line. The opening ratio of each pixel at the first pixel row with the storage capacitor formed between the corresponding pixel electrode and the storage capacitor line differs from the opening ratio of the pixels at the other pixel rows. The difference in the opening ratio is made through forming a light interception pattern at each pixel of the first pixel row, or through differentiating opening areas of the black matrix. In order to prevent leakage of light, light interception patterns may be formed at the region between the display area and the pads. | 2011-11-17 |
20110278608 | High Voltage Low Current Surface Emitting LED - A monolithic LED chip is disclosed comprising a plurality of junctions or sub-LEDs (“sub-LEDs”) mounted on a submount. The sub-LEDs are serially interconnected such that the voltage necessary to drive the sub-LEDs is dependent on the number of serially interconnected sub-LEDs and the junction voltage of the sub-LEDs. Methods for fabricating a monolithic LED chip are also disclosed with one method comprising providing a single junction LED on a submount and separating the single junction LED into a plurality of sub-LEDs. The sub-LEDs are then serially interconnected such that the voltage necessary to drive the sub-LEDs is dependent on the number of the serially interconnected sub-LEDs and the junction voltage of the sub-LEDs. | 2011-11-17 |
20110278609 | PACKAGE STRUCTURE AND PACKAGE PROCESS OF LIGHT EMITTING DIODE - A light emitted diode (LED) package structure and an LED package process are provided. The LED package structure comprises a carrier, a spacer, at least one LED chip, a junction coating, a plurality of phosphor particles, and an encapsulant. The spacer is disposed on the carrier and provided with a reflective layer covering a top surface of the spacer. The LED chip is disposed on the reflective layer and electrically connected to the carrier. The junction coating is disposed over the spacer and covers the LED chip. The phosphor particles are distributed within the junction coating. The encapsulant is disposed on the carrier and encapsulates the LED chip, the spacer and the junction coating. Uniform light output and high illuminating efficiency can be obtained by the phosphor particles uniformly distributed in the junction coating. The junction coating is formed by package level dispensing process to reduce the fabrication cost. | 2011-11-17 |
20110278610 | PACKAGE STRUCTURE AND PACKAGE PROCESS OF LIGHT EMITTING DIODE - A light emitting diode (LED) package structure comprising a carrier, an LED chip, a first encapsulant, at least one bonding wire, a plurality of phosphor particles and a second encapsulant is provided. The LED chip is disposed on the carrier. The LED chip has at least one electrode. The first encapsulant is disposed on the carrier and covering the LED chip. The first encapsulant is provided with at least one preformed opening exposing at least a portion of the at least one electrode. The at least one bonding wire is electrically connected between the at least one electrode and the carrier via the at least one preformed opening. The phosphor particles are distributed within the first encapsulant. The second encapsulant is disposed on the carrier and encapsulates the LED chip, the first encapsulant and the at least one bonding wire. | 2011-11-17 |
20110278611 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate and an organic electroluminescent device. Inside the substrate, there are a plurality of micro-structures proceeded with fusing and then curing. The organic electroluminescent device is disposed on the substrate. | 2011-11-17 |
20110278612 | ORGANIC LIGHT EMITTING DIODE STRUCTURE AND FABRICATING METHOD THEREOF - An organic light emitting diode structure is disclosed. The hole transport layer of the organic light emitting diode structure is used as a first primary color light emitting layer. A second primary color light emitting unit and a third primary color light emitting unit are formed on the first primary color light emitting layer, and a part of the first primary color light emitting layer is exposed. A method for fabricating the organic light emitting diode structure is also disclosed. | 2011-11-17 |
20110278613 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a substrate, a buffer layer on the substrate, a patterned layer having a first reflective index on the buffer layer, a semiconductor layer having a second reflective index on the patterned layer, and an illumination structure on the semiconductor layer. A method for manufacturing the light emitting diode is also provided. | 2011-11-17 |
20110278614 | LIGHT EMITTING DEVICE, AND METHOD FOR THE PRODUCTION THEREOF - The present invention relates to a composition of plastic material that includes from 7 to 20 wt. % inorganic conversion pigments. The pigments include Si, Sr, Ba, Ca and Eu in concentrations of greater than 0 ppm and Al, Co, Fe, Mg, Mo, Na, Ni, Pd, P, Rh, Sb, Ti and Zr in concentrations of less than or equal to 50 ppm | 2011-11-17 |
20110278615 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device and a method of its manufacture are provided, whereby manufacturing processes are simplified and display quality may be enhanced. The display device includes: an active layer of a thin film transistor (TFT), on a substrate and including a semiconducting material; a lower electrode of a capacitor, on the substrate, doped with ion impurities, and including a semiconducting material; a first insulating layer on the substrate to cover the active layer and the lower electrode; a gate electrode of the TFT, on the first insulating layer; a pixel electrode on the first insulating layer; an upper electrode of the capacitor, on the first insulating layer; source and drain electrodes of the TFT, electrically connected to the active layer; an organic layer on the pixel electrode and including an organic emission layer; and a counter electrode facing the pixel electrode, the organic layer between the counter electrode and the pixel electrode. | 2011-11-17 |
20110278616 | MANUFACTURING METHOD OF WAVELENGTH CONVERSION ELEMENT, WAVELENGTH CONVERSION ELEMENT, AND LIGHT EMITTING DEVICE - A manufacturing method of a wavelength conversion element suppresses the changes of the chromaticities among wavelength conversion elements. The manufacturing method of the wavelength conversion element including a glass substrate and a ceramic layer in which a phosphor is dispersed is disclosed. The manufacturing method includes the step of preparing a mixture containing a ceramic precursor, a solvent, and the phosphor, which mixture has viscosity within a range of from 10 cp to 1000 cp, the step of coating the mixture onto at least one surface of a glass substrate, the step of baking the mixture to form the ceramic layer, and the step of dicing the glass substrate and the ceramic layer after the baking. | 2011-11-17 |
20110278617 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package is provided comprising a substrate, a light source unit disposed on the substrate and a dam unit spaced apart from the light source unit and disposed on the substrate, wherein the dam unit including silicon resin and metal oxide, and the metal oxide is contained in an amount of 5 wt % to 150 wt % based on a total amount of the silicon resin. | 2011-11-17 |
20110278618 | SUBSTRATE FOR MOUNTING LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICE - To provide a substrate for a light-emitting element, being less susceptible to the loss of light supplied from a light emitting element, having high utilization efficiency of light, being excellent in flatness of a mounting surface on which a light-emitting element is to be mounted, and having a low heat resistance, when used for a light-emitting device. | 2011-11-17 |
20110278619 | QUATERNARY VERTICAL LIGHT EMITTING DIODE WITH DOUBLE SURFACE ROUGHENING AND MANUFACTURING METHOD THEREOF - The present invention discloses a quaternary vertical light emitting diode with double surface roughening and a manufacturing method thereof, where a Bragg reflective layer is formed on a substrate; a first type of epitaxial layer is formed on the Bragg reflective layer; a light emitting layer is formed on the first type of epitaxial layer; a second type of epitaxial layer is formed on the light emitting layer; a first GaP window layer with small circular holes or in a mesh structure is formed on the second type of epitaxial layer; a second GaP window layer with small circular holes or in a mesh structure is formed on the first GaP window layer; a first electrode is formed on the top surface of the second GaP window layer; and a second electrode is formed on the bottom surface of the GaAs substrate. After conventional processes, the invention forms the alternating small circular holes or the mesh structure between the first GaP window layer and the second GaP window layer to change a light path along which light emitting from the light emitting layer reaches the surface of a light emitting diode die so that more of light emits from inside and the light extracting rate of the invention is 20% higher than that of an existing light emitting diode. | 2011-11-17 |
20110278620 | THIN FILM LIGHT EMITTING DIODE - Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition. | 2011-11-17 |
20110278621 | RADIATION-EMITTING COMPONENT AND METHOD FOR ITS MANUFACTURE - A radiation-emitting component includes a carrier, a semi-conductor chip arranged on the carrier, wherein the semi-conductor chip includes an active layer to generate electromagnetic radiation and a radiation exit surface, a first and a second contact structure for the electrical contacting of the semi-conductor chip, a first and a second contact layer, wherein the semi-conductor chip is electrically conductively connected to the first contact structure via the first, contact layer and to the second contact structure via the second contact layer, a passivation layer arranged on the semi-conductor chip. | 2011-11-17 |
20110278622 | Glass for scattering layer of organic LED device and organic LED device - A glass to be used in a scattering layer of an organic LED element, and an organic LED element using the scattering layer are provided. The organic LED element of the present invention includes, a transparent substrate, a first electrode provided on the transparent electrode, an organic layer provided on the first electrode, and a second electrode provided on the organic layer, and further includes a scattering layer including, in terms of mol % on the basis of oxides, 15 to 30% of P | 2011-11-17 |
20110278623 | METHOD FOR MANUFACTURING LED MODULE, AND LED MODULE - A method for manufacturing an LED module is provided that includes the steps of mounting an LED chip | 2011-11-17 |
20110278624 | SUBSTRATE FOR AN OPTICAL DEVICE, AN OPTICAL DEVICE PACKAGE COMPRISING THE SAME AND A PRODUCTION METHOD FOR THE SAME - The present invention relates to a substrate for an optical device, to an optical device package comprising the same and to a production method for the same. According to the present invention, the substrate for an optical device, the optical device package comprising the same and the production method for the same may comprise: a metal substrate; a first anodized layer which is formed on the top surface of the metal substrate and insulates the metal substrate; and a first and a second electrode formed insulated from each other on the top of the first anodized layer. | 2011-11-17 |
20110278625 | LIGHT-EMITTING ELEMENT - Disclosed are a light emitting device and a method of manufacturing the same. The light emitting device includes a second electrode layer, a light emitting semiconductor layer including a second conductive semiconductor layer, an active layer, and a first conductive semiconductor layer on the second electrode layer, a reflective member spaced apart from the light emitting semiconductor layer on the second electrode layer, and a first electrode layer on the first conductive semiconductor layer. | 2011-11-17 |
20110278626 | LIGHT EMITTING DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A light emitting device package capable of achieving an enhancement in light emission efficiency and a reduction in thermal resistance, and a method for manufacturing the same are disclosed. The method includes forming a mounting hole in a first substrate, forming through holes in a second substrate, forming a metal film in the through holes, forming at least one pair of metal layers on upper and lower surfaces of the second substrate such that the metal layers are electrically connected to the metal film, bonding the first substrate to the second substrate, and mounting at least one light emitting device in the mounting hole such that the light emitting device is electrically connected to the metal layers formed on the upper surface of the second substrate. | 2011-11-17 |
20110278627 | LIGHT EMITTING DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A light emitting device package capable of achieving an enhancement in light emission efficiency and a reduction in thermal resistance, and a method for manufacturing the same are disclosed. The method includes forming a mounting hole in a first substrate, forming through holes in a second substrate, forming a metal film in the through holes, forming at least one pair of metal layers on upper and lower surfaces of the second substrate such that the metal layers are electrically connected to the metal film, bonding the first substrate to the second substrate, and mounting at least one light emitting device in the mounting hole such that the light emitting device is electrically connected to the metal layers formed on the upper surface of the second substrate. | 2011-11-17 |
20110278628 | GaN COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a gallium nitride (GaN) compound semiconductor light emitting element (LED) and a method of manufacturing the same. The present invention provides a vertical GaN LED capable of improving the characteristics of a horizontal LED by means of a metallic protective film layer and a metallic support layer. According to the present invention, a thick metallic protective film layer with a thickness of at least 10 microns is formed on the lateral and/or bottom sides of the vertical GaN LED to protect the element against external impact and to easily separate the chip. Further, a metallic substrate is used instead of a sapphire substrate to efficiently release the generated heat to the outside when the element is operated, so that the LED can be suitable for a high-power application and an element having improved optical output characteristics can also be manufactured. A metallic support layer is formed to protect the element from being distorted or damaged due to impact. Furthermore, a P-type electrode is partially formed on a P-GaN layer in a mesh form to thereby maximize the emission of photons generated in the active layer toward the N-GaN layer. | 2011-11-17 |
20110278629 | LED THERMAL MANAGEMENT - Thermal management solutions for higher power LEDs. In accordance with embodiments, a heat sink, preferably copper, is connected directly to the thermal pad of an LED. Directly connecting the LED thermal pad to the copper heat sink reduces the thermal resistance between the LED package and the heat sink, and more efficiently conducts heat away from the LED through the copper heat sink. In embodiments, the copper heat sink is directly soldered to the LED thermal pad. | 2011-11-17 |
20110278630 | COATING AGENT, SUBSTRATE FOR MOUNTING OPTICAL SEMICONDUCTOR ELEMENT USING SAME, AND OPTICAL SEMICONDUCTOR DEVICE - The coating agent of the invention is a coating agent to be used between conductor members, comprising a thermosetting resin, a white pigment, a curing agent and a curing catalyst, the coating agent to be used between conductor members having a white pigment content of 10-85 vol % based on the total solid volume of the coating agent, and a whiteness of at least 75 when the cured product of the coating agent has been allowed to stand at 200° C. for 24 hours. | 2011-11-17 |
20110278631 | LIGHT EMITTING DIODE CHIP - A light emitting diode (LED) chip includes a first electrode and a second electrode. Each of the first and second electrodes includes several trunks with at least one branch extending from at least one of the trunk, and at least one conductive pad serially connecting the trunks. A distance between a distal end of the branch of the first electrode and the conductive pad of the second electrode is less than that between any of other portions of the branch of the first electrode and the conductive pad of the second electrode, to thereby avoid crowded electric current formed at the first electrode and the conductive pad of the second electrode to save power accordingly. | 2011-11-17 |
20110278632 | LIGHT EMITTING DEVICE AND ILLUMINATION DEVICE - According to one embodiment, a light emitting device includes a substrate, a light emitting element and connectors. The substrate has a surface and a back face, and power supply terminals are formed on the surface. The light emitting element is mounted on the surface of the substrate. The connector includes a contact portion coming into contact with, the power supply terminal on the surface side of the substrate and a connector terminal having a wire connection portion projecting on the back face side of the substrate, and a power supply wire is connected to the wire connection portion of the connector terminal. | 2011-11-17 |
20110278633 | LED Light Bulb With Integrated Heat Sink - The use of an LED light source coupled with an integrated heat sink is described in this application. The most preferred embodiments of the present invention comprise an LED light source surrounded by a plurality of heat vanes, with each heat vane comprising a plurality of heat fins, all positioned to dissipate heat in an enclosure housing the LED light source. In at least some preferred embodiments of the present invention, a pair of waterproof tubes are used to house a pair of electrical conductors that are used to connect the LED light source to a power source. The most preferred embodiments of the present invention further comprise a single LED contained in a housing fitted with a compound parabolic concentrator configuration. | 2011-11-17 |
20110278634 | LIGHT-EMITTING DEVICE AND LIGHTING APPARATUS - Disclosed is a light-emitting device including, a light-emitting structure including a first conductive semiconductor layer including at least a first region and a second region, and an active layer and a second conductive semiconductor layer formed in the first region, a first electrode formed on the first conductive semiconductor layer, and a second electrode formed on the second conductive semiconductor layer. Current spreading and drive voltage can be improved and luminous efficacy of the light-emitting device can be enhanced. | 2011-11-17 |
20110278635 | Method for producing electronic device substrate, method for manufacturing electronic device, electronic device substrate, and electronic device - A method for producing a substrate for an electronic device, that can improve light extraction efficiency, can easily produces and has high liability is provided. The method includes: a step of heat-melting a glass raw material or a glass to produce a molten glass; a forming step of continuously feeding the molten glass to a bath surface of a molten metal bathtub accommodating a molten metal to form a continuous glass ribbon | 2011-11-17 |
20110278636 | LIGHT EMITTING ELEMENT - A heat radiation structure of a light emitting element has leads, each lead having a plurality of leg sections, and a light emitting chip mounted on any one of the leads. The present invention can provide a high-efficiency light emitting element, in which a thermal load is reduced by widening a connecting section through which a lead and a chip seating section of the light emitting element are connected, and the heat generated from a heat source can be more rapidly radiated to the outside. Further, the present invention can also provide a high-efficiency light emitting element, in which heat radiation fins are formed between a stopper and a molding portion of a lead of the light emitting element so that natural convection can occur between the heat radiation fins, and an area in which heat radiation can occur is widened to maximize a heat radiation effect. | 2011-11-17 |
20110278637 | LIGHT EMITTING DEVICE AND FABRICATION METHOD THEREOF AND LIGHT EMITTING SYSTEM USING THE SAME - A light emitting device comprises a light emitting element having a first electrode and a second electrode, and a semiconductor member having a cavity in a principal surface thereof, inside which the light emitting element is mounted, and electrically connected to the light emitting element, wherein the semiconductor member is constructed as a voltage regulating diode for stabilizing a voltage supplied from the exterior. As a result, the light emitting element can be protected from a static electricity or a surge voltage flowed therein from the exterior, the entire size of the system can be remarkably reduced so as to simplify a structure thereof, and heat generated from the system can be effectively discharged to the exterior. In addition, by providing a reflection portion in the cavity, light emitted from the light emitting element can be efficiently condensed. | 2011-11-17 |
20110278638 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/DIELECTRIC/POST HEAT SPREADER - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The heat spreader includes a first post, a second post and a dielectric base. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The first post extends from the dielectric base in a first vertical direction into a first opening in the first adhesive, the second post extends from the dielectric base in a second vertical direction into a second opening in the second adhesive and the dielectric base contacts and is sandwiched between and extends laterally from the posts. The conductive trace provides signal routing between the pad and the terminal. | 2011-11-17 |
20110278639 | LED Package Structure - An LED package structure comprises an LED chip and a fuse electrically connected to the LED chip in series. The fuse has a low melting point such that the fuse melts under a high current to form an open circuit to prevent the high current from flowing through the LED chip. | 2011-11-17 |
20110278640 | RESIN COMPOSITION AND TRANSPARENT ENCAPSULANT FORMED USING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE ENCAPSULANT - An embodiment is directed to a polysiloxane having a moiety represented by the following Chemical Formula 1: | 2011-11-17 |
20110278641 | METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP AND OPTOELECTRONIC SEMICONDUCTOR CHIP - An optoelectronic semiconductor chip includes a semiconductor layer sequence having at least one doped functional layer having at least one dopant and at least one codopant, wherein the semiconductor layer sequence includes a semiconductor material having a lattice structure, one selected from the dopant and the codopant is an electron acceptor and the other an electron donor, the codopant is bonded to the semiconductor material and/or arranged at interstitial sites, and the codopant at least partly forms no bonding complexes with the dopant. | 2011-11-17 |
20110278642 | POWER SEMICONDUCTOR STRUCTURE WITH FIELD EFFECT RECTIFIER AND FABRICATION METHOD THEREOF - A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region. | 2011-11-17 |
20110278643 | SEMICONDUCTOR UNIT AND SEMICONDUCTOR APPARATUS USING SAME - A semiconductor unit of certain aspects of the invention includes electrically conductive plates in the shape of the letter L, each consisting of a horizontally disposed leg portion and a vertically disposed flat body portion that is perpendicular to a cooling plate adhered to the bottom of the semiconductor unit. A pair of the vertically disposed flat body portions sandwiches a semiconductor chip. Owing to this construction, the heat generated in the semiconductor chip can be conducted away through the both surfaces of the chip, thus improving cooling performance. Since the heat is conducted away through the leg portions of the L-shaped electrically conductive plates a projected planar area occupied by the cooling plate required for cooling the semiconductor unit is reduced. Therefore, the size of the semiconductor unit can be reduced. | 2011-11-17 |
20110278644 | GROUP III-NITRIDE ENHANCEMENT MODE FIELD EFFECT DEVICES AND FABRICATION METHODS - Structures and fabrication processes are described for group III-nitride enhancement mode field effect devices in which a two-dimensional electron gas is present at or near the interface between a pair of active layers that include a group III-nitride barrier layer and a group III-nitride semiconductor layer. The barrier layer has a band gap wider than the band gap of the adjacent underlying semiconductor layer. The two-dimensional electron gas is induced by providing one or more layers disposed over the barrier layer. A gate electrode is in direct contact with the barrier layer. Ohmic contacts for source and drain electrodes are in direct contact either with the barrier layer or with a semiconductor nitride layer disposed over the barrier layer. | 2011-11-17 |
20110278645 | STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMING - Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates. | 2011-11-17 |
20110278646 | Balance Step-Height Selective Bi-Channel Structure on HKMG Devices - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 2011-11-17 |
20110278647 | III-NITRIDE SEMICONDUCTOR ELECTRONIC DEVICE, AND METHOD OF FABRICATING III-NITRIDE SEMICONDUCTOR ELECTRONIC DEVICE - A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively. A concentration of impurity in the first portion is the same as that of impurity in the second portion, and the first and second electrodes is provided on the first and second regions, respectively. The first electrode includes a drain electrode or a source electrode. An aluminum composition of the first III-nitride semiconductor is not less than 0.16, and a bandgap of the second III-nitride semiconductor being larger than that of the first III-nitride semiconductor. | 2011-11-17 |
20110278648 | METHOD OF INTRODUCING A STRUCTURE IN A SUBSTRATE - This invention relates to methods for the production of micro-structured substrates and their application in natural sciences and technology, in particular in semiconductor, microfluidic and analysis devices. It concerns a method of introducing a structure, such as a hole or cavity or channel or well or recess or a structural change by providing a controlled electrical discharge. | 2011-11-17 |
20110278649 | NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING - A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric. | 2011-11-17 |
20110278650 | POWER SEMICONDUCTOR DEVICE - A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions. | 2011-11-17 |
20110278651 | NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME - NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer. | 2011-11-17 |
20110278652 | SOLID STATE IMAGING DEVICE - A plurality of pixels PX include effective pixels and optical black pixels. Signal lines VL are provided corresponding to each column of the pixels PX and supplied with output signals of the pixels PX of the corresponding column. Clip transistors CL are provided corresponding to the respective signal lines VL and limit a potential of the corresponding vertical signal lines VL based on a gate potential. At least in a predetermined operating mode, a potential Vclip_dark is supplied to a gate of one of the clip transistors CL corresponding to at least one pixel column formed of the optical black pixels when reading a noise level from the pixels PX corresponding to the clip transistors CL and when reading a data level from the pixels PX corresponding to the clip transistors CL. | 2011-11-17 |
20110278653 | SOLID-STATE IMAGE PICKUP DEVICE - In a solid-state image pickup device according to this invention, because a photodiode | 2011-11-17 |
20110278654 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an interlayer insulation film, a wiring embedded in the interlayer insulation film and an air gap part formed between a side surface of the wiring and the interlayer insulation film. | 2011-11-17 |
20110278655 | Semiconductor Device with Circuit for Reduced Parasitic Inductance - Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad. | 2011-11-17 |
20110278656 | STACKED CAPACITOR FOR DOUBLE-POLY FLASH MEMORY - A stacked capacitor for double-poly flash memory is provided. The stacked capacitor is formed by a lower electrode, a lower dielectric layer, a central electrode, an upper dielectric layer, and an upper electrode, wherein the lower electrode is a doped region in a substrate. The manufacturing process of this stacked capacitor can be fully integrated in to the manufacturing process of the double-poly flash memory cell. | 2011-11-17 |
20110278657 | APPARATUS, SYSTEM, AND METHOD FOR CAPACITANCE CHANGE NON-VOLATILE MEMORY DEVICE - An apparatus, system, and method for a capacitance change non-volatile memory device. The apparatus may include a substrate, a source region in the substrate, a drain region in the substrate, a tunnel oxide layer on the substrate substantially between the source region and the drain region, a floating gate layer on the tunnel oxide layer, a resistance changing material layer on the floating gate layer, and a control gate on the resistance changing material layer. | 2011-11-17 |
20110278658 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction. | 2011-11-17 |
20110278659 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an oxidation film over a first and a second device region, forming an first etching preventing film extending over a first and a second area, removing the first etching preventing film over the first area; removing the oxidation film over the first device region, forming a first gate insulating film over the first device region, removing the oxidation film over the second device region, forming a second gate insulating film over the second device region, forming a first gate electrode over the first gate insulating film, forming a second gate electrode over the second gate insulating film, forming first source and drain regions in the first device region at both sides of the first gate electrode, and forming second source and drain regions in the second device region at both sides of the second gate electrode. | 2011-11-17 |
20110278660 | ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD. | 2011-11-17 |
20110278661 | APPARATUS INCLUDING RHODIUM-BASED CHARGE TRAPS - Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of electronic devices and systems. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge traps. | 2011-11-17 |
20110278662 | SEMICONDUCTOR DEVICE INCLUDING RECESSED CHANNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a recessed channel transistor, and a method of manufacturing the same, provide: a substrate in which an isolation trench is provided; an isolation layer provided in the isolation trench so as to define a pair of source/drain regions in the substrate; a gate pattern provided in the isolation trench between the pair of source/drain regions, the gate pattern having a top surface at a same level as a top surface of the isolation layer and having a bottom surface at a lower depth than the pair of source/drain regions with respect to a top surface of the substrate; and a gate insulating layer provided between the substrate and the gate pattern at a bottom surface of the isolation trench. | 2011-11-17 |
20110278663 | Semiconductor device - The semiconductor device of the present invention includes a first conductive type semiconductor layer; a second conductive type source region formed in a surface layer portion of the semiconductor layer; a groove formed by digging in the source region from a surface thereof; an insulating film laminated on the semiconductor layer to cover a surface of the semiconductor layer; a contact hole penetrating through the insulating film in a layer thickness direction at least at a position facing the groove; a wiring formed on the insulating film; and a contact plug embedded in the contact hole so that a bottom portion thereof enters the groove to electrically connect the wiring and the source. | 2011-11-17 |
20110278664 | Semiconductor device - An inventive semiconductor device includes: a semiconductor layer; a drift region of a first conductivity type provided in the semiconductor layer; a body region of a second conductivity type provided on the drift region in the semiconductor layer; a trench extending from a surface of the body region in the semiconductor layer with its bottom located in the drift region; a gate insulation film provided on an interior surface of the trench; a gate electrode provided in the trench with the intervention of the gate insulation film; a source region of the first conductivity type provided in the surface of the body region; a first impurity region of the second conductivity type provided around the bottom of the trench in spaced relation from the body region; and a second impurity region of the second conductivity type provided on a lateral side of the body region in the semiconductor layer, the second impurity region being isolated from the body region and electrically connected to the first impurity region. | 2011-11-17 |
20110278665 | HIGH-MOBILITY TRENCH MOSFETS - High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility. | 2011-11-17 |
20110278666 | Trench MOSFET with integrated Schottky diode in a single cell and method of manufacture - A trench MOSFET with integrated Schottky diode in a single cell includes a plurality of body regions extending to an epitaxial layer; a first trench extending through one of the body regions and reaching the epitaxial layer, the first trench being substantially filled by a conductive material that is separated from a sidewall of the first trench by a layer of dielectric material; and a second trench positioned between two adjacent body regions and extended into the epitaxial layer. Two source regions, two heavy body contact regions and the two adjacent body regions surround the second trench. The trench MOSFET further includes a Schottky diode having a metal layer formed along a sidewall and near a bottom of the second trench. In its manufacturing method, the spacer and self-alignment are processed two times, thus low cost and high reliability performance of the device are achieved at the same time. | 2011-11-17 |
20110278667 | SEMICONDUCTOR COMPONENT ARRANGEMENT AND METHOD FOR PRODUCING THEREOF - A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged. | 2011-11-17 |
20110278668 | Semiconductor Devices Having Bit Line Interconnections with Increased Width and Reduced Distance from Corresponding Bit Line Contacts and Methods of Fabricating Such Devices - A semiconductor device has a bit line interconnection with a greater width and a reduced level on a bit line contact is provided, as are methods of fabricating such devices. These method includes forming a buried gate electrode to intersect an active region of a substrate. Source and drain regions are formed in the active region. A first conductive pattern is formed on the substrate. The first conductive pattern has a first conductive layer hole configured to expose the drain region. A second conductive pattern is formed in the first conductive layer hole to contact the drain region. A top surface of the second conductive pattern is at a lower level than a top surface of the first conductive pattern. A third conductive layer and a bit line capping layer are formed on the first conductive pattern and the second conductive pattern and patterned to form a third conductive pattern and a bit line capping pattern. The second conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the drain region, constitute first bit line structures, and the first conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the isolation region, constitute second bit line structures. | 2011-11-17 |
20110278669 | SEMICONDUCTOR DEVICE - Disclosed is a high-voltage diode structure which realizes high reverse recovery capability and high maximum allowable forward current. The distance between a longitudinal end of a p well layer in an anode region and an element isolation region formed to surround the diode is 5 μm or shorter so as to allow a depletion layer to reach the element isolation region when a maximum rated reverse voltage is applied. During reverse recovery, the electric field strength at an end portion of a p well layer is reduced, hole current is reduced, and local temperature rises are reduced. | 2011-11-17 |
20110278670 | Apparatus, System, and Method for Tunneling Mosfets Using Self-Aligned Heterostructure Source and Isolated Drain - Apparatuses, systems, and methods for tunneling MOSFETs (TFETs) using a self-aligned heterostructure source and isolated drain. TFETs that have an abrupt junction between source and drain regions have an increased probability of carrier direct tunneling (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. | 2011-11-17 |
20110278671 | LATERALLY DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICE - A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length. | 2011-11-17 |
20110278672 | METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS - A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer. | 2011-11-17 |
20110278673 | METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS - A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer. | 2011-11-17 |
20110278674 | TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION - Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench. | 2011-11-17 |
20110278675 | IGFET Device Having an RF Capability - An IGFET device includes: —a semiconductor body having a major surface, —a source region of first conductivity type abutting the surface, —a drain region of the first conductivity-type abutting the surface and spaced from the source region with a channel therefrom, —an active gate overlying the channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, —a dummy gate positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface. | 2011-11-17 |
20110278676 | METHOD AND APPARATUS FOR ENHANCING CHANNEL STRAIN - An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer. | 2011-11-17 |
20110278677 | SRAM - An exemplary aspect of the present invention is an SRAM including: a first gate electrode that constitutes a first load transistor; a second gate electrode that extends in a longitudinal direction of the first gate electrode so as to be spaced apart from the first gate electrode, and constitutes a first drive transistor; a third gate electrode that extends in parallel to the first gate electrode, and constitutes a second load transistor; a first p-type diffusion region that is formed so as to intersect with the third gate electrode, and constitutes the second load transistor; and a first shared contact formed over the first and second gate electrodes and the first p-type diffusion region. The first p-type diffusion region extends to the vicinity of a first gap region between the first and second gate electrodes, and is not formed in the first gap region. | 2011-11-17 |
20110278678 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - This invention provides a semiconductor device having a semiconductor element that has low-resistance and a stable contact connection, even when the wiring is connected from the side of the single-crystal silicon layer on which the impurity concentration is lower. This invention provides a semiconductor device comprising, on a substrate, a semiconductor device having a single-crystal semiconductor film and a wiring connected to the single-crystal semiconductor film, and in the single-crystal semiconductor film, an impurity concentration on one surface side is different from an impurity concentration on another surface side, the wiring being connected to the surface side on which the impurity concentration is lower, the resistivity of a region of the single-crystal semiconductor film to which the wiring is connected being no less than 1 μΩcm and no more than 0.01 Ωcm. | 2011-11-17 |
20110278679 | SEMICONDUCTOR DEVICE, MASK FOR FABRICATION OF SEMICONDUCTOR DEVICE, AND OPTICAL PROXIMITY CORRECTION METHOD - A semiconductor device includes a circuit portion including at least one real feature, and a plurality of dummy feature groups each including a plurality of dummy features spaced apart from each other by a first distance. The plurality of dummy feature groups are spaced apart from each other by a second distance larger than the first distance, and the circuit portion and the plurality of dummy feature groups are spaced apart from each other by the second distance. | 2011-11-17 |
20110278680 | Strained Semiconductor Device and Method of Making the Same - In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess. | 2011-11-17 |
20110278681 | Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits - An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures. | 2011-11-17 |
20110278682 | Optimized Bonding Wire - Any two segments of a wire bonded on two bond pads at different elevations can be distinguished by a stationary node (or zero-displacement) during its second-mode vibration. In order to boost the natural frequency of such a bond wire to avoid a second-mode resonance occurring at the lowest frequency in the in-plane vibration, a wire can be optimized by connecting two equalized (shortest possible) wire segments to replace a wire consisting of a larger segment and a shorter segment. The purpose is to re-distribute a larger vibration movement in the longer segment with a lower stiffness of an arbitrary bond wire to two smaller equalized segments of an optimized wire to reduce an in-plane vibration to significantly improve the wire natural frequency and reliability in a harsh vibration environment such as over 30 kHz. | 2011-11-17 |
20110278683 | ACOUSTIC SENSOR AND METHOD OF MANUFACTURING THE SAME - In an acoustic sensor, a diaphragm arranged on an upper side of a silicon substrate includes a back chamber, and an anchor supports the diaphragm. An insulating plate portion fixed to an upper surface of the silicon substrate covers the diaphragm with a gap. A conductive fixed electrode film arranged on a lower surface of the plate portion configures a back plate. The change in electrostatic capacitance between the fixed electrode film and the diaphragm outputs to the outside from a fixed side electrode pad and a movable side electrode pad as an electric signal. A protective film is arranged continuously with the plate portion at an outer periphery of the plate portion. The protective film covers the outer peripheral part of the upper surface of the silicon substrate, and the outer periphery of the protective film coincides with the outer periphery of the upper surface of the silicon substrate. | 2011-11-17 |
20110278684 | ACOUSTIC SENSOR - A diaphragm for sensing sound pressure faces a back plate including a plate portion and a fixed electrode film to form a capacitance type acoustic sensor. The back plate is opened with acoustic holes for passing vibration, and is arranged with a plurality of stoppers in a projecting manner on a surface facing the diaphragm. The stopper arranged in an outer peripheral area of the back plate has a small diameter, and the stopper arranged in an internal area has a large diameter. Thus, sticking of the diaphragm is prevented, and the diaphragm is less likely to break by impact when the sensor is dropped. | 2011-11-17 |
20110278685 | SEMICONDUCTOR PRESSURE SENSOR - A semiconductor pressure sensor that can improve diaphragm breakage pressure tolerance is provided. | 2011-11-17 |
20110278686 | Semiconductor device and method of manufacturing semiconductor device - Provided is a semiconductor device for performing photoelectric conversion of incident light, including: a p-type substrate ( | 2011-11-17 |
20110278687 | BACKSIDE-ILLUMINATED SENSOR WITH NOISE REDUCTION - A backside-illuminated sensor includes a substrate, at least one lens and at least one pixel structure. The substrate has a front surface and a backside surface, and the lens is formed on the backside surface of the substrate and the pixel structure is formed on a pixel area included in the front surface of the substrate, where a projected area of the pixel area on the backside surface in a thickness direction of the substrate is covered by the lens. The pixel structure includes a first power node for receiving a first supply voltage, a second power node for receiving a second supply voltage different from the first supply voltage, a sensing element and a capacitor for noise reduction. The sensing element generates a sensing signal according to an incident luminance from the lens. | 2011-11-17 |
20110278688 | Solid-state imaging device - A solid-state imaging device includes a light-receiving portion, an optical filter layer, and quantum dots. The light receiving portion, where a photoelectric conversion is carried out, is formed in a semiconductor substrate. The optical filter layer is directly formed on or formed through another layer on the surface of the semiconductor substrate in which the light-receiving portion is formed. Quantum dots having substantially equal diameters are formed in the optical filter layer. The quantum dots have higher refractive indexes than the refractive index of the optical filter layer in which the quantum dots are embedded. | 2011-11-17 |
20110278689 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - A solid-state imaging device includes an n-type semiconductor substrate | 2011-11-17 |
20110278690 | High Density Photodiodes - The present invention is a front-side contact, back-side illuminated (FSC-BSL) photodiode arrays and front-side illuminated, back-side contact (FSL-BSC) photodiode arrays having improved characteristics, including high production throughput, low-cost manufacturing via implementation of batch processing techniques; uniform, as well as high, photocurrent density owing to presence of a large continuous homogeneous, heavily doped layer; and back to front intrachip connections via the homogenous, heavily doped layers on the front and back sides of the substrate. | 2011-11-17 |
20110278691 | THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS - The invention relates to a method of initiating molecular bonding, comprising bringing one face ( | 2011-11-17 |
20110278692 | SOLID-STATE IMAGE SENSING DEVICE HAVING A DIRECT-ATTACHMENT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A solid-state image sensing element includes an effective pixel section in a central area of a light receiving surface thereof, and a ridge-shaped protruding portion is provided around the effective pixel section. A liquid transparent adhesive is applied on the effective pixel section, and a light transparent substrate is placed thereon. The light transparent substrate is in contact with the protruding portion, and is therefore prevented from sliding with the liquid adhesive serving as a lubricant. Thus, the light transparent substrate can be fixed at a predetermined position. | 2011-11-17 |
20110278693 | HIGH-VOLTAGE VARIABLE BREAKDOWN VOLTAGE (BV) DIODE FOR ELECTROSTATIC DISCHARGE (ESD) APPLICATIONS - Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV | 2011-11-17 |
20110278694 | BIPOLAR PUNCH-THROUGH SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE - A bipolar punch-through semiconductor device has a semiconductor substrate, which includes at least a two-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact. One of the layers in the two-layer structure is a base layer of the first conductivity type. A buffer layer of the first conductivity type is arranged on the base layer. A first layer includes alternating first regions of the first conductivity type and second regions of the second conductivity type. The first layer is arranged between the buffer layer and the second electrical contact. The second regions are activated regions with a depth of at maximum 2 μm and a doping profile, which drops from 90% to 10% of the maximum doping concentration within at most 1 μm. | 2011-11-17 |
20110278695 | Semiconductor device - A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof. | 2011-11-17 |
20110278696 | Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device - A semiconductor device includes an internal circuit provided on a substrate, a plurality of external terminals connected to the internal circuit, a plurality of wires connecting the internal circuit and the external terminals, and a plurality of inductors communicating with an external device. Each of the inductors is connected to each of the wires. The external terminals are formed in a region not to interrupt communication between the inductors and the external device. | 2011-11-17 |
20110278697 | METAL-INSULATOR-METAL CAPACITOR AND METHOD FOR FABRICATING METAL-INSULATOR-METAL CAPACITOR STRUCTURES - A Metal-Insulator-Metal Capacitor and Method for Fabricating Metal-Insulator-Metal Capacitor Structures. The MIM (Metal insulator Metal) capacitor structure comprising a Capacitor Top Metal (CTM); a dielectric; and a Capacitor Bottom Metal (CBM); said CTM comprising an etch stop portion; a conductivity portion having a lower resistivity compared to the etch stop portion; and an interface portion of a different material from the conductivity portion; wherein the conductivity portion is sandwiched between the etch stop portion and the interface portion; and the interface portion interfaces the CTM with the dielectric. | 2011-11-17 |
20110278698 | Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers. | 2011-11-17 |
20110278699 | THREE-TERMINAL METAL-OXIDE-METAL CAPACITOR - A capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one dielectric layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit. | 2011-11-17 |
20110278700 | INTERNAL MATCHING TRANSISTOR - An internal matching transistor comprises: a conductive base material including a groove, a first region, and a second region which is located opposite to the first region across the groove; a transistor bonded onto the first region of the base material; an internal matching circuit bonded onto the second region of the base material; a wire connecting the transistor to the internal matching circuit across above the groove; and a conductive or non-conductive material located between the wire and the groove, wherein capacitance between the wire and the base material is adjusted by the material. | 2011-11-17 |
20110278701 | Scribe line structure for wafer dicing - The scribe line structure for wafer dicing according to the present invention includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and an upper one of the metal structures has a lower metal density than a lower one of the metal structures. In another aspect, the scribe line structure for wafer dicing includes a plurality of metal structures arranged up-and-down on a substrate in a dielectric layer, and each of the metal structures has a lower metal density on a dicing path for the wafer dicing than not on the dicing path. The scribe line structure can effectively avoid interlayer delamination or peeling issue caused by a dicing process, especially on a low-k/Cu wafer. | 2011-11-17 |