46th week of 2012 patent applcation highlights part 42 |
Patent application number | Title | Published |
20120288998 | WAFER LEVEL IC ASSEMBLY METHOD - A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced. | 2012-11-15 |
20120288999 | METHOD FOR MANUFACTURING SEMICONDUCTOR MODULES - A method for fabricating a semiconductor module includes: bonding a semiconductor substrate onto a first insulating resin layer; dicing the semiconductor substrate into a plurality of individual semiconductor devices; widening the spacings between the adjacent semiconductor devices by expanding the first insulating resin layer in a biaxially stretched manner; fixing the plurality of semiconductor devices to a flat sheet, with a second insulating resin layer held between the plurality of semiconductor devices and the flat sheet, and removing the first insulating resin layer; stacking the plurality of semiconductor devices, a third insulating resin layer, and a metallic plate, in this order, so as to form a laminated body having electrodes by which to electrically connect the device electrodes to the metallic plate; forming a wiring layer by selectively removing the metallic plate and forming a plurality of semiconductor modules; and separating the semiconductor modules into individual units. | 2012-11-15 |
20120289000 | DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention relates to a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer laminated in this order, and a film for semiconductor back surface provided on the pressure-sensitive adhesive layer of the dicing tape, where the pressure-sensitive adhesive layer has a thickness of from 20 μm to 40 μm. | 2012-11-15 |
20120289001 | Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance - A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness. | 2012-11-15 |
20120289002 | FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered. | 2012-11-15 |
20120289003 | Method for Forming a Semiconductor Device - A method for forming a semiconductor device is provided. The method includes providing a wafer-stack having a main horizontal surface, an opposite surface, a buried dielectric layer, a semiconductor wafer extending from the buried dielectric layer to the main horizontal surface, and a handling wafer extending from the buried dielectric layer to the opposite surface; etching a deep vertical trench into the semiconductor wafer at least up to the buried dielectric layer, wherein the buried dielectric layer is used as an etch stop; forming a vertical transistor structure comprising forming a first doped region in the semiconductor wafer; forming a first metallization on the main horizontal surface in ohmic contact with the first doped region; removing the handling wafer to expose the buried dielectric layer; and masked etching of the buried dielectric layer to partly expose the semiconductor wafer on a back surface opposite to the main horizontal surface. | 2012-11-15 |
20120289004 | FABRICATION METHOD OF GERMANIUM-BASED N-TYPE SCHOTTKY FIELD EFFECT TRANSISTOR - The present invention discloses a fabrication method of a Ge-based N-type Schottky field effect transistor and relates to a filed of ultra-large-scaled integrated circuit fabrication process. The present invention forms a thin high K dielectric layer between a substrate and a metal source/drain. The thin layer on one hand may block the electron wave function of metal from inducing an MIGS interface state in the semiconductor forbidden band, on the other hand may passivate the dangling bonds at the interface of Ge. Meanwhile, since the insulating dielectric layer has a very thin thickness, and electrons can substantially pass freely, the parasitic resistances of the source and the drain are not significantly increased. The method can weaken the Fermi level pinning effect, cause the Fermi energy level close to the position of the conduction band of Ge and lower the electron barrier, thereby increasing the current switching ratio of the Ge-based Schottky transistor and improve the performance of the NMOS device. | 2012-11-15 |
20120289005 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A thin film transistor having low off-state current and excellent electrical characteristics can be manufactured. In an inverted staggered thin film transistor including a semiconductor film in which at least a microcrystalline semiconductor region and an amorphous semiconductor region are stacked, a conductive film and an etching protective film are stacked over the semiconductor film; a mask is formed over the etching protective film; first etching treatment in which the etching protective film, the conductive film, and the amorphous semiconductor region are partly etched is performed; then, the mask is removed. Next, second etching treatment in which the exposed amorphous semiconductor region and the microcrystalline semiconductor region are partly dry-etched is performed using the etched etching protective film as a mask so that the microcrystalline semiconductor region is partly exposed to form a back channel region. | 2012-11-15 |
20120289006 | METHOD OF MANUFACTURING POLY-SILICON TFT ARRAY SUBSTRATE - An embodiment of the present disclosure relates to a method of manufacturing a poly-silicon TFT array substrate, which accomplishes a patterning process to form a gate electrode, a poly-silicon semiconductor pattern and a pixel electrode with one process by using an HTM or GTM mask. | 2012-11-15 |
20120289007 | MANUFACTURING METHOD FOR THIN FILM TRANSISTOR WITH POLYSILICON ACTIVE LAYER - Embodiments of the disclosed technology relate to a method for manufacturing a thin film transistor (TFT) with a polysilicon active layer comprising: depositing an amorphous silicon layer on a substrate, and patterning the amorphous silicon layer so as to form an active layer comprising a source region, a drain region and a channel region; depositing an inducing metal layer on the source region and the drain region; performing a first thermal treatment on the active layer provided with the inducing metal layer so that the active layer is crystallized under the effect of the inducing metal; doping the source region and the drain region with a first impurity for collecting the inducing metal; and performing a second thermal treatment on the doped active layer so that the first impurity absorbs the inducing metal remained in the channel region. | 2012-11-15 |
20120289008 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured. | 2012-11-15 |
20120289009 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE - A manufacturing method for a semiconductor structure includes providing a substrate having at least a gate structure formed thereon, performing a first wet etching process to etch the substrate at two sides of the gate structure, performing a second wet etching process to etch the substrate to form a recess respectively at two sides of the gate structure, and performing a selective epitaxial growth method to form an epitaxial layer having a diamond shape with a flat bottom respectively in the recess. | 2012-11-15 |
20120289010 | Semiconductor Device and Method of Making Same - A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly. | 2012-11-15 |
20120289011 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor integrated circuit device includes defining a first area by forming a separating area on a substrate, and forming a tunnel film in the first area, a floating gate on the tunnel film, a first electrode in the separating area, a first film on the floating gate, a second film on the first electrode, a control gate on the first film, a second electrode on the second film, and source and drain areas in the first area. The method includes forming a first interlayer film to cover the control gate and the second electrode, forming, in the first interlayer film, a conductive via plug reaching the second electrode, and forming, on the first interlayer film, a second wiring electrically coupled to the second electrode via the conductive via plug, and a first wiring that is capacitively-coupled to the second wiring and to the second electrode. | 2012-11-15 |
20120289012 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion. | 2012-11-15 |
20120289013 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset. | 2012-11-15 |
20120289014 | METHOD FOR FABRICATING TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER - A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor. | 2012-11-15 |
20120289015 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH ENHANCED CHANNEL STRESS - A method for fabricating a semiconductor device with enhanced channel stress is provided. The method includes the following steps. Firstly, a substrate is provided. Then, at least one source/drain region and a channel are formed in the substrate. A dummy gate is formed over the channel. A contact structure is formed over the source/drain region. After the contact structure is formed, the dummy gate is removed to form a trench. | 2012-11-15 |
20120289016 | LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR - One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein. | 2012-11-15 |
20120289017 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D | 2012-11-15 |
20120289018 | SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR - A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area. | 2012-11-15 |
20120289019 | METHODS OF FORMING A PATTERN AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - In a method of forming a pattern, a plurality of first line patterns and first spacers filling spaces between the adjacent first line patterns are formed on an object layer. The first line patterns and the first spacers extend in a first direction. A plurality of second line patterns are formed on the first line patterns and the first spacers. The second line patterns extend in a second direction substantially perpendicular to the first direction. The first spacers are partially removed by a wet etching process. The object layer is etched using the first and second line patterns as an etching mask. | 2012-11-15 |
20120289020 | METHOD FOR FABRICATING VARIABLE RESISTANCE MEMORY DEVICE - A method for fabricating a variable resistance memory device includes forming a semiconductor pattern doped with impurities, forming a resistor over the semiconductor pattern, and forming a diode by performing microwave annealing to activate the impurities in the semiconductor pattern. | 2012-11-15 |
20120289021 | METAL-INSULATOR-METAL STRUCTURE FOR SYSTEM-ON-CHIP TECHNOLOGY - The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer. | 2012-11-15 |
20120289022 | Methods of Forming Capacitors - A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode | 2012-11-15 |
20120289023 | Method for Producing a Semiconductor Device - A method for producing a semiconductor device having a sidewall insulation includes providing a semiconductor body having a first side and a second side lying opposite the first side. At least one first trench is at least partly filled with insulation material proceeding from the first side in the direction toward the second side into the semiconductor body. The at least one first trench is produced between a first semiconductor body region for a first semiconductor device and a second semiconductor body region for a second semiconductor device. An isolating trench extends from the first side of the semiconductor body in the direction toward the second side of the semiconductor body between the first and second semiconductor body regions in such a way that at least part of the insulation material of the first trench adjoins at least a sidewall of the isolating trench. The second side of the semiconductor body is partly removed as far as the isolating trench. | 2012-11-15 |
20120289024 | METHOD FOR FORMING THE SEMICONDUCTOR CELL - A semiconductor cell includes first trenches defining fin type active regions within the semiconductor substrate and adjacent to each other, second trenches disposed at one side and the other side of the first trenches, adjacent to the first trench and including fin type active regions, a first oxide layer formed on each of surfaces of the first trenches, and a second oxide layer formed on each of surfaces of the second trenches and having a thicker thickness than the first oxide layer. Although the critical dimension of the fin is increased, the gate drivability can be improved. | 2012-11-15 |
20120289025 | METHOD FOR MANUFACTURING BONDED WAFER - A method for manufacturing a bonded wafer including bonding together a bond wafer and a base wafer each having a chamfered portion at an outer circumference and thinning the bond wafer, wherein the thinning of the bond wafer includes: a first step of performing surface grinding on the bond wafer such that a thickness of the bond wafer reaches a first predetermined thickness; a second step of removing an outer circumference portion of the ground bond wafer; and a third step of performing surface grinding on the bond wafer such that the thickness of the bond wafer reaches a second predetermined thickness. | 2012-11-15 |
20120289026 | SPLITTING METHOD FOR OPTICAL DEVICE WAFER - In a splitting method for an optical device wafer, the wafer having optical devices formed individually in regions partitioned by a plurality of crossing scheduled splitting lines provided on a front surface and having a reflective film formed on a reverse surface, a focal point of a laser beam is positioned to the inside of the optical device wafer and the laser beam is irradiated along the scheduled splitting lines from the reverse surface side of the wafer to form modification layers in the inside of the wafer. An external force is applied to the wafer to split the wafer along the scheduled splitting lines and form a plurality of optical device chips. The laser beam has a wavelength that produces transmittance through the reflective film equal to or higher than 80%. | 2012-11-15 |
20120289027 | DEVICE PROCESSING METHOD - In a device processing method, a laser beam is applied to a wafer along division lines from the back side of the wafer, thereby forming a division start point inside the wafer along the division lines at a depth not reaching the finished thickness of each device. A protective member is attached to the front side of the wafer before or after performing the division start points are formed. An external force is applied through the protective member to the wafer, thereby dividing the wafer along the division lines to obtain the individual devices. The back side of the wafer is ground to remove the modified layers, and a silicon nitride film is formed on at least the side surface of each device. The silicon nitride film has a gettering effect and is formed on the side surface of each device, which surface is formed by a cleavage plane. | 2012-11-15 |
20120289028 | WAFER DIVIDING METHOD - A wafer dividing method including a step of applying a laser beam to a wafer along division lines with the focal point of the laser beam set inside the wafer, thereby forming modified layers inside the wafer along the division lines; a step of attaching an adhesive tape to the wafer, the adhesive tape having a base sheet and an adhesive layer; a dividing step of applying an external force to the wafer by expanding the adhesive tape, thereby dividing the wafer along the division lines to obtain a plurality of device chips; and a debris catching step of heating the adhesive tape to thereby soften the adhesive layer such that it enters the space between any adjacent ones of the device chips obtained by the dividing step, thereby catching debris generated on the side surface of each device chip in the dividing step to the adhesive layer by adhesion. | 2012-11-15 |
20120289029 | METHOD OF CONTROLLING AMOUNT OF ADSORBED CARBON NANOTUBES AND METHOD OF FABRICATING CARBON NANOTUBE DEVICE - Provided are a method of controlling an amount of adsorbed carbon nanotubes (CNTs) and a method of fabricating a CNT device. The method of controlling an amount of adsorbed CNTs includes adsorbing CNT particles onto a semiconductor structure, and removing some of the adsorbed CNTs by performing an oxygen plasma treatment on the adsorbed CNT particles. | 2012-11-15 |
20120289030 | ION-ASSISTED DIRECT GROWTH OF POROUS MATERIALS - Methods of creating porous materials, such as silicon, are described. In some embodiments, plasma sheath modification is used to create ion beams of various incidence angles. These ion beams may, in some cases, form a focused ion beam. The wide range of incidence angles allows the material to be deposited amorphously. The porosity and pore size can be varied by changing various process parameters. In other embodiments, porous oxides can be created by adding oxygen to previously created layers of porous material. | 2012-11-15 |
20120289031 | COMPOUND SEMICONDUCTOR GROWTH USING ION IMPLANTATION - A workpiece is implanted to affect growth of a compound semiconductor, such as GaN. Implanted regions of a workpiece increase, reduce, or prevent growth of this compound semiconductor. Combinations of implants may be performed to cause increased growth in certain regions of the workpiece, such as between regions where growth is reduced. Growth also may be reduced or prevented at the periphery of the workpiece. | 2012-11-15 |
20120289032 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed. Over the main surface, insulating films | 2012-11-15 |
20120289033 | METHOD AND DEVICE FOR PRODUCING A COMPOUND SEMICONDUCTOR LAYER - In a method for producing a I-III-VI compound semiconductor layer, a substrate is provided with a coating which has a metallic precursor layer. The coating is kept, for the duration of a process time, at temperatures of at least 350 degrees C. and the metallic precursor layer, in the presence of a chalcogen at an ambient pressure of between 500 mbar and 1500 mbar, is converted into a compound semiconductor layer. The coating is kept at temperatures for the duration of an activation time which attain at least an activation barrier temperature, whereby as the activation barrier temperature a value of at least 600° C. is selected. | 2012-11-15 |
20120289034 | Methods of Forming NAND Memory Constructions - Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions. | 2012-11-15 |
20120289035 | NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS - A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing. | 2012-11-15 |
20120289036 | SURFACE DOSE RETENTION OF DOPANTS BY PRE-AMORPHIZATION AND POST IMPLANT PASSIVATION TREATMENTS - The invention generally relates to pre-implant and post-implant treatments to promote the retention of dopants near the surface of an implanted substrate. The pre-implant treatments include forming a plasma from an inert gas and implanting the inert gas into the substrate to render an upper portion of the substrate amorphous. The post-implant treatment includes forming a passivation layer on the upper surface of the substrate after doping the substrate in order to retain the dopant during a subsequent activation anneal. | 2012-11-15 |
20120289037 | METHOD FOR FABRICATING SEMICONDUCTOR POWER DEVICE - A method for fabricating a semiconductor power device includes the following steps. First, a substrate having at least a semiconductor layer and a pad layer thereon is provided. At least a trench is etched into the pad layer and the semiconductor layer. Then, a dopant source layer is deposited in the trench and on the pad layer followed by thermally driving in dopants of the dopant source layer into the semiconductor layer. A polishing process is performed to remove the dopant source layer from a surface of the pad layer and a thermal oxidation process is performed to eliminate micro-scratches formed during the polishing process. Finally, the pad layer is removed to expose the semiconductor layer. | 2012-11-15 |
20120289038 | SEMICONDUCTOR DEVICE HAVING CONTROLLABLE TRANSISTOR THRESHOLD VOLTAGE - In an embodiment, a semiconductor device includes a single-layer gate nonvolatile memory in which a floating gate is formed on a semiconductor substrate. The floating gate is formed above a diffusion layer serving as a control gate of the nonvolatile memory. The diffusion layer may be insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers may be formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film in an embodiment. The configuration described herein may realize a reliable semiconductor device in a low-cost process, may have a control gate which may withstand a high voltage applied when data is erased or written, and may prevent an operation error by minimizing variations in the threshold value, in some embodiments. | 2012-11-15 |
20120289039 | PATTERN FORMING METHOD - According to one embodiment, an opening pattern is formed in the core film above a processing target, and a mask film is conformally formed above the processing target. Next, etch-back of the mask film is performed so that the mask film remains on a side surface of the core film. After that, line-and-space shaped core patterns, made of the core film, is formed in an area other than an area forming the opening pattern. Next, sidewall patterns are formed around the core patterns, and the core patterns are removed. Next, the processing target is patterned by using the mask film and the sidewall patterns. | 2012-11-15 |
20120289040 | FABRICATION METHODS OF INTEGRATED SEMICONDUCTOR STRUCTURE - An integrated circuit device and method for manufacturing an integrated circuit device is disclosed. The integrated circuit device comprises a core device and an input/output circuit. Each of the core device and input/output circuit includes a PMOS structure and an NMOS structure. Each of the PMOS includes a p-type metallic work function layer over a high-k dielectric layer, and each of the NMOS structure includes an n-type metallic work function layer over a high-k dielectric layer. There is an oxide layer under the high-k dielectric layer in the input/output circuit. | 2012-11-15 |
20120289041 | BALLASTED POLYCRYSTALLINE FUSE - A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse. | 2012-11-15 |
20120289042 | Arrangement for solder bump formation on wafers - An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon. | 2012-11-15 |
20120289043 | METHOD FOR FORMING DAMASCENE TRENCH STRUCTURE AND APPLICATIONS THEREOF - A method for fabricating a damascene trench structure, wherein the method comprises steps as follows: A semiconductor structure having an inner layer dielectric (ILD) and a patterned hard mask stacked in sequence is firstly provided, in which a trench extends from the patterned hard mask downwards into the ILD. Subsequently, the patterned hard mask is etched in an atmosphere essentially consisting of nitrogen (N | 2012-11-15 |
20120289044 | SEMICONDUCTOR SUBSTRATE, ELECTRODE FORMING METHOD, AND SOLAR CELL FABRICATING METHOD - A semiconductor substrate having an electrode formed thereon, the electrode including at least silver and glass frit, the electrode including: a multi-layered structure with a first electrode layer joined directly to the semiconductor substrate, and an upper electrode layer formed of at least one layer and disposed on the first electrode layer. The upper electrode layer is formed by firing a conductive paste having a total silver content of 75 wt % or more and 95 wt % or less, the content of silver particles having an average particle diameter of 4 μm or greater and 8 μm or smaller with respect to the total silver content in the upper electrode layer being higher than that in the first electrode layer. | 2012-11-15 |
20120289045 | METHOD FOR MAKING HOLES USING A FLUID JET - The method for making a hole in a layer includes the provision of first and second adhesion areas on a surface of a support. The first area has dimensions corresponding to the dimensions of the hole. The method includes depositing a layer on the first and second adhesion areas. The material of the layer has an adhesion coefficient to the first area lower than the adhesion coefficient to the second area. The part of layer arranged above the first area is eliminated by a fluid jet. | 2012-11-15 |
20120289046 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for forming a polysilicon layer includes forming an amorphous silicon layer over a substrate, performing a first thermal treatment of the amorphous silicon layer by performing an implantation with a gas that includes silicon (Si), and performing a second thermal treatment on the thermally treated layer at a temperature higher than a temperature of the first thermal treatment. | 2012-11-15 |
20120289047 | Method for Producing a Connection Region on a Side Wall of a Semiconductor Body - A method for producing a connection region on a side wall of a semiconductor body is disclosed. A first trench is produced on a first surface of a semiconductor body and extends into the semiconductor body. An insulation layer is formed on the side walls and on the bottom of the first trench, and the first trench is only partially filled. The unfilled part of the first trench is filled with an electrically conductive material. A separating trench is produced along the first trench in such a way that a side wall of the separating trench directly adjoins the first trench. The part of the insulation layer which adjoins the separating trench is at least partially removed, with the result that at least some of the electrically conductive material in the first trench is exposed. | 2012-11-15 |
20120289048 | Method for obtaining a layout design for an existing integrated circuit - A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure. | 2012-11-15 |
20120289049 | COPPER OXIDE REMOVAL TECHNIQUES - A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H | 2012-11-15 |
20120289050 | METHOD OF ETCHING TRENCHES IN A SEMICONDUCTOR SUBSTRATE UTILIZING PULSED AND FLUOROCARBON-FREE PLASMA - A method of etching trenches in a semiconductor substrate. A patterned hard mask is formed over a semiconductor substrate. Using the patterned hard mask as an etching mask, a plasma etching process is then carried out to etch trenches into the semiconductor substrate not covered by the patterned hard mask, wherein the plasma etching process employs a fluorocarbon-free plasma etching chemistry and is performed under a plasma pulse output mode. | 2012-11-15 |
20120289051 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed. | 2012-11-15 |
20120289052 | Methods for Manufacturing High Dielectric Constant Films - Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface. | 2012-11-15 |
20120289053 | Semiconductor Processing System Having Multiple Decoupled Plasma Sources - A semiconductor substrate processing system includes a substrate support defined to support a substrate in exposure to a processing region. The system also includes a first plasma chamber defined to generate a first plasma and supply reactive constituents of the first plasma to the processing region. The system also includes a second plasma chamber defined to generate a second plasma and supply reactive constituents of the second plasma to the processing region. The first and second plasma chambers are defined to be independently controlled. | 2012-11-15 |
20120289054 | Semiconductor Processing System Having Multiple Decoupled Plasma Sources - A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma. | 2012-11-15 |
20120289055 | LIQUID COMPOSITION, METHOD OF PRODUCING SILICON SUBSTRATE, AND METHOD OF PRODUCING LIQUID DISCHARGE HEAD SUBSTRATE - A liquid composition used to carry out crystal anisotropic etching of a silicon substrate provided with an etching mask formed of a silicon oxide film with the silicon oxide film used as a mask includes cesium hydroxide, an alkaline organic compound, and water. | 2012-11-15 |
20120289056 | SELECTIVE SILICON NITRIDE ETCH - Methods and etchant solutions for etching silicon nitride on a workpiece are provided. One method generally includes exposing the workpiece to a chemistry mixture including phosphoric acid and a diluent, wherein the chemistry mixture has a water content of less than 10% by volume, and heating at least one of the workpiece and the chemistry mixture to a process temperature to etch silicon nitride from the workpiece. | 2012-11-15 |
20120289057 | APPARATUS AND METHOD FOR MULTIPLE SYMMETRICAL DIVISIONAL GAS DISTRIBUTION - An apparatus and method for multiple symmetrical divisional gas distribution providing a mounting plate, a plurality of manifolds coupled to the mounting plate, a center purge block coupled to the mounting plate and the plurality of manifolds, a plurality of reactant distribution blocks, wherein each reactant distribution block is stacked atop each other to form a reactant distribution block stack, wherein the reactant distribution block stack sits atop the center purge block, a coupling mechanism to secure the plurality of reactant distribution blocks of the reactant distribution block stack together; and a top cap coupled to the reactant distribution block stack and the coupling mechanism. | 2012-11-15 |
20120289058 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Adverse effects when a carrier is open, such as particles adhesion to the substrate or natural oxidation film deposits on the substrate, as well as a rise in oxygen concentration and contamination of the substrate transfer chamber are prevented. Semiconductor manufacturing apparatus includes a carrier in which a cover unit is provided on a substrate loading/unloading opening for loading and unloading a substrate, a carrier open/close chamber continuously arranged to the carrier, a substrate transfer chamber continuously arranged to the carrier open/close chamber, a substrate processing chamber continuously arranged to the substrate transfer chamber, an exhaust means for exhausting the atmosphere in the carrier open/close chamber by suction, and an exhaust quantity adjuster means for adjusting the suction exhaust quantity of the exhaust means. | 2012-11-15 |
20120289059 | CHEMICAL VAPORIZER FOR MATERIAL DEPOSITION SYSTEMS AND ASSOCIATED METHODS - System and method for operating a material deposition system are disclosed. In one embodiment, the method can include periodically injecting a precursor into a vaporizer through an injector at the vaporizer, vaporizing the precursor in the vaporizer and supplying the vaporized precursor to a reaction chamber in fluid communication with the vaporizer, and shutting down the vaporizer and the reaction chamber after a period of time. The method can also include conducting maintenance of the injector at the vaporizer by using a vapor solvent rinse. | 2012-11-15 |
20120289060 | WAFER PROCESSING METHOD - In a wafer processing method, the back side of a wafer having a plurality of devices on the front side thereof is ground, thereby reducing the thickness of the wafer to a predetermined thickness. The back side of the wafer is polished after performing the back grinding step, thereby removing a grinding strain, and a silicon nitride film is formed on the back side of the wafer. The thickness of the silicon nitride film to be formed in the silicon nitride film forming step is set to 6 to 100 nm. Thus, the silicon nitride film having a thickness of 6 to 100 nm is formed on the polished back side of the wafer from which a grinding strain has been removed. Accordingly, each device constituting the wafer can ensure a sufficient die strength and a sufficient gettering effect. | 2012-11-15 |
20120289061 | NANOLAYER DEPOSITION PROCESS - A hybrid deposition process of CVD and ALD, called NanoLayer Deposition (NLD) is provided. The NLD process is a cyclic sequential deposition process, including introducing a first plurality of precursors to deposit a thin film and introducing a second plurality of precursors to modify the deposited thin film. The deposition using the first set of precursors is not self limiting and is a function of substrate temperature and process time. The second set of precursors modifies the already deposited film characteristics. The second set of precursors can treat the deposited film, including treatments such as modification of film composition and doping or removal of impurities from the deposited film. The second set of precursors can also deposit another layer on the deposited film. The additional layer can react with the existing layer to form a compound layer, or can have minimum reaction to form a nanolaminate film. | 2012-11-15 |
20120289062 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 2012-11-15 |
20120289063 | Methods For Manufacturing High Dielectric Constant Films - Provided are methods for depositing a high-k dielectric film on a substrate. The methods comprise annealing a substrate after cleaning the surface to create dangling bonds and depositing the high-k dielectric film on the annealed surface. | 2012-11-15 |
20120289064 | Slip-Ring Unit - A slip-ring unit includes a first and a second group of components which are arranged in a manner allowing rotation relative to each other about an axis. The first group of components includes a slip-ring brush which is secured to a holder that is mounted between two components which are offset relative to each other in the direction of the axis. The second group of components includes at least one slip ring. The holder and at least one of the components each have an effective area by which a form-locking connection is produced between the holder and the at least one component. Forces having a directional component parallel to the axis are transmittable by the form-locking connection. | 2012-11-15 |
20120289065 | CIRCUIT BOARD AND METHOD OF MANUFACTURING INKJET HEAD - According to one embodiment, a circuit board includes a board main body, an electrode, a circuit plate and a connector. The board main body includes a first surface, a second surface located opposite to the first surface, a first side edge that extends between the first surface and the second surface, and a second side edge that extends between the first surface and the second surface and intersects the first side edge. The second side edge is provided with a fitting part. The electrode is provided on the first surface. The circuit plate is soldered to the electrode and has flexibility. The connector is attached to the board main body. A cable is inserted into the connector in a direction perpendicular to the first side edge. | 2012-11-15 |
20120289066 | CONNECTOR MECHANISM FOR CONNECTING A BOARD CARD - A connector mechanism for connecting a board card is disclosed. The connector mechanism includes a circuit board, and a connector installed on the circuit board. An end of the board card is for inserting into the connector. The connector mechanism further includes a socket installed on the circuit board and located on a side of the connector, a rotating component pivoted to the socket, and at least one connecting component sliably installed on the rotating component and coupled to the circuit board for contacting with the other end of the board card so as to electrically connect to the board card as the end of the board card is inserted into the connector and the rotating component rotates to a connection position. | 2012-11-15 |
20120289067 | WATERPROOF ELECTRICAL CONNECTOR AND SYSTEM - In one possible embodiment, a waterproof connector is provided having pins secured to a bendable board. The bendable board and a portion of each of the pins are encased in a compressible material capable of providing a biasing force on the plurality of pins upon mating with a mating surface. The compressible material also provides a deformable sealing surface for mating with the mating surface. | 2012-11-15 |
20120289068 | MITIGATING ELECTROMAGNETIC INTERFERENCE USING DUMMY PLUGS - A system and method for mitigating EMI in an electronic device rely on a set of foam dummy plugs specially configured for insertion into socket connectors according to connector type. The foam plugs have no electrical terminals or wiring, but are made from a foam composite material that attenuates electromagnetic radiation by absorption. The foam composite material includes a foam matrix and electrically conductive particles impregnated within the foam matrix. A handle may be unitarily formed with the foam plug. The handle may include a stamped through-hole, forming a ring, to facilitate insertion and removal of the dummy plugs by hand. | 2012-11-15 |
20120289069 | Apparatus for Blocking I/O Interfaces of Computing Devices - An input/output (I/O) interface blocking device includes a fitting member. The fitting member includes a protruding portion, which includes a first sidewall and a second sidewall opposite to each other. The first sidewall is slanted in a direction allowing the first fitting member to be inserted into a space in an I/O interface receptacle. The second sidewall is configured to block the fitting member from being pulled out of the space in the I/O interface receptacle. | 2012-11-15 |
20120289070 | LEVER-TYPE CONNECTOR | 2012-11-15 |
20120289071 | ELECTRICAL CONNECTOR HAVING OFFSET MOUNTING TERMINALS - In accordance with one embodiment, an electrical connector includes a housing that supports a plurality of electrical contacts. Each electrical contact defines a mating end and an opposing mounting end, and a plurality of mounting terminals disposed at the mounting end. The mounting terminals of each contact are arranged in at least one column extending along a longitudinal direction, such that each column is spaced along a lateral direction, and the mounting terminals of adjacent contacts are longitudinally offset. | 2012-11-15 |
20120289072 | TERMINATION UNIT FOR MULTI-PHASE SUPERCONDUCTOR CABLE - A termination unit for a multi-phase superconductor cable has, for each phase, a cylindrical modular element ( | 2012-11-15 |
20120289073 | POWER ADAPTER WITH A CHANGEABLE PLUG - A power adapter includes a main body, electrical conductive terminals provided in the main body, and a plug. The plug includes a base, a first insertion piece and a second insertion piece. A first side of the base is formed with first directional grooves, and a second side thereof is formed with second directional grooves. The first insertion piece is provided with first insertion portions. The second insertion piece is provided with second insertion portions. The first side or second side of the plug penetrates the main body. The first insertion portion and the second insertion portion press the electrical conductive terminals, so that the first insertion piece and the second insertion piece are electrically connected with the electrical conductive terminals respectively. By this structure, the direction for the plug being inserted into a power socket can be changed based on practical demands. | 2012-11-15 |
20120289074 | POWER STRIP DEVICE - A power strip device includes a casing and a plurality of socket modules. The casing has a casing body and a plurality of aligned retaining parts formed in the casing body. The socket modules are disposed respectively in the retaining parts. Each of the socket modules has a main body and a socket unit that is formed in the main body. The main body of at least one of the socket modules is movable between a first position to be aligned with the main body of the rest of the socket modules, and a second position to be misaligned with the main body of the rest of the socket modules. | 2012-11-15 |
20120289075 | INDIVIDUAL LOADING MECHANISM WITH SIMPLIFIED LOCKING ARRANGEMENT - An electrical connector assembly includes a printed circuit board, a socket connector assembled on the printed circuit board and a chip module seating on the insulative socket. The socket connector assembly has an insulating socket having a plurality of terminals received therein, a cover located on the insulating housing and three retention members secured to the printed circuit board and mating with the cover. The cover is attached to two of the retention members and capable of linear and rotational movements with regarding to said retention members so that the cover presses the chip module and is secured by another retention member. | 2012-11-15 |
20120289076 | SPRING-TO BOARD I/O-CONNECTOR ASSEMBLY, MEMBERS THEREOF AND BOARD PROVIDED THEREWITH - A board connector assembly, comprises a shield and securing member as well as a connector member. The shield and securing member is configured for mounting on a board close to contacts on the board and is provided with a coupling for securing the connector member thereto. The connector member is provided with coupling for cooperation with the coupling on the shield and securing member for securing the connector member to the shield and securing member, thereby preventing the connector member from disturbing surrounding circuitry, and is further provided with contacts which, when the connector member is secured to the shield and securing member, is connected to the contacts on the board. The present invention also relates to shield and securing member and a connector member, respectively, for use in the board connector assembly, as well as to a printed wiring board comprising one or more board connector assemblies. | 2012-11-15 |
20120289077 | ELECTRICAL CONNECTOR - An electrical connector comprises an insulating seat, a plurality of conductive terminals inserted on the insulating seat, and a cage covering on the insulating seat. The insulating seat comprises a body, a tongue plate projecting forward from the body for the arrangement of the conductive terminals, and a bottom plate extending along from the body under the tongue plate. The cage includes a bottom wall located between the tongue plate and the bottom plate of the insulating seat. The electrical connector further comprises a securing part for securing the insulating seat. The securing part comprises a main body abutting above the bottom plate of the insulating seat and two soldering parts bend downwards and extending from two ends of the main body respectively. | 2012-11-15 |
20120289078 | WIRE HOLDER AND TERMINAL CONNECTOR FOR HOT WIRE CHEMICAL VAPOR DEPOSITION CHAMBER - Apparatus for supporting the wires in a hot wire chemical vapor deposition (HWCVD) system are provided herein. In some embodiments, a terminal connector for a hot wire chemical vapor deposition (HWCVD) system may include a base; a wire clamp moveably disposed with relation to the base along an axis; a reflector shield extending from the wire clamp in a first direction along the axis; and a tensioner coupled to the base and wire clamp to bias the wire clamp in a second direction opposite the first direction. | 2012-11-15 |
20120289079 | TIGHTENING INDICATOR FOR COAXIAL CABLE CONNECTOR - A coaxial cable connector, comprising an outer body having a first end and a second end, the outer body configured to mate with a port, and an inner body having a first end and a second, the inner body configured to radially surround a portion of a coaxial cable, wherein the outer body is moveable with respect to the inner body between a first position in which the connector is not mounted to the port and a second position when the connector is mounted to the equipment port, wherein, in the first position, an indicator portion is not visible, wherein, in the second position, the indicator portion is visible is provided. An associated method is also provided. | 2012-11-15 |
20120289080 | CABLE MODULE CAPABLE OF SIMULTANEOUSLY SUPPORTING QUICK CHARGE AND DATA TRANSMISSION OF ELECTRONIC DEVICE - The present invention discloses a cable module capable of simultaneously supporting quick charge and data transmission of an electronic device, comprising: a USB device, which is a USB connector, and includes a circuit board and a protruding plug portion, and the circuit board has an integrated circuit and a switch electrically coupled to the circuit board, and the integrated circuit has a specification and a property for recognizing a portable electronic device which are saved in the integrated circuit, and the switch is set to at least a quick charge mode and a data transmission mode; and a cable device, with an end electrically coupled to the USB device, and the other end having an electric connector, so that the composite cable module can support quick charge and data transmission of an electronic device simultaneously, manage the electronic device effectively and provide convenient carry and use. | 2012-11-15 |
20120289081 | DECORATIVE POWER OUTLET AND DEVICE CHARGING STATION STAND - The invention is a decorative tree shaped power outlet stand. The device provides power outlets and charging or communication ports through a hollow decorative stand. The outlets, universal serial bus (USB) ports, micro USB ports, mini USB ports, smart phone charging ports, and serial communication ports, are spaced apart on the stand to allow access to the power outlets from several directions. The outlets are spaced apart on the tree shaped stand so that large adapter plugs may easily be plugged in without interfering with or covering the other sockets. The tree has limbs or extensions that are flexible to slightly give under the weight of adapter plugs that are connected to the outlets on the extensions. | 2012-11-15 |
20120289082 | ELECTRICAL INTERFACE AND METHOD - A mounting base is disclosed comprising: a base housing configured to retain an electrical connector at a first base housing end and a flexible shaft at a second base housing end, the base housing providing an electrical path between the electrical connector and a first electrical wire in the flexible shaft; a contact spring for providing an electrical connection to a power terminal on the electrical connector; a insulation sleeve enclosing the contact spring; a contact eyelet electrically attached to a second electrical wire in the flexible shaft, the contact eyelet in electrical contact with the contact spring; and a grounding collar disposed against an end of the flexible shaft, the grounding collar disposed within an interior channel in the second base housing end. | 2012-11-15 |
20120289083 | HIGH-VOLTAGE COAXIAL CABLE AND CONNECTOR - A high-voltage coaxial cable and a connector are provided. The connector includes inner connector electrode, a connector dielectric enclosing an inner connector electrode, and an external connector housing. The inside electrode of a connector is provided with a tapped hole in one side thereof. The tapped hole corresponds to the threaded single core of a high-voltage coaxial cable. The inside electrode of a connector is selectively assembled with and separated from the high-voltage coaxial cable by selectively screwing the threaded single core into and away from the tapped hole. The connector dielectric is formed along the circumferential surface of the inside electrode, and is provided with a coupling portion. The coupling portion couples the connector with another connector, and is formed to a preset depth in a corrugated shape. The connector housing is formed in a shape that surrounds the connector dielectric. | 2012-11-15 |
20120289084 | SWITCH-EQUIPPED COAXIAL CONNECTOR - Instability of an electric connection state due to solder-wicking from a board connecting part of an electrically-conductive shell can be prevented with a simple configuration. A recessed part recessed toward a fixed contact and a movable contact is provided in the board connecting part of the electrically-conductive shell attached to an insulating housing. An excessive amount of a solder material or flux that is used at the board connecting part of the electrically-conductive shell and tries to rise along the wall surfaces of the board connecting part or the electrically-conductive shell is stored in the recessed part. The acting force of the rise is reduced by a reverse-tapered inclined surface constituting a wall surface of the recessed part. Furthermore, the length of the rise of the solder material and flux is extended by a curved wall surface of the recessed part. Thus, so-called solder-wicking is configured to be prevented well. | 2012-11-15 |
20120289085 | SWITCH-EQUIPPED COAXIAL CONNECTOR - Occurrence of defective electrical connection caused by dust that has entered the interior through a corresponding insertion hole can be prevented well by a simple configuration. A through hole facing a corresponding insertion hole is formed to penetrate through a movable contact attached to an insulating housing, and two corresponding connector contact pieces are disposed respectively in both sides sandwiching the through hole. Thus, the dust that has entered the interior through the corresponding insertion hole opened when a corresponding connector is not mated is configured to be discharged through the through hole without accumulating the dust on the movable contact to reduce the risk that the electrical conductivity between the movable contact and the fixed contact may be disturbed by the dust. | 2012-11-15 |
20120289086 | SERVICEABLE INLINE AC FUSE HOLDER - An inline fuse holder for housing a fuse that electrically connects first and second wire terminals is provided. The inline fuse holder can generally include a cannulated fuse holder housing having a cylindrical inner periphery. The fuse holder housing can have a first end that defines a first opening, and a second end that defines a second opening. The first and second ends comprise first locking features. A first wire connector includes a connector housing that defines a through bore. The connector housing can have a boss configured to be received by the first opening of the fuse holder housing. The first wire connector further includes a second locking feature that is configured to selectively lock with one of the first locking features in the installed position. | 2012-11-15 |
20120289087 | CONNECTOR - A connector ( | 2012-11-15 |
20120289088 | COLD HEADED ELECTRIC PLUG ARM - A power adapter plug arm manufactured from a single piece of material is provided. The plug arm can include a plug operative to extend into a wall socket, an elongated plate coupled to an end of the plug such that the plug extends from a first surface of one end of the plate, and a pin coupled to the opposite end of the plate and extending from the opposite surface of the plate. The pin can be operative to engage a circuit board of the power adapter to provide power received from the wall socket to an electronic device coupled to the power adapter. To enhance the strength of the plug arm, the plate can be manufactured by creating a co-axial plug and a stem from a single piece of material, bending the stem, and cold heading the bent portion of the stem to form a plate. | 2012-11-15 |
20120289089 | USB Connector - The present invention relates to a USB connector, which comprises: a connector main body having plural open slots, plural first terminals and plural second terminals; and a substrate having plural first contact pads and plural second contact pads respectively exposed outside the substrate, and the plural first contact pads and the plural second contact pads are staggeringly arranged for being respectively coupled to the plural first terminals and the plural second terminals, thereby forming a USB connector. The USB connector allows a USB2.0 connector and a USB3.0 connector to be respectively inserted. | 2012-11-15 |
20120289090 | ELECTRICAL CONNECTOR AND HARNESS - A waterproof connector includes a female contact, a housing, and a retainer. The housing includes a first inner wall surface, a second inner wall surface, a first engaging part, and a lance. The female contact includes a pressed surface that is pressed by the lance, and a first engaged part that is formed to protrude in a direction away from the pressed surface. A second engaging part is formed in the housing and a second engaged part that can be engaged with the second engaging part is formed in the female contact so that a second engagement between the housing and the female contact is achieved on a side opposite to the side of a first engagement between the first engaging part and the first engaged part with respect to a central axis of the female contact. | 2012-11-15 |
20120289091 | SENSOR - The object of the present invention is to provide a sensor which has an advantage in reduction of the noise and for down sizing, and also which are capable to produce easily. A sensor comprising: a case member housing a resistance substrate and a mobile element which slides against said resistance substrate and formed with an aperture leading to said resistance substrate; a connector member having a connector terminal, a cover unit which is a part of a resin covering said connector terminal and covers said aperture of said case member, and a connector unit which is other part of the resin covering said connector terminal and is connected with an external terminal; and a clip resiliently contacting with said connector terminal and said resistance substrate, and electrically connecting said connector terminal and said resistance substrate. Said clip comprises a fulcrum and two leg units consisting of a first leg unit and a second leg unit extending to two directions from said fulcrum and said clip has a cross sectional shape of roughly a V shape or U shape. Said clip is engaged with an end unit of said resistance substrate in a status that said resistance substrate is sandwiched between said first leg unit and said second leg unit. A housing depression is formed in said connector member at a position opposing said resistance substrate, said housing depression comprises a first lateral wall contacting with a first external face which is an external face of said first leg unit and a second lateral wall contacting with a second external face which is an external face of said second leg unit, and said housing depression houses said clip in a status that said clip is sandwiched between said first lateral wall and said second lateral wall. A part of said connector terminal is exposed from the resin covering said connector terminal to form at least one of said first lateral wall and said second lateral wall. | 2012-11-15 |
20120289092 | ELECTRICAL CONNECTOR - An electrical connector including a housing to be mounted on an outer surface of a main circuit board, conductive contacts arranged in the housing and an actuator operative to take selectively a first station for releasing each of the conductive contacts from press-contact with one of connecting terminals on a flat circuit device inserted in the housing and a second station for causing each of the conductive contacts to maintain the press-contact with the connecting terminal, wherein the actuator has a particular outer portion thereof which faces upward on the outer surface of the main circuit board when the actuator takes one of the first and second stations and faces toward a direction in parallel with the outer surface of the main circuit board when the actuator takes the other of the first and second stations. | 2012-11-15 |
20120289093 | CONNECTOR - A connector is capable of facilitating a rotation manipulation of a pressing member. A pair of first manipulation portions projecting backward from both sides in the width direction are provided on the back ends of the pressing member, and the first manipulation portions are for performing the pressing manipulation in the top-to-bottom direction with a finger upon rotation of the pressing member. The length from the rotation fulcrum of the pressing member to each first manipulation portion (power point) is increasable, and the pressing force for performing the rotation manipulation of the pressing member is reducible. The protrusions projecting upward are on the back end sides of the first manipulation portions. Furthermore, the first manipulation portions are outside in the width direction of the pressing member from the terminals. | 2012-11-15 |
20120289094 | CONNECTOR ASSEMBLY - A connector assembly connecting two electronic components includes a connector and a connection member. The connector is detachably and electrically connected to one electronic component. When the connector is electrically connected to the electronic component, the connection member is detachably and electrically connected between the connector and another electronic component. Thus, the connection between the connector and the connection member is detachable and flexible, and the connector does not need to be disassembled from an electronic device to replace a different lengthed connection members. Thus, the connector can correspondingly match different lengths of connection members, which can improve the versatility of the connector. | 2012-11-15 |
20120289095 | DIFFERENTIAL ELECTRICAL CONNECTOR WITH IMPROVED SKEW CONTROL - An electrical interconnection system with high speed, differential electrical connectors. The connector is assembled from wafers each containing a column of conductive elements, some of which form differential pairs. Skew control is provided for at least some of the pairs by providing a profile on an edge of the shorter signal conductor of the pair. The profile may contain multiple curved segments that effectively lengthen the signal conductor without significantly impacting its impedance. For connectors in which ground conductors are included between adjacent pairs of signal conductors, patterned segments of varying parameters may be included on edges of the signal conductors and ground conductors to equalize electrical lengths of all edges in a set of edges for which there is common mode or differential mode coupling as a signal propagates along each pair. | 2012-11-15 |
20120289096 | ELECTRICAL CONNECTOR - Upon plug and receptacle connectors of an electrical connector being fitted with each other, positioning recesses of a block of the plug connector engage positioning protrusions of a housing of the receptacle connector to achieve positioning of the two connectors in their width directions. Inclined portions of receptacle contacts of the receptacle connector are commensurate with inclined portions of inserting holes of the housing so that a backup function of the housing for the receptacle contacts is adjusted to obtain a stable connection between the plug and receptacle connectors. First chamfered portions of the receptacle contacts engage recesses of the plug contacts to generate tactile clicks and to achieve the positioning and contacting between the plug and receptacle contacts. The plug contacts are embraced between contact portions and elastic portions of the receptacle contacts to obtain a stable connection between the both contacts. | 2012-11-15 |
20120289097 | ELECTRICAL CONNECTOR - An electrical connector for connecting a flat conductive member includes a housing that has a receiving portion for receiving the flat conductive member; a plurality of terminals; a movable member; and a regulating member. The regulating member is disposed between the movable member and the flat conductive member. Accordingly, it is possible to securely confirm that the flat conductive member is not completely inserted. When the movable member is moved to the closed position, the movable member pushes the regulating member, so that the entire portion of the movable member is moved. If the flat conductive member is situated at the incomplete insertion position, the regulating member abuts against the flat conductive member and stays at the middle position, so that the regulating member restricts the movement of the movable member. | 2012-11-15 |