46th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120286293 | ELECTRONIC DEVICE AND MANUFACTURING THEREOF - An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane. | 2012-11-15 |
20120286294 | ORGANIC EL ELEMENT - An organic EL element includes: an organic EL layer including a transparent electrode, a reflective electrode, and a light-emitting layer; a transparent layer disposed on a light-exiting side of the transparent electrode; and a light extraction structure disposed on a light-exiting side of the transparent layer and having a protruding shape with inclined portions. The transparent layer and the light extraction structure have a larger refractive index than the light-emitting layer. The inclined portions of the light extraction structure satisfy Condition 1 or 2 for extracting guided wave light emitted from the light-emitting layer and incident on the light extraction structure from the light extraction structure to the outside of the organic EL element, in a cross section taken along a plane perpendicular to the reflective electrode, where two inclination angles φ | 2012-11-15 |
20120286295 | Organic Light-Emitting Display Device - An organic light-emitting display device comprises a substrate including a plurality of light-emitting regions separated by a non-light-emitting region, an organic light-emitting element disposed on each of the light-emitting regions, and a photoactive element disposed on the non-light-emitting region. | 2012-11-15 |
20120286296 | METHOD AND APPARATUS FOR SENSING INFRARED RADIATION - Embodiments of the invention pertain to a method and apparatus for sensing infrared (IR) radiation. In a specific embodiment, a night vision device can be fabricated by depositing a few layers of organic thin films. Embodiments of the subject device can operate at voltages in the range of 10-15 Volts and have lower manufacturing costs compared to conventional night vision devices. Embodiments of the device can incorporate an organic phototransistor in series with an organic light emitting device. In a specific embodiment, all electrodes are transparent to infrared light. An IR sensing layer can be incorporated with an OLED to provide IR-to-visible color up-conversion. Improved dark current characteristics can be achieved by incorporating a poor hole transport layer material as part of the IR sensing layer. | 2012-11-15 |
20120286297 | LED PACKAGE STRUCTURE AND MODULE THEREOF - The present invention discloses a LED package structure and a module thereof. The LED package structure comprises a metallic chip-carrying lead frame, a metallic anode lead frame, a metallic cathode lead frame and a forming resin. At least one LED chip is stuck to the metallic chip-carrying lead frame. The metallic anode lead frame and metallic cathode lead frame are arranged beside the metallic chip-carrying lead frame. The forming resin includes a top member, a first sidewall, and a second sidewall. The top member is arranged on the metallic chip-carrying lead frame and has an opening to reveal the LED chip. A reflective wall is formed along the opening. The first sidewall is arranged between the metallic chip-carrying lead frame and the metallic anode lead frame to join them. The second sidewall is arranged between the metallic chip-carrying lead frame and the metallic cathode lead frame to join them. | 2012-11-15 |
20120286298 | BUS LINE DESIGNS FOR LARGE-AREA OLED LIGHTING - Systems, and methods for the design and fabrication of OLEDs, including large-area OLEDs with metal bus lines, are provided. Various bus line design rules for large area OLED light panels may include mathematical models developed to optimize bus line design and/or layout on large area OLED light panels. For a given panel area dimension, target luminous emittance, OLED device structure and efficiency (as given by the JVL characteristics of an equivalent small area pixel), and electrical resistivity and thickness of the bus line material and electrode onto which the bus lines are disposed, a bus line pattern may be designed such that Fill Factor (FF), Luminance Uniformity (U) and Power Loss (PL) may be optimized. One general design objective may be to maximize FF, maximize U and minimize PL. Another approach may be, for example, to define minimum criteria for U and a maximum criteria for PL, and then to optimize the bus line layout to maximize FF. OLED panels including bus lines with different resistances (R | 2012-11-15 |
20120286299 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device is disclosed. The display device includes a substrate; a first electrode on the substrate; an auxiliary electrode patterned on and insulated from the first electrode, and having a top surface that has surface roughness; an intermediate layer on the first electrode and the auxiliary electrode; and a second electrode on the intermediate layer and facing the first electrode. The auxiliary electrode and the second electrode are electrically connected to each other via the surface roughness of the top surface of the auxiliary electrode. | 2012-11-15 |
20120286300 | DISPLAY DEVICE, DISPLAY, AND ELECTRONIC UNIT - A display device includes: a third electrode provided on a side of the second electrode opposite to the light-emitting layer; and an efficiency improving layer improving an efficiency of light extraction from the light-emitting layer, and the efficiency improving layer being provided between the second and third electrodes. The first and third electrodes are each in a laminated structure including a first layer being transmissive, and a second layer being transmissive and having a refractive index higher than a refractive index of the first layer. | 2012-11-15 |
20120286301 | LED MODULE - An LED (Light Emitting Diode) module includes an LED unit having one or more LED chips and a case. The case includes: a body including a base plate made of ceramic, the base plate having a main surface and a bottom surface opposite to the main surface; a through conductor penetrating through the base plate; and one or more pads formed on the main surface and making conductive connection with the through conductor, the pads mounting thereon the LED unit. The through conductor includes a main surface exposed portion exposed to the main surface and overlapping the LED unit when viewed from top, a bottom surface reaching portion connected to the main surface exposed portion and reaching the bottom surface. The pads cover at least a portion of the main surface exposed portion. | 2012-11-15 |
20120286302 | Flexible Lighting Devices - A first device and methods for manufacturing the first device are provided. The first device may comprise a flexible substrate and at least one organic light emitting device (OLED) disposed over the flexible substrate. The first device may have a flexural rigidity between 10 | 2012-11-15 |
20120286303 | DISPLAY APPARATUS - The present invention supplied a display apparatus using plastic substrate instead of glass substrate, which can solve such problems that the plastic substrate has a low heat conductivity and its heat release performance becomes bad so that it is difficult to obtain stable performance and reliability. In the display apparatus being formed by bonding semiconductor thin film element on a plastic substrate, a thin film metal layer is formed on surface of the semiconductor thin film element for promoting heat release. | 2012-11-15 |
20120286304 | Recipient Luminophoric Mediums Having Narrow Spectrum Luminescent Materials and Related Semiconductor Light Emitting Devices and Methods - Light emitting devices include a light emitting diode (“LED”) and a recipient luminophoric medium that is configured to down-convert at least some of the light emitted by the LED. In some embodiments, the recipient luminophoric medium includes a first broad-spectrum luminescent material and a narrow-spectrum luminescent material. The broad-spectrum luminescent material may down-convert radiation emitted by the LED to radiation having a peak wavelength in the red color range. The narrow-spectrum luminescent material may also down-convert radiation emitted by the LED into the cyan, green or red color range. | 2012-11-15 |
20120286305 | Light-Emitting Element, Light-Emitting Module, Light-Emitting Panel, and Light-Emitting Device - A light-emitting element, a light-emitting module, a light-emitting panel, or a light-emitting device in which loss due to electrical resistance is reduced is provided. The present invention focuses on a surface of an electrode containing a metal and on a layer containing a light-emitting organic compound. The layer containing a light-emitting organic compound is provided between one electrode including a first metal, whose surface is provided with a conductive inclusion, and the other electrode. | 2012-11-15 |
20120286306 | DIFFUSELY RADIATING LED LIGHT SYSTEM - A lighting device ( | 2012-11-15 |
20120286307 | SEMICONDUCTOR LIGHT EMITTING STRUCTURE - A semiconductor light emitting structure including a substrate, a second type electrode layer, a reflecting layer, an insulating layer, a first type electrode layer, a first type semiconductor layer, an active layer and a second type semiconductor layer is provided. The second type electrode layer formed on the substrate has a current spreading grating formed by several conductive pillars and conductive walls, which are staggered and connected to each other. The reflecting layer and the insulating layer are formed on the second type electrode layer in sequence, and cover each conductive pillar and each conductive wall. The first type electrode layer, the first type semiconductor layer and the active layer are formed on the insulating layer in sequence. The second type semiconductor layer is formed on the active layer, and covers each conductive pillar and each conductive wall. | 2012-11-15 |
20120286308 | LED PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - An LED package structure and a method of fabricating the same. The LED package structure includes: a package unit including a submount with a cavity, and a light emitting chip disposed in the cavity; a first light-pervious element disposed in the cavity; a multi-layered dam structure concentrically disposed on the first light-pervious element or around a rim of the cavity; a first light-pervious packaging material filled in the dam structure; and a second light-pervious element that combines with the dam structure. Accordingly, the multi-layered dam structure provides an advantage of eliminating gaps and overcomes the problem resulting from the uneven thickness of the first light-pervious packaging material used in the prior technique, thereby ensuring high illumination efficiency and enhanced airtightness. | 2012-11-15 |
20120286309 | SEMICONDUCTOR LIGHT EMITTING DIODE CHIP AND LIGHT EMITTING DEVICE USING THE SAME - A semiconductor light emitting device includes: a light emitting diode unit including a light-transmissive substrate having a face sloped upwardly at a lower edge thereof. A rear reflective lamination body is formed on the lower face and the surrounding sloped face of the light-transmissive substrate. The rear reflective lamination body includes an optical auxiliary layer and a metal reflective film formed on a lower face of the optical auxiliary layer. A junction lamination body is provided to a lower face of the rear reflective lamination body. The junction lamination body including a junction metal layer made of a eutectic metal material and a diffusion barrier film. | 2012-11-15 |
20120286310 | LIGHT EMITTING DIODE DEVICE - A light emitting diode device includes: a cathode lead frame; an anode lead frame which is electrically insulated from the cathode lead frame; a light emitting diode chip which is electrically connected to the cathode lead frame and the anode lead frame respectively; a synthetic resin member which forms an indentation receiving the light emitting diode chip and fixes the cathode lead frame and the anode lead frame; and a metallic heat-radiation/light-reflection member which covers at least a portion of the indentation and covers an upper surface of the synthetic resin member. | 2012-11-15 |
20120286311 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF MANUFACTURE - A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers. | 2012-11-15 |
20120286312 | LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE USING THE LIGHT-EMITTING DEVICE - An object is to provide a method for manufacturing a light-emitting device including a flexible substrate, in which separation is performed without separation at the interface between the light-emitting layer and the electrode. A spacer formed of a light absorbing material which absorbs laser light is formed over a partition of one of substrates, a coloring layer is formed over the other substrate, and the substrates are bonded to each other with the use of a bonding layer. The light-emitting layer and the electrode which are formed over the spacer are irradiated with laser light through the coloring layer, so that at least the bonding layer among the light-emitting layer, the electrode, the coloring layer, and the bonding layer is melted to form a fixed portion where the bonding layer and the spacer are bonded by welding. | 2012-11-15 |
20120286313 | RADIATION-EMITTING SEMICONDUCTOR COMPONENT - A radiation-emitting semiconductor component includes a semiconductor body having an active layer which emits electromagnetic radiation of a first wavelength λ | 2012-11-15 |
20120286314 | WHITE LED LIGHTING DEVICE, AND OPTICAL LENS - Disclosed are a white LED lighting device and an optical lens used in it. The white LED lighting device comprises a white LED and an optical lens. The white LED includes: a LED chip which emits blue light: and a fluorescent material which is excited by emission light of the LED chip and converts a wavelength into fluorescence of a complementary color of blue. The optical lens is formed with a scattering light guide which is given uniform scattering power in terms of a volume. The scattering light guide includes scattering particles for the scattering efficiency in a short wavelength range of light to be higher than that in a long wavelength range of light. | 2012-11-15 |
20120286315 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - (OBJECT) The object is to provide a lightened semiconductor device and a manufacturing method thereof by pasting a layer to be peeled to various base materials. | 2012-11-15 |
20120286316 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed are a semiconductor light emitting device. The semiconductor light emitting device comprises a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active; an electrode on a first region of the first conductive semiconductor layer; a conductive support member under the light emitting structure; a metal layer between the light emitting structure and the conductive support member; and a reflective layer between the metal layer and the light emitting structure, wherein the metal layer is physically contacted with a lower surface of the reflective layer, wherein the reflective layer includes a first layer and a second layer, wherein the first layer has a different material from the second layer, wherein the metal layer has a protrusion, wherein the first conductive semiconductor layer includes a roughness. | 2012-11-15 |
20120286317 | LIGHT-EMITTING ELEMENT AND THE MANUFACTURING METHOD THEREOF - A light-emitting element includes a light-emitting stack includes: a first semiconductor layer; an active layer formed on the first semiconductor layer; and a second semiconductor layer formed on the active layer; a recess structure formed through the second semiconductor layer, the active layer, and extended in the first semiconductor layer, wherein the first semiconductor layer includes a contact region defined by the recess structure; a first electrode structure including a first contact portion on the contact region of the first semiconductor layer, and a second contact portion laterally extended from the first contact portion into the first semiconductor layer; and a dielectric layer formed on side surfaces of the second semiconductor layer and the active layer to insulate the second semiconductor layer and the active layer from the first contact portion. | 2012-11-15 |
20120286318 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device includes a substrate, an anode including Ag on the substrate, a transparent inorganic thin-film layer on the anode, the transparent inorganic thin-film layer being in contact with the anode and having non-conductive characteristics; and an emitting layer and a cathode disposed sequentially on the inorganic thin-film layer. | 2012-11-15 |
20120286319 | LIGHT EMITTING DEVICE PACKAGE AND ULTRAVIOLET LAMP HAVING THE SAME - Provided is a light emitting device package. The light emitting device package comprises a body, a heat diffusing member, a light emitting diode (LED), and a buffer layer. A cavity with an opened topside is formed in the body. The heat dissipation member is disposed between a bottom surface of the cavity and a lower surface of the body. The LED is disposed on one of an electrode disposed on the bottom surface of the cavity. The buffer layer is disposed between the heat dissipation member and a pad and has a thickness thinner than a thickness of the heat dissipation member. | 2012-11-15 |
20120286320 | LIGHT EMITTING DEVICE - A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving. | 2012-11-15 |
20120286321 | High-Performance Device for Protection from Electrostatic Discharge - The semiconductor device for protection from electrostatic discharges comprises several modules (MDi) for protection from electrostatic discharges comprising triggerable elements (TRi) coupled with triggering means, the said modules being connected between two terminals by the intermediary of a resistive network (R). A common semiconductor layer contacts all of the modules, each triggerable element (TRi) having at least one gate (GHi), and the triggering means comprise a single triggering circuit (TC) common to all of the triggerable elements and whose output is connected to the gates of all of the triggerable elements. | 2012-11-15 |
20120286322 | METHODS AND STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region. | 2012-11-15 |
20120286323 | SEMICONDUCTOR COMPONENT WITH IMPROVED SOFTNESS - A semiconductor component includes a semiconductor body, a first emitter region of a first conductivity type in the semiconductor body, a second emitter region of a second conductivity type arranged distant to the first emitter region in a vertical direction of the semiconductor body, a base region of one of the first and second conductivity types arranged between the first and second emitter regions and having a lower doping concentration than the first second emitter regions, a first field stop zone of the same conductivity type as the base region arranged in the base region, and a second field stop zone of the same conductivity type as the base region arranged in the base region. The second field stop zone is arranged distant to the first field stop in the vertical direction of the semiconductor, the first field stop zone is arranged between the second field stop zone and the second emitter zone, and the second field stop zone includes a plurality of field stop zone sections arranged mutually distant from each other in at least one horizontal direction of the semiconductor body. | 2012-11-15 |
20120286324 | MANUFACTURING METHOD FOR INSULATED-GATE BIPOLAR TRANSITOR AND DEVICE USING THE SAME - Provided is a manufacturing method for an insulated-gate bipolar transistor (IGBT). The manufacturing method includes providing a structure including a substrate, a first conductivity type epitaxial layer formed on the substrate, a gate electrode formed on a first surface of the epitaxial layer, a second conductivity type body region formed at opposite sides of the gate electrode in the first surface of the epitaxial layer, and a first conductivity type source region formed within the body region; removing a portion of the substrate by back grinding; and removing the other portion of the substrate by etching until the second surface of the epitaxial layer is exposed. | 2012-11-15 |
20120286325 | APPARATUS FOR ELECTROSTATIC DISCHARGE PROTECTION - An apparatus includes an electrostatic discharge (ESD) protection device. In one embodiment, the protection device electrically coupled between a first node and a second node of an internal circuit to be protected from transient electrical events. The protection device includes a bipolar device or a silicon-controlled rectifier (SCR). The bipolar device or SCR can have a modified structure or additional circuitry to have a selected holding voltage and/or trigger voltage to provide protection over the internal circuit. The additional circuitry can include one or more resistors, one or more diodes, and/or a timer circuit to adjust the trigger and/or holding voltages of the bipolar device or SCR to a desired level. The protection device can provide protection over a transient voltage that ranges, for example, from about 100 V to 330V. | 2012-11-15 |
20120286326 | POWER SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n | 2012-11-15 |
20120286327 | OVERVOLTAGE AND/OR ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An overvoltage protection device in combination with a filter, the overvoltage protection device having a first node for connection to a node to be protected, a second node for connection to a discharge node; and a control node; and wherein the filter comprises at least one of: (a) a capacitor connected between the first node and the discharge node; (b) a capacitor connected between the control node and the discharge node; or (c) an inductor in series connection with the first node. | 2012-11-15 |
20120286328 | COMPOUND SEMICONDUCTOR LIGHT-RECEIVING ELEMENT ARRAY - An array structure solves issues that exist in conventional compound semiconductor photodiode arrays, such as large cross talk, large surface leaks, large stray capacitance, narrow detection wavelength bands, and bad manufacturing yield, simultaneously. A photodiode array has, laminated upon a semiconductor substrate, a buffer layer ( | 2012-11-15 |
20120286329 | SOI FET with embedded stressor block - A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the insulating layer. The voids are epitaxially filled with a semiconductor material of a differing lattice constant than the one of the SOI layer, thus becoming a stressor block, and imparts a strain onto the FET device body. | 2012-11-15 |
20120286330 | PLANAR MOSFET WITH TEXTURED CHANNEL AND GATE - A semiconductor device is disclosed that includes a semiconductor substrate having a channel region and respective source and drain regions formed on opposite sides of the channel region. The channel region includes at least one pore. A gate is formed on the semiconductor substrate between the source and drain regions and includes at least one pin received by respective ones of the at least one pore. A dielectric layer is disposed between the gate and the semiconductor substrate. | 2012-11-15 |
20120286331 | INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS - Integrated circuit ( | 2012-11-15 |
20120286332 | CHEMICALLY SENSITIVE SENSORS WITH SAMPLE AND HOLD CAPACITORS - Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis. | 2012-11-15 |
20120286333 | LOW NOISE CHEMICALLY-SENSITIVE FIELD EFFECT TRANSISTORS - Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis. | 2012-11-15 |
20120286334 | Semiconductor Device and Method of Making Same - Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line. | 2012-11-15 |
20120286335 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are disclosed. The method comprises: providing a substrate with a first dielectric layer and a gate, wherein the gate is embedded in the first dielectric layer and an upper portion of the gate is an exposed first metal; and covering only the exposed first metal with a conductive material that is harder to be oxidized than the first metal by a selective deposition. An advantage of the present invention is that the metal of the upper surface of the gate is prevented from being oxidized by covering the metal gate with the conductive material that is relatively harder to be oxidized, thereby facilitating the formation of an effective electrical connection to the gate. | 2012-11-15 |
20120286336 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall. | 2012-11-15 |
20120286337 | FIN FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance. | 2012-11-15 |
20120286338 | CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES - A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices. | 2012-11-15 |
20120286339 | SEMICONDUCTOR STORAGE DEVICE - A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90-a tan(⅓)) degrees. | 2012-11-15 |
20120286340 | CONTROLLING FERROELECTRICITY IN DIELECTRIC FILMS BY PROCESS INDUCED UNIAXIAL STRAIN - A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress. | 2012-11-15 |
20120286341 | Adding Decoupling Function for TAP Cells - A tap cell includes a well region and a well pickup region on the well region; a VDD power rail; and a VSS power rail. A MOS capacitor includes a gate electrode line acting as a first capacitor plate, and the well pickup region acting as a part of a second capacitor plate. A first one of the first and second capacitor plates is coupled to the VDD power rail, and a second one of the first and second capacitor plates is coupled to the VSS power rail. | 2012-11-15 |
20120286342 | SEMICONDUCTOR DEVICE - A semiconductor device having a transistor gate length greatly reduced as a result of promotion of semiconductor integrated circuit miniaturization where leakage current generation in a gate insulating film can be inhibited to enhance the transistor function. The semiconductor device includes: a semiconductor substrate having a main surface; a pair of source/drain regions formed over the main surface of the semiconductor substrate; a gate insulating film formed, over a region between the pair of source/drain regions, to be in contact with the main surface; and a gate electrode formed to be in contact with the upper surface of the gate insulating film. In the semiconductor device, the gate electrode has a length of less than 45 nm in a direction from a first one of the pair of source/drain regions to a second one of the pair of source/drain regions, and the gate insulating film has an antiferroelectric film. | 2012-11-15 |
20120286343 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory device includes a MISFET on a semiconductor substrate of a first conductivity type, and a MIS capacitor on a first well of a second conductivity type. The MISFET includes a gate insulating film on the semiconductor substrate, a gate electrode, and a source/drain located at both sides of the gate electrode. The MIS capacitor includes a capacitor insulating film on the first well serving as a first electrode, a second electrode, and a first impurity layer of the first conductivity type. The gate electrode and the second electrode are electrically connected together, and form a floating gate. The gate insulating film and the capacitor insulating film are made of a same material, and have a same thickness. | 2012-11-15 |
20120286344 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A non-volatile may include a plurality of device isolation patterns disposed in a substrate to define an active region extending in a first direction, a gate pattern disposed on the substrate to extend in a second direction crossing the first direction, a charge storing pattern disposed between the active region and the gate pattern, a blocking dielectric layer disposed between the charge storing pattern and the gate pattern, and a tunnel dielectric layer disposed between the active region and the charge storing pattern. A center area of a top surface of the active region includes one of a rounded surface or a tip, and the center area of the top surface of the active region corresponds to an uppermost portion of the active region and the uppermost portion of the active region is disposed at a level lower than a lowermost portion of the gate pattern. | 2012-11-15 |
20120286345 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a substrate including a cell region and a peripheral circuit region, a first insulation layer formed over the substrate to cover the peripheral circuit region thereof, and interlayer dielectric patterns and first conductive patterns alternately formed over the substrate of the cell region. Each of the interlayer dielectric patterns and the first conductive patterns includes a horizontal part extending along a surface of the substrate and a vertical part extending along a sidewall of the first insulation layer. | 2012-11-15 |
20120286346 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench formed in an element isolating area of the semiconductor substrate, and a silicon oxide film that is embedded in the trench and contains an alkali metal element or alkali earth metal element. | 2012-11-15 |
20120286347 | Semiconductor device - In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate | 2012-11-15 |
20120286348 | Structures and Methods of Improving Reliability of Non-Volatile Memory Devices - In one example, the memory device disclosed herein includes a gate insulation layer and a charge storage layer positioned above the gate insulation layer, wherein the charge storage layer has a first width. The device further includes a blocking insulation layer positioned above the charge storage layer and a gate electrode positioned above the blocking insulation layer, wherein the gate electrode has a second width that is greater than the first width. An illustrative method disclosed herein includes forming a gate stack for a memory device, wherein the gate stack includes a gate insulation layer, an initial charge storage layer, a blocking insulation layer and a gate electrode, and wherein the initial charge storage layer has a first width. The method further includes performing an etching process to selectively remove at least a portion of the initial charge storage layer so as to produce a charge storage layer having a second width that is less than the first width of the initial charge storage layer. | 2012-11-15 |
20120286349 | Non-Volatile Memory Device With Additional Conductive Storage Layer - In one example, the memory device includes a gate insulation layer, a first conductive storage layer positioned above the gate insulation layer and a first non-conductive charge storage layer positioned above the first conductive storage layer. The device further includes a blocking insulation layer positioned above the first non-conductive charge storage layer and a gate electrode positioned above said blocking insulation layer. | 2012-11-15 |
20120286350 | TUNNEL FIELD EFFECT TRANSISTOR - An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side. | 2012-11-15 |
20120286351 | CELL ARRAY - A semiconductor device includes a plurality of pillars disposed to protrude from a semiconductor substrate, bit lines surrounding perimeters of portions of the plurality of pillars and extending in a first direction, gates spaced apart from the bit lines, surrounding perimeters of portions of the plurality of pillars over the bit lines, and extending to a second direction perpendicular to the first direction, and separation layers separating the gates parallel to the second direction. Therefore, the semiconductor device suitable to the high integration of semiconductor devices can be implemented. | 2012-11-15 |
20120286352 | TRENCH MOS STRUCTURE AND METHOD FOR MAKING THE SAME - A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring. | 2012-11-15 |
20120286353 | TRENCH MOS STRUCTURE AND METHOD FOR FORMING THE SAME - A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures. | 2012-11-15 |
20120286354 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a buried gate is provided. The semiconductor device is formed in a structure in which a plurality of contacts having small step differences are stacked without forming a metal contact applying an operation voltage to the buried gate in a single contact and a contact pad is formed between the contacts so that failure due to misalignment can be prevented without a separate additional process for forming the contacts. | 2012-11-15 |
20120286355 | Power Semiconductor Device and a Method for Forming a Semiconductor Device - A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided. | 2012-11-15 |
20120286356 | SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON - A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2012-11-15 |
20120286357 | SENSE-AMP TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A sense-amp transistor for a semiconductor device and a method for manufacturing the same are disclosed. A sense-amp transistor for a semiconductor device includes a recess array formed in a gate region of a sense-amp, a plurality of buried gates formed in each recess of the recess array so as to form a vertical channel region, and an upper gate configured to form a horizontal channel region in an active region between the buried gates. As a result, the number of additional processes is minimized, and the sensing margin of the sense-amp is guaranteed. | 2012-11-15 |
20120286358 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a first groove. The first groove has a bottom and first and second side surfaces opposite to each other. A first gate insulator extends alongside the first side surface. A first gate electrode is formed in the first groove and on the first gate insulator. A second gate insulator extends alongside the second side surface. A second gate electrode is formed in the first groove and on the second gate insulator. The second gate electrode is separate from the first gate electrode. | 2012-11-15 |
20120286359 | LATERAL-DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE (LDMOS) AND FABRICATION METHOD THEREOF - A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well. | 2012-11-15 |
20120286360 | Field Effect Transistor Device with Self-Aligned Junction and Spacer - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, a first spacer portion disposed on the source region, the drain region and a first portion of the source extension portion, and a first portion of the drain extension portion, a second spacer portion disposed on a second portion of the source extension portion, and a second portion of the drain extension portion, a gate stack portion disposed on the channel region. | 2012-11-15 |
20120286361 | High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device which includes: a substrate having a first isolation structure to define a device region; a source and a drain in the device region; a gate on the substrate and between the source and the drain; and a second isolation structure including: a first isolation region on the substrate and between the source and the drain, wherein from top view, the first isolation region is partially or totally covered by the gate; and a second isolation region in the substrate and below the gate, wherein the second isolation region has a depth in the substrate which is deeper than the depth of the first isolation region in the substrate, and the length of the second isolation region in a direction along an imaginary line connecting the source and the drain does not exceed one-third length of the first isolation region. | 2012-11-15 |
20120286362 | Semiconductor Structure and Circuit with Embedded Schottky Diode - A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region. | 2012-11-15 |
20120286363 | Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices - A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion. | 2012-11-15 |
20120286364 | Integrated Circuit Diode - A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process. | 2012-11-15 |
20120286365 | SWITCHING POWER SUPPLY DEVICE AND A SEMICONDUCTOR INTEGRATED CIRCUIT - In a switching power source which controls a current which flows in an inductor through a switching element which performs a switching operation in response to a PWM signal, and forms an output voltage by a capacitor which is provided in series in the inductor, a booster circuit which is constituted of a bootstrap capacity and a MOSFET is provided between an output node of the switching element and a predetermined voltage terminal. The boosted voltage is used as an operational voltage of a driving circuit of the switching element, another source/drain region and a substrate gate are connected with each other, and a junction diode between one source/drain region and the substrate gate is inversely directed with respect to the boosted voltage which is formed by the bootstrap capacity. | 2012-11-15 |
20120286366 | Field Effect Transistor Device and Fabrication - In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET. | 2012-11-15 |
20120286367 | One-Time Programmable Semiconductor Device - According to one disclosed embodiment, an integrated one-time programmable (OTP) semiconductor device pair includes a split-thickness dielectric under an electrode and over an isolation region formed in a doped semiconductor substrate, where a reduced-thickness center portion of the dielectric forms, in conjunction with the isolation region, programming regions of the OTP semiconductor device pair, and where the thicker, outer portions of the dielectric form dielectrics for transistor structures. In one embodiment, the split-thickness dielectric comprises a gate dielectric. In one embodiment, multiple OTP semiconductor device pairs are formed in an array that minimizes the number of connections required to program and sense states of specific OTP cells. | 2012-11-15 |
20120286368 | Layout Methods of Integrated Circuits Having Unit MOS Devices - A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types. | 2012-11-15 |
20120286369 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region. | 2012-11-15 |
20120286370 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and method for manufacturing the same are disclosed. The method comprises: forming a gate insulating layer and a gate above a substrate; forming a spacer on both sides of the gate respectively; etching the substrate with the gate and spacers as mask to form indents; respectively forming a dummy sidewall on the side of the spacers opposite to the gate; etching substrate with the gate, spacers and dummy sidewalls as mask to form recesses which are deeper than the indents; removing the dummy sidewalls; and filling SiGe in the indents and recesses to form source/drain extent regions and source/drain regions of the semiconductor device; wherein before the step of filling SiGe, a step of heating the substrate to reflow the substrate material so as to at least change the shape of the side surface of the indent on the side close to the gate is implemented. | 2012-11-15 |
20120286371 | Field Effect Transistor Device With Self-Aligned Junction - A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, wherein the channel region includes a source transition portion including n-type and p-type ions and a drain transition portion including n-type and p-type ions, and a gate stack portion disposed on the channel region. | 2012-11-15 |
20120286372 | Reliability of high-K gate dielectric layers - A method for improving the reliability of a high-k gate dielectric layer comprises incorporating a noble metal into a transistor gate stack that contains the high-k gate dielectric layer and annealing the transistor gate stack in a molecular hydrogen or deuterium containing atmosphere. The annealing process drives at least a portion of the molecular hydrogen or deuterium toward the high-k gate dielectric layer. When the molecular hydrogen or deuterium contacts the noble metal, it is converted into atomic hydrogen or deuterium that is able to treat the high-k gate dielectric layer and improve its reliability. | 2012-11-15 |
20120286373 | GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Gates structures and methods for manufacturing the same are disclosed. In an example, the gate structure comprises a gate stack formed on a semiconductor substrate, the gate stack comprising a high-K dielectric layer and a metal gate electrode from bottom to top; a first dielectric layer on sidewalls of the gate stack, the first dielectric layer serving as first sidewall spacers; and a sacrificial metal layer on the first dielectric layer, the sacrificial metal layer serving as second sidewall spacers. The sacrificial metal layer in the gate structure reduces a thickness of an interfacial oxide layer in the step of annealing. The gate structure may be applied to a semiconductor device having a small size because the gate dielectric layer has a low EOT value. | 2012-11-15 |
20120286374 | HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF - Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen. | 2012-11-15 |
20120286375 | PRESERVING STRESS BENEFITS OF UV CURING IN REPLACEMENT GATE TRANSISTOR FABRICATION - A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices. | 2012-11-15 |
20120286376 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is disclosed. The semiconductor device includes: a substrate having a region; a gate structure disposed on the region of the substrate; a raised epitaxial layer disposed in the substrate adjacent to two sides of the gate structure, wherein the surface of the raised epitaxial layer is even with the surface of the gate structure. | 2012-11-15 |
20120286377 | Nanoelectromechanical Structures Exhibiting Tensile Stress And Techniques For Fabrication Thereof - Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions. | 2012-11-15 |
20120286378 | MICROELECTROMECHANICAL SYSTEM WITH BALANCED CENTER OF MASS - MEMS and fabrication techniques for positioning the center of mass of released structures in MEMS are provided. A released structure may include a member with a recess formed into an end face of its free end. A released structure may include a plurality of members, with the longitudinal lengths of the members being of differing lengths. Mass of a member disposed below a plane of a flexure may be balanced by mass of a second substrate affixed to the member. In an embodiment, a mirror substrate is affixed to a member partially released from a first substrate and a through hole formed in the second substrate is accessed to complete release of the member. | 2012-11-15 |
20120286379 | SENSOR ELEMENT - A sensor element includes: a first substrate in which a diaphragm is configured on a main surface; a second substrate which is provided on the side opposite to the diaphragm of the first substrate; a cavity which is provided just below the diaphragm of the first substrate; a bonding position which is provided at a bonding position between the first substrate and the second substrate for airtight sealing of the cavity; and a bump portion which is provided at the fitting portion, and protects a fitted state between the first substrate and the second substrate. | 2012-11-15 |
20120286380 | PROCESSES AND MOUNTING FIXTURES FOR FABRICATING ELECTROMECHANICAL DEVICES AND DEVICES FORMED THEREWITH - Processes and fixtures for producing electromechanical devices, and particularly three-dimensional electromechanical devices such as inertial measurement units (IMUs), through the use of a fabrication process and a three-dimensional assembly process that entail joining single-axis device-IC chips while positioned within a mounting fixture that maintains the orientations and relative positions of the chips during the joining operation. | 2012-11-15 |
20120286381 | ELECTRONIC MEMS DEVICE COMPRISING A CHIP BONDED TO A SUBSTRATE AND HAVING CAVITIES AND MANUFACTURING PROCESS THEREOF - An electronic MEMS device is formed by a chip having with a main face and bonded to a support via an adhesive layer. A cavity extends inside the chip from its main face and is closed by a flexible film covering the main face of the chip at least in the area of the cavity. The support has a depressed portion facing the cavity and delimited by a protruding portion facing the main face of the chip. Inside the depressed portion, the adhesive layer has a greater thickness than the projecting portion so as to be able to absorb any swelling of the flexible film as a result of the expansion of the gas contained inside the cavity during thermal processes. | 2012-11-15 |
20120286382 | Co/Ni multilayers with improved out-of-plane anisotropy for magnetic device applications - A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni) | 2012-11-15 |
20120286383 | EFFICIENTLY INJECTING SPIN-POLARIZED CURRENT INTO SEMICONDUCTORS BY INTERFACING CRYSTALLINE FERROMAGNETIC OXIDES DIRECTLY ON THE SEMICONDUCTOR MATERIAL - A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO | 2012-11-15 |
20120286384 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SOLID-STATE IMAGING DEVICE - A semiconductor package includes: a sheet-like thin plate on which a semiconductor chip is secured; and a substrate including a wiring layer, disposed on the thin plate to extend over a part of a region surrounding the region where the semiconductor chip is secured or over the entire surrounding region, wherein the semiconductor chip and the substrate are electrically connected. | 2012-11-15 |
20120286385 | SEMICONDUCTOR DEVICE, CAMERA MODULE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device is provided which has a semiconductor element having an element forming surface at which a sensor element is formed, a back surface on the opposite side of the element forming surface, and a light transmissive protective member laminated over the element forming surface via an adhering portion. The semiconductor device includes a region exposed from the protective member at the outer peripheral end portion of the semiconductor element, when viewed from the protecting member in a laminating direction. | 2012-11-15 |
20120286386 | SOLID-STATE IMAGING DEVICE AND SOLID-STATE IMAGING DEVICE DESIGNING METHOD - A solid-state imaging device includes light receiving sections which are arranged in an image area on a semiconductor substrate at the same pitch and which light exiting from an imaging optical system enters, condensing lenses respectively arranged above the light receiving sections, and light shielding sections each of which is provided at one end of each of the light receiving sections. The condensing lenses are arranged in a peripheral portion in a first direction in the image area at a first pitch, and arranged in a peripheral portion in a second direction opposite the first direction at a second pitch which is smaller than the first pitch. | 2012-11-15 |
20120286387 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening. | 2012-11-15 |
20120286388 | SOLID STATE IMAGE PICKUP DEVICE AND METHOD OF PRODUCING SOLID STATE IMAGE PICKUP DEVICE - Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed. | 2012-11-15 |
20120286389 | Method of design and growth of single-crystal 3D nanostructured solar cell or detector - Photovoltaic devices conformally deposited on a nano-structured substrate having hills and valleys have corresponding hills and valleys in the device layers. We have found that disposing an insulator in the valleys of the device layers such that the top electrode of the device is insulated from the device layer valleys provides beneficial results. In particular, this insulator prevents electrical shorts that otherwise tend to occur in such devices. | 2012-11-15 |
20120286390 | ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME - An electrical fuse structure includes a top fuse, a bottom fuse and a via conductive layer positioned between the top fuse and the bottom fuse for providing electric connection. The top fuse includes a top fuse length and the top fuse length is equal to or larger than a predetermined value. The bottom fuse includes a bottom fuse length larger than the top fuse length. | 2012-11-15 |
20120286391 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit is provided. The semiconductor circuit includes a metal layer, a conductive layer disposed under the metal layer and a semiconductor device disposed under the conductive layer. The metal layer forms an inductor device. The semiconductor device is coupled to the inductor device. | 2012-11-15 |
20120286392 | SUPPRESSION OF DIFFUSION IN EPITAXIAL BURIED PLATE FOR DEEP TRENCHES - Dopants of a first conductivity type are implanted into a top portion of a semiconductor substrate having a doping of the first conductivity type to increase the dopant concentration in the top portion, which is a first-conductivity-type semiconductor layer. A semiconductor material layer having a doping of the second conductivity type, a buried insulator layer, and a top semiconductor layer are formed thereupon. Deep trenches having a narrow width have a bottom surface within the second-conductivity-type semiconductor layer, which functions as a buried plate. Deep trenches having a wider width are etched into the first-conductivity-type layer underneath, and can be used to form an isolation structure. The additional dopants in the first-conductivity-type semiconductor layer provide a counterdoping against downward diffusion of dopants of the second conductivity type to enhance electrical isolation. | 2012-11-15 |