46th week of 2013 patent applcation highlights part 31 |
Patent application number | Title | Published |
20130301303 | POWER CONTROLLERS AND CONTROL METHODS - Disclosed include power controllers and related control methods. A disclosed power controller has a pulse generator, a sample/hold device, a comparator, and a switch controller. The pulse generator provides an enable signal, defining an enable time. The comparator has two inputs capable of being coupled to a reference signal and a feedback signal, respectively, and an output coupled to a compensation capacitor. When enabled by the enable signal, the comparator charges/discharges the compensation capacitor. The switch controller controls a power switch according to a compensation voltage of the compensation capacitor. A feedback voltage of the feedback signal is able to correspond to an output voltage of the power supply. | 2013-11-14 |
20130301304 | DC-DC CONVERTER - A DC-DC converter in which a primary side and a secondary side are insulated by a transformer, includes: two diodes having anodes respectively connected to both ends of a secondary winding of the transformer and cathodes connected to each other; a series circuit composed of a resistor and a capacitor connected in series; and a snubber circuit formed by connecting the cathodes of the diodes to the connection point between the resistor and the capacitor. Surge voltage caused on the secondary side of the transformer is clamped at the voltage of the capacitor, and surge energy stored in the capacitor is regenerated to a load via the resistor. Thus, surge voltage caused on the secondary side of the transformer is suppressed with a simple configuration, and effective use of surge energy is ensured. | 2013-11-14 |
20130301305 | LLC CONTROLLER WITH PROGRAMMABLE FRACTIONAL BURST FREQUENCY - A method of controlling an LLC resonant converter includes programming a burst stop frequency and a burst start frequency in response to a maximum switching frequency of the LLC resonant converter. The burst stop frequency and the burst start frequency are fractions of the maximum switching frequency. The LLC resonant converter is switched in response to a feedback signal to regulate an output of the LLC resonant converter. The steps of switching the LLC resonant converter in a run state in response to the feedback signal reaching a value corresponding to the programmed burst start frequency, and stopping the switching of the LLC resonant converter in a stop state in response to the feedback signal reaching a value corresponding to the programmed burst stop frequency are repeated. | 2013-11-14 |
20130301306 | SWITCHING POWER SUPPLY DEVICE - In a switching power supply device with reduced size and increased power conversion efficiency, a secondary-side rectifier circuit includes an adder-rectifier circuit that stores a voltage generated in a secondary winding in a capacitor as electrostatic energy in an on period of one of a high-side and low-side switching circuits or, and adds the voltage in the capacitor and the voltage generated in the secondary winding and outputs the sum as a direct-current voltage during in an on period of the other of the high-side and low-side switching circuits. A switching control circuit adjusts an output power to be output from the secondary-side rectifier circuit, by using on-period ratio controller that controls a proportion of periods during which the respective high-side side and low-side switching elements are brought into a conductive state. | 2013-11-14 |
20130301307 | RESONANT POWER CONVERTER - A resonant power converter includes a resonance tank formed by a capacitance component and an inductance component, at least two switches connected to the resonance tank and a voltages source in a bridge configuration, a number of snubber capacitors connected in parallel to each of the switches, a controller configured to control ON and OFF timings of the at least two switches so as to excite the resonance tank, and a voltage sensor configured to sense a voltage drop across at least one of the switches. The controller is configured to switch the at least one of the switches to the ON state when the absolute value of the sensed voltage drop reaches a minimum. | 2013-11-14 |
20130301308 | SWITCHING POWER SUPPLY DEVICE - In a switching power supply device with reduced size and increased power conversion efficiency, a first resonant circuit including a series resonant inductor and a series resonant capacitor, and a second resonant circuit including a series resonant inductor and a series resonant capacitor, are caused to resonate with each other to cause sympathetic vibration of each resonant circuit, such that transmission is performed by utilizing both magnetic field coupling and electric field coupling between a primary winding and a secondary winding. Operation at a switching frequency higher than a specific resonant frequency of an overall multi-resonant circuit allows a ZVS operation to be performed, enabling a significant reduction in switching loss and high-efficiency operation. | 2013-11-14 |
20130301309 | CONTROL CIRCUITS AND CONTROL METHODS FOR FLYBACK CONVERTERS AND AC-DC POWER CONVERTERS THEREOF - The present invention relates to control circuits and methods for a flyback converter and AC-DC power converters thereof. In one embodiment, a control circuit can include: (i) a turn-on signal generating circuit that is configured, in each switching cycle, to receive a drain-source voltage of a power switch of the flyback converter, and to activate a turn-on signal to turn on the power switch when the drain-source voltage reaches a valley value; (ii) a turn-off signal generating circuit that is configured, in each switching cycle, to activate a turn-off signal to turn off the power switch based on a power switch feedback error signal after a power switch conducting time interval has elapsed; and (iii) where input current and voltages of the flyback converter can be maintained as substantially in phase, and an output electrical signal of the flyback converter can be maintained as substantially constant. | 2013-11-14 |
20130301310 | ISOLATED SWITCHING MODE POWER SUPPLY AND THE METHOD THEREOF - An isolated switching mode power supply, having: an input terminal; an output terminal; a transformer having a primary winding and a secondary winding; a primary power switch coupled to the primary winding; a secondary power switch coupled between the secondary winding and the output terminal of the power supply; a secondary controller configured to generate a frequency modulation signal based on the output voltage and the first feedback signal; a coupled device configured to provide a frequency control signal based on the output voltage and the frequency modulation signal; and a primary controller configured to provide a switching signal to control the primary power switch based on the current sense signal and the frequency control signal. | 2013-11-14 |
20130301311 | SWITCHING MODE POWER SUPPLY AND THE METHOD THEREOF - A switching mode power supply, having: an input port; an output port; an energy storage component and a pair of power switches coupled between input port and the output port; an error amplifier configured to generate an amplified error signal based on the feedback signal and the reference signal; an error comparator configured to generate a frequency control signal based on the amplified error signal and the first sawtooth signal; a peak current generator configured to generate a peak current signal based on the frequency control signal; a peak current comparator configured to generate a current limit signal based on the peak current signal and the current sense signal; and a logic circuit configured to generate a switching signal to control the power switches based on the frequency control signal and the current limit signal. | 2013-11-14 |
20130301312 | ISOLATED SWITCHING POWER SUPPLY APPARATUS - An isolated switching power supply apparatus includes a transformer, a primary-side circuit that includes at least a switching element and supplies input power from an input terminal to a primary winding by controlling on/off of the switching element, and a secondary-side circuit that is electrically isolated from the primary-side circuit and that outputs output power resulting from power conversion performed by the transformer from a secondary winding to an output terminal. The apparatus includes a first circuit board to which the primary winding is connected and that includes the primary-side circuit and the input terminal, and a second circuit board to which the secondary winding is connected and that includes the secondary-side circuit and the output terminal. The first and second circuit boards are stacked in a multilayer manner. The primary and secondary windings are arranged around a core that extends through the first and second circuit boards. | 2013-11-14 |
20130301313 | HVDC SYSTEM AND METHOD TO CONTROL A VOLTAGE SOURCE CONVERTER IN A HVDC SYSTEM - A method to control a voltage source converter (CON | 2013-11-14 |
20130301314 | Multilevel Inverter Device and Method - An embodiment multilevel inverter comprises a first boost apparatus having an input coupled to a positive dc bus and a second boost apparatus having an input coupled to a negative dc bus. The multilevel inverter further comprise a first switch coupled to an input of an L-C filter and the first boost apparatus, a second switch coupled to the input of the L-C filter and the second boost apparatus, a third switch coupled between the positive dc bus and the first switch and a fourth switch coupled between the negative dc bus and the second switch. | 2013-11-14 |
20130301315 | METHOD FOR OPERATING AN INVERTER, AND CONTROL DEVICE - A method for limiting an output power of an inverter having an output bridge and an upstream boost converter includes determining a first measurement variable representative of a bridge temperature and a second measurement variable representative of an output power of the inverter. The method also includes determining a third measurement variable representative of a generator voltage at generator connections of the inverter or a fourth measurement variable representative of an output voltage at a power output of the inverter, and reducing the output power supplied to a power supply grid to a reduced power value. The reduced power value is determined based on the first measurement variable, the second measurement variable and at least one of the third and fourth measurement variables. A control device having such functionality is also disclosed | 2013-11-14 |
20130301316 | POWER-LEVEL WAVEFORM GENERATION METHOD - The present invention relates to a method of generating various alternating current waveforms, at power level. The AC mains power supply is rectified, processed by various circuits, controlled by a control unit and inverted as required at the output. This method may be employed with converter isolation from the mains. It is also possible to employ the system so that the input current is sinusoidal and the power factor of the converter is unity. The present invention produces preferably the sinusoidal output waveform with fundamental component at the desired frequency, where this waveform is produced employing a DC bus from which output voltage with the fundamental component at the desired shape and frequency is obtained using pulse width modulation techniques. The output stage is simply an inverter which inverts this waveform at zero-crossings of the rectified waveform to obtain an AC output. | 2013-11-14 |
20130301317 | SWITCHING POWER SUPPLY DEVICE - Provided is a switching power supply device capable of sufficiently removing ripple noise due to the switching frequency, the ripple noise being superimposed on an AC line, thereby stabilizing an output voltage. The switching power supply device includes: a switch including a first main terminal and a second main terminal, the first main terminal being connected to an inductor, the second main terminal being connected to a predetermined constant power supply unit, the switch being configured to connect or disconnect between the inductor and the constant power supply unit; and a control circuit configured to drive the switch at a predetermined switching frequency. The control circuit varies the switching frequency in accordance with a ratio of a connected time of the switch to a disconnected time of the switch. | 2013-11-14 |
20130301318 | DRIVE UNIT FOR SWITCHING ELEMENT AND METHOD THEREOF - The present application provides a drive unit for a switching element, the driving unit having a function that is capable of promptly detecting the flow of excess current. The unit is usable for an electrical rotating machine. A drive unit for a switching element, comprising: a sense terminal output current detecting means for detecting an output current of a sense terminal that outputs a minute current having correlation with a current flowing between an input terminal and an output terminal of a switching element; a switching element drive control means for restricting the driving of the switching element when the output current detected by the sense terminal output current detecting means exceeds a predetermined threshold value; and a threshold changing means for changing the threshold value on the basis of a difference of electric potential between the input terminal and the output terminal of the switching element. | 2013-11-14 |
20130301319 | PRINTED CIRCUIT BOARD - A power source circuit includes a switching circuit | 2013-11-14 |
20130301320 | COMPACT HIGH-POWER DIODE/THYRISTOR RECTIFIER ARCHITECTURE - A Graëtz-bridge converter-rectifier in which at least one rectifier arm situated between a single AC terminal and a single DC terminal includes multiple unidirectional electronic components connected in parallel and connected on one side to the DC terminal by means of a conductive component set and on the other side to the AC terminal. The invention is characterized in that the component set for at least one rectifier arm includes a plurality of separate component busbars each having at least one end connected to the DC terminal, the unidirectional components being divided between the component busbars into as many component sets connected in parallel as there are component busbars. | 2013-11-14 |
20130301321 | TRACKING CONVERTERS WITH INPUT OUTPUT LINEARIZATION CONTROL - In a preferred embodiment, a voltage inverter comprises a voltage converter circuit and a controller. The voltage inverter produces a time-varying output voltage from an input voltage, which can be a DC input voltage or an AC input voltage. The controller provides a control signal at a duty ratio determined dynamically by a set of signals. The set of signals include the time-varying output voltage, a predetermined output voltage, a gain factor and an inductor current in the voltage converter circuit. The predetermined output voltage can have an AC waveform or an arbitrary time-varying waveform. The voltage inverter operates to match the time-varying output voltage to the predetermined output voltage. Input-output linearization is used to design a buck inverter, and input-output linearization with leading edge modulation is used to design boost and buck-boost inverters under conditions where left half plane zero effects are present. | 2013-11-14 |
20130301322 | METHOD AND APPARATUS FOR IMPROVED BURST MODE DURING POWER CONVERSION - A method and apparatus for power conversion. In one embodiment, the method comprises operating an inverter in bursts by (i) enabling power production by the inverter during a first plurality of periods, and (ii) disabling power production by the inverter during a second plurality of periods. | 2013-11-14 |
20130301323 | POWER CONVERSION APPARATUS - A power conversion apparatus includes: a bridge circuit between AC and DC ends; a converter circuit between the bridge circuit and the DC end; and a control device for the converter circuit. The converter circuit includes: first and second switches in series between terminals of the bridge circuit; third and fourth switches in series between terminals of the DC end; and a reactor between an intermediate point of the first and second switches and an intermediate point of the third and fourth switches. The control device includes: a first controller defining a part of a cycle of an AC voltage as a stop period and stopping switching the first and second switches during the stop period; and a second controller performing voltage/power factor correction controls over an entire cycle by switching the third and/or fourth switches. | 2013-11-14 |
20130301324 | ELECTRO-MAGNETIC INTERFERENCE REDUCTION CIRCUIT FOR POWER CONVERTERS AND METHOD THEREOF - The present invention provides a circuit of reducing electro-magnetic interference for a power converter. The circuit includes an oscillator, a switching voltage divider, and a sample-and-hold circuit. The oscillator has a terminal for receiving a modulation voltage. The modulation voltage is correlated with an input voltage obtained from an input of the power converter. The switching voltage divider is enabled and disabled by a switch to attenuate the input voltage into a sampled voltage in response to a sampling signal. The sample-and-hold circuit receives the sampled voltage to generate the modulation voltage. A switch of the sample-and-hold circuit controlled by a holding signal conducts the sampled voltage to a capacitor of the sample-and-hold circuit to generate the modulation voltage across the capacitor. | 2013-11-14 |
20130301325 | Procedures for the Operation of an Electrical Circuit - A method for operating an electrical circuit is described. The electrical circuit is equipped with a power converter ( | 2013-11-14 |
20130301326 | METHOD AND APPARATUS FOR CONTROLLING THERMAL CYCLING - A method for reducing thermal cycling of a semiconductor power switch includes obtaining a value indicative of a junction temperature of the power switch. The method also includes selecting one of several pre-determined gate drive voltages, based on the obtained value, and providing the selected gate drive voltage to a gate of the power switch. This reduces thermal cycling of a power switch relative to the thermal cycling that would be present during operation at a single gate temperature. | 2013-11-14 |
20130301327 | SYSTEM AND METHOD OF PARALLEL CONVERTER CURRENT SHARING - In one aspect, a method of converting power is described. One embodiment of the method comprises receiving direct current (DC) power; channeling the DC power through an inverter including a first bridge and a second bridge, wherein each of the first bridge and the second bridge includes at least one switch; controlling the at least one switch of the first bridge and the at least one switch of the second bridge to convert the DC power to alternating current (AC) power; and, channeling the AC power through an inductor that includes a first winding and a second winding, wherein the first winding is coupled to an output of the first bridge and the second winding is coupled to an output of the second bridge and wherein the inductor is configured to have a first magnetic path for common mode inductance and a second magnetic path for differential mode inductance. | 2013-11-14 |
20130301328 | POWER CONVERSION APPARATUS - A power conversion apparatus according to an embodiment includes a cooling jacket. The cooling jacket includes a mounting face on which a power module including a power semiconductor device is mounted, a plurality of radiation fins that are arranged along a predetermined direction over the substantially whole area of the back side of the mounting face, and a boss that is placed along the predetermined direction in the central area of the substantially whole area of the back side. | 2013-11-14 |
20130301329 | ELECTRICAL CIRCUIT, IN PARTICULAR USED FOR GENERATING ELECTRICAL POWER - An electrical circuit, in particular a circuit used for generating electric power, wherein this circuit comprises a generator with n phases, a converter and a transformer to which a p-phase load can be connected. The converter comprises m partial converters, each of the partial converters is composed of p units and each of these units is provided with n/m switching circuits. The switching circuits of the individual units are connected symmetrical to the generator. | 2013-11-14 |
20130301330 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines. | 2013-11-14 |
20130301331 | SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile. | 2013-11-14 |
20130301332 | SEMICONDUCTOR DEVICE - To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions. The first data storage portion is electrically connected to the fourth data storage portion through a transistor, and the second data storage portion is electrically connected to the third data storage portion through a transistor. The transistors are turned off when the SRAM operates, and the transistors are turned on when the SRAM does not operate, so that data in the SRAM is saved to the non-volatile memory. Precharge is performed when the SRAM is restored. | 2013-11-14 |
20130301333 | Photonic Quantum Memory - A photonic quantum memory is provided. The photonic quantum memory includes entanglement basis conversion module configured to receive a first polarization-entangled photon pair and to produce a second entangled photon pair. The second polarization-entangled photon pair can he a time-bin entangled or a propagation direction-entangled photon pair. The photonic quantum memory further includes a photonic storage configured to receive the second entangled photon pair from the basis conversion module and to store the second entangled photon pair. | 2013-11-14 |
20130301334 | METHODS, ARTICLES AND DEVICES FOR PULSE ADJUSTMENTS TO PROGRAM A MEMORY CELL - Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells. | 2013-11-14 |
20130301335 | ARCHITECTURE, SYSTEM AND METHOD FOR TESTING RESISTIVE TYPE MEMORY - Example embodiments include a method for massive parallel stress testing of resistive type memories. The method can include, for example, disabling one or more internal analog voltage generators, configuring memory circuitry to use a common plane voltage (VCP) pad or external pin, connecting bit lines of the memory device to a constant current driver, which works in tandem with the VCP pad or external pin to perform massive parallel read or write operations. The inventive concepts include fast test setup and initialization of the memory array. The data can be retention tested or otherwise verified using similar massive parallel testing techniques. Embodiments also include a memory test system including a memory device having DFT circuitry configured to perform massive parallel stress testing, retention testing, functional testing, and test setup and initialization. | 2013-11-14 |
20130301336 | PERMUTATIONAL MEMORY CELLS - Various embodiments comprise apparatuses having at least two resistance change memory (RCM) cells. In one embodiment, an apparatus includes at least two electrical contacts coupled to each of the RCM cells. A memory cell material is disposed between pairs of each of the electrical contacts coupled to each of the RCM cells. The memory cell material is capable of forming a conductive pathway between the electrical contacts with at least a portion of the memory cell material arranged to cross-couple a conductive pathway between select ones of the at least two electrical contacts electrically coupled to each of the at least two RCM cells. Additional apparatuses and methods are described. | 2013-11-14 |
20130301337 | Resistive Devices and Methods of Operation Thereof - In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse. | 2013-11-14 |
20130301338 | HYBRID RESISTIVE MEMORY DEVICES AND METHODS OF OPERATING AND MANUFACTURING THE SAME - Hybrid resistive memory devices and methods of operating and manufacturing the same, include at least two resistive memory units. At least one of the at least two resistive memory units is a resistive memory unit configured to operate in a long-term plasticity state. | 2013-11-14 |
20130301339 | SEMICONDUCTOR MEMORY DEVICE - A control circuit controls a voltage applied to a memory cell array. A first electrode contacts to a first surface of a variable resistance element, while a second electrode contacts to a second surface of the variable resistance element. The first electrode is configured by a metal, and the second electrode is configured by a P type semiconductor. The control unit, when performing a setting operation of a memory cell, applies a voltage such that a current flows in a direction from the first electrode toward the second electrode. | 2013-11-14 |
20130301340 | ERASING METHOD OF RESISTIVE RANDOM ACCESS MEMORY - An erase method of a resistive random access memory which includes a plurality of cell strings, each having a plurality of memory cells and a string selection transistor, includes applying a first voltage to bit lines connected with string selection transistors of the plurality of cell strings, applying a turn-on voltage to at least one string selection line selected from string selection lines connected with the string selection transistors, applying a turn-off voltage to unselected string selection lines of the string selection lines, applying a second voltage to at least one word line selected from word lines connected with memory cells of the plurality of cell strings, and floating unselected word lines of the word lines. | 2013-11-14 |
20130301341 | HERETO RESISTIVE SWITCHING MATERIAL LAYER IN RRAM DEVICE AND METHOD - A non-volatile memory device includes a first electrode, a resistive switching material stack overlying the first electrode. The resistive switching material stack comprising a first resistive switching material and a second resistive switching material. The second resistive switching material overlies the first electrode and the first resistive switching material overlying the second resistive switching material. The first resistive switching material is characterized by a first switching voltage having a first amplitude. The second resistive switching material is characterized by a second switching voltage having a second amplitude no greater than the first switching voltage. A second electrode comprising at least a metal material physically and electrically in contact with the first resistive switching material overlies the first resistive switching material. | 2013-11-14 |
20130301342 | MEMORY ELEMENT, STACKING, MEMORY MATRIX AND METHOD FOR OPERATION - Disclosed is a memory element, a stack, and to a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V | 2013-11-14 |
20130301343 | THRESHOLD VOLTAGE MEASUREMENT DEVICE - A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments. | 2013-11-14 |
20130301344 | MULTIPLE-PORT MEMORY DEVICE COMPRISING SINGLE-PORT MEMORY DEVICE WITH SUPPORTING CONTROL CIRCUITRY - An apparatus comprises a clock generator, first and second memory drivers and a multiple-port memory device having at least first and second ports configured to receive input signals from and supply output signals to respective ones of the first and second memory drivers, the multiple-port memory device further comprising a single-port memory device and control circuitry coupled between the first and second ports and the single port of the single-port memory device. The clock generator generates first and second clock signals having respective first and second clock rates, the clock rate of the second clock signal being an integer multiple of the clock rate of the first clock signal. The first and second memory drivers are configured to operate using the first clock signal at the first clock rate, and the single-port memory device is configured to operate using the second clock signal at the second clock rate. | 2013-11-14 |
20130301345 | MAGNETIC RANDOM ACCESS MEMORY AND MEMORY SYSTEM - According to one embodiment, a magnetic random access memory includes a write circuit to write s-bit (s is a natural number equal to 2 or greater) write data to magnetoresistive elements, and a read circuit to read s-bit read data from the magnetoresistive elements. The control circuit is configured to select one of first and second modes based on a mode selection signal, read the read data by the read circuit and write one of the write data and inversion data of the write data to the magnetoresistive elements by the write circuit based on the read data and the write data if free space of the buffer memory is equal to a fixed value or more when the second mode is selected. | 2013-11-14 |
20130301346 | SELF REFERENCING SENSE AMPLIFIER FOR SPIN TORQUE MRAM - Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin. | 2013-11-14 |
20130301347 | Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bit Lines - An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. | 2013-11-14 |
20130301348 | ROW DECODER CIRCUIT FOR A PHASE CHANGE NON-VOLATILE MEMORY DEVICE - A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal. | 2013-11-14 |
20130301349 | Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making - An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. | 2013-11-14 |
20130301350 | Vertical Structure Nonvolatile Memory Device - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 2013-11-14 |
20130301351 | Channel Boosting Using Secondary Neighbor Channel Coupling In Non-Volatile Memory - In a non-volatile storage system, a programming portion of a program-verify iteration has multiple programming pulses, and storage elements along a word line are selected for programming according to a pattern. Unselected storage elements are grouped to benefit from channel-to-channel capacitive coupling from both primary and secondary neighbor storage elements. The coupling is helpful to boost channel regions of the unselected storage elements to a higher channel potential to prevent program disturb. Each selected storage element has a different relative position within its set. For example, during a first programming pulse, first, second and third storage elements are selected in first, second and third sets, respectively. During a second programming pulse, second, third and first storage elements are selected in the first, second and third sets, respectively. During a third programming pulse, third, first and second storage elements are selected in the first, second and third sets, respectively. | 2013-11-14 |
20130301352 | METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE METHOD - A method of programming a nonvolatile memory device including multi-level cells that store multi-bit data, includes performing a pre-programming operation that programs at least some of the multi-level cells to a plurality of intermediate states which are different from an erased state, and performing a main programming operation that programs the multi-level cells to a plurality of target states corresponding to the multi-bit data. At least some of the intermediate program states have threshold voltage distributions that partially overlap each other. | 2013-11-14 |
20130301353 | Methods of Driving a Memory - Methods of driving a memory include erasing a plurality of memory cells of a memory device, testing whether the memory cells have been erased, and programming the memory cells without erasing the memory cells again if more than a predetermined percentage of the memory cells, but less than all of the memory cells, were successfully erased. | 2013-11-14 |
20130301354 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes memory cells and a voltage generating circuit for generating a voltage for memory cells. The first voltage generating circuit includes a first diode connected between first and second nodes, a first transistor connected between the output terminal and a third node and having a gate connected to the second node, a second transistor connected between the third node and a fourth node and having a gate connected to the second node, a third transistor connected between the output terminal and the first node and having a gate connected to the fourth node, a second diode connected between the first and fourth nodes, and a charge pump circuit configured to supply a voltage to the fourth node. The first voltage generating circuit functions to adjust the generated voltage when it overshoots a desired value which may be caused by capacitive coupling with adjacent wirings. | 2013-11-14 |
20130301355 | EEPROM MEMORY UNIT AND EEPROM MEMORY DEVICE - An EEPROM memory unit is disclosed. The EEPROM memory unit includes a first memory cell, a second memory cell, and a word line controller. The first memory cell includes a source that is connected to a first bit line of the EEPROM memory unit and a drain that is connected to a source of the word line controller. The word line controller includes a drain that is connected to a source of the second memory cell. The second memory cell includes a drain that is connected to a second bit line of the EEPROM memory unit. An EEPROM memory device is also disclosed. | 2013-11-14 |
20130301356 | SEMICONDUCTOR DEVICE WITH ONE-TIME PROGRAMMABLE MEMORY CELL INCLUDING ANTI-FUSE WITH MAETAL/POLYCIDE GATE - A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate. | 2013-11-14 |
20130301357 | REDUCING NOISE IN SEMICONDUCTOR DEVICES - The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage. | 2013-11-14 |
20130301358 | BIT LINE BL ISOLATION SCHEME DURING ERASE OPERATION FOR NON-VOLATILE STORAGE - A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data. | 2013-11-14 |
20130301359 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage. | 2013-11-14 |
20130301360 | Data Storage in Analog Memory Cells Using Modified Pass Voltages - A method for data storage includes storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing a storage value into the target memory cell. The storage value written into the target memory cell is verified while biasing the other memory cells in the group with respective first pass voltages. After writing and verifying the storage value, the storage value is read from the target memory cell while biasing the other memory cells in the group with respective second pass voltages, wherein at least one of the second pass voltages applied to one of the other memory cells in the group is lower than a respective first pass voltage applied to the one of the other memory cells. The data is reconstructed responsively to the read storage value. | 2013-11-14 |
20130301361 | ROW DRIVER ARCHITECTURE - Devices and circuits for row driver in a memory device. The proposed row driver circuit architectures may reduce size of the row driver circuitry and enhance the row driver circuit's reliability. Specifically, the proposed embodiments of the row driver may reduce the required sizing of the boosting capacitor or alternatively eliminate the boosting capacitor entirely. Further, the embodiments of the row driver may reduce the risk of charge-leakage on K-nodes, enhancing the row driver's reliability in driving the x-path of the memory array. | 2013-11-14 |
20130301362 | PULSE-BASED MEMORY READ-OUT - A pulse-based memory read-out device, including: a pulse generator at a first end of a bit line and a detector at a second end of the bit line. The pulse generator is configured to send an electrical pulse along the bit line from the first end of the bit line. The detector is configured to: detect the electrical pulse at the second end; and output a digital signal representing a current state of a selected memory cell in the bit line, wherein the digital signal is based on an amplitude of the electrical pulse at the second end. | 2013-11-14 |
20130301363 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING SEMICONDUCTOR MEMORY DEVICE - Upon programming a semiconductor memory device including a first and a second n-wells, a first and a second p-channel memory transistors respectively formed in the first and the second n-wells, and a bit line connected to a drain of the first p-channel transistor and a drain of the second p-channel memory transistor, a first voltage is applied to the first bit line, a second voltage is applied to the first n-well, and a third voltage lower than the second voltage is applied to the second n-well. | 2013-11-14 |
20130301364 | SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 2013-11-14 |
20130301365 | DEDICATED REFERENCE VOLTAGE GENERATION CIRCUIT FOR MEMORY - A memory includes a data pin, an address pin, and a reference voltage generation circuit. The reference voltage generation circuit includes a first reference voltage generation circuit and a second reference voltage generation circuit. The first reference voltage generation circuit is electronically connected to the data pin, and supplies a reliable first reference voltage to the data pin. The second reference voltage generation circuit is electronically connected to the address pin, and supplies a reliable second reference voltage to the address pin. | 2013-11-14 |
20130301366 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device of the present invention includes a memory cell array with cell strings having word lines stacked on a substrate and a vertical channel layer formed through the word lines, a peripheral circuit configured to select one of the word lines and perform a program operation on the selected word line, and a control circuit configured to control the peripheral circuit to perform the program operation by applying a program voltage to a word line selected for the program operation, applying a ground voltage to a word line of which a program operation has been completed and applying a pass voltage to the other word lines. | 2013-11-14 |
20130301367 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in off-state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided. | 2013-11-14 |
20130301368 | Supporting Calibration For Sub-Rate Operation In Clocked Memory Systems - The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ⅛ of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate. | 2013-11-14 |
20130301369 | MECHANISMS FOR BUILT-IN SELF REPAIR OF MEMORY DEVICES USING FAILED BIT MAPS AND OBVIOUS REPAIRS - A method of self-testing and self-repairing a random access memory (RAM) is includes collecting failure data of the RAM with redundant rows and columns, wherein the failure data of all failed cells of the RAM are stored in two failure bit map (FBM) data structures. The method further includes performing obvious repair of failed cells during the collecting of the failure data and analyzing the failure data in the two FBM data structure to determine repair methods. The method further includes repairing failed cells of the RAM by using the redundant rows and columns. | 2013-11-14 |
20130301370 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME - A device includes first memory blocks each including a first local bit line, first memory cells connected to the first local bit line and a first hierarchy switch connected between a first global bit line and the first local bit line, a dummy global bit line connected to the second node of a first sense amplifier, a dummy block including a dummy local bit line, dummy memory cells connected to the dummy local bit line and a dummy hierarchy switch connected between the dummy global bit line and the dummy local bit line, and a control circuit supplied with address information and configured to respond to the address information designating any one of the first memory blocks to turn ON each of the dummy hierarchy switch of the dummy block and the first hierarchy switch of one of the first memory blocks designated by the address information. | 2013-11-14 |
20130301371 | DYNAMIC RANDOM ACCESS MEMORY WITH MULTIPLE THERMAL SENSORS DISPOSED THEREIN AND CONTROL METHOD THEREOF - A dynamic random access memory (DRAM) with multiple thermal sensors disposed therein and a control method for the DRAM. A DRAM in accordance with an exemplary embodiment of the invention provides multi-zone temperature detection. The DRAM comprises a plurality of banks, a plurality of thermal sensors and a control unit. The thermal sensors are disposed between the banks. The control unit controls the thermal sensors to obtain sensed temperatures, and sets a self-refresh cycle for all of the banks based on the highest one of the sensed temperatures. | 2013-11-14 |
20130301372 | MEMORY DEVICE, MEMORY SYSTEM, AND POWER MANAGEMENT METHOD - A power management method includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die, after receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an immediate execution of the second high power operation would overlap the first high power operation, and delaying execution of second high power operation through a first waiting period that ends upon completion of the first high power operation, while applying a reference voltage to a second word line of the second memory die indicated by the second address. | 2013-11-14 |
20130301373 | Memory Chip Power Management - A power supply voltage for a memory chip is compared with a plurality of threshold voltages that correspond to voltages below which classes of memory operations can no longer be guaranteed. When the power supply voltage drops below a threshold voltage, appropriate action is taken, which may include generating an indicator such as a flag, proceeding with the operations in some modified manner, or disabling operations that are no longer guaranteed, either permanently or until power is restored, or until some other appropriate time. | 2013-11-14 |
20130301374 | WORD LINE DRIVER HAVING A CONTROL SWITCH - A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse. | 2013-11-14 |
20130301375 | METHOD FOR OPERATING AN APPARATUS WITH AT LEAST ONE ROTATING SHAFT - A method for operating an apparatus with at least one rotating shaft, the at least one rotating shaft comprising functional elements which act on material to be processed in the apparatus, the apparatus comprising a filling orifice and an outlet orifice with an adjustable lower edge, and material being conveyed continuously through the apparatus from the filling orifice to the outlet orifice, said method comprising the following steps:
| 2013-11-14 |
20130301376 | PORTIONING AND KNEADING DRUM - A device for portioning and kneading dough is provided, comprising a chamber drum incrementally rotatable about a drive shaft by a main drive provided at the circumferential sections thereof with accommodation chambers, wherein in each accommodation chamber there may be slid one or a plurality of weighing stamps in the radial direction of the chamber drum by motion-according coupling with a control device. At least one circumferential section of the chamber drum, which has at least one accommodation chamber, may be removed and re-attached in the axial direction together with the weighing stamp situated in the accommodation chamber. Each weighing chamber is motion-accordingly coupled with the control device by a lever shaft, which is provided at one of its lever shaft ends with a cam roller housed in a cam-like curved compulsory guiding of a control device. | 2013-11-14 |
20130301377 | Bubble Implosion Reactor Cavitation Device, Subassembly, and Methods for Utilizing the Same - An apparatus is disclosed. The apparatus includes a bubble implosion reactor cavitation device. The bubble implosion reactor cavitation device includes a tube-shaped cylindrical body including an upstream, a distal end surface and a downstream, proximal end surface. The tube-shaped cylindrical body defines an axial passage that extends through the tube-shaped cylindrical body between the upstream, distal end surface and the downstream, proximal end surface. The apparatus also includes a bubble generator subassembly connected to the tube-shaped cylindrical body. The bubble generator subassembly is at least partially disposed within the axial passage defined by the tube-shaped cylindrical body. The apparatus also includes a retaining member connected to the tube-shaped cylindrical body for retaining the bubble generator subassembly within the axial passage defined by the tube-shaped cylindrical body. | 2013-11-14 |
20130301378 | LIQUID CONDIMENT DISPENSERS - A liquid condiment dispenser comprises a container closed by a lid and an agitator within the container. The agitator includes an elongate connector portion and an agitator portion. One end of the connector portion is connected to the agitator portion. The connector portion is capable of pivotal movement with respect to the lid. The cross sectional area of the connector portion transverse to its length is substantially less than that of the agitator portion. The agitator portion includes at least one passage extending through it and a weight of relatively dense material, such as metal, embedded within it. | 2013-11-14 |
20130301379 | LAYER MULTIPLIER FOR FLUIDS WITH HIGH VISCOSITY - A layer multiplier ( | 2013-11-14 |
20130301380 | METHOD FOR DUAL MODALITY OPTOACOUSTIC IMAGING - A real-time imaging method that provides ultrasonic imaging and optoacoustic imaging coregistered through application of the same hand-held probe to generate and detect ultrasonic and optoacoustic signals. These signals are digitized, processed and used to reconstruct anatomical maps superimposed with maps of two functional parameters of blood hemoglobin index and blood oxygenation index. The blood hemoglobin index represents blood hemoglobin concentration changes in the areas of diagnostic interest relative to the background blood concentration. The blood oxygenation index represents blood oxygenation changes in the areas of diagnostic interest relative to the background level of blood oxygenation. These coregistered maps can be used to noninvasively differentiate malignant tumors from benign lumps and cysts. | 2013-11-14 |
20130301381 | METHOD AND APPARATUS FOR GENERATING VOLUME IMAGE - A volume image generating method including transmitting an ultrasonic signal to a target body divided into a plurality of regions and generating a first sub-volume image corresponding to a first region from among the plurality of regions of the target body, based on a response signal reflected from the target body; generating a second sub-volume image corresponding to a second region contacting the first region from among the plurality of regions; connecting the second sub-volume image to the first sub-volume image according to a location relationship between the first region and the second region of the target body; and re-generating the second sub-volume image based on a concordance rate between sectional images of the first and second sub-volume images that contact each other, and connecting the re-generated second sub-volume image to the first sub-volume image. | 2013-11-14 |
20130301382 | Method and Device for Ultrasound Imaging - A method of high-resolution ultrasound imaging, in which transducers are made to emit ultrasound waves in a field of observations containing micro bubbles, by making the micro bubbles burst one by one in tandem with the emissions of ultrasound waves. At each shot j of an ultrasound wave, raw reverberated signals S | 2013-11-14 |
20130301383 | PORTABLE ACOUSTIC HOLOGRAPHY SYSTEMS FOR THERAPEUTIC ULTRASOUND SOURCES AND ASSOCIATED DEVICES AND METHODS - The present technology relates generally to portable acoustic holography systems for therapeutic ultrasound sources, and associated devices and methods. In some embodiments, a method of characterizing an ultrasound source by acoustic holography includes the use of a transducer geometry characteristic, a transducer operation characteristic, and a holography system measurement characteristic. A control computer can be instructed to determine holography measurement parameters. Based on the holography measurement parameters, the method can include scanning a target surface to obtain a hologram. Waveform measurements at a plurality of points on the target surface can be captured. Finally, the method can include processing the measurements to reconstruct at least one characteristic of the ultrasound source. | 2013-11-14 |
20130301384 | ACQUIRING AZIMUTH RICH SEISMIC DATA IN THE MARINE ENVIRONMENT USING A REGULAR SPARSE PATTERN OF CONTINUOUSLY CURVED SAIL LINES - A method for determining a sail plan for a towed-array marine seismic survey includes: dividing a survey area into a regular grid of tiles; and identifying a subset of the tiles as nodes around which continuously curved sail lines are defined. The nodes define regular pattern further including: a first subpattern of nodes; and a second subpattern of nodes offset from the first subpattern. A method for conducting a towed array marine survey includes: traversing a plurality of continuously curved sail lines across a survey area, each sail line being relative to a node; and acquiring seismic data while traversing the continuously curved sail lines. The set of nodes defining a regular pattern further including: a first subpattern of nodes; and a second subpattern of nodes offset from the first subpattern. | 2013-11-14 |
20130301385 | System and Method for Towed Marine Geophysical Equipment - A system comprises towed marine geophysical equipment, adapted for towing through a body of water; and a surface covering, comprising a textural attribute of shark skin, attached to the marine geophysical equipment. A method comprises towing marine geophysical equipment having a surface covering, comprising a textural attribute of shark skin, attached thereto. | 2013-11-14 |
20130301386 | METHOD, DEVICE AND PROCESSING ALGORITHM FOR MULTIPLE AND NOISE ELIMINATION FROM MARINE SEISMIC DATA - Computing device, computer instructions and method for simultaneously denoising and attenuating multiples in seismic data recorded with seismic receivers. The method includes receiving the seismic data, wherein the seismic data includes a pressure P component and a vertical Z component; separating the seismic data into up-going U wave-fields and down-going D wave-fields; calculating an up-down deconvolution R based on the up-going U and the down-going D wave-fields; generating a multiple model M based on the up-down deconvolution R; and adaptively subtracting the multiple model M from the pressure P component to obtain a corrected pressure P | 2013-11-14 |
20130301387 | Redatuming Seismic Data with Correct Internal Multiples - Method for redatuming seismic data to any arbitrary location in the subsurface in a way that is consistent with the internal scattering in the subsurface. Direct arrival times are estimated from every point to every point on the edges of a virtual box in the subsurface ( | 2013-11-14 |
20130301388 | MISALIGNMENT COMPENSATION FOR DEEP READING AZIMUTHAL PROPAGATION RESISTIVITY - An apparatus and method for estimating a parameter of interest of an earth formation involving alignment information between receivers and their corresponding oriented transmitters. The method may include generating signals indicative responses to energy transmitted into an earth formation; estimating differences in alignment between transmitters and receivers; using the estimated differences in alignment to compensate for misalignment; and estimating a parameter of interest using the misalignment compensated signals. The apparatus may include a bottom hole assembly with one or more oriented transmitters, one or more oriented receivers, one or more alignment sensors, and at least one processor configured to compensate for misalignment using information about difference in alignment between the at least one oriented transmitter and at least one oriented receiver. | 2013-11-14 |
20130301389 | System And Method For Communicating Data Between Wellbore Instruments And Surface Devices - A method for synchronizing an actuation of a seismic source with at least one of an acquisition and storage of an acoustic wave by a seismic tool having steps of determining at least one of a drilling pause and a seismic measurement, transmitting a trigger signal to a tool controller, actuating the seismic source; receiving the trigger signal and recording seismic waves in a data storage medium. | 2013-11-14 |
20130301390 | OCCUPANCY SENSING WITH SELECTIVE EMISSION - A method includes energizing an ultrasound driver to emit ultrasonic energy in a space, sensing ultrasonic energy within the space, determining an occupancy condition of the space in response to sensing ultrasonic energy reflected from the ultrasound driver, and determining the occupancy condition of the space in response to sensing ultrasonic energy in the space that was not emitted by the ultrasound driver. | 2013-11-14 |
20130301391 | SYSTEM AND METHOD FOR OBJECT POSITION ESTIMATION BASED ON ULTRASONIC REFLECTED SIGNALS - A system for small space positioning comprises a transmitting element at a fixed and known location, which transmitting a modulated continuous wave, for example an ultrasonic wave, having a continuous carrier signal part and a base-band signal modulated thereon. The transmitting element transmits the modulated continuous wave over a range in which an object to be positioned may appear. A receiving element receives signals transmitted by the transmitting device and reflected by the object, and a position detection element determines a position of the object from analysis of both the carrier signal part and the base-band signal received from the reflected signal. | 2013-11-14 |
20130301392 | METHODS AND APPARATUSES FOR COMMUNICATION OF AUDIO TOKENS - An apparatus for transmitting audio tokens includes an acoustic transmitter to generate a range of audio frequencies including an infrasonic range, a sonic range, and an ultrasonic range. An audio token generator assembles the audio tokens, which include a timestamp and an identifier, and modulates the audio token in to the range of audio frequencies. A synchronizer determines the timestamp relative to an input audio stream and a mixer mixes the audio stream and the audio token for presentation by the acoustic transmitter. An apparatus for receiving the audio tokens includes an acoustic receiver to receive the range of audio frequencies. An audio token extractor extracts the audio token including the timestamp and the identifier from the range of audio frequencies. An interpreter determines user information responsive to at least one of the timestamp and the identifier and a user interface element present the user information to a user. | 2013-11-14 |
20130301393 | DIGITAL AIR GUN - A marine air gun generates an acoustic signal in water, for example, during a marine seismic survey. The marine air gun includes digital electronic circuitry. The digital electronic circuitry may control an actuator of the marine air gun, digitize and store data from sensors located on or near the marine air gun, send and/or receive digital communications, store and/or output electrical energy, and/or perform other functions. A marine seismic source system that includes multiple air gun clusters may have a separate digital communication link between a command center and each air gun cluster. Each communication link may provide power and digital communication between the command center and one of the air gun clusters. | 2013-11-14 |
20130301394 | CMUT ASSEMBLY WITH ACOUSTIC WINDOW - In some implementations, a capacitive micromachined ultrasonic transducer (CMUT) apparatus includes one or more CMUTs or CMUT arrays, an acoustic window, a coupling medium, and a packaging substrate. The acoustic window may have various configurations, such as for reducing acoustic reflectance or increasing mechanical properties. In some examples, at least one of the CMUTs, the acoustic window or the coupling medium may include a focusing capability for focusing acoustic energy to or from the CMUT. | 2013-11-14 |
20130301395 | ULTRASOUND PROBE THERMAL DRAIN - An ultrasound probe includes a thermal drain across which heat is thermally conducted from an ultrasound transducer to an outer polymeric casing wall of the ultrasound probe. | 2013-11-14 |
20130301396 | HOUSING FOR VIBRATION GENERATING APPARATUS AND VIBRATION GENERATING APPARATUS INCLUDING THE SAME - There is provided a housing for a vibration generating apparatus, the housing including: a bracket including a protrusion part protruding from an edge thereof; and a case coupled to the bracket and having an insertion hole into which the protrusion part is inserted when the case is coupled to the bracket. | 2013-11-14 |
20130301397 | OPTICAL DISK DEVICE - An optical disc device includes an optical pickup that causes a laser beam to be incident on an optical disc and detects a reflected beam, an A/D converter that converts into a digital signal a plurality of analog signals obtained from the reflected beam detected by the optical pickup, an error signal generating circuit that generates a servo signal for the optical pickup based on the digital signal converted by the A/D converter, a low-pass filter that removes noise of a specific band included in the servo error signal generated by the error signal generating circuit, a main processor that switches a noise removal band of the low-pass filter based on states of the optical disc, and an actuator that performs servo control for the optical pickup based on the servo error signal from which the noise has been removed by the low-pass filter. | 2013-11-14 |
20130301398 | HIGHLY ADAPTIVE RECORDING METHOD AND OPTICAL RECORDING APPARATUS - An optical disk recording method includes the steps of: providing a multi-pulse chain from a recording wave; independently changing the pulse rise timing and pulse fall timing (pulse width) of the first pulse in the multi-pulse chain in accordance with a preceding space length and a recording mark length; changing the pulse rise timing and pulse fall timing (pulse width) in accordance with a following space length and the recording mark length in a predetermined timing or in independence; and in relation to the smallest mark recorded by irradiation with mono pulse, changing the rise timing in accordance with the preceding space length and the recording mark length and the fall timing (pulse width) in accordance with the following space length and recording mark length, compensating various optical disks different in recording material without change of the fundamental waveform. | 2013-11-14 |
20130301399 | INFORMATION RECORDING MEDIUM, AND RECORDING METHOD AND REPRODUCING METHOD THEREOF - An information recording medium in which bottoms of a guide groove and a pit array formed on a disc substrate are allocated on a same flat plane and shaped in flat. Further, in a transition area from a pit array to a guide groove or from a guide groove to a pit array, the information recording medium is provided with an intermediate area composed of a pit array of which height changes from a height between a bottom and a side of a groove to another height between the bottom and a side of the pit array. | 2013-11-14 |
20130301400 | System Access and Synchronization Methods for MIMO OFDM Communications Systems and Physical Layer Packet and Preamble Design - A method and apparatus are provided for performing acquisition, synchronization and cell selection within an MIMO-OFDM communication system. A coarse synchronization is performed to determine a searching window. A fine synchronization is then performed by measuring correlations between subsets of signal samples, whose first signal sample lies within the searching window, and known values. The correlations are performed in the frequency domain of the received signal. In a multiple-output OFDM system, each antenna of the OFDM transmitter has a unique known value. The known value is transmitted as pairs of consecutive pilot symbols, each pair of pilot symbols being transmitted at the same subset of sub-carrier frequencies within the OFDM frame. | 2013-11-14 |
20130301401 | PHICH Transmission in Time Division Duplex Systems - A method is provided for communication in a wireless telecommunication system. The method comprises multiplexing, by a network element, at least one symbol of a PHICH onto at least one resource element of a PCFICH. | 2013-11-14 |
20130301402 | MESSAGE PASSING TO ASSURE DELETION OF LABEL SWITCHED PATH - A label switched path through a network of nodes, is torn down by sending a message along the path from an ingress node. If there is a fault along the path, a path error message ( | 2013-11-14 |