46th week of 2008 patent applcation highlights part 41 |
Patent application number | Title | Published |
20080280344 | Subtilase Variants Having Altered Immunogenictiy - The present invention relates to subtilase subtilases with an altered immunogenicity, particularly subtilases with a reduced allergenicity. Furthermore, the invention relates to expression of said subtilase variants and subtilases and to their use, such as in detergents and oral care products. | 2008-11-13 |
20080280345 | Screening Method - The present invention relates to a method for screening for variant peptides using mass spectrometry (MS). The present invention also relates to a system and a kit for performing the method. | 2008-11-13 |
20080280346 | System For the Production of Dimeric Proteins Based on the Transport System of Hemolysin of Escherichia Coli - The system comprises a DNA construct comprising: a) a first nucleic acid sequence containing the nucleotide sequence coding for a product of interest; b) a second nucleic acid sequence containing the nucleotide sequence coding for a dimerization domain; and c) a third nucleic acid sequence containing the nucleotide sequence coding for | 2008-11-13 |
20080280347 | Method for Manufacture of Sanitised Organic Sludge - It is described a method for manufacture of sanitised organic sludge, said method comprising the following steps: mechanical mixing of a cellulose containing component, a super absorbent and dewatered organic sludge; leading the mixture to a sanitising container; continuously supplying air to the sludge mixture until the desired temperature has been reached. The super absorbent increases the moisture retention of the sludge mixture, such that odour and leakage is prevented during composting. The cellulose component, preferably shredded newspaper, admits increased air supply to the sludge mixture. The method may be used to treat sewage sludge, hydrocarbon polluted soil and waste from fish processing or abattoirs. | 2008-11-13 |
20080280348 | Method for Converting Aloeresin a to Aloesin - The invention provides a process for hydrolytically converting aloeresin A to aloesin by the following reaction: The amount of aloesin available for extraction from sap of aloe plants is thereby increased and the extraction and purification of the aloesin is also made easier and less costly. As aloesin is more commercially valuable than aloeresin A, the process also increases the commercial value of the sap or aloe bitters from the aloe plant. The process optionally also includes the step of separating the aloesin from the p-coumaric acid. Typical hydrolysis steps that are used in the process are acid hydrolysis, base hydrolysis and enzymatic hydrolysis. In the case of acid hydrolysis, the acid is any suitable organic or inorganic acid, such as hydrochloric acid, sulfuric acid, nitric acid or phosphoric acid. In the case of enzymatic hydrolysis, the hydrolytic enzyme is typically an esterase, a lipase or a protease. | 2008-11-13 |
20080280349 | Temperature Control Device - The present invention has an object to selectively culture either one of mold and yeast, both of which are fungi, with priority. In order to attaint the object, a cell parts group | 2008-11-13 |
20080280350 | REAL-TIME PCR SYSTEM - A real-time PCR system for detecting gene expression levels includes plural reaction regions, a like plural number of heating portions arranged corresponding to the reaction regions and having heat sources, respectively, an optical unit capable of irradiating exciting light of a specific wavelength to all of the plural reaction regions, and a like plural number of fluorescence detecting portions arranged corresponding to the reaction regions, respectively. The heating portions are each provided with a temperature detector for detecting a temperature in a vicinity of the corresponding heat source and converting the temperature into an electrical signal and also with a controller for controlling a thermal dose from the corresponding heat source based on a correlation between electrical signals and calorific values of the heat source stored beforehand. | 2008-11-13 |
20080280351 | METHOD AND APPARATUS FOR PREPARING CELLS FOR MICROTOME SECTIONING AND ARCHIVING NUCLEIC ACIDS AND PROTEINS - A method and apparatus for embedding cells that utilizes a flow-through embedding technique maximizes the efficiency of extractions and decreases time for embedding the cell fragments, minimizes cell loss, and automatically positions cell samples at the position in which a microtome blade will section them. The apparatus includes a cell flow pathway defined by an inflow tube for delivering cell fragments from a cell sample to a sample port. The sample port is in fluid communication with a tissue cassette having attached thereto a filter. The cell flow pathway is in communication with a reagent flow pathway for delivering the reagents through the sample port to the cassette. The apparatus is configured such that the application of pressure directs the cell fragments from the cell sample through the cell flow pathway, and effects delivery of the reagents through the reagent flow pathway. The apparatus produces an embedded cell block having concentrated cells near the plane of the block to be sectioned in a quick and efficient manner. | 2008-11-13 |
20080280352 | Method and equipment for cultivating anaerobic ammonium-oxidizing bacteria - The present invention can feed substrates without waste to generate seed sludge with high bacterial cell concentrations and can start up operation within a short time, in cultivating anaerobic ammonium oxidizing bacteria with ammonium and nitrite as substrates. Equipment for cultivating anaerobic ammonium-oxidizing bacteria, which cultivates, in a cultivation tank, novel anaerobic ammonium-oxidizing bacteria that anaerobically denitrify nitrite and ammonium used as substrates, comprises an ammonium feed device which feeds ammonium at a given concentration into the cultivation tank, a nitrite feed device which feeds nitrite at a given concentration into the cultivation tank, and a control device which controls a feed rate Y of the substrate. | 2008-11-13 |
20080280353 | Hybrid nucleic acid assembly - A detection device comprised of a hybrid nucleic acid assembly. The device further comprises a nucleic acid polymer, a first nanoparticle conjugated to the nucleic acid polymer, a second nanoparticle conjugated with the nucleic acid polymer, a means for introducing energy into the first nanoparticle, means for detecting energy from the second nanoparticle, and means for determining a physical property of the nucleic acid polymer, wherein the means of introducing energy into the first nanoparticle is a source of mechanical energy. | 2008-11-13 |
20080280354 | Recombinant poxvirus for chimeric proteins of the human immunodeficiency virus - The invention relates to HIV chimeric gene formed by the union of fragments of different genes of said virus, wherein said fragments contains epitopes for cytotoxic T cells (CTL) or HIV-1 auxiliary T cells, which are presented by a wide range of antigens of type Major Histocompatibility Complex (HLA-I). Recombinant poxviruses are obtained from said genes, which are useful for prophylactic and therapeutic vaccination against HIV/AIDS infections, are capable of generating a protective immune cell response in vaccinated laboratory animals and are recognized by the CTL lymphocytes of HIV/AIDS patients. | 2008-11-13 |
20080280355 | Control of Gene Expression with the Use of a Transcription Attenuator - This invention relates to a system for the expression of heterologous genes, comprising an attenuator element which inhibits the elongation of the transcription of the heterologous genes, the expression of which is to be controlled, and two regulating modules which control the expression of the attenuator element. The invention also relates to the use of said expression system for the amplification of the expression of recombinant proteins, RNAs or apolipoproteins in bacteria. The invention further relates to vectors containing said expression system. | 2008-11-13 |
20080280356 | Compositions and methods for enhanced expression of recombinant polypeptides from a single vector using a peptide cleavage site - Vector constructs for expression of two or more functional proteins or polypeptides under operative control of a single promoter and methods of making and using the same are described. The vectors comprise a self-processing cleavage site between each respective protein or polypeptide coding sequence. The vector constructs include the coding sequence for a self-processing cleavage site and may further include an additional proteolytic cleavage sequence which provides a means to remove the self processing peptide sequence from expressed protein(s) or polypeptide(s). The vector constructs find utility in methods for enhanced production of biologically active proteins and polypeptides in vitro and in vivo. | 2008-11-13 |
20080280357 | Cryopreservation of Hepatocytes - The invention relates to processes for the preparation of liver cells for cryopreservation, processes for cryopreservation of isolated liver cells and processes for the preparation of a culture of cryopreserved isolated liver cells. | 2008-11-13 |
20080280358 | Synthetic Peptides that Cause F-Actin Bundling and Block Actin Depolymerization - Synthetic peptides derived from sucrose synthase, and having homology to actin and actin-related proteins, sharing a common motif, useful for causing acting bundling and preventing actin depolymerization. Peptides exhibiting the common motif are described, as well as specific synthetic peptides which caused bundled actin and inhibit actin depolymerization. These peptides can be useful for treating a subject suffering from a disease characterized by cells having neoplastic growth, for anti-cancer therapeutics, delivered to subjects solely, or concomitantly or sequentially with other known cancer therapeutics. These peptides can also be used for stabilizing microfilaments in living cells and inhibiting growth of cells. | 2008-11-13 |
20080280359 | Oligoribonucleotide Inhibiting Growth of Tumor Cells and Method Therefor - The present inventors found that NEK2 kinase (accession number NM_002497) is expressed specifically in tumor cells such as bile duct carcinoma cells and that repression of the expression of NEK2 kinase by the use of RNA interference method led to inhibition of the growth of the tumor cells. | 2008-11-13 |
20080280360 | Method for Producing Biomaterial Scaffolds - The present invention provides a multilayer scaffold for tissue engineering. The scaffold comprises at least a first layer comprised of a polymer having a pattern of microchannels therein; and at least a second layer comprised of a polymer having a pattern of microchannels therein. The first and second layers are joined together (preferably by lamination) and the channels are connected for the circulation of fluid through the layers. The scaffold is coated with bacterial cellulose. The scaffold may further include a mammalian cell. | 2008-11-13 |
20080280361 | PREPARATION AND USE OF PLANT EMBRYO EXPLANTS FOR TRANSFORMATION - The present invention relates to excision of explant material comprising meristematic tissue from seeds, and storage of such material prior to subsequent use in plant tissue culture and genetic transformation. Methods for tissue preparation, storage, and transformation are disclosed, as is transformable meristem tissue produced by such methods, and apparati for tissue preparation. | 2008-11-13 |
20080280362 | Methods for reprogramming somatic cells - The invention provides methods for reprogramming somatic cells to generate multipotent or pluripotent cells. Such methods are useful for a variety of purposes, including treating or preventing a medical condition in an individual. The invention further provides methods for identifying an agent that reprograms somatic cells to a less differentiated state. | 2008-11-13 |
20080280363 | Pseudotyped Baculovirus and its Use - A viral G protein-pseudotyped baculovirus, in which the G protein is truncated and comprises the ectodomain, transmembrane domain and cytoplasmic tail domain. Such a baculovirus can be used for transduction of cells and for gene therapy. | 2008-11-13 |
20080280364 | Control of Apoptosis By Controlling the Propensity of Ceramide Channel Formation - The present invention relates to a novel target to control the apoptotic process, and to the use of this target to identify compounds capable of affecting the apoptotic process, The invention also relates to the use of such identified compounds in the treatment of cancer, stroke, neurodegenerative diseases, viral diseases and other diseases and conditions involving apoptosis. | 2008-11-13 |
20080280365 | Apparatus and Method for Determining the Volume Fractions of the Phases in a Suspension - An apparatus for determining the volume fractions of the phases in a suspension includes a body, a channel structure, which is formed in the body, and an inlet area and a blind channel, which is fluidically connected to and capable of being filled via the same. Furthermore, a drive for imparting the body with rotation, so that phase separation of the suspension in the blind channel takes place, is provided. The blind channel includes such a channel cross-section and/or such wetting properties that, when filling same via the inlet area, higher capillary forces act in a first cross-sectional area than in a second cross-sectional area, so that at first the first cross-sectional area fills in the direction from the inlet area toward the blind end of the blind channel and then the second cross-sectional area fills in the direction from the blind end toward the inlet area. | 2008-11-13 |
20080280366 | Quantitative Detection of Lead in Water - The present invention provides compositions and methods for extracting, isolating, and measuring lead dissolved in aqueous solutions, including water. | 2008-11-13 |
20080280367 | Modulators Of NOD2 Signalling - The present invention relates to intracellular signaling molecules, in particular the Nod2 protein and nucleic acids encoding the Nod2 protein. The present invention provides methods of identifying modulators of Nod2 signaling. In particular, the present invention additionally provides methods of screening immune modulators such as adjuvants using Nod2. The present invention further provides methods of altering Nod2 signaling. | 2008-11-13 |
20080280368 | PARASITIC HELMINTH CUTICLIN PROTEINS AND USES THEREOF - The present invention relates to: parasitic helminth cuticlin proteins; parasitic helminth cuticlin nucleic acid molecules, including those that encode such cuticlin proteins; antibodies raised against such cuticlin proteins; and compounds that inhibit parasitic helminth cuticlin activity. The present invention also includes methods to obtain such proteins, nucleic acid molecules, antibodies, and inhibitory compounds. Also included in the present invention are therapeutic compositions comprising such proteins, nucleic acid molecules, antibodies and/or inhibitory compounds as well as the use of such therapeutic compositions to protect animals from diseases caused by parasitic helminths. | 2008-11-13 |
20080280369 | COMPOSITIONS FOR DETECTION AND ANALYSIS OF POLYNUCLEOTIDES USING LIGHT HARVESTING MULTICHROMOPHORES - Methods, compositions and articles of manufacture for assaying a sample for a target polynucleotide are provided. A sample suspected of containing the target polynucleotide is contacted with a polycationic multichromophore and a sensor PNA complementary to the target polynucleotide. The sensor PNA comprises a signaling chromophore to absorb energy from the excited multichromophore and emit light in the presence of the target polynucleotide. The methods can be used in multiplex form. Kits comprising reagents for performing such methods are also provided. | 2008-11-13 |
20080280370 | METHODS AND COMPOSITIONS FOR DETECTING GLYPHOSATE AND METABOLITES THEREOF - The present invention provides various methods and compositions which allow for determining the presence or amount of glyphosate, N-acetylglyphosate, N-acetyl AMPA or aminomethyl phosphoric acid (AMPA) and its various metabolites in a variety of test matrices. In one method, determining the presence or amount of N-acetylglyphosate and/or N-acetyl AMPA in a test sample comprises providing the test sample suspected of containing N-acetylglyphosate and/or N-acetyl AMPA; extracting the N-acetylglyphosate and/or N-acetyl AMPA from the test sample; and, detecting the N-acetylglyphosate and/or N-acetyl AMPA in the extract. In other methods, the presence or amount of at least one of glyphosate, N-acetylglyphosate, N-acetyl AMPA or aminomethyl phosphonic acid (AMPA) or a metabolite thereof in a test sample is determined. The method comprises providing the test sample suspected of containing at least one of glyphosate, N-acetylglyphosate, N-acetyl AMPA or AMPA or a metabolite thereof, extracting from the test sample at least one of the glyphosate, N-acetylglyphosate, N-acetyl AMPA or AMPA; and, detecting at least one of the glyphosate, the N-acetylglyphosate, the N-acetyl AMPA and the AMPA from the test sample; wherein detection of the glyphosate, N-acetylglyphosate, N-acetyl AMPA or AMPA occurs without derivatization of the glyphosate, the N-acetylglyphosate, N-acetyl AMPA or the AMPA. | 2008-11-13 |
20080280371 | Acoustic resonance based urea quality sensor - A urea quality sensor includes an acoustic resonator in order to measure the accurate concentration of urea by measuring change in molecular weight. A change in molecular weight of urea proportionately affects the speed of sound. The change in the composition of the urea solution manifests itself as a change in frequency. The concentration of the urea solution can be determined based on the frequency data obtained as a result of the frequency measurement utilizing the acoustic wave sensor. The urea quality sensor can be used with an NH | 2008-11-13 |
20080280372 | Continuous monitor for cyanide and cyanogen blood agent detection in water - A device for continuous detection of the presence of a cyanide analyte and/or cyanogen analyte in an aqueous sample which relies upon continuous sampling and controlled delivery of reagents for a chemical reaction which forms a colored dye in the presence of the analyte(s). The device employs a single chemical detection pathway which detects both cyanide and cyanogen and demonstrates continuous user-free operational stability over at least a one month period of time. The continuous monitoring device optionally may include a command post computer interface for enabling the remote monitoring of one or more devices, a wireless communication module for providing real-time data monitoring of the devices to a central monitoring facility, and a global positioning system module to enable the determination of an exact location of the analyte contamination in a water network. A method for detecting these analytes is also provided. | 2008-11-13 |
20080280373 | Method and apparatus for measuring pH of low alkalinity solutions - Systems and methods are described for measuring pH of low alkalinity samples. The present invention provides a sensor array comprising a plurality of pH indicators, each indicator having a different indicator concentration. A calibration function is generated by applying the sensor array to a sample solution having a known pH such that pH responses from each indicator are simultaneously recorded versus indicator concentration for each indicator. Once calibrated, the sensor array is applied to low alkalinity samples having unknown pH. Results from each pH indicator are then compared to the calibration function, and fitting functions are extrapolated to obtain the actual pH of the low alkalinity sample. | 2008-11-13 |
20080280374 | METHODS AND SYSTEMS FOR DETECTING BIOLOGICAL AND CHEMICAL MATERIALS ON A SUBMICRON STRUCTURED SUBSTRATE - Methods and systems for detecting biological or biochemical analytes generally comprising, a metal film having one or more surfaces comprising one or more submicron structures; a device for applying one or more analytes to at least a portion of the film surface to interact with said metal film; a light source for illuminating a surface of the metal film so that at least some of the light is adapted to be optically altered by the functionalized metal film; and an optical detection subsystem for collecting the optically altered light, wherein the altered light is indicative of surface plasmon resonance on the film, and detecting one or more properties of the analytes based on the collected light. | 2008-11-13 |
20080280375 | Arsenic-Specific Stain for Identifying Arsenic-Treated Wood - A novel reagent is used to identify arsenic-treated wood. The stain may detect arsenic extracted from wood into solution; arsenic transferred from wood to a wipe, which is then extracted into solution; or the stain may be directly applied at a predetermined location on the wood's surface. Copper preservatives are not detected by the stain and phosphate interference is minimized. The process is quick, inexpensive, and easy to use. Development of a blue color (i.e., reduction of at least some Mo (VI) to Mo (V) in molybdenum blue) indicates the presence of arsenic. | 2008-11-13 |
20080280376 | Method of Evaluation of the Relative Risk of Developing Atherosclerosis in Patients - The present invention relates to a method for determining the amount of circulating CD36 protein or a fraction thereof which is present in cell-free plasma, preferably in a high molecular weight plasma fraction, such as a lipoprotein fraction selected from Low Density Lipoprotein, Intermediate Density Lipoprotein, and Very Low Density Lipoprotein using an immunological method which comprises the steps of (i) providing a plasma sample to be investigated, (ii) providing an anti-CD36 antibody, (iii) exposing the sample to be investigated to the antibody, and (iv) detecting and quantifying the amount of CD36 which binds to the antibody. | 2008-11-13 |
20080280377 | HUMAN B-TYPE NATRIURETIC PEPTIDE ASSAY HAVING REDUCED CROSS-REACTIVITY WITH OTHER PEPTIDE FORMS - The present disclosure provides among other things assays, methods and kits for assessing the presence or amount of human B-type natriuretic peptide in a test sample wherein the assay exhibits reduced cross-reactivity with other forms of the peptide. | 2008-11-13 |
20080280378 | Grading of Immune Responses - The invention is a method for grading a polyclonal antibody response with respect to a desired 5 binding specificity. The response is provoked by an antigenic agent in a host, preferably a vertebrate host. The characteristic feature of the method comprises the steps of: (i) providing a reaction microcavity having an inlet end and an outlet end and containing a solid phase that exposes an immobilized binding structure (BS) that are capable of affinity binding antibodies (Ab) of the response, (ii) flowing a liquid sample containing antibodies of the response in the direction from the inlet end to the outlet end through the solid phase, (iii) determining the distribution of antibodies, which are captured during step (ii), along the flow direction of the solid phase, and (iv) grading the response based on the distribution determined in step (iii). | 2008-11-13 |
20080280379 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE AND MANUFACTURING SYSTEM USING THE SAME - Provided is a method of manufacturing a thin film transistor substrate and a manufacturing system using the same, wherein the production of corrosive substances is reduced during the process of manufacturing the thin film transistor substrate. The method includes providing an etching unit with an insulation substrate on which a thin metal film has been deposited, and dry-etching the insulation substrate so as to form a predetermined circuit pattern; providing a waiting unit with the insulation substrate waiting to be cleaned; performing a preliminary cleaning operation by a cleaning unit having a plurality of nozzles while the insulation substrate waits and checking the preliminary cleaning operation; and performing a main cleaning operation with regard to the insulation substrate based on the result of the check. | 2008-11-13 |
20080280380 | Fluid Storage and Dispensing System Including Dynamic Fluid Monitoring of Fluid Storage and Dispensing Vessel - A monitoring system ( | 2008-11-13 |
20080280381 | Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key - In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key. | 2008-11-13 |
20080280382 | Wafer-level test module for testing image sensor chips, the related test method and fabrication - A wafer-level test module is disclosed to include a base layer having multiple first apertures spaced from one another at a pitch corresponding to the pitch of the image sensor chips of an integrated circuit wafer, a cover layer having second apertures respectively axially aimed at the first apertures, and an optical layer sandwiched between the base layer and the cover layer having multiple optical lenses of which the optical axes pass through the first apertures and the second apertures, so that when one image capturing device of the image sensor chips of an integrated circuit wafer is adjusted to the image plane of one of the optical lenses and the wafer-level test module is set in alignment with the integrated circuit wafer horizontally and vertically, then the effective test light can be simultaneously projected onto the image capturing devices of the respective image sensor chips through the wafer-level test module to achieve an effective wafer-level test on multiple image sensor chips of the integrated circuit wafer accurately and rapidly. | 2008-11-13 |
20080280383 | Method of real-time monitoring implantation - A method of real-time monitoring implantation includes plotting a calibration curve for monitoring implantation first. Next, a testing substrate covered a photoresist is provided and then implanted. Since photoresist surface roughness will be changed after implantation, surface roughness change could be quantitatively determined by monitoring scattering light. Finally, the detected scattering light intensity is used to calculate the corresponding implantation condition by the use of the calibration curve. | 2008-11-13 |
20080280384 | SOLID-STATE LIGHT EMITTING DISPLAY AND FABRICATION METHOD THEREOF - A solid-state light emitting display and a fabrication method thereof are proposed. The light emitting display includes a metallic board formed with conductive circuits, and a plurality of luminous microcrystals disposed on a surface of the metallic board and electrically connected to the conductive circuits. The metallic board provides the features of lightness and thinness, and flexibility, and the luminous microcrystals are in the form of light emitting components, so as to improve the luminous efficiency of display and attain the effect of environmental protection and energy saving, thereby providing display technology with performance satisfactory for various display requirements. | 2008-11-13 |
20080280385 | Thin-film transistor, TFT-array substrate, liquid-crystal display device and method of fabricating the same - A thin-film transistor includes a gate layer, a gate insulting layer, a semiconductor layer, a drain layer, a passivation layer (each of which being formed on or over an insulating substrate), and a conductive layer formed on the passivation layer. The conductive layer is connected to the gate layer or the drain layer by way of a contact hole penetrating at least the passivation layer. The passivation layer has a multiple-layer structure comprising at least a first sublayer and a second sublayer stacked, the first sublayer having a lower etch rate than that of the second sublayer. The first sublayer is disposed closer to the substrate than the second sublayer. The second sublayer has a thickness equal to or less than that of the conductive layer. The shape or configuration of the passivation layer and the underlying gate insulating layer can be well controlled in the etching process, and the conductive layer formed on the passivation layer is prevented from being divided. | 2008-11-13 |
20080280386 | METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE - A method for manufacturing an laser diode includes: providing a wafer having thereon a semiconductor structure; depositing an SiO | 2008-11-13 |
20080280387 | Layout design and fabrication of SDA micro motor for low driving voltage and high lifetime application - Provided is a new design and fabrication of scratch drive actuator (SDA) micro rotary motor with low driving voltage and high lifetime characteristics. To substantially reduce the driving voltage from 30˜150 V | 2008-11-13 |
20080280388 | CCD type solid-state imaging device and method for manufacturing the same - A CCD type solid-state imaging device is provided and includes: photodiodes (PD) in a light receiving area of a semiconductor substrate; vertical charge transfer paths; a horizontal charge transfer path; channel stops including linear high density impurity regions for separating mutually adjoining sets from each other, each set including a PD array and a vertical charge transfer path; a first light-shielding film which is stacked on the light receiving area and has openings in the respective PDs, and also to which a control pulse voltage is applied; a second light-shielding film spaced from the first light-shielding film for covering a connecting portion between the horizontal charge transfer path and light receiving area; and a contact portion of a high density impurity region for connecting the channel stops to the second light-shielding film and also for applying a reference potential to the channel stops. | 2008-11-13 |
20080280389 | CAMERA MODULE AND METHOD FOR ASSEMBLING SAME - A method for assembling a camera module includes following steps: providing a circuit board having a connecting region; disposing a liquid anisotropic conductive adhesive on the connecting region of the circuit board; placing an image sensor module, on the connecting region of the circuit board; thermal press-bonding the image sensor module onto the circuit board to fix the image sensor module with the circuit board. Because the anisotropic conductive adhesive before being disposed on the circuit board is liquid and doesn't needs to be cut, flow-shop operations are easy to achieve, and costs are decreased. | 2008-11-13 |
20080280390 | METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE HAVING SELF-ALIGNED ELECTRODE, RELATED DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME - A method of fabricating a semiconductor memory device having a self-aligned electrode is provided. An interlayer insulating layer having a contact hole is formed on a substrate. A phase change pattern partially filling the contact hole is formed. A bit line which includes a bit extension self-aligned to the phase change pattern and crosses over the interlayer insulating layer is formed. The bit extension may extend in the contact hole on the phase change pattern. The bit extension contacts the phase change pattern. | 2008-11-13 |
20080280391 | METHODS OF MANUFACTURING MOS TRANSISTORS WITH STRAINED CHANNEL REGIONS - In some methods of manufacturing transistors, a gate electrode and a gate insulation layer pattern are stacked on a substrate. Impurity regions are formed at portions of the substrate that are adjacent to the gate electrode by implanting Group III impurities into the portions of the substrate. A diffusion preventing layer is formed on the substrate and covering the gate electrode. A nitride layer is formed on the diffusion preventing layer. The substrate is thermally treated to form a strained silicon region in the substrate between the impurity regions and to activate the impurities in the impurity regions. A high performance PMOS transistor and/or CMOS transistor may thereby be manufactured on the substrate. | 2008-11-13 |
20080280392 | CONVEX DIE ATTACHMENT METHOD - A method for assembling a microelectronic device is provided comprising the step of adhering a die to a substrate using a convex die attachment process. The convex die attachment process generally comprises a) providing a die having an underfill material thereon, b) picking up and inverting the die, c) heating the underfill until it liquefies at least slightly and forms a convex surface, and d) placing the die on a substrate. | 2008-11-13 |
20080280393 | METHODS FOR FORMING PACKAGE STRUCTURES - A method for forming a semiconductor structure includes forming a first connector over at least one pad of a first substrate, the first connector having at least one curved sidewall. An encapsulation layer is formed at least partially over the first connector so as to partially expose a top surface of the first connector. A solder structure is formed, contacting the first connector. | 2008-11-13 |
20080280394 | SYSTEMS AND METHODS FOR POST-CIRCUITIZATION ASSEMBLY - A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern. | 2008-11-13 |
20080280395 | Semiconducting device with stacked dice - Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the substrate. The first die includes active circuitry (e.g., a flash memory array or logic circuitry) on an upper surface of the first die. The semiconducting device further includes a spacer that covers the active circuitry on the upper surface of the first die and a second die that is stacked onto the spacer and the first die. The spacer extends from a first side of the first die to an opposing second side of the first die. The spacer also extends near a third side of the first die and an opposing fourth side of the first die such that the active circuitry is exposed near the third and fourth sides of the first die. | 2008-11-13 |
20080280396 | STACKED DIE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE - An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed. | 2008-11-13 |
20080280397 | METHOD FOR MANUFACTURING STRIP LEVEL SUBSTRATE WITHOUT WARPAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME - A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist is performed to be removed together with a solder resist part applied on the scribe line in order to reduce an early warpage of the strip level substrate. | 2008-11-13 |
20080280398 | System And Method For Direct Bonding Of Substrates - A method of forming a MEMS (Micro-Electro-Mechanical System), includes forming an ambient port through a MEMS cap which defines a cavity containing a plurality of MEMS actuators therein; and bonding a lid arrangement to the MEMS cap to hermetically seal the ambient port. | 2008-11-13 |
20080280399 | Methods for Forming Co-Planar Wafer-Scale Chip Packages - Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position. | 2008-11-13 |
20080280400 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A field effect transistor having a T-shaped gate electrode is formed on a GaAs substrate, and the T-shaped gate electrode of the field effect transistor is coated with a SiO | 2008-11-13 |
20080280401 | INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES - A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more. | 2008-11-13 |
20080280402 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - Silicide films with high quality are formed with treatment of laser light irradiation, so that miniaturization and higher performance is achieved in a field-effect transistor that is formed over an insulating substrate and has little variation in electric characteristics. An island-shaped semiconductor film including a pair of impurity regions and a channel formation region is formed over an insulating substrate, a first metal film is formed on the pair of impurity regions, and a second metal film that functions as a reflective film is formed over a gate electrode located over the channel formation region with a gate insulating film interposed therebetween. The first metal film is irradiated with laser light and a region where the second metal film is formed reflects the laser light, so that the island-shaped semiconductor film and the first metal film selectively react with each other in the pair of impurity regions. | 2008-11-13 |
20080280403 | TRANSISTOR FABRICATION METHOD - A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed. | 2008-11-13 |
20080280404 | RESIDUE FREE PATTERNED LAYER FORMATION METHOD APPLICABLE TO CMOS STRUCTURES - A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different NFET and pFET gate electrode materials. | 2008-11-13 |
20080280405 | Semiconductor device - A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode. | 2008-11-13 |
20080280406 | Semiconductor device and its manufacturing method - A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers. | 2008-11-13 |
20080280407 | CMOS DEVICE WITH DUAL POLYCIDE GATES AND METHOD OF MANUFACTURING THE SAME - A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well and the p+ polycide gate at the N-well are formed. An interlayer dielectric layer is formed on the resultant of the silicon substrate having the n+ polycide gate and the p+ polycide gate. A first bit-line contact hole for exposing the n+ polycide gate is formed, and a second bit-line contact hole for exposing the p+ polycide gate is formed. Bit-lines with a bridge structure on the interlayer dielectric layer is formed. The bit-lines simultaneously contact the n+ polycide gate and the p+ polycide gate through the first and second bit-line contact holes. | 2008-11-13 |
20080280408 | SEMICONDUCTOR DEVICE WITH IMPROVED OVERLAY MARGIN AND METHOD OF MANUFACTURING THE SAME - Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed. | 2008-11-13 |
20080280409 | Memory Arrays, Semiconductor Constructions And Electronic Systems; And Methods Of Forming Memory Arrays, Semiconductor Constructions And Electronic Systems - Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory. | 2008-11-13 |
20080280410 | SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE - A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate. | 2008-11-13 |
20080280411 | METHOD FOR MANUFACTURING PHASE CHANGE MEMORY DEVICE USING A PATTERNING PROCESS - A phase change memory device is made by processes including forming a first interlayer dielectric on a semiconductor substrate that has junction regions. Then etching the first interlayer dielectric and thereby defining contact holes that expose the junction regions. A conductive layer is formed on the first interlayer dielectric to fill the contact holes. Forming a hard mask layer on the conductive layer and etching the hard mask layer and the conductive layer to form contact plugs in the contact holes. Finally, forming a conductive layer pattern that is located on the contact plug and portions of the first interlayer dielectric adjacent to the contact plug and having a hard mask thereon. | 2008-11-13 |
20080280412 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the inter-band scattering is prevented from causing, and since the effective electron mass is reduced due to the crystal lattice interval change, the carrier mobility in the SiC crystal is improved, the resistance of the SiC crystal is reduced and, therefore, the on-resistance of the SiC semiconductor device is reduced. | 2008-11-13 |
20080280413 | METHODS FOR FORMING A TRANSISTOR - Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon carbide material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon carbide material to form a source/drain region having a second conductivity. | 2008-11-13 |
20080280414 | Systems and Methods for Fabricating Vertical Bipolar Devices - Systems and methods for fabricating bipolar and/or biCMOS devices are described. A combination of bipolar fabrication steps and CMOS, and in particular, SOI fabrication steps may be used. In one embodiment, a collector region and/or a base region of a bipolar device may be formed using a bipolar mask, and an emitter region may be defined by a CMOS mask. | 2008-11-13 |
20080280415 | Method of manufacturing semiconductor memory device - A method of manufacturing a semiconductor memory device of the present invention consists of a step of forming a selection transistor and a separate selection transistor and a step of forming a variable resistance element and a capacitance element, characterized by forming the variable resistance element by sequentially laminating a first electrode that is connected to the selection transistor, a variable resistance layer, and a second electrode; forming the capacitance element by sequentially laminating a third electrode that is connected to the separate selection transistor, a dielectric layer, and a fourth electrode; forming the dielectric layer and the variable resistance layer with a mutually identical material; forming either one of the first electrode or the second electrode with the same material as the third electrode and the fourth electrode; and forming the other one of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode. | 2008-11-13 |
20080280416 | Techniques for Layer Transfer Processing - Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided. | 2008-11-13 |
20080280417 | Method for manufacturing semiconductor device - An object is to provide a method for manufacturing, with high yield, a semiconductor device having a crystalline semiconductor layer even if a substrate with low upper temperature limit. A groove is formed in a part of a semiconductor substrate to form a semiconductor substrate that has a projecting portion, and a bonding layer is formed to cover the projecting portion. In addition, before the bonding layer is formed, a portion of the semiconductor substrate to be the projecting portion is irradiated with accelerated ions to form a brittle layer. After the bonding layer and the supporting substrate are bonded together, heat treatment for separation of the semiconductor substrate is performed to provide a semiconductor layer over the supporting substrate. The semiconductor layer is selectively etched, and a semiconductor element is formed and a semiconductor device is manufactured. | 2008-11-13 |
20080280418 | METHOD FOR MANUFACTURING THE SHALLOW TRENCH ISOLATION STRUCTURE - A method for manufacturing a shallow trench isolation (STI) structure is provided. In the method, a substrate is initially provided. Then, a patterned pad layer and a patterned mask layer are successively formed in order on the substrate. After that, a portion of the substrate is removed by using the patterned mask layer and the patterned pad layer as a mask to form trenches in the substrate. Next, a first insulation layer is formed in the trenches. Afterwards, a protection layer is conformally formed on the substrate. Then, a second insulation layer is formed on the protection layer above the first insulation layer. Next, the patterned mask layer and the patterned pad layer are removed. Finally, a portion of the protection layer and the second insulation layer are removed. | 2008-11-13 |
20080280419 | METHOD FOR NANOSTRUCTURING OF THE SURFACE OF A SUBSTRATE - Under consideration here is a method for the production of periodic nanostructuring on one of the surfaces of a substrate ( | 2008-11-13 |
20080280420 | Method for manufacturing substrate of semiconductor device - A method for manufacturing a substrate of a semiconductor device is provided, which comprises a step of forming a fragile layer in a semiconductor substrate by irradiating the semiconductor substrate with ion species, a step of forming a bonding layer over the semiconductor substrate, a step of bonding the semiconductor substrate and a substrate having an insulating surface with the bonding layer interposed therebetween, a step of separating the semiconductor substrate with a semiconductor layer left over the substrate having the insulating surface by heating at least the semiconductor substrate, and a step of reprocessing the semiconductor substrate from which the semiconductor layer is separated. | 2008-11-13 |
20080280421 | WAFER DIVIDING METHOD - A wafer dividing method that includes a modifying layer forming step in which a laser beam with a wavelength that can pass through the wafer is focused on the inside of the wafer from a rear surface side thereof, and applied along the street to form a modifying layer having a thickness corresponding to at least a device-finishing thickness from the front surface of the wafer; a rear surface grinding step in which an area, corresponding to the device area, of the rear surface of the wafer subjected to the modifying layer forming step is ground and formed to have a thickness corresponding to the device-finishing thickness and to have an annular reinforcing section at an area corresponding to the outer circumferential redundant area; a reinforcing section cutting step in which the wafer is cut along the inner circumference of the annular reinforcing section; a wafer support step in which the rear surface of the wafer whose annular reinforcing section is cut is stuck to a dicing tape attached to an annular frame; and a wafer rupture step in which an external force is applied to the wafer stuck to the dicing tape to rupture it along the street formed with the modifying layer. | 2008-11-13 |
20080280422 | Ultra Thin Bumped Wafer with Under-Film - A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die. | 2008-11-13 |
20080280423 | CHILLED WAFER DICING - A method and system for dicing a wafer is disclosed. One illustrative method includes forming a layer of frozen material above a plurality of integrated circuit die on a substrate and performing a cutting process to cut through the layer of frozen material and the substrate to singulate the plurality of die. Another method includes performing a cutting process to singulate a plurality of integrated circuit die having a layer of frozen material formed above the plurality of die. One illustrative system comprises a substrate having a plurality of integrated circuit die, a cooled layer of material attached to the substrate and a dicing saw for singulating the plurality of die. Another illustrative system comprises a semiconducting substrate comprising a backside and a plurality of integrated circuit die, a layer of material attached to the backside of the substrate, the layer of material being at a temperature of 10° C. or less and a dicing saw for singulating the plurality of die. | 2008-11-13 |
20080280424 | Manufacturing method of SOI substrate and manufacturing method of semiconductor device - After the plurality of single-crystal semiconductor layers are provided adjacent to each other with a certain distance over a glass substrate which is a support substrate, heat treatment is performed on the glass substrate. The support substrate shrinks by this heat treatment, and the adjacent single-crystal semiconductor layers are in contact with each other due to the shrink. Energy beam irradiation is performed with the plurality of single-crystal semiconductor layers being in contact with each other, the plurality of single-crystal semiconductor layers are integrated, and thus a continuous single-crystal semiconductor layer is formed. | 2008-11-13 |
20080280425 | Beam Homogenizer, and Laser Irradiation Method, Laser Irradiation Apparatus, and Laser Annealing Method of Non-Single Crystalline Semiconductor Film Using the Same - A rectangular beam having the energy density distribution homogenized in its short-side direction is formed in a beam homogenizer wherein two light reflection surfaces are parallel-provided in a beam progression optical waveguide with a predetermined space so as to face each other at surfaces along the beam progression direction and a course change reflection surface for changing the beam progression direction is formed at a surface in the direction intersected with the light reflection surfaces. The beam enters a cylindrical lens array and a cylindrical lens sequentially to homogenize the energy density distribution in its long-side direction. Then, the irradiation laser from the cylindrical lens is projected onto a non-single crystalline semiconductor film to perform annealing. | 2008-11-13 |
20080280426 | Gallium nitride-on-silicon interface - A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al | 2008-11-13 |
20080280427 | Low etch pit density (EPD) semi-insulating GaAs wafers - A method for manufacturing wafers using a low EPD crystal growth process and a wafer annealing process is provided that results in GaAs/InGaP wafers that provide higher device yields from the wafer. | 2008-11-13 |
20080280428 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including heating a semiconductor substrate, has forming a cap film on a surface of said semiconductor substrate; selectively removing said cap film at least from an upper surface of an edge of said semiconductor substrate, a bevel surface of the edge of said semiconductor substrate and a side surface of the edge of said semiconductor substrate; selectively removing at least a device forming film formed on the upper surface of the edge of said semiconductor substrate, the bevel surface of the edge of said semiconductor substrate and the side surface of the edge of said semiconductor substrate; and heating said semiconductor substrate by irradiating said semiconductor substrate with light having a pulse width of 0.1 milliseconds to 100 milliseconds from a light source after removing said device forming film, wherein said cap film has a lower reflectance at a peak wavelength of said light than said semiconductor substrate. | 2008-11-13 |
20080280429 | Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method - A method for depositing metals on surfaces is provided which comprises (a) providing a substrate ( | 2008-11-13 |
20080280430 | METHOD OF FORMING FILMS IN A TRENCH - A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process. | 2008-11-13 |
20080280431 | METHOD OF FABRICATING FLASH MEMORY DEVICE - The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching an insulating layer for a hard mask. Spacers are formed on top surfaces and sidewalls of the plurality of first hard mask patterns. A second hard mask film is formed over a total surface including the spacers. Second hard mask patterns are formed in spaces between the spacers by performing an etch process so that a top surface of the spacers is exposed. The spacers are removed. Accordingly, gate patterns can be formed by employing hard mask patterns having a pitch of exposure equipment resolutions or less. | 2008-11-13 |
20080280432 | Barrier Material and Process for Cu Interconnect - A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods. | 2008-11-13 |
20080280433 | Method for manufacturing semiconductor device - A four-layer structured hard mask composed of a SiC film, a first SiO | 2008-11-13 |
20080280434 | Enhanced Mechanical Strength Via Contacts - The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer. | 2008-11-13 |
20080280435 | Producing a Covered Through Substrate Via Using a Temporary Cap Layer - The present invention relates to a method for producing a substrate with at least one covered via that electrically and preferably also thermally connects a first substrate side with an opposite second substrate side. The processing involves forming a trench on a the first substrate side remains and covering the trench with a permanent layer on top of a temporary, sacrificial cap-layer, which is decomposed in a thermal process step. The method of the invention provides alternative ways to remove decomposition products of the sacrificial cap-layer material without remaining traces or contamination even in the presence of the permanent layer This is, according to a first aspect of the invention, achieved by providing the substrate trench with an overcoat layer that has holes. The holes in the overcoat layer leave room for the removal of the decomposition products of the cap-layer material. According to the second aspect of the invention, opening the covered trench from the second substrate side and allowing the cap-layer material to be removed through that opening provides a solution. Both methods of the present invention are based on the common idea of using a temporary cap-layer even in a situation where the substrate opening is permanently covered before the removal of the temporary cap-layer | 2008-11-13 |
20080280436 | METHOD FOR FABRICATING AN INDUCTOR STRUCTURE OR A DUAL DAMASCENE STRUCTURE - A method for fabricating an inductor structure or a dual damascene structure is disclosed. First, a dielectric layer is provided. Subsequently, a first etching process is performed on the dielectric layer so as to form a first opening in the dielectric layer. A polymer is also formed in the first opening during the first etching process. Next, a polymer-removing step is performed to remove the polymer. Thereafter, a second etching process is performed on the dielectric layer to form a second opening in the dielectric layer. Furthermore, the first opening and the second opening are filled with a conductive material so as to form an inductor structure or a dual damascene structure. | 2008-11-13 |
20080280437 | Substrate Processing Method and Substrate Processing Apparatus - A CoWB film is formed as a cap metal on a Cu interconnection line formed on a substrate or wafer W, by repeating a plating step and a post-cleaning step a plurality of times. The plating step is arranged to apply electroless plating containing CoWB onto the Cu interconnection line. The post-cleaning step is arranged to clean the wafer W by use of a cleaning liquid, after the plating step. | 2008-11-13 |
20080280438 | METHODS FOR DEPOSITING TUNGSTEN LAYERS EMPLOYING ATOMIC LAYER DEPOSITION TECHNIQUES - In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer. In one example, the barrier layer contains titanium nitride, the first and second soak processes independently comprise at least one reducing gas selected from the group consisting of hydrogen, silane, disilane, dichlorosilane, borane, diborane, derivatives thereof and combinations thereof and the nucleation layer may be deposited by an atomic layer deposition process or a pulsed chemical vapor deposition process while the bulk layer may be deposited by a chemical vapor deposition process or a physical vapor deposition process. | 2008-11-13 |
20080280439 | OPTIMAL CONCENTRATION OF PLATINUM IN A NICKEL FILM TO FORM AND STABILIZE NICKEL MONOSILICIDE IN A MICROELECTRONIC DEVICE - A method of forming a nickel monosilicide layer on silicon-containing features of an electronic device that includes depositing a nickel film over the silicon-containing features. The nickel film is co-deposited with a selected material. The selected material has an atomic percentage in a range of about 10% to 25%. A single anneal step is then applied to the nickel film thus directly forming the nickel monosilicide layer. | 2008-11-13 |
20080280440 | METHOD FOR FORMING A PN DIODE AND METHOD OF MANUFACTURING PHASE CHANGE MEMORY DEVICE USING THE SAME - Disclosed is a method of forming a PN diode and a method of manufacturing a phase change memory device using the same. Formation of a PN diode includes forming a first conductivity type region in a surface of a semiconductor substrate. A polysilicon layer doped with second conductivity type impurities is then deposited on the semiconductor substrate formed with the first conductivity type region. Forming a plurality of second conductivity type regions by etching the polysilicon layer doped with the second conductivity type impurities completes the PN diode. Since the P-regions of a PN diode are formed through the deposition and etching of a polysilicon layer doped with second conductivity type impurities rather than an SEG process, a uniformity of resistance in the PN diode can be obtained. | 2008-11-13 |
20080280441 | Method of Forming Isolation Layer of Flash Memory Device - An embodiment of the invention relates to a method of forming an isolation layer of a flash memory device. An isolation layer is formed using a PSZ-based material and a nitride film of liner form is deposited on a trench before the PSZ film is deposited. An oxide film can be prevented from remaining on a top of the sidewalls of a conductive film for a floating gate through an etch process employing the etch rate. The thickness of a dielectric film can be prevented from increasing when a dielectric film is deposited. Accordingly, the contact area of the floating gate and the dielectric film can be increased and the coupling ratio between the floating gate and the control gate can be improved. | 2008-11-13 |
20080280442 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. A substrate includes two different regions, each of which has a different pattern density. A polish target layer is formed over the substrate to cover the patterns in the regions and a planarization guide layer is formed along a top surface of the polish target layer. The planarization guide layer has a polish selectivity ratio with respect to the polish target layer. Subsequently, the planarization guide layer formed in a first region is removed such that the planarization guide layer remains only in a second region having the patterns with low pattern density and the remaining planarization guide layer and the polish target layer are polished to remove a step between the first and second regions. | 2008-11-13 |
20080280443 | Exposure Mask And Method Of Forming A Contact Hole Of A Semiconductor Device Employing The Same - An exposure mask and a method of forming a contact hole of a semiconductor device using the same, in which micro patterns can be formed are disclosed herein. In an aspect, an exposure mask method includes a mask substrate, a light-shield pattern formed on the mask substrate, and a transparent pattern in which a plurality of patterns, which are limited to the light-shield pattern and have different short-direction widths and long-direction widths, form a group which is repeatedly arranged. Accordingly, micro photoresist patterns can be formed uniformly. | 2008-11-13 |