46th week of 2008 patent applcation highlights part 19 |
Patent application number | Title | Published |
20080278143 | Remote Display and Control for Test and Measurement Apparatus - A remote display for a test and measurement apparatus is provided including a control panel. The control panel is removable and user-replaceable with an alternate control panel. The control panel can be connected to the remote display device to control and interact with the test and measurement apparatus, and to control the display of information on the remote display device. | 2008-11-13 |
20080278144 | Monitoring Device to Provide Electrical Access in Restricted Spaces - An elongated, spring-biased, connector clip carries, at a distal end thereof, a plurality of electrical contacts. The clip can be used to access a plurality of terminals or contact points in an electrical unit which are not readily accessible. Distal ends of the clip are spring-biased to move toward one another so as to clamp the electrical terminals or contact points of interest. An open region is provided between the elongated fingers of the clip so that other electrical devices in the case can be avoided during insertion and use of the clip for diagnostic or test purposes. | 2008-11-13 |
20080278145 | Process measurement instrument adapted for wireless communication - A process measurement instrument adapted for wireless communication, comprising a measurement unit ( | 2008-11-13 |
20080278146 | GUIDE DEVICE AND TEST APPARATUS FOR ELECTRONIC DEVICES - The present invention relates to a guide device comprising a baseplate unit having formed therein a guide channel for guiding electronic devices, wherein at least two portions of the baseplate unit are spatially fixed, said guide device being characterized in that means for compensating the thermal expansion of the baseplate unit are provided. The invention additionally relates to a test apparatus which comprises the guide device according to the present invention. | 2008-11-13 |
20080278147 | EXTRA BUCKING COILS AS AN ALTERNATIVE WAY TO BALANCE INDUCTION ARRAYS - An electromagnetic logging tool is disclosed that includes a support; and at least one four-coil array disposed on the support, wherein the at least one four-coil array comprises: a transmitter, a bucking coil, a receiver, and a trim coil. A method for balancing an induction array is disclosed that includes applying an alternating current to a transmitter of the induction array that comprises the transmitter, a bucking coil and a receiver; measuring a mutual coupling between the transmitter and the receiver; and adding an extra bucking coil, if the mutual coupling exceeds a selected criterion. | 2008-11-13 |
20080278148 | Method of sensing a position of a movable component - A method of sensing a position of a movable component of an operator interface includes a step of receiving a first signal from a first Hall effect sensor and a second signal from a second Hall effect sensor. The method also includes a step of determining the position of the movable component based on the first signal and the second signal if the first and second signals represent expected values. The method includes a further step of determining the position of the movable component based on one of the first and second signals if the other of the first and second signals represents an unexpected value. | 2008-11-13 |
20080278149 | AIR-CORE TRANSFORMER POSITION SENSOR - An air-core transformer position sensor includes an excitation coil, an output coil, and a sensor coil. The excitation coil is adapted to be electrically excited with an excitation signal. The output coil is inductively coupled to the excitation coil upon electrical excitation of the excitation coil. The sensor coil is electrically shorted, is movable relative to the excitation coil and the output coil and, upon electrical excitation of the excitation coil, is inductively coupled to at least one of the excitation coil or the output coil. | 2008-11-13 |
20080278150 | ROTATION ANGLE DETECTOR - A rotation angle detector id arranged to detect a rotation angle of an object. The rotation angle detector includes a rotor rotating about a rotation axis according to a rotation of the object, a detecting unit for detecting a rotation of the rotor, a controller for detecting a rotation angle of the rotor based on a detection signal output from the detecting unit, and a case for accommodating the rotor rotatably. The case has at least three elongate holes provided therein. The elongated holes have longitudinal directions extending radially from the rotation axis of the rotor. This rotation angle detector detects the rotation angle of the object reliably with a simple structure. | 2008-11-13 |
20080278151 | SYSTEM AND METHODS FOR INSPECTING INTERNAL CRACKS - A method for inspecting an internal cavity in a part is provided. The method includes inserting a probe into the internal cavity. The method also includes controlling movement of the probe using a defined scan path to scan the probe over a region of interest in the internal cavity. The method also includes applying multiple multifrequency excitation signals to the probe to generate a number of multifrequency response signals. The multifrequency excitation signals are applied at multiple positions within the internal cavity. The method further includes performing a multifrequency phase analysis on the multifrequency response signals to inspect the internal cavity. | 2008-11-13 |
20080278152 | Disturbance Elimination System for Inductive Sensors - The invention relates to a disturbance elimination system for inductive sensors for monitoring the movement of mobile objects, including an inductive element formed by two magnetically-opposed identical half-coils (L | 2008-11-13 |
20080278153 | Systems for Measuring Magnetostriction in Magnetoresistive Elements - A system for use when measuring a magnetostriction value of a magnetoresistive element according to one embodiment includes a mechanism for applying a first magnetic field about parallel to a substrate having one or more magnetoresistive elements, and for applying a second magnetic field about perpendicular to the substrate and about parallel to magnetoresistive layers of the elements; and a mechanism for applying a mechanical stress to the substrate during application of the magnetic fields. | 2008-11-13 |
20080278154 | Device for Determining an Object, in Particular a Locating Device or Material Identification Device - The invention relates to a device for determining an object ( | 2008-11-13 |
20080278155 | System and Use Concerning Under Water Eddy Current Measurements on Components for Nuclear Reactors - The invention concerns a system suited for carrying out eddy current measurements on components for nuclear reactors when these components are located in water. The system comprises a control unit, a measurement probe and a first cable suited to constitute at least a part of the connection between the control unit and the measurement probe. The system also comprises a switching unit, suited to be located in water and arranged to be connected with said first cable, and to be connected with the measurement probe. The switching unit has a switching device which can assume at least a first and a second state. In the first state, the first cable is connected with the measurement probe. In the second state, the first cable is not connected with the measurement probe. The invention also concerns the use of the system. | 2008-11-13 |
20080278156 | Sensor Device With Generator and Sensor Current Sources - The invention relates to a magnetic sensor device ( | 2008-11-13 |
20080278157 | Eddy current probe - An eddy current probe moves along a longitudinal axis and includes a support structure defining a surface, the surface including a set of panels. Conductor coils are distributed across said surface, each panel includes at least one coil section, each coil section lies transverse to the longitudinal axis. | 2008-11-13 |
20080278158 | Sensor for Sensing a Magnetic Field Direction, Magnetic Field Direction Sensing, Method for Producing Magnetic Field Sensors, and Write-In Apparatus for Producing Magnetic Field Sensors - A sensor for sensing a magnetic field direction has a plurality of magnetoresistive sensor elements, each of which having a main sensitivity direction with respect to a present magnetic field. Lines associated with the main sensitivity directions of the magnetoresistive sensor elements and passing through the magnetoresistive sensor elements intersect in an area outside the magnetoresistive sensor elements themselves. | 2008-11-13 |
20080278159 | TURBOSPIN ECHO IMAGING SEQUENCE WITH LONG ECHO TRAINS AND OPTIMIZED T1 CONTRAST - In a method in the form of a turbo spin echo imaging sequence with long echo trains and optimized T1 contrast for generation of T1-weighted images of an examination subject by magnetic resonance, magnetization in the examination subject is excited with an RF excitation pulse, a number N of RF refocusing pulses with variable flip angle are radiated to generate multiple spin echoes for an excitation pulse, a restoration pulse chain is activated after switching of the N refocusing pulses and before the next RF excitation pulse. The restoration pulse chain influences the magnetization such that the magnetization is aligned opposite to the direction of the basic magnetic field by the restoration pulse chain before the next RF excitation pulse. | 2008-11-13 |
20080278160 | Dynamic pMRI using GRAPPA-operator - Example systems, methods, and apparatus facilitate providing a k-space line that is missing in an under-sampled time frame. The missing line is computed by applying a GRAPPA-operator to a known k-space line in the under-sampled time frame. One example method includes controlling a dynamic parallel magnetic resonance imaging (DpMRI) apparatus to acquire a first under-sampled time interleaved frame having at least one first k-space line and controlling the DpMRI apparatus to acquire a second under-sampled time interleaved frame having at least one second k-space line that neighbors the first k-space line. The method includes assembling a reference data set from the first under-sampled time frame and the second under-sampled time frame and then determining the GRAPPA-operator from neighboring k-space lines in the reference data set. | 2008-11-13 |
20080278161 | Conjugate symmetry in parallel imaging - Example systems, methods, and apparatus associated with conjugate symmetry in parallel imaging are provided. One example method includes controlling a parallel magnetic resonance imaging (pMRI) apparatus to acquire a first magnetic resonance (MR) signal from a first point in k-space using a phased array of receiving coils. The method also includes identifying a second point in k-space that is related to the first point by a conjugate symmetry relation. The relation may be, for example, a reflection, a rotation, and so on. The method also includes determining a second MR signal associated with the second point based, at least in part, on the first MR signal and the conjugate symmetry relation and then reconstructing an MR image based, at least in part, on both the first MR signal and the second MR signal. | 2008-11-13 |
20080278162 | Cartesian continuous sampling with unequal gradients - Example methods and apparatus control ratios between a maximum gradient amplitude (MGA) of a readout lobe (G | 2008-11-13 |
20080278163 | METHOD AND SYSTEM FOR MAGNETIC RESONANCE IMAGING USING LABELED CONTRAST AGENTS - A method and system for imaging using labeled contrast agents and a magnetic resonance imaging (MRI) scanner are provided. The method comprises performing a prescan at a frequency selected to be substantially similar to a frequency of the labeled contrast agent and performing an examination scan at the frequency of the labeled contrast agent substantially immediately after administering the labeled contrast agent to a subject. | 2008-11-13 |
20080278164 | NOVEL METHOD FOR SEQUENCE DETERMINATION USING NMR - The invention relates to methods for analyzing polysaccharides. In particular, compositional and sequence information about the polysaccharides are derived. Some methods use NMR in conjunction with another experimental method, such as, capillary electrophoretic techniques for the analysis. | 2008-11-13 |
20080278165 | Method and apparatus for reconstruction of an image in image space using basis functions (RIB) for partially parallel imaging - Embodiments of the invention pertain to a method and apparatus for image reconstruction for parallel Magnetic Resonance Imaging (MRI). In a specific embodiment, a method for image reconstruction in image space is provided. The method can suppress aliasing caused by undersampling when the number of sampling lines in k-space is reduced to increase the imaging speed. In an embodiment, suppressing aliasing from under-sampling can improve the quality of images reconstructed from the data acquired using a MRI coil array. In an embodiment, the method operates in image space and achieves a good resolution. In the reconstruction, the sum of square errors can be minimized within a region of interest, which can allow the image reconstruction to be optimized in a particular imaging region of interest by sacrificing the reconstruction of other regions. In a further embodiment, image reconstruction can be implemented region by region, allowing global optimization by spending a longer time in reconstruction. | 2008-11-13 |
20080278166 | Superconducting Loop, Saddle and Birdcage Mri Coils - New MRI coil and resonators are disclosed based solely on superconducting inductive element and built-in capacitive elements as well as hybrid superconducting-metal inductive and capacitive elements having superior SNR. Single and multiple small animal MRI imaging units are also disclosed including one or more resonators of this invention surrounding one or more small animal cavities. Methods for making and using the MRI coils and/or arrays are also disclosed. | 2008-11-13 |
20080278167 | RF COIL FOR IMAGING SYSTEM - An RF coil suitable for use in imaging systems is provided which coil has a dielectric filled cavity formed by a surrounding conducting enclosure, the conducting enclosure preferably being patterned to form continuous electrical paths around the cavity, each of which paths may be tuned to a selected resonant frequency. The patterning breaks up any currents inducted in the coil and shortens path lengths to permit higher frequency, and thus higher field strength operation. The invention also includes improved mechanisms for tuning the resonant frequency of the paths, for selectively detuning the paths, for applying signal to the coil, for shortening the length of the coil and for controlling the field profile of the coil and the delivery of field to the object to the image. | 2008-11-13 |
20080278168 | Transmission Line for Use in Rf Fields - An electrically conductive link (connection lead) or transmission line ( | 2008-11-13 |
20080278169 | Electromagnetic Wave Resistivity Tool Having a Tilted Antenna for Determining the Horizontal and Vertical Resistivities and Relative Dip Angle in Anisotropic Earth Formations - This invention is directed to a downhole method and apparatus for simultaneously determining the horizontal resistivity, vertical resistivity, and relative dip angle for anisotropic earth formations. The present invention accomplishes this objective by using an antenna configuration in which a transmitter antenna and a receiver antenna are oriented in non-parallel planes such that the vertical resistivity and the relative dip angle are decoupled. Preferably, either the transmitter or the receiver is mounted in a conventional orientation in a first plane that is normal to the tool axis, and the other antenna is mounted in a second plane that is not parallel to the first plane. Although this invention is primarily intended for MWD or LWD applications, this invention is also applicable to wireline and possibly other applications. | 2008-11-13 |
20080278170 | SELECTABLE TAP INDUCTION COIL - An electromagnetic logging tool includes a support configured for disposal in a well; at least one antenna mounted on the support; and a plurality of coils mounted on the support proximate the at least one antenna, wherein the plurality of the coils are configured for selective connection with the at least one antenna. A methods for balancing an induction array on an electromagnetic logging tool includes measuring a mutual coupling between a transmitter and a receiver on the electromagnetic logging tool; and selectively connecting a subset of a plurality of coils on the electromagnetic logging tool to the transmitter or the receiver based on the measured mutual coupling. | 2008-11-13 |
20080278171 | Two-Axial Pad Formation Resistivity Imager - A resistivity imaging device injects currents in two orthogonal directions using two pairs of return electrodes and performing impedance measurements of the buttons placed between the returns. | 2008-11-13 |
20080278172 | VOLTAGE SENSOR MODULE AND VOLTAGE MONITORING APPARATUS - Provided is a voltage sensor module monitoring a voltage of each of a plurality of battery cells, including: first and second terminals each receiving a voltage applied between both ends of the plurality of battery cells; third and fourth terminals each receiving a voltage applied between both ends of a battery cell to be monitored which is included in the plurality of battery cells; a first reference voltage generation circuit connected to each of the first and second terminals and generating a first reference voltage based on the voltage applied between the both ends of the plurality of battery cells; and a first comparator circuit comparing a first regulated voltage generated based on a voltage applied between the third and fourth terminals, with the first reference voltage. As a result, low voltage detection can be performed with accuracy even when an output of a battery cell decreases. | 2008-11-13 |
20080278173 | IONIZATION VACUUM GAUGE - An ionization vacuum gauge includes a linear cathode, an anode, and an ion collector. The linear cathode, the anode, and the ion collector are concentrically aligned and arranged from center to outer, in that order. The linear cathode includes a linear base and a field emission film deposited coating on the linear base. The ionization vacuum gauge with low power consumption can be used in a high vacuum system and/or some special vacuum system that is sensitive to heat and light. Such a gauge can be used to determine, simply yet accurately, pressures at relatively high vacuum levels. | 2008-11-13 |
20080278174 | Circuit and Method for Detecting a Dielectric Breakdown Fault - An improved circuit and method for detecting dielectric breakdown and ground fault conditions is provided. The circuitry and method of the present invention include taking a continuous voltage reading of the high voltage battery and sampling the continuous voltage reading of the high voltage battery at a fixed time interval. The circuitry and method calculate a change in the continuous voltage reading of the high voltage battery over the change in time and repeatedly calculate an optimum fixed time interval and an optimum change in voltage over time. Storage of the optimum fixed time interval and optimum change in voltage over time provides for repeatedly comparing the optimum change in voltage over the fixed time interval to the constant voltage of the high voltage battery to calculate the resistance of the dielectric breakdown fault. The calculation of the resistance of the dielectric breakdown fault is carried out independently of the capacitance of the electric circuit. The circuit and method provide adjustment of the optimum fixed time interval to improve the speed of the comparison of the optimum change in voltage over time to the constant voltage of the high voltage battery to calculate the resistance of the dielectric breakdown fault. | 2008-11-13 |
20080278175 | SYSTEMS AND APPARATUS FOR MONITORING INTERNAL TEMPERATURE OF A GRADIENT COIL - Systems, methods and apparatus are provided through which in some embodiments a thermal sensor of a magnetic coil of a magnetic resonance imaging system (MRI) is positioned, placed and/or mounted externally to the magnetic coil. The external placement of the thermal sensor does not require replacement of the entire magnetic coil, yielding less expensive replacement of a failed thermal sensor. | 2008-11-13 |
20080278176 | CALIBRATED S-PARAMETER MEASUREMENTS OF A HIGH IMPEDANCE PROBE - A new methodology for the measurement of the S-parameters of a high impedance probe allows obtaining a full two port S-parameter set for the high impedance probe. The measured probe S-parameters are then used for characterization of probes. An alternative method characterizes half of the fixture and termination as a one-port network and expanding it into a two-port error box. The two-port error box is then cascaded with the probe input. | 2008-11-13 |
20080278177 | Method for Direct Measurement of the Mixed-Mode Scattering Matrix With a Vectorial Network Analyser - In a method for the excitation of port groups of a multi-port device under test with coherent incident waves of the same frequency, which provide defined amplitude ratios and phase differences within each port group, the waves are generated respectively by one signal generator of a vectorial network analyzer per test port. The network analyzer has unbalanced test ports. A system-error correction of the unbalanced incident and reflected waves with reference to the ports of the device under test is implemented in order to obtain corrected waves. The amplitude and phase changes required in the signal generators to fulfil the desired amplitude and phase conditions are calculated from these corrected waves. | 2008-11-13 |
20080278178 | Capacative Position Sensor - A sensor for determining a position for an adjacent object in two dimensions is described. The sensor comprises a substrate with a sensitive area defined by a pattern of electrodes, wherein the pattern of electrodes includes a first group of drive elements interconnected to form a plurality of row electrodes extending along a first direction, a second group of drive elements interconnected to form a plurality of column electrodes extending along a second direction, and a group of sense elements interconnected to form a sense electrode extending along both the first and second directions. The sensor further comprises a controller comprising a drive unit for applying drive signals to the row and column electrodes, and a sense unit for measuring sense signals representing a degree of coupling of the drive signals applied to the row and column electrodes to the sense electrode. Thus a 2D position sensor requiring only a single sense channel is provided. | 2008-11-13 |
20080278179 | Method and measurement apparatus for determining the transition impedance between two parts of a subdivided neutral electrode - A method and a measurement apparatus are provided for determining the transition impedance between two electrode parts of a subdivided neutral electrode used in high-frequency surgery. These makes it possible for the purely capacitive component of the transition impedance to be measured. For this purpose a resonant-frequency shift is measured, which occurs when a basic resonant circuit is expanded to an expanded resonant circuit by incorporating the two electrode parts into it in parallel. In particular, in order to determine the basic resonant frequency of the basic resonant circuit and/or the sample resonant frequency of the expanded resonant circuit, the phase shift between current and voltage is measured and the frequency is adjusted until current and voltage are in phase. | 2008-11-13 |
20080278180 | Systems, Methods, and Apparatus for Measuring Capacitance in a Stator Component - Embodiments of the invention can provide systems, methods, and apparatus for providing a capacitance paddle for measuring capacitance in a stator component such as a stator bar. In one embodiment, a system for measuring capacitance can include an output device operable to measure capacitance in an object. Furthermore, the system can include at least three contacts operable to mount to the object to be sensed. In addition, the system can include at least one conductive material operable to mount to the object to be sensed. Moreover, the system can include a compressible material adjacent to at least some of the at least three contacts and the at least one conductive material, wherein the compressible material can be compressed to permit the contacts to simultaneously contact the object to be sensed, and wherein the output device can output a measure of capacitance associated with the object. | 2008-11-13 |
20080278181 | OXIDATION-RESISTANT, LIGAND-CAPPED COPPER NANOPARTICLES AND METHODS FOR FABRICATING THEM - The present invention is directed toward oxidation-resistant, ligand-capped nanoparticles, each comprising one or more capping ligands on a copper-containing core. Methods of making and using these nanoparticles are also disclosed. | 2008-11-13 |
20080278182 | Test Structure for Statistical Characterization of Metal and Contact/Via Resistances - A test structure for measuring resistances of a large number of interconnect elements such as metal, contacts and vias includes an array of test cells in rows and columns. Power is selectively supplied to test cells in a given column while current is selectively steered from test cells in a given row. A first voltage near the power input node of a device under test (DUT) is selectively sensed, and a second voltage near the current measurement tap is selectively sensed. The resistance of the DUT is the difference of the first and second voltages divided by the current. Additional voltage taps are provided for test cells having multiple resistive elements. This array of test cells can be used to characterize the statistical distribution of resistance variation and to identify physical location of defects in resistive elements. | 2008-11-13 |
20080278183 | FUEL CELL TEST SYSTEM - A fuel cell test system including a controller, a housing defining a test chamber, a test subject fuel cell positioned in the test chamber, the test subject fuel cell being in communication with the controller to provide the controller with signals indicative of a performance of the test subject fuel cell, a fuel feed in communication with the test subject fuel cell, the fuel feed having a humidity, a flow rate and a pressure, wherein at least one of the humidity, the flow rate and the pressure of the fuel feed is controllable by the controller, and an oxidant feed in communication with the test subject fuel cell, the oxidant feed having a humidity, a flow rate and a pressure, wherein at least one of the humidity, the flow rate and the pressure of the oxidant feed is controllable by the controller, wherein the controller monitors the performance of the test subject fuel cell in response to the fuel feed and the oxidant feed. | 2008-11-13 |
20080278184 | Grid Sensor - The invention relates to a grid sensor, including grids of electrode wires, for measuring the electroconductivity of a flow medium in the cross-section of a pipeline. The invention can be especially applied where the flow medium flows at a high pressure and at high temperatures. According to the invention, each electrode wire is mechanically connected to a spring on one side by means of an insulating bead, the spring being arranged in a hole in the sensor body having an axis which is oriented in the tensioning direction of the wire, and fixed to the sensor body in this position. Each electrode wire on the side opposing the spring is covered with an insulating tube arranged in an outwardly guided channel in the sensor body. The insulating tube ends inside the channel, in a cavity filled with a sealing material. Neither the insulating bead nor the insulating tube are located in the cross-section wherein the measurement is to be carried out. | 2008-11-13 |
20080278185 | ELECTRICAL CONTACT DEVICE AND ITS MANUFACTURING PROCESS - A method of making an electrical contact device includes the step of (a) preparing a substrate, (b) forming a dielectric layer on a surface of the substrate and forming a well on the dielectric layer by means of a non-etching technique, (c) forming a first sacrifice layer in the well, (d) forming a second sacrifice layer on the dielectric layer and the first sacrifice layer and defining a probe body contour and forming a probe body metal layer in the probe body contour and then repeating this step once or several times to form a probe structure, and (e) removing the sacrifice layers to obtain the desired electrical contact device having the substrate and the probe structure. | 2008-11-13 |
20080278186 | PIPELINE TEST APPARATUS AND METHOD - A pipeline test apparatus is provided. The pipeline test apparatus includes a test board. A plurality of stages of sockets are installed on the test board. Each socket is configured to be connected to a device under test (DUT). The sockets of each stage are connected to one of a plurality of different testing devices. Each testing device is configured to perform a unique test on all the DUTs of a corresponding stage. | 2008-11-13 |
20080278187 | Test pin, method of manufacturing same, and system containing same - A test pin includes a compression element ( | 2008-11-13 |
20080278188 | PROBE CARD AND METHOD FOR FABRICATING THE SAME - A probe card for testing semiconductor chips on a semiconductor wafer, includes a circuit board receiving electrical signals from outside, a plurality of unit probe modules contacting the semiconductor chips on the wafer to transfer the electrical signals, a space transformer having the plurality of probe modules seated on the upper portion thereof and electrically connected to the circuit board, wherein the respective probe modules are arranged at intervals from each other on the space transformer and the space transformer has vertical apertures penetrating through it up and down, and at least one vertical conductive medium electrically connecting the respective unit probe modules and the circuit board, wherein the vertical conductive medium is arranged in the vertical apertures provided in the space transformer and the respective unit probe modules are arranged at positions spaced from the vertical conductive medium. | 2008-11-13 |
20080278189 | TEST CIRCUIT FOR PERFORMING MULTIPLE TEST MODES - A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse. | 2008-11-13 |
20080278190 | Testing fuse configurations in semiconductor devices - Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal. | 2008-11-13 |
20080278191 | Leakage Power Management with NDR Isolation Devices - A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current. | 2008-11-13 |
20080278192 | DATA OUTPUT DRIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS - A data output driving circuit for a semiconductor apparatus includes a code converter that varies an input on-die termination code according to a control signal and outputs the code, and a driver block having impedance which can be modified according to the code generated by the code converter. | 2008-11-13 |
20080278193 | Reference voltage generators for reducing and/or eliminating termination mismatch - A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator. | 2008-11-13 |
20080278194 | Semiconductor integrated circuit and operation method of the same - A semiconductor integrated circuit including on the same semiconductor substrate: a first circuit block including a switching transistor which is off when the first circuit block is inactive and on when the first circuit block is active, the first circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a first power line maintained at a low-level source voltage; a second circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a second power line maintained at a low-level source voltage; a power line switch section connected between the first and second power lines; and a control circuit adapted to control the power line switch section so that the first and second power lines are connected together at a later timing or gradually over a longer period of time than the switching transistor turns on. | 2008-11-13 |
20080278195 | STRUCTURE FOR EXECUTING SOFTWARE WITHIN REAL-TIME HARDWARE CONSTRAINTS USING FUNCTIONALLY PROGRAMMABLE BRANCH TABLE - A computer system is disclosed which includes a design structure including a CPU or microprocessor to drive tightly constrained hardware events. The system comprises a processor having a set of system inputs to drive a functionally programmable event, and a fast branch in the CPU including a state handler to execute instructions from the CPU to process the event. A queue in the CPU stores the events such that the non-pre-empted events are serviced in the order they are received. | 2008-11-13 |
20080278196 | LOGIC CIRCUITS HAVING DYNAMICALLY CONFIGURABLE LOGIC GATE ARRAYS - A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates. | 2008-11-13 |
20080278197 | PROGRAMMABLE LOGIC DEVICE WITH EMBEDDED SWITCH FABRIC - The invention in the simplest form is a programmable logic device consisting of gate arrays, external I/O endpoints, and an embedded switch fabric configurable for connecting gates to gates, endpoints to endpoints and gates to endpoints. The architecture may employ a fabric interface of non-blocking crossbar switches for making complex bus connections of multiple devices to facilitate high speed processing. | 2008-11-13 |
20080278198 | Buffer for Object Information - A buffer that is state-aware and/or node-oriented. In a state-aware buffer, one or more operations relating to a state can be performed. In a node-oriented buffer, instances of a node can be accessed without regard to an object structure in which the instance is included. | 2008-11-13 |
20080278199 | OFF-CHIP DRIVER - A driver includes a plurality of first PMOS transistors, a first resistor, a amplifier, a second PMOS transistor and a second resistor. The amplifier herein receives a reference voltage and outputs a regulating voltage. The above-mentioned reference voltage is produced in accordance with a band-gap reference voltage. Since the band-gap reference voltage is unlikely affected by a process variation, thus, the present invention is capable of providing an output current robust from process characteristic and the output current is more reliable to indicate a data signal. | 2008-11-13 |
20080278200 | Current Weighted Voltage Interpolation Buffer - A voltage interpolation buffer for interpolating voltages by adjusting ratio of bias currents includes a first difference voltage to current unit for outputting corresponding difference current according to a first voltage, a first bias current and voltage of a voltage output end, a second difference voltage to current unit for outputting corresponding difference current according to a second voltage, a second bias current and the voltage of the voltage output end, and a current to voltage unit coupled to the first difference voltage to current unit, the second difference voltage to current unit and the voltage output end for outputting a interpolation result of the first voltage and the second voltage corresponding to a ratio of the first bias current and the second bias current according to the difference currents outputted by the first difference voltage to current unit and the second difference voltage to current unit. | 2008-11-13 |
20080278201 | Buffering circuit of semiconductor device - A buffering circuit of a semiconductor device includes: a first buffer configured to receive a first power voltage and a second power voltage as driving power voltages to buffer an input signal; a power supplier configured to adjust supply amounts of the first and second power voltages in response to a plurality of driving power signals to supply first and second driving power voltages; and a second buffer configured to receive the first and second driving power voltages, and to buffer an output signal of the first buffer. | 2008-11-13 |
20080278202 | Capacitive load driving device - An improved capacitive load driving device that provides increased signal voltage gain, over-voltage, over-current, and over-temperature protections, over-modulation prevention, output level control, minimized harmonic generation, and compensation for propagation medium distortion. The device includes driver/amplifier circuitry, protection circuitry, and an output stage. The driver/amplifier circuitry simultaneously modulates and discretizes an analog input signal by comparing it with a specified digitally-synthesized modulation waveform, which is a repeating series of approximately parabolic waveforms. The resulting PWM waveform is processed to generate a discrete low-harmonic sine wave approximation used to produce gate drive signals for the output stage. The protection circuitry monitors the device for fault conditions, and, in the event a fault condition is detected, controls startup and automatic shutdown. The output stage includes an H-bridge that drives an impedance-matching transformer feeding an inductor. When the device is used to drive a capacitive transducer, the impedance-matching transformer, the inductor, and the transducer form a series-resonant circuit for boosting the signal voltage gain, reducing power consumption, and filtering higher harmonics. | 2008-11-13 |
20080278203 | SYSTEMS AND METHODS FOR PROVIDING A CLOCK SIGNAL - Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled. | 2008-11-13 |
20080278204 | INJECTION-LOCKED FREQUENCY DIVIDER EMBEDDED AN ACTIVE INDUCTOR - An injection-locked frequency divider is provided. The present invention includes an active inductor unit, a source injection unit, a first transistor and a second transistor. A first terminal of the active inductor unit is coupled to a first voltage. A first terminal of the source injection unit receives a signal source. A second terminal and a third terminal of the source injection unit are respectively coupled to a second terminal and a third terminal of the active inductor unit. A first terminal, a gate terminal and a second terminal of the first transistor are respectively coupled to the second terminal and the third terminal of the source injection unit and a second voltage. A first terminal, a gate terminal and a second terminal of the second transistor are respectively coupled to the third terminal and a second terminal of the source injection unit and the second voltage. | 2008-11-13 |
20080278205 | Programmable clock control architecture for at-speed testing - According to one exemplary embodiment, an N-stage programmable clock control architecture includes N flip-flops, where the N flip-flops are clocked by a primary clock source, such as a PLL. The N-stage programmable clock control architecture further includes means for programming the N flip-flops such that the N-stage programmable clock control architecture outputs N programmed at-speed clock pulses. For example, when N is equal to 3, three programmed clock pulses can be outputted by the N-stage programmable clock control architecture, with a total of eight different patterns of programmed clock pulses. The N-stage programmable clock control architecture can thus adequately test, for example, combinational logic requiring greater than two consecutive clock pulses for complete at-speed testing. In one embodiment, scan-shift registers can be utilized to program the N flip-flops. In another embodiment, a look-up table can be used to program the N flip-flops. | 2008-11-13 |
20080278206 | DLL CIRCUIT - A DLL circuit can enable a semiconductor integrated circuit to perform a stable data processing operation. The DLL circuit includes a phase splitter that controls the phase of a delay clock, thereby generating a rising clock and a falling clock, an amplifying unit that performs differential amplification on the rising clock and the falling clock in response to first and second duty control signals, thereby generating an amplified rising clock and an amplified falling clock, and a duty cycle control unit that detects the duty rates of the amplified rising clock and the amplified falling clock, thereby generating the first and second duty control signals. | 2008-11-13 |
20080278207 | FALL TIME ACCELERATOR CIRCUIT - Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus. | 2008-11-13 |
20080278208 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data output circuit includes a data output clock signal generating unit that generates a rising data output clock signal and a rising latch signal from a rising clock signal in response to a falling latch signal, and generates a falling data output clock signal and the falling latch signal from a falling clock signal in response to the rising latch signal; and a data output pre-driver that drives a rising data in response to the rising data output clock signal, and drives a falling data in response to the falling data output clock signal. | 2008-11-13 |
20080278209 | METHOD OF PULSE WIDTH MODULATION SIGNAL PROCESSING AND DEVICE INCLUDING SIGNAL PROCESSING FOR PULSE WIDTH MODULATION - A method and system process a signal for PWM modulation. An amplitude control signal adjusts the amplitude of an input signal, and an offset is added to the amplitude-adjusted signal to produce an offset-adjusted signal. The offset is selected according to the amplitude adjustment applied to the input signal. The offset-adjusted signal is pulse-width modulated the to produce a pulse-width modulated signal, and the pulse-width modulated signal is filtered to reduce high frequency components thereof. | 2008-11-13 |
20080278210 | SYSTEM FOR GLITCH-FREE DELAY UPDATES OF A STANDARD CELL-BASED PROGRAMMABLE DELAY - A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals. | 2008-11-13 |
20080278211 | USE OF MULTIPLE VOLTAGE CONTROLLED DELAY LINES FOR PRECISE ALIGNMENT AND DUTY CYCLE CONTROL OF THE DATA OUTPUT OF A DDR MEMORY DEVICE - A DLL circuit uses a rising edge DLL to align the rising edge of the output data to the system clock and a falling edge DLL to align the falling edge of the output data. The DLL circuit does not use the falling edge of the input clock to provide a reference for the falling edge DLL. The DLL circuit uses the rising edge of a first reference clock (a buffered version of the input clock) to align the rising edge of the output data. An additional DLL is used to generate a precise second reference clock that is delayed by exactly one-half period of the first reference clock to align the falling edge of the output data. Any variation in the duty cycle of the input clock or the input clock buffer does not effect the duty cycle of the output data. | 2008-11-13 |
20080278212 | DC OFFSET CANCELING CIRCUIT - The present invention provides a circuit for canceling DC offset, comprising: a first circuit accumulating a first square value of a plurality of signal values in a time period; a second circuit calculation a second square value of an accumulation of said signal values in said time period, wherein said square value is divided by a quantity of said signal values in said time period to generate a DC offset value; and a third circuit, connected to said first circuit and second circuit, calculating a difference between said first square value and said DC offset value. | 2008-11-13 |
20080278213 | HIGH OHMIC INTEGRATED RESISTOR WITH IMPROVED LINEARITY - An integrated circuit that includes a resistor module with improved linearity is disclosed. The resistor module includes a diffused resistor body of a first conductivity type; a first terminal and a second terminal, each making direct electrical contact with the diffused resistor body; a doped well of a second conductivity type substantially surrounding the diffused resistor body on all but one major surface of the diffused resistor body, the doped well having contact regions; a first amplifier connected to the first terminal and to one contact region of the doped well; and a second amplifier connected to the second terminal and to another contact region of the well, such that the first amplifier and the second amplifier are connected for power supply only to the first terminal and second terminal, respectively. The first and second amplifiers may be unity gain buffer amplifiers or inverting opamps. | 2008-11-13 |
20080278214 | Method for removing noise, switching circuit for performing the same and display device having the switching circuit - A method for removing noise of a gate signal that is outputted from a gate driving circuit including a plurality of stages, the method includes electrically connecting two terminals of two adjacent stages that have noise components opposite in phase to each other during a first period, and electrically disconnecting the two terminals of the two adjacent stages that have the noise components opposite in phase to each other during a second period. | 2008-11-13 |
20080278215 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention is a semiconductor device for driving and controlling a power device in the high-potential side of two power devices connected in series between a main power source potential of a high potential and a main power source potential of a low potential, and is equipped with a pulse generating circuit for generating first and second pulse signals corresponding to the level transition to first and second states of input signals having a first state showing the conduction of the power device in the high-potential side and a second state showing the non-conduction of the power device in the high-potential side, respectively; a level shift circuit for obtaining first and second level-shifted pulse signals by level-shifting the first and second pulse signals to the high-potential side; an SR-type flip-flop circuit inputting the first level-shifted pulse signals from set input terminal and the second level-shifted pulse signals from reset input terminal; and a delay circuit for delaying the output of the SR-type flip-flop circuit by at least the pulse width of the first and second pulse signals. | 2008-11-13 |
20080278216 | Modular Switching Arrangement - The present invention relates to a switching arrangement and method of manufacturing such an arrangement, wherein first and second series-shunt diode structures (D | 2008-11-13 |
20080278217 | PROTECTION FOR CIRCUIT BOARDS - A system comprising a circuit board and an integrated circuit device mounted on the circuit board by means of an external contact, and comprising an anti-tamper device being connectable to the external contact to switch the integrated circuit device into a safe mode upon application of a predetermined electrical state at the external contact is described. | 2008-11-13 |
20080278218 | Operator interface assembly including a Hall effect element and machine using same - A machine having an operator interface for requesting an action from an actuator of the machine includes a movable component of the operator interface. The movable component is movable among at least two positions. One of a magnet and a Hall effect sensor is positioned to move in response to movement of the movable component. The other of the magnet and the Hall effect sensor has a stationary position relative to the movable component. A pulse width modulator is operably coupled to the Hall effect sensor for producing a first pulse width modulated signal. The first pulse width modulated signal is altered in response to movement of one of the Hall effect sensor and the magnet relative to the other. An electronic controller is in communication with the pulse width modulator and the actuator and is configured to actuate the actuator in response to evaluation of the first pulse width modulated signal. | 2008-11-13 |
20080278219 | BIAS SWITCHING CIRCUIT - An embodiment of a bias switching circuit may include a first transfer switch that transmits a bias voltage to a first output node in response to a first switching signal, a second transfer switch that transmits a first power voltage to the first output node in response to a second switching signal, a third transfer switch that transmits the bias voltage to a second output node in response to the second switching signal, a fourth transfer switch that transmits the first power voltage to the second output node in response to the first switching signal. The circuit may further include a first transistor that transmits a second power voltage to the first output node in response to a third switching signal, and a second transistor that transmits the second power voltage to the second output node in response to a fourth switching signal. | 2008-11-13 |
20080278220 | HIGH-LINEARITY LOW NOISE AMPLIFIER AND METHOD - Embodiments of a high-linearity low-noise amplifier (LNA) and method are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier and a common-gate stage. The common-gate stage is dynamically biased based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage. | 2008-11-13 |
20080278221 | POWER DISTRIBUTION CIRCUIT FOR USE IN A PORTABLE TELECOMMUNICATIONS DEVICE - A power distribution circuit for use in a personal telecommunications device comprises a switched mode power supply configured to convert an input voltage and current from an energy source into an output voltage and current, a plurality of series-connected charge storage components arranged to be charged by the output voltage and a charge balancing circuit configured to substantially equalise voltages across each of the charge storage components, wherein the charge balancing circuit comprises a charge pump. | 2008-11-13 |
20080278222 | CHARGE PUMP CIRCUIT - A latch-type charge pump circuit is provided having first and second charge pump stages interconnected by an intermediate circuit node. The charge pump circuit includes first pump capacitors respectively coupled between first and second enable terminals and respective first inner circuit nodes, second pump capacitors respectively coupled between the second and first enable terminals and respective second inner circuit nodes, latch transistors coupled between each of the first and second inner circuit nodes and the intermediate circuit node, and a stabilization circuit having at least one stabilization stage coupled between the intermediate circuit node and the first and second enable terminals and connected to control terminals of the latch transistors for supplying them with suitable control signals so as to ensure their correct turn-on and turn-off during a charge sharing period of the charge pump circuit. | 2008-11-13 |
20080278223 | APPARATUS AND METHOD FOR CONTROLLING THE PROPAGATION DELAY OF A CIRCUIT BY CONTROLLING THE VOLTAGE APPLIED TO THE CIRCUIT - The voltage applied to an integrated circuit is controlled by a temporal process monitor formed as part of the integrated circuit. The temporal process monitor includes a voltage controlled oscillator for producing a first output signal having a first period. A comparator compares the first period to one or more reference values. Should the first period be greater than a first selected reference value the comparator sends a signal to increase the voltage being supplied to the integrated circuit. Should the first period be less than a second selected reference value, the comparator sends a signal to decrease the voltage applied to the integrated circuit. In some embodiments a scaling circuit is provided for producing a second output signal having a second period different from (typically but not necessarily longer than) the first period. By placing the temporal process monitor on an integrated circuit chip, process variations and environmental factors which affect the performance of the integrated circuit can be automatically compensated so that the integrated circuit performs within specifications. Two or more temporal process monitors can be placed on a single integrated circuit chip or on different integrated circuit chips and the longest period produced by the temporal process monitors can be used to control the voltage supplied to all the sections of the integrated circuit chip associated with the temporal process monitors or to all the integrated circuit chips associated with the temporal process monitors. In some embodiments voltages related to the frequency of a temporal process monitor signal and the frequency of a fixed frequency clock are provided to an error amplifier, which changes the voltage applied to the integrated circuit such that the two frequencies are the same. | 2008-11-13 |
20080278224 | Apparatus and method for recovery of wasted power from differential drivers - An apparatus and method for supplying power to circuits of an integrated circuit (IC) from the wasted power in low-swing high-speed differential line drivers used in the IC, is disclosed. In a high speed line driver the load resistors of the driver are connected to a power supply, either the local power supply or the receiver power supply. DC power for the driver is supplied through these resistors. A large portion of this power, supplied from the power supply is wasted in the DC set-up circuit of the differential line driver. It is proposed to use this wasted power to power selected circuits of an IC. The use of this wasted power from the drivers for powering the circuits reduces the overall power dissipation of the system. | 2008-11-13 |
20080278225 | METHOD AND APPARATUS FOR REGULATING POWER IN A FLYBACK CONVERTER - An integrated circuit includes an operational amplifier configured to receive a current sense voltage (V | 2008-11-13 |
20080278226 | METHOD AND APPARATUS FOR POWERING DOWN ANALOG INTEGRATED CIRCUITS - A method and an apparatus powers down an analog integrated circuit. A power down circuit is electrically coupled to the analog circuit and is adapted to power down the analog circuit in response to receiving a power down signal. A node protection circuit is electrically coupled to the analog circuit and is adapted to provide a predetermined voltage potential to at least one predetermined node in the analog circuit in response to receiving the power down signal when a voltage potential at the at least one predetermined node is not determined by the power down circuit. | 2008-11-13 |
20080278227 | SQUELCH DETECTION SYSTEM FOR HIGH SPEED DATA LINKS - An apparatus comprising a first comparator circuit, a second comparator circuit, a third comparator circuit, and a difference circuit. The first comparator circuit may be configured to generate a first intermediate current in response to a first input voltage and a second input voltage. The second comparator circuit may be configured to generate a second intermediate current in response to the first input voltage and the second input voltage. The third comparator circuit may be configured to generate an intermediate reference current in response to a first reference voltage and a second reference voltage. The difference circuit may be configured to generate a first compare voltage and a second compare voltage in response to the first intermediate current, the second intermediate current, and the intermediate reference current. The apparatus may indicate a squelch condition when the first compare voltage is greater than the second compare voltage. | 2008-11-13 |
20080278228 | CONTROL DEVICE WITH A SWITCHABLE BANDWIDTH - A control device with a switchable bandwidth including: an integrating element with a first capacitance, which is charged and discharged by at least one current; at least one second capacitance, which can be connected in parallel with the first capacitance via a first switch; and at least one voltage follower, via which the voltage present at the first capacitance can be fed to the second capacitance. In this case, the first switch is open if the voltage present at the first capacitance is fed to the second capacitance by means of the voltage follower. The first switch is closed if the second capacitance is connected in parallel with the first capacitance. The invention enables a further capacitance to be supplementarily connected without a disturbance signal arising. | 2008-11-13 |
20080278229 | Active Compensation Filter - An active compensation filter for the application in the electric power supply in a land vehicle, which comprises a high-pass filter which is to be coupled with a supply voltage line which carries a supply voltage, in order to detect frequency and amplitude of interference voltage components of the supply voltage. A signal amplifier which is connected in series with the high-pass filter amplifies the detected interference voltage components and supplies them to a coupling element as output signals, which is connected in series with the signal amplifier and comprises a primary side and a secondary side. The primary side is fed with the output signals of the signal amplifier and the secondary side is looped into the supply voltage line. | 2008-11-13 |
20080278230 | Systems and Methods for Correcting Errors Resulting from Component Mismatch in a Feedback Path - Systems and methods for minimizing performance degradation due to component mismatch in the feedback path of a digital PWM amplifier feedback loop. One embodiment comprises a digital pulse width modulated (PWM) amplifier with feedback. The amplification subsystem receives a digital audio signal and produces an analog output signal. The feedback loop produces a feedback signal based on the filtered analog output signal and modifies the digital audio signal based on the feedback signal. The feedback loop includes a filter configured to filter the analog output signal and correction circuitry configured to correct component mismatch errors introduced by the filter. In one embodiment, the correction circuitry receives a measurement of a power supply voltage, multiplies the measured voltage by a gain and adds the scaled measurement to the feedback signal to correct for the component mismatch errors. | 2008-11-13 |
20080278231 | AMPLIFIER - An object of the present invention is, in a high-frequency amplifier using a semiconductor device as an amplifying device, to achieve a high efficiency by controlling input/output matching circuits so that they are always optimized, when a bias voltage applied to the semiconductor device is controlled to correspond to an envelope of a signal. The bias voltage that is applied to the semiconductor device for amplification is changed to corresponding to the envelope of the signal using a bias control circuit, control voltages for controlling impedance of input/output matching circuits are created from the bias voltage, and the bias voltage and the control voltages that are used to control the impedance of the input/output matching circuits of semiconductor device | 2008-11-13 |
20080278232 | Operational Amplifier with Rail-to-Rail Common-mode Input and Output Range - An operational amplifier with a rail-to-rail common-mode input and output range comprises a differential input stage consisting of a first differential pair and a second differential pair for receiving an input signal; a summing circuit coupled to the differential input stage for outputting a summation result of the output signals of the first differential pair and second differential pair; and a push-pull output stage coupled to the summing circuit for outputting an amplified signal comprising an output terminal for outputting the amplified signal, a source coupled transistors for generating a control voltage according to output current of the summing circuit, and a first output transistor and a second output transistor for controlling current of the first output transistor and the second output transistor according to the control voltage of the source coupled transistor. | 2008-11-13 |
20080278233 | BUFFER DRIVE - The present invention relates to a CMOS buffer circuit for liquid crystal display (LCD) drivers, which includes a single stage operational transconductance amplifier (OTA) with a differential of transistors for receiving a differential input voltage, a bias current source coupled to the differential pair and a single-ended output, the first bias current generating stage with a differential pair of transistors coupled to receive the differential input voltage to produce an output current in an output current path in response to a positive differential input voltage, a second bias current generating stage with a differential pair of transistors coupled to receive the inverted differential input voltage to produce an output current in an output current path in response to a negative input voltage, wherein the output current paths of both bias current generating stages are combined in a common current path and the current in the common current path is mirrored to the bias current source of the single stage OTA, so as to increase the bias current through the bias current source in response to an increasing magnitude of the differential input voltage. | 2008-11-13 |
20080278234 | Output stage - An output stage, comprising a first transistor operable to pull a voltage at an output node towards a first voltage, and a rechargeable energy store having a potential difference between first and second terminals wherein the rechargeable energy store is arranged to be controllably connected between the output node and a second voltage supply such that the voltage at the output node can be driven to a voltage outside of a range defined between the first and second voltages. | 2008-11-13 |
20080278235 | METHOD AND APPARATUS FOR PROTECTING DEVICES IN AN RF POWER AMPLIFIER - A method and apparatus are provided for use with a power amplifier for protecting active devices on the power amplifier. A peak detector is used by control circuitry to detect the presence of a peak voltage that exceeds a threshold voltage. In response to the detection of a peak voltage, the gain of the power amplifier is reduced. | 2008-11-13 |
20080278236 | Rf Power Amplifiers - A Solid State Power Amplifier (SSPA) for powering a single element of a multi-element antenna, the SSPA comprising: | 2008-11-13 |
20080278237 | Techniques to reduce the power consumption of an RF log-amp detector - An embodiment of the present invention provides an RF log-amp detector, comprising a pre-amplifer at the input of the RF log-amp detector, a plurality of limiters with variable gain connected to the pre-amplifier, wherein the gain of the preamplifier is set to its minimum and the dynamic range is expanded by modifying the amplification gain of the plurality of limiters, thereby increasing the dynamic range and reducing accuracy, after which a coarse measurement of a power level is taken and wherein the RF log-amp detector then defines which pre-amplification level is required based on the course measurement to bring the signal at the output of the preamp within an optimum dynamic range of the log-amp and wherein the pre-amplification gain is then set while the gain of the plurality of limiters are set to their minimum value with the RF log-amp then performing a second measurement with higher accuracy and calculating the final measurement from fine measurements and the pre-amplification gain. | 2008-11-13 |
20080278238 | Variable gain circuit - Disclosed is a variable gain circuit including a gain change region in which the gain is changed substantially exponentially as a function of a control voltage. The gain is changed in the gain change region substantially exponentially based on a function {(1+x) | 2008-11-13 |
20080278239 | POWER AMPLIFIER WITH CONTROLLED OUTPUT POWER - The invention includes a power amplifier with an amplifier core including parallel amplifier cells, a replica cell made of one amplifier cell similar to those of the amplifier core, a power controller to select a combination of amplifier cells to activate, a regulator to fix the top voltage of the replica cell to a reference voltage, a voltage generator to provide the voltage reference to the regulator, a current generator to provide a reference current through the replica cell, and a drive unit controlled by the regulator output to drive the combination of amplifier cells, so that each selected combination of activated cells defines a predetermined attenuation level of power amplifier output signal so that it is attenuated in a stepwise manner. | 2008-11-13 |
20080278240 | RECEIVER CIRCUITRY - Receiving circuitry having a plurality of amplifiers coupled in series, a first of the amplifiers receiving an input signal and each of the amplifiers outputting an amplified signal; a plurality of comparators each coupled to the output of one of the amplifiers and having an input for receiving the amplified signal; signal identification circuitry coupled to the outputs of the comparators and arranged to determine whether the outputs of the comparators validly represent data; and signal selection circuitry arranged to select the best signal originating from the comparators based on the validity of the outputs of the comparators. | 2008-11-13 |
20080278241 | Device Comprising an Element with Electrodes Coupled to Connections - An adaptive cruise control system and a method for controlling the speed of a vehicle are disclosed. The system generally includes a controller which determines a torque instruction associated with a limit speed of the vehicle which is less than a selected speed. The method generally includes determining a distance between the vehicle and an object detected in the path of the vehicle, determining a torque instruction which is associated with a limit speed which is less than a selected speed from at least the distance, and transmitting the torque instruction to an engine controller of the vehicle. | 2008-11-13 |
20080278242 | Amplifier - An amplifier has a self-bias circuit to generate the bias voltage for the input of the amplifying circuit in the amplifier, thereby simplifying the circuit complexity to reduce the size and cost of the amplifier. | 2008-11-13 |