| 46th week of 2008 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20080277640 | RAIL AND RAMP SYSTEMS WITH ADJUSTABLE FITTINGS - Modular railing and ramp systems having adjustable fittings to allow a multitude of rail configurations utilizing a series of mechanical connections. | 2008-11-13 |
| 20080277641 | Inverted variable resistance memory cell and method of making the same - An inverted variable resistance memory cell and a method of fabricating the same. The memory cell is fabricated by forming an opening in an insulating layer deposited over a semiconductor substrate, etching the top portion of the opening to have a substantially hemispherical-shape, forming a metal layer in the opening, and overlying a variable resistance material over the metal layer. | 2008-11-13 |
| 20080277642 | Fabrication of Phase-Change Resistor Using a Backend Process - A phase change resistor device has a phase change material (PCM) for which the phase transition occurs inside the PCM and not at the interface with a contact electrode. For ease of manufacturing the PCM is an elongate line structure ( | 2008-11-13 |
| 20080277643 | PHASE CHANGE MEMORY DEVICE USING PNP-BJT FOR PREVENTING CHANGE IN PHASE CHANGE LAYER COMPOSITION AND WIDENING BIT LINE SENSING MARGIN - A phase change memory device includes a semiconductor substrate having bar-shaped active regions which extend in a first direction; base regions and emitter regions alternately formed in each active region; lower electrodes formed over the emitter regions to connect to the respective emitter regions; a phase change layer and an upper electrode stacked on each of the lower electrodes; sub bit lines formed over the upper electrodes to come into contact with the corresponding upper electrodes; word lines arranged over the sub bit lines to come into contact with the base regions; and a main bit line formed over the word line to come into contact with the sub bit lines. The phase change memory device is able to prevent a change in the composition of the phase change layer and additionally is able to widen the sensing margin of a bit line. | 2008-11-13 |
| 20080277644 | SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS - The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in contact with a second portion of the heating element, a third terminal in contact with one of the at least two programmable vias, and a fourth terminal in contact with another one of the at least two programmable vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first field effect transistor in contact with one of the first and second terminals; and a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting the source region of the first field effect transistor. A method of operating the at least one programmable via structure is also provided. | 2008-11-13 |
| 20080277645 | Ferromagneic Influence on Quantum Dots - A semiconductor magnetic body comprises a layer ( | 2008-11-13 |
| 20080277646 | Vertical Type Nanotube Semiconductor Device - A vertical type nanotuhe semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved. | 2008-11-13 |
| 20080277647 | Materials and Optical Devices Based on Group IV Quantum Wells Grown on Si-Ge-Sn Buffered Silicon - A semiconductor structure including a single quantum well Ge | 2008-11-13 |
| 20080277648 | Conductive Thin Film and Thin Film Transistor - [Object] To provide an inexpensive and flexible conductive thin film which is excellent in carrier mobility and electric conductivity and which is formed by highly orienting nanotube or an electronic functional organic material by simple and convenient means, as well as a thin film transistor using the conductive thin film. | 2008-11-13 |
| 20080277649 | Field Effect Transistor and Method of Producing Same - A field effect transistor is provided which comprises an organic semiconductor layer comprising a compound having a monobenzoporphyrin skeleton represented by the general formula (1): | 2008-11-13 |
| 20080277650 | ORGANIC PHOTODETECTOR AND FABRICATING METHOD OF ORGANIC PHOTODETECTOR AND ORGANIC THIN FILM TRANSISTOR - An organic photodetector including a substrate, a first electrode, an insulation layer, an organic layer, and a second electrode is provided. The first electrode is disposed on the substrate. The insulation layer is disposed on the first electrode. The organic layer is disposed on the substrate and the insulation layer and covers a side surface of the insulation layer and a side surface of the first electrode. The second electrode is disposed on the organic layer and located above the insulation layer. | 2008-11-13 |
| 20080277651 | ORGANIC NON-VOLATILE MEMORY MATERIAL AND MEMORY DEVICE UTILIZING THE SAME - Disclosed is an organic non-volatile memory (ONVM) material including nanoparticles evenly dispersed in a first polymer. The nanoparticles have a metal core covered by a second polymer to form a core/shell structure, and the first polymer has a higher polymerization degree and molecular weight than the second polymer. The ONVM material of the invention has high uniformity, thereby stabilizing the electric properties of the memory device, such as increasing rewrite counts, increasing data retention time, reducing driving voltage, reducing write current, and enhancing current on/off ratio. | 2008-11-13 |
| 20080277652 | CARBON-CONTAINING SEMICONDUCTING DEVICES AND METHODS OF MAKING THEREOF - Embodiments of the present invention relate to semiconducting carbon-containing devices and methods of making thereof. The semi-conducting carbon containing devices comprise an n-type semiconducting layer and a p-type semiconducting layer, both of which are positioned over a substrate. The n-type semiconducting layer can be formed by pyrolyzing a carbon- and nitrogen-containing polymer, and the p-type semiconducting layer can be formed by pyrolyzing an aromatic- and aliphatic-group-containing polymer. In some embodiments, the devices are solar cell devices. | 2008-11-13 |
| 20080277653 | Semiconductor Element, and Display Pixel and Display Panel using the same - In a semiconductor element, and a display pixel and a display panel using the same, the semiconductor element includes a first electrode, a second electrode, an organic light-emitting layer and a third electrode. The second electrode and the first electrode are disposed separately. The organic light-emitting layer is electrically connected with the first electrode and the second electrode. The third electrode is disposed above the organic light-emitting layer. | 2008-11-13 |
| 20080277654 | Organic light emitting diode with fluorinion-doped anode and method for fabricating same - An exemplary organic light emitting diode ( | 2008-11-13 |
| 20080277655 | ORGANIC SEMICONDUCTOR DEVICE - An organic semiconductor device with a vertical structure having both functions of an organic thin film transistor and light-emitting element, where the electrical characteristics as both the organic thin film transistor and light-emitting element can be controlled in the case of forming a gate electrode with an organic conductive film, and a manufacturing method thereof. The above organic semiconductor device has such a structure that organic semiconductor films are sandwiched between a pair of electrodes functioning as a source electrode and drain electrode of an organic thin film transistor and also functioning as an anode and cathode of a light-emitting element, a thin organic conductive film functioning as a gate electrode is sandwiched between the organic semiconductor films, and a part of the organic conductive film is electrically connected to an auxiliary electrode, thereby the electrical characteristics as both the organic thin film transistor and light-emitting element can be controlled. | 2008-11-13 |
| 20080277656 | METHOD OF MANUFACTURING ZnO SEMICONDUCTOR LAYER FOR ELECTRONIC DEVICE AND THIN FILM TRANSISTOR INCLUDING THE ZnO SEMICONDUCTOR LAYER - Provided are a method of manufacturing a ZnO semiconductor layer for an electronic device, which can control the size of crystals of the ZnO semiconductor layer and the number of carriers using a surface chemical reaction between precursors, and a thin film transistor (TFT) including the ZnO semiconductor layer. The method includes: (a) loading a substrate into a chamber; (b) injecting a Zn precursor into the chamber to adsorb the Zn precursor on the substrate; (c) injecting an inert gas or N | 2008-11-13 |
| 20080277657 | THIN FILM TRANSISTOR AND ORGANIC LIGHT EMITTING DISPLAY USING THE SAME - Thin film transistors and organic light emitting displays using the same are provided. The thin film transistor may include a substrate, a semiconductor layer, a gate electrode, and source/drain electrodes on the substrate. The semiconductor layer is composed of a P-type semiconductor layer obtained by diffusing phosphorus into a zinc oxide semiconductor. The phosphorus is doped in the semiconductor layer to a concentration ranging from about 1×10 | 2008-11-13 |
| 20080277658 | Thin film transistor, method of manufacturing the same, organic light emitting display apparatus comprising the thin film transistor, and method of manufacturing the same - A thin film transistor includes a gate electrode; an active layer formed of an oxide and insulated from the gate electrode; and a source electrode and a drain electrode formed of an oxide on the active layer such that the source electrode and the drain electrode are insulated from the gate electrode and electrically connected to the active layer, wherein the active layer, the source and the drain electrode are formed using an atomic layer deposition (ALD) and an insitu process, and a root mean square (RMS) value of the surface roughness of the active layer which contacts with the source and drain electrodes is less than 1 nm in order to reduce the contact resistance between the active layer and the source and drain electrodes, a method of manufacturing the same, an organic light emitting display apparatus including the thin film transistor, and a method of manufacturing the same. | 2008-11-13 |
| 20080277659 | Test structure for semiconductor chip - A test structure for use in a semiconductor chip. In a preferred embodiment, a number of die are formed in an array on a semiconductor wafer substrate. Each die includes an active area defined by a seal ring and is separated from those adjacent to it by a thin scribe line. In addition to the operational structures formed in the active area of each die, one or more test structures are formed. In a preferred embodiment, these test structures are formed into one or more PCM (process control monitor) test pattern layout areas that are positioned near the seal ring and outside of the operational bond pads. Some or all of individual pads in the PCM test pattern layout area may then be connected to corresponding features on adjacent dice, and in some applications enable the simultaneous performance of WAT (wafer acceptance test) and CP (circuit probe) testing. | 2008-11-13 |
| 20080277660 | Semiconductor Device, Manufacturing Method Thereof, and Measuring Method Thereof - To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed. | 2008-11-13 |
| 20080277661 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A technique of manufacturing a semiconductor device capable of performing a probe test by a common test apparatus as normal LSI chips even for large-area chips is provided. A chip comprising a device formed on a device area by a semiconductor process and including a plurality of test areas sectioned by chip areas is prepared. Next, pads to be electrically connected to the device are formed at corresponding positions on the respective plurality of test areas. Subsequently, the respective test areas are tested by a same probe card via the plurality of pads. | 2008-11-13 |
| 20080277662 | SEMICONDUCTOR STRUCTURES - A semiconductor structure is disclosed. The semiconductor structure includes a polycrystal substrate, a first single crystal layer formed thereon and a second single crystal layer formed on the first single crystal layer. A variation of coefficients of thermal expansion (CTE) between the first single crystal layer and the polycrystal substrate is less than 25%. There is no lattice mismatch between the first single crystal layer and the polycrystal substrate. | 2008-11-13 |
| 20080277663 | Thin film transistor and method of manufacturing the same - Provided is a thin film transistor that includes a substrate on which an insulating layer is formed, a gate formed on a region of the insulating layer, a gate insulating layer formed on the insulating layer and the gate, a channel region formed on the gate insulating layer on a region corresponding to the location of the gate, a source and a drain respectively formed by contacting either side of the channel region; and a passivation layer formed of a compound made of a group II element and a halogen element on the channel region. | 2008-11-13 |
| 20080277664 | DISPLAY APPARATUS AND METHOD THEREOF - A display apparatus includes pixel electrodes disposed on a first base substrate, a second base substrate which faces the first base substrate, color pixels disposed on the second base substrate, the color pixels correspond to the pixel electrodes in a one-to-one correspondence, each color pixel partially covers the corresponding pixel electrode, a common electrode disposed on the second base substrate to cover the pixel electrodes and an electrophoretic layer including a plurality of electrophoretic particles, the electrophoretic layer being interposed between the pixel electrodes and the common electrode. | 2008-11-13 |
| 20080277665 | SEMICONDUCTOR DEVICE, NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a conductive layer including a first and a second polysilicon layers having different grain boundaries, wherein a portion or an entire region of the first polysilicon layer is crystallized and wherein a grain boundary in a crystallized region is bigger than the grain boundary of the second polysilicon layer. | 2008-11-13 |
| 20080277666 | Thin film transistor, organic light emitting display device including the same, and method of manufacturing the organic light emitting display device - A thin film transistor (TFT) may include a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, and a semiconductor layer on the gate insulating layer. The semiconductor layer may include a top surface, a channel area aligned in a vertical direction with the gate electrode, a plurality of doped areas proximate to the channel area, and a plurality of non-doped areas. Source and drain electrodes may be on the top surface of the semiconductor layer aligned above respective ones of the plurality of non-doped areas of the semiconductor layer. A planarization layer may be on the gate insulating layer, the source and drain electrodes and the semiconductor layer channel area, and may include a plurality of openings respectively exposing the plurality of doped areas of the semiconductor layer and a portion of the source electrode and the drain electrode. | 2008-11-13 |
| 20080277667 | Method of producing III-nitride substrate | 2008-11-13 |
| 20080277668 | SIS semiconductor having junction barrier schottky device - A semiconductor device having a junction barrier Schottky diode includes: a SiC substrate; a drift layer on the substrate; an insulation film on the drift layer having an opening in a cell region; a Schottky barrier diode having a Schottky electrode contacting the drift layer through the opening of the insulation film and an ohmic electrode on the substrate; a terminal structure having a RESURF layer surrounding the cell region; and multiple second conductive type layers on an inner side of the RESURF layer. The second conductive type layers and the drift layer provide a PN diode. The Schottky electrode includes a first Schottky electrode contacting the second conductive type layers with ohmic contact and a second Schottky electrode contacting the drift layer with Schottky contact. | 2008-11-13 |
| 20080277669 | SiC semiconductor having junction barrier Schottky device - A semiconductor device having a JBS diode includes: a SiC substrate; a drift layer on the substrate; an insulation film on the drift layer having an opening in a cell region; a Schottky barrier diode having a Schottky electrode contacting the drift layer through the opening and an ohmic electrode on the substrate; a terminal structure having a RESURF layer in the drift layer surrounding the cell region; and multiple second conductive type layers in the drift layer on an inner side of the RESURF layer contacting the Schottky electrode. The second conductive type layers are separated from each other. The second conductive type layers and the drift layer provide a PN diode. Each second conductive type layer has a depth larger than the RESURF layer. | 2008-11-13 |
| 20080277670 | SiC crystal and semiconductor device - The present invention discloses a SiC crystal, comprising: acceptor impurities that are in a concentration greater than 5×10 | 2008-11-13 |
| 20080277671 | Semiconductor device, method of manufacturing the same, electro-optic device and electronic apparatus - The invention provides a semiconductor device, a method of manufacturing the same, an electro-optic device and an electronic apparatus which are capable of addressing or solving a problem of mechanical mounting of a semiconductor element chip on a substrate. A semiconductor device includes a tile-shaped microelement bonded to a substrate, and an insulating functional film provided to cover at least a portion of the tile-shaped microelement. | 2008-11-13 |
| 20080277672 | Lid structure for microdevice and method of manufacture - A system and a method are described for forming features at the bottom of a cavity in a substrate. Embodiments of the systems and methods provide an infrared transmitting, hermetic lid for a microdevice. The lid may be manufactured by first forming small, subwavelength features on a surface of an infrared transmitting substrate, and coating the subwavelength features with an etch stop material. A spacer wafer is then bonded to the infrared transmitting substrate, and a device cavity is etched into the spacer wafer down to the etch stop material, exposing the subwavelength features. The etch stop material may then be removed, and the microdevice enclosed in the device cavity, by bonding the device wafer to the lid. | 2008-11-13 |
| 20080277673 | CAVITY EXPLORATION WITH AN IMAGE SENSOR - A head of a cavity exploration device, with an integrated circuit support which has first and second surfaces and a plurality of through-holes associated with corresponding first and second conducting pads positioned on the respective first and second surfaces of the integrated circuit support, a respective conducting micro-cable is placed in the through-hole, with this micro-cable having a portion which is uninsulated for a length greater than or equal to the thickness of the support. The micro-cable is soldered to the associated first and second conducting pads. Next the micro-cable is glued to the first and second associated conducting pads. The micro-cable is molded in first and second resin layers onto the respective first and second conducting pads, with the resin layers covering the uninsulated portion of the micro-cable. | 2008-11-13 |
| 20080277674 | Semiconductor Light Emitting Device, Lighting Module, Lighting Apparatus, and Manufacturing Method of Semiconductor Light Emitting Device - An LED bare chip which is one type of a semiconductor light emitting device ( | 2008-11-13 |
| 20080277675 | LIGHT-EMITTING DIODE ASSEMBLY WITHOUT SOLDER - An electrical device in the form of a light emitting diode (LED) assembly. A plurality of LEDs are provided, wherein each has an anode and a cathode. A base holds this plurality of LEDs in a substantially fixed relationship. One or more anode conductors then each connect electrically to one or more of the LED anodes in a manner characterized by not including any solder material. Similarly, one or more cathode conductors each connect electrically to one or more of the LED cathodes in a manner characterized by not including any solder material. | 2008-11-13 |
| 20080277676 | Light emitting diode using semiconductor nanowire and method of fabricating the same - Provided are a light emitting diode (LED) using a Si nanowire as an emission device and a method of fabricating the same. The LED includes: a semiconductor substrate; first and second semiconductor protrusions disposed on the semiconductor substrate to face each other; a semiconductor nanowire suspended between the first and second semiconductor protrusions; and first and second electrodes disposed on the first and second protrusions, respectively. | 2008-11-13 |
| 20080277677 | LIGHT EMITTING DIODE ASSEMBLY AND LIGHT EMITTING DIODE DISPLAY DEVICE - An exemplary light emitting diode (LED) assembly includes a cover, a substrate, a LED unit, a first electrode terminal, and a second electrode terminal. The substrate includes a first surface and a second surface on an opposite side of the substrate thereto. The substrate and the cover cooperatively define a cavity. The LED unit is received in the cavity. The first and the second electrode terminals extend from the second surface. The first electrode terminal is electrically connected to one of a positive lead and a negative lead of the LED unit and the second electrode terminal is electrically connected to the other. The second electrode terminal includes a first electrode portion and a second electrode portion symmetrically arranged at opposite sides of the first electrode terminal. The first and the second electrode portions are at least partially symmetrical with respect to the first electrode terminal. | 2008-11-13 |
| 20080277678 | Light emitting device and method for making the same - A method for making a light emitting device includes: forming a multi-layer structure on a substrate; forming a patterned mask material on one side of the multi-layer structure such that the patterned mask material covers an etch region of the multi-layer structure; forming a roughened layer on the multi-layer structure; removing the patterned mask material from the multi-layer structure so as to expose the etch region of the multi-layer structure; forming an etch mask material on the roughened layer; dry etching the multi-layer structure at the exposed etch region so as to define an electrode-forming region on the first semiconductor layer that corresponds to the etch region of the multi-layer structure; and forming an electrode on the electrode-forming region of the first semiconductor layer. | 2008-11-13 |
| 20080277679 | Light-emitting device - A light-emitting device, including a compound semiconductor layer disposed on a substrate, includes a light-emitting layer, and a dielectric constant change structure formed in a part of the compound semiconductor layer including a main surface as a light extraction surface of the compound semiconductor layer. The dielectric constant change structure is devoid of revolution symmetry provided by randomly changing a periodicity of a dielectric constant in a two-dimensional lattice pattern, with respect to a photonic crystal structure in which more than two kinds of materials having different dielectric constants are periodically and alternately disposed on the main surface in the two-dimensional lattice pattern. | 2008-11-13 |
| 20080277680 | Led With Improved Light Emittance Profile - The present invention relates to a LED comprising a substrate layer with a first surface and a second surface opposing the first surface and having a refractive index of n | 2008-11-13 |
| 20080277681 | LIGHT EMITTING DIODE - A light emitting diode includes a substrate, a reflecting layer, an active layer, a transparent electrode, a first photonic crystal structure, and a second photonic crystal structure. The reflecting layer is disposed on the substrate. The active layer is disposed on the reflecting layer. The transparent electrode is disposed on the active layer and includes an upper surface and a lower surface. The lower surface of the transparent electrode combines with the active layer. The first photonic crystal structure is formed on the upper surface of the transparent electrode. The second photonic crystal structure formed in the active layer. | 2008-11-13 |
| 20080277682 | DUAL SURFACE-ROUGHENED N-FACE HIGH-BRIGHTNESS LED - A light emitting diode, comprising a substrate, a buffer layer on the substrate, an active layer on the buffer layer and between an n-type layer and a p-type layer, a tunnel junction adjacent the p-type layer, and n-type contacts to the tunnel junction and the n-type layer, wherein the buffer layer, n-type layer, p-type layer, active region and tunnel junction comprise III-nitride material grown in a nitrogen-face (N-face) orientation. The substrate surface upon which the III-nitride material is deposited is patterned to provide embedded backside roughening. A top surface of the tunnel junction, which also the top surface of the III-nitride material, is roughened. | 2008-11-13 |
| 20080277683 | SOLDERING METHOD FOR SEMICONDUCTOR OPTICAL DEVICE, AND SEMICONDUCTOR OPTICAL DEVICE - A method for soldering a semiconductor optical device including a resin-made optical lens to an object by a reflow soldering process using a lead-free solder, and a semiconductor optical device for use in the method. A semiconductor optical device including a silicone resin-made optical lens as the resin-made optical lens is used; | 2008-11-13 |
| 20080277684 | SURFACE LIGHT EMITTING DIODE MODULE WITH A SURFACE LIGHT EMITTING DIODE CONNECTED TO A CONDUCTIVE SUBSTRATE TIGHTLY - A surface light emitting diode module includes a conductive substrate including a first electrode section. A first hole is formed on the first electrode section. The surface light emitting diode module further includes a surface light emitting diode installed on the conductive substrate. The surface light emitting diode includes a first electrode pin for contacting with the first electrode section. A second hole is formed on the first electrode pin and disposed in a position corresponding to the first hole. The surface light emitting diode module further includes a first fixing component passing through the second hole and the first hole so as to fix the conductive substrate and the surface light emitting diode. | 2008-11-13 |
| 20080277685 | Light emitting diode package - Provided is a light emitting diode package in accordance with the present invention including a lead frame composed of at least a pair of lead terminals; a mold receiving a part of the lead frame therein and equipped with an irradiation window opened to radiate light, and further including one or more holes formed to expose a part of a bottom surface of the lead frame received in the inside of the mold; an LED chip mounted on the lead frame positioned in the mold; an electrode connection unit for electrically connecting the LED chip and the lead frame; and a molding agent composed of any one selected from transparent epoxy, silicon, and phosphor blends charged in the mold and protecting the LED chip. | 2008-11-13 |
| 20080277686 | Light emitting device and method for making the same - A light emitting diode includes: an epitaxial substrate having a roughened side and formed with alternately disposed ridges and valleys at the roughened side, each of the ridges having a roughened surface that is formed with a dense concentration of alternately disposed pits and protrusions; and an epitaxial layered structure formed on and covering the ridges and the valleys of the epitaxial substrate. A method for making the light emitting diode involves forming the epitaxial substrate with the ridges and valleys prior to the formation of the epitaxial layered structure. | 2008-11-13 |
| 20080277687 | High power density switch module with improved thermal management and packaging - A semiconductor power device, e.g., an Insulated Gate Bi-polar Transistor (IGBT) or a Metal-Oxide Field Effect Transistor (MOSFET) may be constructed in a reusable and repairable cost-effective sealed shell. The switch may be provided with direct-pressure-contact caps which may perform as electrical conductors for a semiconductor die of the switch and also as thermal heat-sink contacts for the device. The switch may be provided with internal self-powered gate driving control and PHM incorporated in sealed shell. Embodiments of the switch may be constructed with no external gating/PHM connection pin penetrations through the shell. | 2008-11-13 |
| 20080277688 | Semiconductor device and fabrication method thereof - A p-type collector layer is formed on a reverse side of an n-type high-resistivity first base layer, a p-type second base layer is formed on an obverse side of the first base layer, an emitter layer is formed on the second base layer, gate electrodes are formed inside trenches extending in a direction and intruding through the emitter layer and the second base layer into intermediate depths of the first base layer, with gate insulating films in between, a collector electrode is connected to the collector layer, an emitter electrode is connected to the emitter layer, the first base layer and the second base layer, the emitter layer is composed of first emitter layers extending along the trenches in the direction, and second emitter layers extending in a perpendicular direction for a ladder form interconnection between first emitter layers, and the base contact layer has a higher impurity density than the second base layer, and envelopes the second emitter layers. | 2008-11-13 |
| 20080277689 | ELECTRO-STATIC DISCHARGE PROTECTION DEVICE - An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply. The second high concentration second conductive type region is set to a potential different from the first power supply. | 2008-11-13 |
| 20080277690 | STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER - A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations. | 2008-11-13 |
| 20080277691 | Production of a Transistor Gate on a Multibranch Channel Structure and Means for Isolating This Gate From the Source and Drain Regions - A method for fabricating a microelectronic device including a support, an etched stack of thin layers including at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, plural semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or plural transistor channels. A gate surrounds the bars and is located between the first block and the second block, the gate being in contact with a first and second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via the insulating spacers. | 2008-11-13 |
| 20080277692 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer made of an Al | 2008-11-13 |
| 20080277693 | IMAGER ELEMENT, DEVICE AND SYSTEM WITH RECESSED TRANSFER GATE - An imager element, device and imaging system image sensor pixel. The image sensor pixel includes a collection region, a floating diffusion region, and a transfer transistor having a recessed gate. The recessed gate is configured to couple the collection region to the floating diffusion region so that collected charge is transferred during activation. The recessed gate has an effective gate length greater than the physical gate length. | 2008-11-13 |
| 20080277694 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer. The second epitaxial layer has a higher resistivity than the semiconductor substrate. A Schottky device and a non-Schottky semiconductor device are manufactured from the second epitaxial layer. In accordance with another embodiment, a semiconductor material includes an epitaxial layer disposed over a semiconductor substrate. The epitaxial layer has a higher resistivity than the semiconductor substrate. A doped region is formed in the epitaxial layer. A Schottky device and a non-Schottky semiconductor device are manufactured from the epitaxial layer. | 2008-11-13 |
| 20080277695 | MOSFET Having a JFET Embedded as a Body Diode - A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode. | 2008-11-13 |
| 20080277696 | Lateral Junction Field Effect Transistor and Method of Manufacturing The Same - A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties. | 2008-11-13 |
| 20080277697 | SEMICONDUCTOR DEVICE FOR HIGH FREQUENCY - A semiconductor device for high frequency includes a channel region fabricated on a compound semiconductor substrate, a gate electrode fabricated on the channel region, a source electrode and a drain electrode alternately fabricated on the channel region by sandwiching the gate electrode, a bonding pad to be connected to an external circuit, and an air-bridge having one end connected to the source electrode or the drain electrode above and outside the channel region, and the other end connected to the bonding pad. | 2008-11-13 |
| 20080277698 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a channel region fabricated on a compound semiconductor substrate,
| 2008-11-13 |
| 20080277699 | Recess Etch for Epitaxial SiGe - A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer. | 2008-11-13 |
| 20080277700 | Imaging Device by Buried Photodiode Structure - To achieve an image sensor with low noise, small dark current and the high sensitivity, an n-type region serving as a charge storage region ( | 2008-11-13 |
| 20080277701 | High energy implant photodiode stack - An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multifunction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set. | 2008-11-13 |
| 20080277702 | SOLID-STATE IMAGING DEVICE AND CAMERA HAVING THE SAME - Provided is a solid-state imaging device including unit pixels, wherein the unit pixels include two kinds of unit pixels including a first unit pixel and a second unit pixel that are formed on a common well on a semiconductor substrate. The first unit pixel includes: at least one photoelectric conversion region which converts light into a signal charge; the first semiconductor region that is formed on the common well and has a conductivity type identical to that of the common well; and the first contact electrically connected to the first semiconductor region. The second unit pixel includes: at least one photoelectric conversion region; the second semiconductor region that is formed on the common well and has a conductivity type opposite to that of the common well; and the second contact electrically connected to the second semiconductor region. | 2008-11-13 |
| 20080277703 | MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic random access memory includes a single tunnel junction element which includes a first fixed layer, a first recording layer, and a first nonmagnetic layer, a double tunnel junction element which includes a second fixed layer and a third fixed layer, a second recording layer, a second nonmagnetic layer formed between the second fixed layer and the second recording layer, and a third nonmagnetic layer formed between the third fixed layer and the second recording layer, and in which the magnetization directions in the second fixed layer and the second recording layer take one of the parallel state and the antiparallel state in accordance with a direction of an electric current flowing between the second fixed layer and the second recording layer, and a transistor connected to a memory cell having the single tunnel junction element and the double tunnel junction element connected in parallel. | 2008-11-13 |
| 20080277704 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided within the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connected to between the contact plug and the switching transistor; a barrier metal covering a whole upper surface of the upper electrode; and an insulation sidewall film provided on a side surface of the barrier metal and provided substantially on a same plane as a side surface of the upper electrode. | 2008-11-13 |
| 20080277705 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER STRUCTURE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR WAFER STRUCTURE - There is provided a semiconductor device including, a semiconductor substrate having a circuit forming region and a peripheral region, a base insulating film formed over the semiconductor substrate, a capacitor formed of a lower electrode, a capacitor dielectric film made of a ferroelectric material, and an upper electrode in this order over the base insulating film in the circuit forming region, an uppermost interlayer insulating film formed over the capacitor, a seal ring formed over the semiconductor substrate in the peripheral region, the seal ring having a height that reaches at least the upper surface of the interlayer insulating film, and surrounding the circuit forming region, a block film formed over the seal ring and over the interlayer insulating film in the circumference of the seal ring, and an electrode conductor pattern which is formed over the interlayer insulating film in the peripheral region, the electrode conductor pattern having an electrode pad, and having a cross-section exposed to a dicing surface. | 2008-11-13 |
| 20080277706 | FERROELECTRIC MEMORY DEVICE, FERROELECTRIC MEMORY MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING METHOD - A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode; and forming a compound film including silicon (Si) and a CH group on a surface of the interlayer insulating film and a surface of the conductive plug by depositing a Si compound containing Si atoms and the CH groups; wherein the compound film is formed after forming the conductive plug, and the compound film is formed before forming the lower electrode; and a self-orientation film is formed on a surface of the compound film. | 2008-11-13 |
| 20080277707 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - It is an object of the invention to provide a digital circuit which can operate normally regardless of binary potentials of an input signal. A semiconductor device having a correcting unit and a logic unit wherein the correcting unit includes a capacitor, first and second switches, wherein the first electrode of the capacitor is connected to the input terminal and the second electrode of the capacitor is connected to the gate of the transistor in the logic circuit, wherein the first switch controls the connection between a gate and drain of the transistor and the second switch controls the potential to be supplied to the drain of the transistor is provided. | 2008-11-13 |
| 20080277708 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A highly integrated semiconductor device has a device isolation layer demarcating a first active region in a first region of a substrate, and a second active region in a second region of the substrate. A first gate pattern and a second gate pattern are formed on the first active region and the second active region, respectively. A first spacer layer and a second spacer layer are formed over the gate patterns. Then, the second and first spacer layers in the first region are anisotropically etched to form a gate spacer on sidewalls of the first gate pattern. The gate spacer has a lower spacer section formed from the first spacer layer and an upper spacer section formed from the second spacer layer. Then, ions are implanted into the first active region. Subsequently, the upper spacer section and the second spacer layer on the first and second regions, respectively, are removed. A selective growth process is then performed to form a buffer insulating layer on the first active region beside the lower spacer sections. An etch stop layer and an interlayer dielectric may be then formed on the substrate. | 2008-11-13 |
| 20080277709 | DRAM STRUCTURE - A DRAM structure includes a substrate, a MOS transistor, a deep trench capacitor, a surface strap positioned on the surface of the substrate and interconnecting a drain of the MOS transistor and an electrode of the deep trench capacitor, wherein the sidewall and the top surface of the surface strap are covered with an insulating layer. A passing gate is positioned on the insulating layer. | 2008-11-13 |
| 20080277710 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern. | 2008-11-13 |
| 20080277711 | MEMORY CELL - A memory cell including a substrate with a protruding portion, the protruding portion having a side wall and a bottom, an upper doped region connected to a bit line, a lower region being closer to a bottom of the protruding portion than the upper region, a substrate contact, a control element configured to control a current flow between the lower region and the substrate contact, and a wordline portion, a first insulator near the wordline portion, a floating gate near the wordline portion, and a second insulator between the floating gate and the side wall of the protruding portion, wherein the wordline portion and the floating gate are arranged so that the channel is generateable in the substrate near the side wall between the upper doped region and the lower region. | 2008-11-13 |
| 20080277712 | Flash memory cell with a flair gate - An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width. | 2008-11-13 |
| 20080277713 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area. | 2008-11-13 |
| 20080277714 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a control gate formed along a first direction over a substrate, an active region formed over the substrate, the active region being defined along a second direction crossing the control gate and including a fin type protruding portion having rounded top corners at a region where the control gate and the active region overlap, a floating gate formed over a surface of the protruding portion of the active region below the control gate and formed to a substantially uniform thickness along the surface profile of the protruding portion of the active region, a tunneling insulation layer formed between the floating gate and the active region, and a dielectric layer formed between the floating gate and the control gate. | 2008-11-13 |
| 20080277715 | Dielectric film and formation method thereof, semiconductor device, non-volatile semiconductor memory device, and fabrication method for a semiconductor device - In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silicon surface to a first inert gas plasma. Thereafter a silicon compound layer is formed on the surface of the silicon gas by generating plasma while using a mixed gas of a second inert gas and one or more gaseous molecules, such that there is formed a silicon compound layer containing at least a pat of the elements constituting the gaseous molecules, on the surface of the silicon gas. | 2008-11-13 |
| 20080277716 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a device formation region, a tunnel insulating film formed on the device formation region, a floating gate electrode formed on the tunnel insulating film, isolation insulating films which cover side surfaces of the device formation region, side surfaces of the tunnel insulating film, and side surfaces of a lower portion of the floating gate electrode, an inter-electrode insulating film which covers an upper surface and side surfaces of an upper portion of the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein upper corner portions of the floating gate electrode are rounded as viewed from a direction parallel with the upper surface and the side surfaces of the upper portion of the floating gate electrode. | 2008-11-13 |
| 20080277717 | MINORITY CARRIER SINK FOR A MEMORY CELL ARRAY COMPRISING NONVOLATILE SEMICONDUCTOR MEMORY CELLS - A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during operation of the semiconductor memory cells, and the minority carrier sink having a shorter minority carrier lifetime in comparison with a semiconductor zone reaching as far as a surface of the semiconductor body. | 2008-11-13 |
| 20080277718 | 1T MEMS scalable memory cell - This invention relates to the use of a gate dielectric placed under the mobile gate electrode of MOS transistor, without the need of a conductive floating gate. The invention exploits the electromechanical hysteretic behavior of the mobile gate when down contacting (pull-in) and up separating (pull-out) from the gate dielectric, based on the (non)equilibrium between electrical and elastic forces. | 2008-11-13 |
| 20080277719 | NON-VOLATILE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a non-volatile memory cell and a method of fabricating the same. The non-volatile memory cell according to the present invention comprises a substrate, a first oxide film formed over an active region of the substrate, a source and drain formed within the active region, a charge storage unit formed on the first oxide film, a second oxide film configured to surround the charge storage unit and formed on the first oxide film, and a gate formed to surround the second oxide film. According to the non-volatile memory cell and a cell array including the same in accordance with the present invention, the charge storage unit is fully surrounded by the gate or the gate line, thus a disturbance phenomenon that may occur due to the memory operation of cells formed in other neighboring gate or gate line can be minimized. | 2008-11-13 |
| 20080277720 | NON-VOLATILE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A non-volatile memory device which can be highly-integrated without a decrease in reliability, and a method of fabricating the same, are provided. In the non-volatile memory device, a first doped layer of a first conductivity type is disposed on a substrate. A semiconductor pillar of a second conductivity type opposite to the first conductivity type extends upward from the first doped layer. A first control gate electrode substantially surrounds a first sidewall of the semiconductor pillar. A second control gate electrode substantially surrounds a second sidewall of the semiconductor pillar and is separated from the first control gate electrode. A second doped layer of the first conductivity type is disposed on the semiconductor pillar. | 2008-11-13 |
| 20080277721 | THIN FILM TRANSISTOR, PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer. | 2008-11-13 |
| 20080277722 | Semiconductor device and method of manufacturing the semiconductor device - A method of manufacturing a semiconductor. A first epitaxial layer is formed on a gate nitride layer, and a protection nitride layer is formed on the first epitaxial and gate nitride layers. A first gate insulation layer is formed on a drain silicide, a gate oxide layer is formed on a portion of the first epitaxial layer exposed by a trench. A second epitaxial layer is formed on the first layer. Polysilicon fills the trench to form a gate electrode. Ion-implanting impurities on the second epitaxial layer forms a source region. A second gate insulation layer is formed on the gate electrode and the gate oxide layer, a source silicide is formed on the second gate insulation layer, and an interlayer insulation layer is formed on the second epitaxial layer, source region and source silicide. Source, gate and drain contact holes expose the source silicide, gate electrode and drain silicide. | 2008-11-13 |
| 20080277723 | Semiconductor Device - In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region. | 2008-11-13 |
| 20080277724 | ELECTRONIC DEVICE HAVING A DIELECTRIC LAYER - An electronic device, such as a thin film transistor, is disclosed having a dielectric layer formed from a composition comprising a compound having at least one phenol group and at least one group containing comprising silicon. The resulting dielectric layer has good electrical properties. | 2008-11-13 |
| 20080277725 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a memory comprising a semiconductor layer extending in a first direction; a source; a drain; a body between the source and the drain; a bit-line extending in the first direction; a first gate-dielectric on a first side-surface of the body; a first gate-electrode on the first side-surface of the body via the first gate dielectric film; a first gate line extending in the first direction, connected to a bottom of the first gate-electrode, and formed integratedly with the first gate-electrode using same material; a second gate dielectric on a second side-surface of the body; a second gate-electrode on the second side surface of the body via the second gate dielectric film; and a second gate line extending in a second direction crossing the first direction, connected to an upper portion of the second gate-electrode, and formed integratedly with the second gate-electrode using same material. | 2008-11-13 |
| 20080277726 | Devices with Metal Gate, High-k Dielectric, and Butted Electrodes - FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. As a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. The FET device structures further contain stressed device channels, and gates with effective workfunctions of n | 2008-11-13 |
| 20080277727 | Apparatus and method for electrostatic discharge protection with p-well integrated components - An electrostatic protection circuit has a transistor for pumping charge into the substrate and a transistor, including a parasitic transistor, for removing charge from the substrate and tabs. The circuit is enclosed by barrier that prevents the migration of charge from the region of the transistors. The added charge in the region of the parasitic transistor, resulting from the increased charge in the region of the parasitic transistor, increases the flow of current between electrodes of the transistor, thereby removing the electrostatic charge more efficiently. removing the electrostatic charge more efficiently. | 2008-11-13 |
| 20080277728 | Semiconductor structure for protecting an internal integrated circuit and method for manufacturing the same - A semiconductor structure for protecting an internal integrated circuit comprises a substrate; a plurality of first doping regions formed in the substrate and disposed substantially within an N-well; a plurality of second doping regions, formed in the substrate and disposed within an P-well; a N+ section, formed in the substrate and enclosing the N-well and the P-well; a pad, formed above the substrate and electrically connected to at least one of the first doping regions; and a first ground and a second ground respectively disposed to positions corresponding to outside and inside of the N+ section. Also, the second doping regions are isolated from the first doping regions. The first and second doping regions located within the N+ section are isolated from the substrate by the N+ section. Furthermore, the second ground is electrically connected to at least one of the second doping regions. | 2008-11-13 |
| 20080277729 | ELECTROSTATIC DISCHARGE PROTECTION ELEMENT - A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event. | 2008-11-13 |
| 20080277730 | Semiconductor Device Manufactured Using a Laminated Stress Layer - There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater. | 2008-11-13 |
| 20080277731 | BODY BIAS TO FACILITATE TRANSISTOR MATCHING - One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed. | 2008-11-13 |
| 20080277732 | P-CHANNEL MOS TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions. | 2008-11-13 |
| 20080277733 | SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate; a gate electrode formed on the semiconductor substrate; source and drain extension regions formed in the semiconductor substrate on a first and a second side corresponding to a first sidewall surface and a second sidewall surface, respectively, of the gate electrode; a first piezoelectric material pattern formed on the semiconductor substrate continuously covering the first sidewall surface of the gate electrode from the first side of the gate electrode; a second piezoelectric material pattern formed on the semiconductor substrate continuously covering the second sidewall surface of the gate electrode from the second side of the gate electrode; and source and drain regions formed in the semiconductor substrate outside the source extension region and the drain extension, respectively. | 2008-11-13 |
| 20080277734 | IMPLANTATION PROCESSES FOR STRAINING TRANSISTOR CHANNELS OF SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICES WITH STRAINED TRANSISTOR CHANNELS - The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavties, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed. | 2008-11-13 |
| 20080277735 | MOS devices having elevated source/drain regions - A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region. | 2008-11-13 |
| 20080277736 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has an n-channel MISFET having first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including a first metal layer formed on the first gate insulating film, and a first n-type polysilicon film formed on the first metal layer, and a p-channel MISFET having second diffusion layers containing boron as a dopant and formed in a second region of the surface portion of the semiconductor substrate so as to sandwich a second channel region therebetween, a second gate insulating film formed on the second channel region, and a second gate electrode including a second metal layer containing nitrogen or carbon and formed on the second gate insulating film and a second n-type polysilicon film formed on the second metal layer and having a boron concentration of not more than 5×10 | 2008-11-13 |
| 20080277737 | Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtained with Such a Method - The invention relates to a method of manufacturing a semiconductor device ( | 2008-11-13 |
| 20080277738 | MEMORY CELLS, MEMORY BANKS, MEMORY ARRAYS, AND ELECTRONIC SYSTEMS - Some embodiments include memory cells containing vertical floating bodies, and containing gates which entirely laterally surround the floating bodies. Some embodiments include memory banks which contain multiple memory cells extending from a conductively-doped diffusion region. Some embodiments include memory arrays in which electrically insulative partitions extend through a conductively-doped diffusion region to divide the diffusion region into a plurality of lines, and in which multiple memory cells extend vertically upward from each of such lines. Some embodiments include electronic systems containing processors in data communication with memory, and in which the memory includes an array of zero capacitor one transistor memory cells. Some embodiments include methods of forming vertically-extending memory cells. Some embodiments include methods of forming of banks of memory cells in which all of the memory cells extend to a conductively-doped region. Some embodiments include methods of forming memory arrays. | 2008-11-13 |
| 20080277739 | Finfet Transistors - A fin FET array includes a number of fins | 2008-11-13 |
