45th week of 2010 patent applcation highlights part 41 |
Patent application number | Title | Published |
20100285595 | MYOGLOBIN AS EARLY PREDICTOR OF MYOCARDIAL INFARCTION - The present invention relates to a method for diagnosing myocardial infarction in a subject who suffers from acute coronary syndrome and has a cardiac troponin level, which is detectable, but lower than the level that is considered as being indicative for a myocardial infarction. Moreover, the present invention relates to a method for identifying a subject being susceptible to cardiac intervention, wherein the subject suffers from acute coronary syndrome and has a cardiac troponin level which is detectable, but lower than a level that is considered as being indicative for a myocardial infarction. The methods of the present invention are based on the determination of myoglobin and, optionally, Heart-type fatty acid binding protein (H-FABP) in a sample of said subject and comparing the amount of myoglobin and, optionally, H-FABP to reference amounts. Also comprised by the present invention are kits or devices to carry out the methods of the present invention. | 2010-11-11 |
20100285596 | METHODS FOR ISOLATING FUNCTIONALIZED MACROMOLECULES - The invention provides methods of isolating, purifying, analyzing and/or detecting, functionalized macromolecules, e.g., peptides, phosphopeptides, polypeptides, proteins, oligonucleotides, or phospholipids in a sample, e.g., a biological mixture, using solid phase extraction with an alumina sorbent packed in a micro-elution plate. | 2010-11-11 |
20100285597 | DETECTION OF FRAGMENTS OF NECTIN-1 FOR THE DIAGNOSIS OF ALZHEIMER'S DISEASE - Methods for diagnosing Alzheimer's Disease by detection of fragments of nectin-1 are described. Nectin-1 is shown to be a substrate for proteases associated with the onset of Alzheimer's Disease, including α-secretase, γ-secretase and BACE1 or a BACE1-like protease. The fragments produced by the action of these and other proteases on Nectin-1 can be used to diagnosis Alzheimer's Disease or a predilection towards Alzheimer's Disease. | 2010-11-11 |
20100285598 | Novel Artificial Base Pairs and Uses Thereof - The present invention provides nucleic acids based on novel artificial base pairing, as well as a preparation method and uses thereof. | 2010-11-11 |
20100285599 | Method and Device for the Quantitative Real Time Analysis of Fluorescent Samples - A method for the quantitative real time analysis of fluorescent samples is provided, at which each of the samples is excited to fluoresce by a sample individual light source ( | 2010-11-11 |
20100285600 | Markers associated with the therapeutic efficacy of glatiramer acetate - The present invention is directed to methods and kits based, at least in part, on the identification of allele-specific responsiveness or non-responsiveness to glatiramer acetate for the treatment of autoimmune disorders, such as relapsing-remitting multiple sclerosis. The allele-specific responsiveness or non-responsiveness is based on polymorphisms in the following genes, CTSS, MBP, TCRB, CD95, CD86, IL-1R1, CD80, SCYA5, MMP9, MOG, SPP1 and IL-12RB2. | 2010-11-11 |
20100285601 | METHOD OF ELECTRICALLY DETECTING A NUCLEIC ACID MOLECULE - The method is performed by means of a pair of electrodes that are arranged at a distance and within a sensing zone. A nucleic acid capture molecule with an uncharged backbone and a nucleotide sequence that is at least partially complementary to at least a portion of a strand of the target nucleic acid molecule, is immobilised on an immobilisation unit. The immobilisation unit, which is arranged within the sensing zone, is contacted with a solution suspected to comprise the target nucleic acid molecule, which hybridizes to the nucleic acid capture molecule. An activation agent is added, which has an electrostatic net charge complementary to the net charge of the target nucleic acid molecule. It associates to the complex of nucleic acid capture molecule and target nucleic acid molecule. Added is a water soluble polymer with at least one polymer strand and with an electrostatic net charge that is complementary to the net charge of the activation agent. Thus the polymer associates to the activation agent. A metal salt is added, which can act as an oxidant and the metal ions of which have an electrostatic net charge complementary to the net charge of the polymer. The metal ions associate to the polymer. Upon adding a reducing agent, the latter reduces the metal ions, forming a metal wire. The presence of the analyte molecule is determined based on an electrical characteristic of a region in the sensing zone that is affected by the metal wire. | 2010-11-11 |
20100285602 | ORGANOMETALLIC SENSOR DEVICE - The present invention relates to detectors for detecting fluorine-containing compounds and/or cyanide containing compounds, including hydrogen fluoride (HF) or HCN gas, hydrofluoric acid in solution, selected chemical warfare agents, selected industrial chemicals which may be hydrolysed to release HF or HCN gas, compounds containing a cyanide group, and compounds that can release HF or HCN. The detectors comprise i) an organometallic component containing at least one bis-substituted boryl group of the formula —B(R | 2010-11-11 |
20100285603 | MEASUREMENT OF VITAMIN D - The present invention relates to a method of measuring a vitamin D metabolite in a sample, the method comprising the steps of (a) treating said sample with a vitamin D metabolite releasing reagent under conditions appropriate to release a vitamin D metabolite from vitamin D-binding protein and not to cause protein precipitation, (b) subjecting the treated sample obtained in step (a) to a chromatographic separation, and (c) measuring a vitamin D metabolite during or after said chromatographic separation. The present invention also relates to methods for determining the vitamin D status of a subject, for use in the diagnosis of disease, and to agents and kits for use in performing the methods of the invention. | 2010-11-11 |
20100285604 | DISSOLVABLE FILM WITH DETECTION FUNTIONALITY - Provided are films having a visual cue agent present in a sufficient amount to present a visual cue when the film is contacted by an aqueous solution, and methods of detecting when a film is contacted by an aqueous solution. | 2010-11-11 |
20100285605 | Neurofibrillary labels - Disclosed are methods for determining the stage of neurofibrillary degeneration associated with a tauopathy in a subject believed to suffer from the disease, which methods comprise the steps of: (i) introducing into the subject a ligand capable of labelling aggregated paired helical filament (PHF) tau protein, (ii) determining the presence and\or amount of ligand bound to extracellular aggregated PHF tau in the medial temporal lobe of the brain of the subject, (iii) correlating the result of the determination made in (ii) with the extent of neurofibrillary degeneration in the subject. The methods can be used for pre-mortem diagnosis and staging of tauopathies such as Alzheimer's Disease. Preferred ligands include sulphonated-benzothiazole-like compounds and diaminophenothiazines. Novel ligands (e.g. sulphonated-benzothiazole-like compounds) are also provided. The method may also include the use of “blocking ligands” to block competing binding sites. In other aspects the invention provides in vitro methods for identifying ligands capable of labeling aggregated PHF tau protein, the methods comprising the steps of: (i) providing a first agent suspected of being capable of labeling aggregated PHF tau protein, (ii) contacting (a) a tau protein or a derivative thereof containing the tau core fragment bound to a solid phase so as to expose a high affinity tau capture site, with (b) a liquid phase tau protein or derivative thereof capable of binding to the solid phase tau protein or derivative, and (c) said selected first agent and (d) a second agent known to be tau-tau binding inhibitor, (iii) selecting first agent which fully or partially relieves the inhibition of binding of the liquid phase tau protein or derivative of (b) to the solid phase tau protein or derivative of (a) by the inhibitor (d). Ligands may also be tested to confirm that they are not themselves inhibitors. | 2010-11-11 |
20100285606 | DENSITY-BASED METHODS FOR SEPARATION OF MATERIALS, MONITORING OF SOLID SUPPORTED REACTIONS AND MEASURING DENSITIES OF SMALL LIQUID VOLUMES AND SOLIDS - The ability to levitate, to separate, and to detect changes in density using diamagnetic particles suspended in solutions containing paramagnetic cations using an inhomogeneous magnetic field is described. The major advantages of this separation device are that: i) it is a simple apparatus that does not require electric power (a set of permanent magnets and gravity are sufficient for the diamagnetic separation and collection system to work); ii) it is compatible with simple optical detection (provided that transparent materials are used to fabricate the containers/channels where separation occurs; iii) it is simple to collect the separated particles for further processing; iv) it does not require magnetic labeling of the particles/materials; and v) it is small, portable. The method and kits provided provide for separation and collection of materials of different densities, diagnostics for detection of analytes of interest, monitoring of solid-supported chemical reactions and determination of densities of solid and liquid mixtures. | 2010-11-11 |
20100285607 | METHOD FOR DETECTING AND QUANTIFYING ANALYTES ON A SOLID SUPPORT WITH LIPOSOME-ENCAPSULATED FLUORESCENT MOLECULES - The present invention relates to an improved method for detecting and quantifying analytes on a solid support, with liposome-encapsulated fluorescent molecules. | 2010-11-11 |
20100285608 | CONFORMATIONAL ENTROPY IN MOLECULAR RECOGNITION - The present invention provides methods for the determination of the degree of molecular recognition of a protein with a ligand, including a first protein with a second protein. The methods may comprise determining the squared generalized order parameter (hereinafter, O) for at least one intramolecular bond of the first protein. The protein is then formed into a complex with a ligand. The value or values of O2 for the said at least one bond of the protein is then determined while the protein and the ligand are in the complex. The O value or values determined for the protein while the protein and the ligand are in a complex are compared or related to the O value or values determined for the uncomplexed protein. | 2010-11-11 |
20100285609 | SENSOR - This invention relates to a method for detecting an analyte in a sample, comprising the steps of exposing the sample to a transducer which is capable of transducing a change in energy to an electrical signal, the transducer having at least one tethered reagent on or proximal thereto, the at least one tethered reagent having a binding site which is capable of binding the analyte; introducing a labelled reagent into the sample, wherein the labelled reagent contains a binding site for the analyte or the tethered reagent and a label which is capable of absorbing electromagneticradiation generated by a radiation source to generate energy; allowing the labelled reagent to bind to the analyte or tethered reagent in a first period in which the transducer is oriented such that the labelled reagent is caused to settle, at least in part, on the transducer; subsequently, in a second period, causing the labelled reagent to become unsettled; irradiating the sample with electromagnetic radiation during the first and second periods, transducing the energy generated into an electrical signal; detecting the electrical signal. A device for performing the method is also provided. | 2010-11-11 |
20100285610 | Lateral Flow Test Kit and Method for Detecting an Analyte - A method and device for detecting analytes in a test sample. Embodiments include methods for quantitatively detecting analytes within a range of concentrations. In an embodiment the method includes a lateral flow test strip with multiple test areas for capturing a labeled receptor to provide a detectable signal. | 2010-11-11 |
20100285611 | PHOTOBLEACHING RESISTANT PH SENSITIVE DYE NANOREACTORS WITH DUAL WAVELENGTH EMISSION - A pH sensitive nanoreactor can include an aqueous core within a liposome. The aqueous core can include a pH responsive dye dispersed or dissolved within the core. The liposome provides a nanoscale environment for the dye. Further, a nanoshell can be present which encapsulates the liposome. The nanoshell can be permeable to hydrogen ions while also protecting the dye from exposure to deleterious compounds and photobleaching. | 2010-11-11 |
20100285612 | FLOW RATE MEASUREMENT APPARATUS, ANTIGEN CONCENTRATION MEASUREMENT APPARATUS, FLOW CELL, FLOW RATE MEASUREMENT METHOD, AND ANTIGEN CONCENTRATION MEASURING METHOD - A flow rate measurement apparatus includes a light oscillator; a thin metallic film which causes surface plasmon resonance by light output from the light oscillator; a focusing unit which fixes the thin metallic film and converts the output light of the light oscillator into incident light having a plurality of incident angles to focus the incident light at a location of a focal line in a straight line shape on the thin metallic film; a measurement part having antibody fixed areas to which an antibody is fixed and reference areas to which an antibody is not fixed, the antibody fixed areas and the reference areas being alternately arranged at a location along the focal line location on the thin metallic film; a light receiver which receives reflected light, at the focal line location, of the output light by surface plasmon resonance occurring at the focal line location, at each of the plurality of incident light angles; an SPR angle calculator which obtains a temporal change of an SPR angle in each of the antibody fixed areas and the reference areas in the measurement part; and a flow rate operation unit which calculates the flow rate of the sample flowing in the flow cell based on the temporal change of the SPR angle obtained by the SPR angle calculator. | 2010-11-11 |
20100285613 | IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND FABRICATION METHOD THEREOF - An in-plane switching mode liquid crystal display device includes a first substrate including a pixel electrode in a pixel region, a second substrate facing the first substrate and including a common electrode, a first alignment layer on the pixel electrode, a second alignment layer on the common electrode, a first ferroelectric liquid crystal layer on the first alignment layer and including a first spontaneous polarization, a second ferroelectric liquid crystal layer on the second alignment layer and including a second spontaneous polarization, a rotational direction of the first ferroelectric liquid crystal layer with respect to the first alignment layer being different from a rotational direction of the second ferroelectric liquid crystal layer with respect to the second alignment layer, and a twisted nematic liquid crystal layer between the first and second ferroelectric liquid crystal layers. | 2010-11-11 |
20100285614 | SEMICONDUCTOR WAFER METROLOGY APPARATUS AND METHOD - A semiconductor wafer metrology technique comprising performing atmospheric buoyancy compensated weighing of a wafer, in which the wafer is weighed in a substantially upright condition. A vertical or near vertical wafer orientation causes the surface area in the direction of a force (weight) sensor to be reduced compared with a horizontal wafer orientation. Hence, the electrostatic force components acting in the same direction as the wafer weight force component is reduced. | 2010-11-11 |
20100285615 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed. | 2010-11-11 |
20100285616 | TRANSITIONING DIGITAL INTEGRATED CIRCUIT FROM STANDBY MODE TO ACTIVE MODE VIA BACKGATE CHARGE TRANSFER - Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode. | 2010-11-11 |
20100285617 | LIQUID DISCHARGE HEAD SUBSTRATE, LIQUID DISCHARGE HEAD USING THE SUBSTRATE, AND MANUFACTURING METHOD THEREFOR - Provided is a liquid discharge head substrate including: a substrate; a heating resistor layer formed on the substrate; a flow path for a liquid; a wiring layer stacked on the heating resistor layer and having an end portion which forms a step portion on the heating resistor layer; and a protective layer covering the heating resistor layer and the wiring layer including the step portion, and formed between the heating resistor layer and the flow path, in which the protective layer is formed by a Cat-CVD method. | 2010-11-11 |
20100285618 | Pixel Structure of LCD and Fabrication Method Thereof - In this pixel structure, a metal layer/a dielectric layer/a heavily doped silicon layer constitutes a bottom electrode/a capacitor dielectric layer/a top electrode of a storage capacitor. At the same time, a metal shielding layer is formed under the thin film transistor to decrease photo-leakage-current. | 2010-11-11 |
20100285619 | METHOD FOR MANUFACTURING A SOLID STATE LASER HAVING A PASSIVEQ-SWITCH, - A method for manufacturing a laser-active solid having a bonded passive Q-switch is provided, which is particularly suitable for large quantities. | 2010-11-11 |
20100285620 | LED PACKAGING METHODS AND LED-BASED LIGHTING PRODUCTS - A method of packaging a light-emitting diode (LED) chip includes coupling the LED chip to a printed circuit board (PCB) and forming a conductor on a cover plate. Conductive epoxy is applied to at least one of the LED chip and the conductor. The cover plate is coupled to the PCB such that the conductive epoxy forms a circuit connection between the LED chip and the conductor. An LED-based lighting product includes a PCB with one or more LED chips mounted directly thereon. A cover plate has conductors that couple at least to the one or more LED chips and to the PCB, such that the conductors form electrical connections between the one or more LED chips and the PCB. | 2010-11-11 |
20100285621 | METHOD OF MAKING DIODE HAVING REFLECTIVE LAYER - A method of forming a light emitting diode includes forming a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A p-electrode is formed on the p-GaN layer and an n-electrode is formed on the n-GaN layer. A reflective layer is formed on a second side of the transparent substrate. A scribe line is formed on the substrate for separating the diodes on the substrate. Also, a cladding layer of AlGaN is between the p-GaN layer and the active layer. | 2010-11-11 |
20100285622 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a light emitting device and a method of manufacturing the same. The light emitting device comprises a transparent substrate, an n-type compound semiconductor layer formed on the transparent substrate, an active layer, a p-type compound semiconductor layer, and a p-type electrode sequentially formed on a first region of the n-type compound semiconductor layer, and an n-type electrode formed on a second region separated from the first region of the n-type compound semiconductor layer, wherein the p-type electrode comprises first and second electrodes, each electrode having different resistance and reflectance. | 2010-11-11 |
20100285623 | Array Substrate and Method for Fabricating Thereof - The invention provides a method for manufacturing an array substrate utilizing a laser ablation process. A conductive layer can be selectively patterned by the laser ablation process without a photo mask due to different adhesions between the conductive layer and other materials. The patterned conductive layer thus formed adjoins an inorganic passivation layer to provide a substantially continuous surface. | 2010-11-11 |
20100285624 | DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME - A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film. | 2010-11-11 |
20100285625 | LIGHT-EMITTING ELEMENT ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME - A method for making a light-emitting element assembly including a support substrate having a first surface, a second surface facing the first surface, a recessed portion, and a conductive material layer formed over the first surface and the inner surface of the recessed portion, and a light-emitting element. The light-emitting element has a laminated structure including a first compound semiconductor layer, a light-emitting portion, and a second compound semiconductor layer, at least the second compound semiconductor layer and the light-emitting portion constituting a mesa structure. The light-emitting element further includes an insulating layer formed, a second electrode, and a first electrode. The mesa structure is placed in the recessed portion so that the conductive material layer and the second electrode are in at least partial contact with each other, and light emitted from the light-emitting portion is emitted from the second surface side of the first compound semiconductor layer. | 2010-11-11 |
20100285626 | FABRICATION METHOD OF LIGHT EMITTING DIODE - A fabrication method of light emitting diode is provided. A first type doped semiconductor layer is formed on a substrate. Subsequently, a light emitting layer is formed on the first type doped semiconductor layer. A process for forming the light emitting layer includes alternately forming a plurality of barrier layers and a plurality of quantum well layers on the first type doped semiconductor layer. The quantum well layers are formed at a growth temperature T | 2010-11-11 |
20100285627 | MICRO-ELECTRO-MECHANICAL DEVICE AND MANUFACTURING METHOD FOR THE SAME - It is an object of the present invention to provide a micro-electro-mechanical-device having a microstructure and a semiconductor element over one surface. In particular, it is an object of the present invention to provide a method for simplifying the process of forming the microstructure and the semiconductor element over one surface. A space in which the microstructure is moved, that is, a movable space for the microstructure is formed by procecssing an insulating layer which is formed in a process of forming the semiconductor element. The movable space can be formed by forming the insulating layer having a plurality of openings and making the openings face each other to be overlapped each other. | 2010-11-11 |
20100285628 | Micromachined microphone and multisensor and method for producing same - A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top silicon layer of the wafer. Various polysilicon microphone structures are formed above a front side of the top silicon layer by depositing at least one oxide layer, forming the structures, and then removing a portion of the oxide underlying the structures from a back side of the top silicon layer through trenches formed through the top silicon layer. The trenches allow sound waves to reach the diaphragm from the back side of the top silicon layer. In an SOI wafer, a cavity is formed through a bottom silicon layer and an intermediate oxide layer to expose the trenches for both removing the oxide and allowing the sound waves to reach the diaphragm. An inertial sensor may be formed on the same wafer, with various inertial sensor structures formed at substantially the same time and using substantially the same processes as corresponding microphone structures. | 2010-11-11 |
20100285629 | METHOD FOR PLASMA DEPOSITION AND PLASMA CVD SYSTEM - In a film-forming process with a capacitively-coupled plasma (CCP) chemical vapor deposition (CVD) device, pulse control is performed on a low-frequency radio-frequency power source. During the pulse control, an ON time and an OFF time form one period. Furthermore, in the pulse control, a time interval between a time period from the moment that the electric power supply is stopped till the electron density decreases to a residual plasma threshold capable of causing an arc discharge and a time period from the moment that the electric power supply is stopped till the density of high-temperature electrons decreases to a specific plasma state serves as the OFF time; a saturation time during the rising process of the density of the high-temperature electrons in the plasma after the electric power supply is started serves as an upper limit of the ON time; and electric power is intermittently supplied under the above conditions. | 2010-11-11 |
20100285630 | Method of manufacturing an image sensor having improved anti-reflective layer - In a method of manufacturing an image sensor, a photodiode may be formed in a light receiving region of a substrate having a first surface. A conductive wiring may be formed on the first surface of the substrate. After removing a portion of the substrate opposite to the first surface, an anti-reflective layer may be formed on a second surface of the substrate. The second surface may be opposite to the first surface. The anti-reflective layer and the light receiving region may be thermally treated to cure defects including dangling bonds in the substrate and to improve a refraction index of the anti-reflective layer. The image sensor may have an enhanced light transmittance and may produce high-definition images. | 2010-11-11 |
20100285631 | METHOD OF SELECTIVELY DOPING A SEMICONDUCTOR MATERIAL FOR FABRICATING A SOLAR CELL - The present disclosure provides a method of selectively doping a semiconductor material for fabricating a solar cell. The method comprises forming at least one angled groove in the semiconductor material and forming a diffusion barrier on the semiconductor material. The diffusion barrier comprises a diffusion barrier material that is selected so that diffusing of a dopant material through the diffusion barrier is reduced. The method also comprises doping the semiconductor material by exposing the semiconductor material to the dopant material in a manner such that a region of the semiconductor material that is covered by the diffusion barrier has a predetermined first dopant concentration. In addition, the method comprises forming an electrical contact within the at least one angled groove after exposing the semiconductor material to the dopant material. The method is conducted so that a surface area of the semiconductor material within the at least one groove is substantially free from diffusion barrier material and has a second dopant concentration that is higher than the first dopant concentration. | 2010-11-11 |
20100285632 | TFT SUBSTRATE AND METHOD FOR MANUFACTURING TFT SUBSTRATE - An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate includes: a substrate; a gate electrode and a gate wire formed above the substrate; a gate insulating film formed above the gate electrode and the gate wire; a first oxide layer formed above the gate insulating film which is formed at least above the gate electrode; and a second oxide layer formed above the first oxide layer; wherein at least a pixel electrode is formed from the second oxide layer. | 2010-11-11 |
20100285633 | NON VOLATILE MEMORY CELLS INCLUDING A FILAMENT GROWTH LAYER AND METHODS OF FORMING THE SAME - A non volatile memory cell that includes a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including dielectric material and metal atoms; and a second electrode. In other embodiments, a memory array is disclosed that includes a plurality of non volatile memory cells, each non volatile memory cell including a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including clusters of a first electrically conductive atomic component interspersed in an oxidized second atomic component; and a second electrode; at least one word line; and at least one bit line, wherein the word line is orthogonal to the bit line and each of the plurality of non volatile memory cells are operatively coupled to a word line and a bit line. In still other embodiments, methods are disclosed that include forming a non volatile memory cell include forming a first electrode; forming a variable resistive layer on the first electrode; depositing a two phase alloy layer on the variable resistive layer; converting the two phase alloy layer to a filament growth layer; and depositing a second electrode on the filament growth layer, thereby forming a non volatile memory cell. | 2010-11-11 |
20100285634 | INDUCTIVELY COUPLED INTEGRATED CIRCUIT WITH MAGNETIC COMMUNICATION PATH AND METHODS FOR USE THEREWITH - An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit. | 2010-11-11 |
20100285635 | CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE - A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes. | 2010-11-11 |
20100285636 | MANUFACTURING METHOD OF A PACKAGING STRUCTURE OF ELECTRONIC COMPONENTS - A manufacturing method of a packaging structure of electronic components includes the steps of: providing a substrate including a plurality of electronic components; covering the electronic components disposed on the substrate with a molding body; forming a plurality of pre-cut grooves on the molding body so as to define a plurality of molding units on the molding body; forming an electromagnet barrier layer covering the molding units on the molding units and the pre-cut grooves; and cutting along at least one of the pre-cut grooves deeply down to break the substrate so as to form separately a plurality of packaging structures of the electronic components. | 2010-11-11 |
20100285637 | Die Down Ball Grid Array Packages and Method for Making Same - A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of a substrate, the opening of the substrate extending through the substrate, such that a portion of the heat spreader is accessible through the opening and coupling a first surface of a second substrate to the IC die via a bump interconnect. The second surface of the second substrate has an array of contact pads capable of coupling to a board. | 2010-11-11 |
20100285638 | METHOD FOR FABRICATING QFN SEMICONDUCTOR PACKAGE - A method for making a quad flat non-lead (QFN) semiconductor package includes half etching a first side of a carrier to form top portions of a lead array and a die attach surface of a die attach pad, wherein the lead array includes at least one inner terminal lead disposed adjacent to the die attach pad, at least one extended, outer terminal lead disposed along periphery of the QFN semiconductor package, and at least one intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead, wherein the intermediary terminal is disposed between the inner terminal lead and the extended, outer terminal lead. | 2010-11-11 |
20100285639 | Devices With Graphene Layers - A method includes an act of providing a crystalline substrate with a diamond-type lattice and an exposed substantially (111)-surface. The method also includes an act of forming a graphene layer or a graphene-like layer on the exposed substantially (111)-surface. | 2010-11-11 |
20100285640 | ETCHANT FOR ETCHING METAL WIRING LAYERS AND METHOD FOR FORMING THIN FILM TRANSISTOR BY USING THE SAME - The present invention discloses an etchant for etching at least two different metal layers, the etchant comprising hydrogen peroxide (H | 2010-11-11 |
20100285641 | MASK ROM DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE MASK ROM DEVICE, AND METHODS OF FABRICATING MASK ROM DEVICE AND SEMICONDUCTOR DEVICE - A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity. | 2010-11-11 |
20100285642 | Method of Doping Impurity Ions in Dual Gate and Method of Fabricating the Dual Gate using the same - A method of doping impurity ions in a dual gate includes doping first conductivity type impurity ions in a gate conductive layer over a semiconductor substrate having a first region and a second region, wherein the doping is performed with a concentration gradient so that a doping concentration in an upper portion of the gate conductive layer is higher than that in a lower portion; doping second conductivity type impurity ions in a portion of the gate conductive layer in the second region using a mask for opening the portion of the gate conductive layer in the second region; and diffusing the first conductivity type impurity ions and the second conductivity type impurity ions by performing heat treatment. | 2010-11-11 |
20100285643 | Modifying Work Function in PMOS Devices by Counter-Doping - A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode. | 2010-11-11 |
20100285644 | Methods of Forming Semiconductor Devices Having Recessed Channels - A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided. | 2010-11-11 |
20100285645 | METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES - Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region. | 2010-11-11 |
20100285646 | Method of fabricating power semiconductor device - Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base. | 2010-11-11 |
20100285647 | INSULATED GATE SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n | 2010-11-11 |
20100285648 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area. | 2010-11-11 |
20100285649 | Field-Effect Heterostructure Transistors - An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located on one of the region and the layer and a gate electrode located to control a conductivity of a channel portion of the semiconductor heterostructure. The channel portion is located between the source and drain electrodes. The gate electrode is located vertically over the channel portion and portions of the source and drain electrodes. | 2010-11-11 |
20100285650 | METHOD OF FABRICATING SEMICONDUCTOR TRANSISTOR DEVICES WITH ASYMMETRIC EXTENSION AND/OR HALO IMPLANTS - A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed. Thereafter, the method creates heavy dose extension implants and/or halo implants in the semiconductor material by bombarding the device structure with ions at a tilted angle relative to the exposed surface of the semiconductor material, and toward the plurality of gate structures. During this step, the plurality of gate structures and the patterned mask are used as a second implantation mask. | 2010-11-11 |
20100285651 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer. | 2010-11-11 |
20100285652 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE THAT IS LESS PRONE TO DC FAILURES BROUGHT ABOUT BY UNWANTED DEFECTS ON CAPACITORS THEREIN - A method for manufacturing a semiconductor device that is less prone to DC failures brought about by unwanted defects on capacitors in the device is presented. Manufacturing defects such as scratches are known to occur when making capacitors and that these defects are thought to be a primary cause of subsequent performance DC failures in the completed semiconductor devices. The method includes the steps of depositing, removing, forming, polishing, etching and forming. A sacrificial layer is exploited to allow a subsequent polishing down step to mechanically remove defects from the capacitors. | 2010-11-11 |
20100285653 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device includes a first conductor over a semiconductor substrate; forming a first insulator over the first conductor; forming a second insulator, having an etching characteristic different from an etching characteristic of the first insulator, over the first insulator; forming a second conductor on the second insulator, the second conductor being in contact with the second insulator; forming a third insulator, having an etching characteristic different from the etching characteristic of the second insulator, over the second conductor; forming a first contact hole though the third insulator and the second conductor, the first contact hole exposing the second insulator; forming a second contact hole through the third insulator and the first insulator, the second contact hole exposing the first conductor; forming a third conductor in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; forming a fourth conductor in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor. | 2010-11-11 |
20100285654 | SEMICONDUCTOR DEVICE HAVING REDUCED DIE-WARPAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer into at least two discrete sections. The stress-relieving pattern may be in the form of an interface between the discrete sections of the first layer, or a wall of material different from the material of the first layer. | 2010-11-11 |
20100285655 | METHOD OF PRODUCING BONDED WAFER - In the production of a bonded wafer by bonding a silicon wafer for active layer with an internal oxide film to a silicon wafer for support layer directly or indirectly with an insulating layer to form a silicon wafer composite and removing an upperlayer-side silicon portion and the internal oxide film of the silicon wafer composite to leave only an active layer with a given thickness, the active layer forming step is conducted only by polishing under given conditions. | 2010-11-11 |
20100285656 | FORMATION OF METAL-CONTAINING NANO-PARTICLES FOR USE AS CATALYSTS FOR CARBON NANOTUBE SYNTHESIS - The present invention relates to a method for forming metal-silicide catalyst nanoparticles with controllable diameter. The method according to embodiments of the invention leads to the formation of ‘active’ metal-suicide catalyst nanoparticles, with which is meant that they are suitable to be used as a catalyst in carbon nanotube growth. The nano-particles are formed on the surface of a substrate or in case the substrate is a porous substrate within the surface of the inner pores of a substrate. The metal-silicide nanoparticles can be Co-silicide, Ni-silicide or Fe-silicide particles. The present invention relates also to a method to form carbon nanotubes (CNT) on metal-silicide nanoparticles, the metal-silicide containing particles hereby acting as catalyst during the growth process, e.g. during the chemical vapour deposition (CVD) process. Starting from very defined metal-containing nanoparticles as catalysts, the diameter of grown CNT can be well controlled and a homogeneous set of CNT will be obtained. | 2010-11-11 |
20100285657 | GROWTH REACTOR FOR GALLIUM-NITRIDE CRYSTALS USING AMMONIA AND HYDROGEN CHLORIDE - The present invention in one preferred embodiment discloses a new design of HVPE reactor, which can grow gallium nitride for more than one day without interruption. To avoid clogging in the exhaust system, a second reactor chamber is added after a main reactor where GaN is produced. The second reactor chamber may be configured to enhance ammonium chloride formation, and the powder may be collected efficiently in it. To avoid ammonium chloride formation in the main reactor, the connection between the main reactor and the second reaction chamber can be maintained at elevated temperature. In addition, the second reactor chamber may have two or more exhaust lines. If one exhaust line becomes clogged with powder, the valve for an alternative exhaust line may open and the valve for the clogged line may be closed to avoid overpressuring the system. The quartz-made main reactor may have e.g. a pyrolytic boron nitride liner to collect polycrystalline gallium nitride efficiently. The new HYPE reactor which can grow gallium nitride crystals for more than 1 day may produce enough source material for ammonothermal growth. Single crystalline gallium nitride and polycrystalline gallium nitride from the HYPE reactor may be used as seed crystals and a nutrient for ammonothermal group III-nitride growth. | 2010-11-11 |
20100285658 | INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS - A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact. | 2010-11-11 |
20100285659 | Method for Fabricating Dual Poly Gate in Semiconductor Device - A method for fabricating a dual poly gate in a semiconductor device, comprising: forming a gate insulation layer and a polysilicon layer on a semiconductor substrate that defines a first region and a second region; implanting first and second conductive type impurity ions into the first region and the second region of the polysilicon layer, respectively; forming first and second conductive type polysilicon layer in the first and second regions, respectively, by annealing the semiconductor substrate; forming a barrier metal layer on the first and second conductive type polysilicon layers; forming an oxide layer that lowers resistance of a metal by an oxidation process; forming a metal layer and a hard mask layer on the oxide layer; and forming a first conductive type poly gate on the first region and a second conductive type poly gate on the second region by a patterning process. | 2010-11-11 |
20100285660 | COPPER DEPOSITION FOR FILLING FEATURES IN MANUFACTURE OF MICROELECTRONIC DEVICES - A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal thereon, electrolessly depositing copper onto the initial metal deposit to fill the feature with copper. A method for plating copper onto a semiconductor integrated circuit device substrate by forming a deposit comprising a copper wettable metal in the feature, forming a copper-based deposit on the top-field surface, and depositing copper onto the deposit comprising the copper wettable metal to fill the feature with copper. | 2010-11-11 |
20100285661 | SEMICONDUCTOR ELEMENT AND DISPLAY DEVICE USING THE SAME - Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor, a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second nitride insulating film, in which a first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion. | 2010-11-11 |
20100285662 | METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING AIR SPACERS SEPARATING CONDUCTIVE STRUCTURES AND CONTACT PLUGS - An integrated circuit device includes first and second conductive structures spaced apart from one another on a substrate along a first direction. The first and second conductive structures extend in a second direction substantially perpendicular to the first direction. A contact plug is interposed between the first and second conductive structures and is separated therefrom along the first direction by respective air gaps on opposite sides of the contact plug. The air gaps define first and second air spacers that electrically insulate the contact plug from the first and second conductive structures, respectively. An upper insulation layer covers the first and second air spacers and the first and second conductive structures. The air spacers may sufficiently reduce the loading capacitance between the conductive structures. Related fabrication methods are also discussed. | 2010-11-11 |
20100285663 | COMPOSITION AND METHOD FOR LOW TEMPERATURE DEPOSITION OF SILICON-CONTAINING FILMS SUCH AS FILMS INCLUDING SILICON, SILICON NITRIDE, SILICON DIOXIDE AND/OR SILICON-OXYNITRIDE - Silicon precursors for forming silicon-containing films in the manufacture of semiconductor devices, such as low dielectric constant (k) thin films, high k gate silicates, low temperature silicon epitaxial films, and films containing silicon nitride (Si | 2010-11-11 |
20100285664 | COMPOSITION AND METHODS FOR FORMING METAL FILMS ON SEMICONDUCTOR SUBSTRATES USING SUPERCRITICAL SOLVENTS - Compositions and methods for forming metal films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing at least one metal precursor comprising at least one ligand, an excess amount of neutral labile ligands, a supercritical solvent, and optionally at least one source of B, C, N, Si, P, and mixtures thereof; exposing the composition to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; disassociating the at least one ligand from the metal precursor; and forming the metal film while minimizing formation of metal oxides. | 2010-11-11 |
20100285665 | SEMICONDUCTOR WAFER MANUFACTURING METHOD - In a method of manufacturing semiconductor wafers, front and hack surfaces of the semiconductor wafers are simultaneously polished with a double-side polishing machine that includes: a carrier for accommodating the semiconductor wafer; and an upper press platen and a lower press platen for sandwiching the carrier. The method includes: accommodating the semiconductor wafer in the carrier while a thickness of the semiconductor wafer is set to be larger than a thickness of the carrier by 0 μm to 5 μm; and polishing the semiconductor wafer while feeding a polishing slurry to between the surfaces of the semiconductor wafer and surfaces of the press platens. In the polishing, an allowance of both surfaces of the semiconductor wafer is set at 5 μm or less in total. | 2010-11-11 |
20100285666 | PROCESS SEQUENCE TO ACHIEVE GLOBAL PLANARITY USING A COMBINATION OF FIXED ABRASIVE AND HIGH SELECTIVITY SLURRY FOR PRE-METAL DIELECTRIC CMP APPLICATIONS - A method and apparatus for polishing or planarizing a pre-metal dielectric layer by a chemical mechanical polishing process are provided. The method comprises providing a semiconductor substrate having feature definitions formed thereon, forming a pre-metal dielectric layer over the substrate, wherein the as-deposited pre-metal dielectric layer has an uneven surface topography, and planarizing the uneven surface topography of the pre-metal dielectric layer using chemical mechanical polishing techniques, wherein planarizing the uneven surface topography comprises polishing the pre-metal dielectric layer with a fixed abrasive polishing pad and a first polishing composition to remove a bulk portion of the pre-metal dielectric layer and achieve a first predetermined planarity, and polishing the pre-metal dielectric layer with a non-abrasive polishing pad and high selectivity slurry to remove a residual portion of the pre-metal dielectric and achieve a second predetermined planarity. | 2010-11-11 |
20100285667 | METHOD TO PRESERVE THE CRITICAL DIMENSION (CD) OF AN INTERCONNECT STRUCTURE - A method of restoring the dielectric constant, loss and leakage of an exposed surface of a low k dielectric material caused during dry etching of the low k dielectric material prior to the removal of the damaged layer by wet etch chemistries is provided. Once restored, the surface of the dielectric material will no longer be susceptible to removal by the highly anisotropic wet etching process. However, the wet etch will still pose an advantage as it can remove any etch/ash residues at the bottom of a feature formed into the low k dielectric material. | 2010-11-11 |
20100285668 | TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL - By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer. | 2010-11-11 |
20100285669 | DRY ETCHING METHOD - After etching a polysilicon film, when a protective film made of a carbon polymer is formed on a sidewall of the polysilicon film using plasma containing carbons, a metallic material as a lower film is etched using plasma containing a halogen gas under an etching condition in which volatility is improved due to the rise in a wafer temperature or the low pressure of a processing pressure, thereby preventing a side etching and unevenness of a sidewall of the polysilicon film. Further, by using the protective film made of a carbon polymer, metallic substances scattered at the time of etching the metallic material are not directly attached to the polysilicon film, but can be simply removed along with the protective film made of a carbon polymer in an asking step. | 2010-11-11 |
20100285670 | PLASMA PROCESSING APPARATUS INCLUDING ETCHING PROCESSING APPARATUS AND ASHING PROCESSING APPARATUS AND PLASMA PROCESSING METHOD USING PLASMA PROCESSING APPARATUS - A diameter of a mounting unit of the stage of an asking processing apparatus is less than a diameter of a mounting unit of the stage of an etching processing apparatus, and the diameter of the mounting unit of the stage of the etching processing apparatus is less than a diameter of an objective item. | 2010-11-11 |
20100285671 | STRIP WITH REDUCED LOW-K DIELECTRIC DAMAGE - A method for forming etched features in a low-k dielectric layer disposed below the photoresist mask in a plasma processing chamber is provided. Features are etched into the low-k dielectric layer through the photoresist mask. The photoresist mask is stripped, wherein the stripping comprising at least one cycle, wherein each cycle comprises a fluorocarbon stripping phase, comprising flowing a fluorocarbon stripping gas into the plasma processing chamber, forming a plasma from the fluorocarbon stripping gas, and stopping the flow of the fluorocarbon stripping gas into the plasma processing chamber and a reduced fluorocarbon stripping phase, comprising flowing a reduced fluorocarbon stripping gas that has a lower fluorocarbon flow rate than the fluorocarbon stripping gas into the plasma processing chamber, forming the plasma from the reduced fluorocarbon stripping gas, and stopping the flow of the reduced fluorocarbon stripping gas. | 2010-11-11 |
20100285672 | VARIABLE CONFIGURATION APPARATUS - A variable configuration apparatus has components or sub-systems. At least some components ( | 2010-11-11 |
20100285673 | BARREL NUT CONNECTOR ASSEMBLY - A connector assembly comprises a connector having a connector threaded section with threads along a length of an external surface of the connector threaded section; and a barrel nut. The barrel nut comprises a nut threaded section having threads along an internal surface of the nut threaded section, wherein the nut threaded section is barrel shaped having a length and a diameter; a fastening section coupled to the nut threaded section, the fastening section having a length and a non-circular shape comprising a plurality of sides; and a nut circular opening extending through the entire length of the fastening section and the entire length of the nut threaded section; wherein the diameter of the nut threaded section is larger than a diameter of the connector threaded section and smaller than a diameter of an opening in a barrier through which the nut is coupled to the connector. | 2010-11-11 |
20100285674 | APPARATUS FOR TRANSFERRING ELECTRICAL POWER - An apparatus and method for transferring power from a stationary unit to a mobile unit are introduced in order to improve on the existing methods of supplying power to appliances and mobile devices. | 2010-11-11 |
20100285675 | ELECTRICAL CONNECTOR ASSEMBLY HAVING CONNECTORS MOUNTED TO A CIRCUIT BOARD - An electrical connector assembly is configured to be mounted to a circuit board having opposite first and second sides that are interconnected by a board edge. The connector assembly includes first and second connectors disposed along the board edge. The connectors are configured to mate with at least one of mating connectors and a circuit board of an external device to electrically couple the first and second connectors with the external device. Each of the first and second connectors has a center signal contact and a shield shell that extends around the center signal contact. The center signal contact of the first connector engages the first side of the circuit board and the center signal contact of the second connector engages the second side of the circuit board. The first and second connectors mate with the at least one of the mating connectors and the circuit board along parallel mating directions. | 2010-11-11 |
20100285676 | CONNECTION TERMINAL AND TRANSMISSION LINE - A lead terminal includes signal lead pins and GND lead pins. The signal lead pin connects one signal pattern on a flexible substrate and another signal pattern on a rigid substrate. The GND lead pin connects one GND pattern on the flexible substrate and another GND pattern in the rigid substrate. A holding member has an insulating property and holds pairs of the signal lead pins and the GND lead pins at a distance. One main part of the signal lead pin and another main part of the GND lead pin form a microstrip line structure. | 2010-11-11 |
20100285677 | POWER SUPPLY CONNECTOR - A power supply connector is provided, which is applicable to both large current charging and low current charging, the power supply connector being able to not only maintain the accuracy of monitoring low current charging and the volumetric efficiency of a board by appropriately arranging two types of connector parts, but also contribute to the downsizing of the power supply connector and improvement of the reliability thereof by striking a balance between the volumetric efficiency and the heat radiation characteristics, and ensure safety in the use of the power supply connector while reducing the cost. Insertion holes | 2010-11-11 |
20100285678 | MULTIPURPOSE CABLE CONNECTOR - A cable connector assembly comprising an insulating block defining a plurality of cable receiving channels therein. Each cable receiving channel has an entrance at a periphery of the insulating block. A plurality of ground connectors are coupled to the insulating block and positioned such that a ground connector is located proximate to the entrance of each cable receiving channel. Each ground connector comprises a U-shaped member for engaging a ground braid of a heating cable and a grounding screw for engaging a ground wire of a power cable. A ground linking structure electrically connects the plurality of ground connectors. A plurality of first and second wire connectors are adjustably coupled to the insulating block and positioned such that a first wire connector is selectively extendible into a first side of each cable receiving channel and a second wire connector is positioned to selectively extend into a second side of each cable receiving channel. First and second wire linking structures electrically connect the plurality of first wire connectors and the plurality of second wire connectors, respectively. The first and second wire linking structures may comprise leaf springs. | 2010-11-11 |
20100285679 | SPRING BOOT - An electrical terminal connector assembly includes a protective cover for substantially enclosing an electrical terminal on a vehicle component when the assembly is in a connected or disconnected condition. | 2010-11-11 |
20100285680 | TERMINAL FOR ELECTRICAL RESISTANCE ELEMENT - A terminal for electrical resistive elements of molybdenum silicide or alloys of this material, which terminal is arranged to pass through a furnace wall or a furnace ceiling or corresponding insulated wall, where the terminal located at each end of the hot zone of the element has a diameter that is larger than the diameter of the element in the hot zone. The invention is characterised in that a terminal connector is connected to each terminal, in that the terminal connector is made from aluminium, in that the terminal connector has a length that fully or partially constitutes the length of the combined terminal length, where the combined terminal length is the length of the relevant terminal of the element and the terminal connector. | 2010-11-11 |
20100285681 | CONNECTOR HOLDING DEVICE - A connector holding device includes a body-side connector attached to an apparatus body; a cord-side connector for fitting with the body-side connector, provided on the front end of a cord drawn out opposite to the side fitting with the body-side connector; and a connector holding member for holding the cord-side connector, having an opening formed with its cord side smaller than its side fitting with the body-side connector. The device attaches the connector holding member to the apparatus body in a state where the cord-side connector fits with the body-side connector. | 2010-11-11 |
20100285682 | ELECTRICAL CONNECTOR ASSEMBLY WTH IMPROVED LATCHING MECHANISM - An electrical connector assembly ( | 2010-11-11 |
20100285683 | ELECTRICAL CONNECTOR HAVING IMPROVED LATCHING MEANS - An electrical connector ( | 2010-11-11 |
20100285684 | ELECTRICAL CONNECTOR HAVING IMPROVED LATCHING MEMBERS - An electrical connector ( | 2010-11-11 |
20100285685 | ELECTRICAL CONNECTING ELEMENT AND DISK EQUIPPED WITH SUCH AN ELEMENT - Electrical connecting element ( | 2010-11-11 |
20100285686 | INSULATION DISPLACEMENT CONNECTION, AND METHOD FOR CONNECTING TWO COMPONENTS - The invention relates to an insulation displacement connection and to a method for connecting two components, especially for high current applications, said connection comprising a first insulation displacement element, which is fixed to a first component, and a second insulation displacement element, which is fixed to a second component. The two insulation displacement elements can be inserted into each other in the direction of assembly, the first and/or second insulation displacement element being fixed to the first and/or second component in such a way that the insulation displacement element is moveably arranged in a plane transversal to the direction of assembly. | 2010-11-11 |
20100285687 | ELECTRIC PLUG AND METHODS OF PROVIDING THE SAME - Embodiments of electric plugs and related methods are described herein. Other embodiments and related methods are also disclosed herein. | 2010-11-11 |
20100285688 | CABLE CONNECTOR AND CABLE CLAMP - Cable connector including a connector housing and a cable clamp for clamping a cable to the housing. The cable clamp having an intermediate portion between a first and a second mounting portion. At least one of the two mounting portions of the cable clamp is provided with locking means selectively cooperative with at least two matching locking means, such as slots, of the connector housing to hold the cable clamp in respective different positions corresponding to different cable diameters. | 2010-11-11 |
20100285689 | Power strip with 110 and 220 volt outlets - A mechanism that will provide 220 volts AC when the devise is properly plug-in to two home duplex outlets as shown in the attached drawing Figure Two and described in Summery of the Invention. The devise will also provide current in excess of 30 amperes at 110 volts when properly plug-in to two home duplex outlets as shown in the attached drawing Figure Three and described in Summery of the invention. | 2010-11-11 |
20100285690 | INTEGRATED DIN RAIL ATTACHMENT FEATURE FOR OPTIMIZED CONSTRAINT - An electronics module includes a base including a recess adapted to receive an associated mounting rail such as a DIN rail. At least one rail constraining tab is located adjacent a first side of the recess and is adapted to capture a first flange of the associated mounting rail in the recess. First and second flexible resilient latch arms are located adjacent a second side of the recess. The first and second flexible latch arms include respective first and second locking tabs connected thereto, wherein the first and second locking tabs project into the recess and are located to capture a second flange of the associated mounting rail in the recess when the first and second latch arms are in respective latched positions, and wherein the first and second locking tabs are withdrawn from the recess when the first and second latch arms are in respective unlatched positions. The first and second latch arms are located in a common plane and move between their respective latched and unlatched positions in the common plane. | 2010-11-11 |
20100285691 | MODULAR NUT ASSEMBLY - A modular nut assembly includes a substantially cylindrical body portion having a threaded interior surface and an exterior surface. The exterior surface includes a first portion configured for engagement by a mechanical tool and a second portion. A textured ring is configured for engagement by a hand of a user, wherein the second portion is configured to receive the textured ring. | 2010-11-11 |
20100285692 | Electrical Connector Shield with Improved Grounding - An electrical connector is connected to a mated electrical connector through an insertion interface. The electrical connector includes a shielding shell, an insulation body clad with the shielding shell, and several signal terminals received in the insulation body. The insulation body has a mating surface facing the insertion interface. The shielding shell has a first wall. Several ground terminals extend towards the direction of the insertion interface and bent towards the interior of the shielding shell from a mating side of the first wall close to the mating surface, and each ground terminal has a contact portion. Each of the ground terminals of the present invention has an elastic arm with a width nearly the same as that of the electrical connector, so as to provide enough flexibility to ensure the connection stability with the mated electrical connector, and thereby an ideal grounding effect is achieved. | 2010-11-11 |
20100285693 | OVERVOLTAGE PROTECTION MAGAZINE - A connecting strip ( | 2010-11-11 |
20100285694 | CONNECTOR - An electrical connector comprises a support body, first and second metal cases assembled with the support frame, and first and second terminal groups. The support frame comprises a first tongue part, a second tongue part, and a partition part which partitions the first and second tongue parts. The first terminal group is arranged in the first tongue part, and the second terminal group is arranged in the second tongue part. The support frame is sheltered with a metal sheltering casing comprising a front sheltering casing and a back sheltering casing which are assembled together. First and second holding plates extend from the first and second metal casings, the front sheltering casing is provided with notches, the support frame is provided with recesses, so that the first and second holding plates are held in the notches and recesses. | 2010-11-11 |