45th week of 2010 patent applcation highlights part 16 |
Patent application number | Title | Published |
20100283092 | SEMICONDUCTOR DEVICE - The semiconductor device includes a first conductor formed over a semiconductor substrate; a first insulator formed over the first conductor; a second insulator formed over the first insulator, the second insulator having an etching characteristic different from an etching characteristic of the first insulator; a second conductor formed on the second insulator, the second conductor being in contact with the second insulator; a third insulator formed over the second conductor, the third insulator having an etching characteristic different from the etching characteristic of the second insulator; a first contact hole formed through the third insulator and the second conductor, the first contact hole reaching the second insulator; a third conductor formed in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; a second contact hole formed through the third insulator and the first insulator, the second contact hole reaching the first conductor; and a fourth conductor formed in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor. | 2010-11-11 |
20100283093 | Structure and Method to Form EDRAM on SOI Substrate - A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench. | 2010-11-11 |
20100283094 | SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR AND METHOD OF FABRICATING THE SAME - There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively. | 2010-11-11 |
20100283095 | Flash Memory Device - A method of manufacturing a flash memory device is disclosed. The method includes the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region. | 2010-11-11 |
20100283096 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment. | 2010-11-11 |
20100283097 | MOS SEMICONDUCTOR MEMORY DEVICE - The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film | 2010-11-11 |
20100283098 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a plurality of bit line diffusion layers formed in a semiconductor region, and extending in a row direction; a plurality of first insulating films, each being formed on the semiconductor region and between adjacent two of the bit line diffusion layers, and including a charge trapping film; a plurality of bit line insulating films formed above the respective bit line diffusion layers; and a plurality of word lines formed above the semiconductor region to cover the first insulating films and the bit line insulating films, intersecting the bit line diffusion layers, and extending in a column direction. The bit line insulating films have smaller thicknesses than the first insulating films, and upper surfaces of the bit line insulating films are parallel to upper surfaces of the first insulating films. | 2010-11-11 |
20100283099 | Non-Volatile Semiconductor Memory Device and Manufacturing Method Thereof - A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric. | 2010-11-11 |
20100283100 | SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION - A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures. | 2010-11-11 |
20100283101 | PATTERNING NANOCRYSTAL LAYERS - A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with first and second regions with a first device layer. A second device layer including nanocrystals is also formed. A cover layer is provided over the second device layer. The cover layer is patterned to expose portions of the second device layer in the first and second regions. The exposed portions of the second device layer in the first and second regions are processed to form modified portions. The processing of the exposed portions at least reduces the nanocrystals to a diameter below a threshold diameter in the modified portions. The modified portions are removed. | 2010-11-11 |
20100283102 | VERTICAL CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions. | 2010-11-11 |
20100283103 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND DISPLAY APPARATUS - A method for manufacturing a semiconductor device includes: a first step of forming a base layer, which includes an element portion having a gate electrode and a flat interlayer insulating film formed so as to cover the gate electrode; a second step of ion implanting a delamination material into the base layer to form a delamination layer; a third step of bonding the base layer to a substrate; and a fourth step of separating and removing a part of the base layer along the delamination layer. An implantation depth of the delamination material in the gate electrode is substantially the same as that of the delamination material in the interlayer insulating film. | 2010-11-11 |
20100283104 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An element portion forming step includes an insulating film forming step of forming an insulating film on a surface of a base layer, a conductive layer forming step of uniformly forming a conductive layer on a surface of the insulating film, and an electrode forming step of patterning the conductive layer to form an electrode. A delamination layer forming step of ion implanting a delamination material into the base layer to form a delamination layer is performed before the electrode forming step. | 2010-11-11 |
20100283105 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer. | 2010-11-11 |
20100283106 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR LAYER ON INSULATING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer. | 2010-11-11 |
20100283107 | MOS Transistor With Better Short Channel Effect Control and Corresponding Manufacturing Method - The integrated circuit comprises at least one MOS transistor (T) including a gate (GR) having a bottom part in contact with the gate oxide. Said bottom part has an inhomogeneous work function (WFB, WFA) along the length of the gate between the source and drain regions, the value of the work function being greater at the extremities of the gate than in the centre of the gate. The gate comprises a first material (A) in the centre and a second material (B) in the remaining part. Such configuration is obtained for example by silicidation. | 2010-11-11 |
20100283108 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced. | 2010-11-11 |
20100283109 | MOSFET HAVING A CHANNEL MECHANICALLY STRESSED BY AN EPITAXIALLY GROWN, HIGH K STRAIN LAYER - A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material. | 2010-11-11 |
20100283110 | INTEGRATED SENSOR CHIP UNIT - An integrated sensor chip unit and fabrication method includes a measured-value pickup for determining measurement data and a circuit arrangement for enabling a wireless power supply and interrogation of the measurement data. The measured-value pickup is formed as an integratable sensor, and the circuit arrangement is formed as an integrated semiconductor circuit module. The sensor and the semiconductor circuit module are mechanically and electrically conductively connected to one another using one or more microsystems engineering techniques. | 2010-11-11 |
20100283111 | Photo detector - Disclosed is an improved photo detector, which includes a substrate, a light reception chip, and a coating layer. The substrate includes a first electrode member and a second electrode member. The light reception chip is set on the substrate and is electrically connected to the first and second electrode members of the substrate. The coating layer is formed on the light reception chip and functions to filter out visible light and allows only invisible light to transmit therethrough. As such, efficacies of receiving only visible light and minimizing the overall size can be realized. | 2010-11-11 |
20100283112 | Light Guide Array for An Image Sensor - An image sensor pixel that includes a photoelectric conversion unit ( | 2010-11-11 |
20100283113 | WAFER SCALE ARRAY OF OPTICAL PACKAGE AND METHOD FOR FABRICATING THE SAME - A wafer-scale array of optical packages and a method for fabricating the same. The wafer-scale array of optical packages includes at least one wafer-scale array of lens structures, including a wafer-scale array of first barrel structures and a wafer-scale array of lenses directly formed on the wafer-scale array of first barrel structures such that the wafer-scale array of lenses is integrally combined with the wafer-scale array of first barrel structures, the wafer-scale array of first barrel structures being made of a material different from a material of the lens of the wafer-scale array of lenses; and at least one wafer-scale array of second barrel structures stacked on and combined with the at least one wafer-scale array of lens structures. | 2010-11-11 |
20100283114 | CHIP-TYPE SEMICONDUCTOR CERAMIC ELECTRONIC COMPONENT - A chip-type semiconductor ceramic electronic component including a ceramic body made of a semiconductor ceramic, first external electrodes formed on opposite end surfaces of the ceramic body, and second external electrodes extending to cover surfaces of the first external electrodes and part of side surfaces of the ceramic body. A curvature radius of a corner portion of the ceramic body is R (μm), a maximum thickness of a layer of the first external electrode layer, which is in contact with the ceramic body, measured from the end surface of the ceramic body is y (μm), and a minimum thickness of a layer of the second external electrode, which is in contact with the side surface of the ceramic body, measured from an apex of the corner portion of the ceramic body is x (μm), and 20≦R≦50, −0.4 x+0.6≦y≦0.4 is satisfied when 0.5≦x≦1.1, and −0.0076 x+0.16836≦y≦0.4 is satisfied when 1.1≦x≦9.0. | 2010-11-11 |
20100283115 | SCHOTTKY DIODE WITH IMPROVED HIGH CURRENT BEHAVIOR AND METHOD FOR ITS PRODUCTION - In the diffusion region ( | 2010-11-11 |
20100283116 | SEMICONDUCTOR DEVICE DRIVING BRIDGE-CONNECTED POWER TRANSISTOR - A semiconductor device includes a low-side circuit, high-side circuit, a virtual ground potential pad, a common ground potential pad and a diode, formed on a semiconductor substrate. The low-side circuit drives a low-side power transistor. The high-side circuit is provided at a high potential region, and drives a high-side power transistor. The virtual ground potential pad is arranged at the high potential region, and coupled to a connection node of both power transistors to supply a virtual ground potential to the high-side circuit. The common ground potential pad supplies a common ground potential to the low-side circuit and high-side circuit. The diode has its cathode connected to the virtual ground potential pad and its anode connected to the common ground potential pad. | 2010-11-11 |
20100283117 | FUSE BOX GUARD RINGS INCLUDING PROTRUSIONS AND METHODS OF FORMING SAME - A structure included in a semiconductor device can include a fuse box guard ring that defines an interior region of the fuse box inside the fuse box guard ring and that defines an exterior region of the fuse box outside the fuse box guard ring. The fuse box guard ring can include protruding support members that protruding from an interior sidewall or from an exterior sidewall of the fuse box guard ring. | 2010-11-11 |
20100283118 | OXIDATION AFTER OXIDE DISSOLUTION - A method for manufacturing a SeOI substrate that includes a thin working layer made from one or more semiconductor material(s); a support layer; and a thin buried oxide layer between the working layer and the support layer. The method includes a manufacturing step of an intermediate SeOI substrate having a buried oxide layer with a thickness greater than a thickness desired for the thin buried oxide layer; and a dissolution step of the buried oxide layer in order to form therewith the thin buried oxide layer. After the dissolution step, an oxidation step of the substrate is conducted for creating an oxidized layer on the substrate, and an oxide migration step for diffusing at least a part of the oxide layer through the working layer in order to increase the electrical interface quality of the substrate and decrease its Dit value. | 2010-11-11 |
20100283119 | Semiconductor Device Including a Deep Contact and a Method of Manufacturing Such a Device - A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped. | 2010-11-11 |
20100283120 | FUSE CHAMBERS ON A SUBSTRATE - Embodiments of a system with first means for forming a chamber adjacent to a component formed on a substrate and a single orifice between the chamber and a first surface of the first means that is opposite a second surface of the first means adjacent to the substrate and second means for enclosing the chamber on at least a portion of the first surface that encompasses the single orifice are disclosed. | 2010-11-11 |
20100283121 | ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors. | 2010-11-11 |
20100283122 | SYSTEMS AND METHODS FOR PROVIDING HIGH-DENSITY CAPACITORS - The present invention describes systems and methods for providing high-density capacitors. An exemplary embodiment of the present invention provides a high-density capacitor system comprising a substrate and a porous conductive layer formed on the substrate, wherein the porous conductive layer is formed in accordance with a predetermined pattern. Furthermore, the high-density capacitor system includes a dielectric material formed on the porous conductive layer and a second conductive layer formed on the dielectric material. Additionally, the high-density capacitor system includes a plurality of conductive pads configured in communication with the second conductive layer. | 2010-11-11 |
20100283123 | BIPOLAR JUNCTION TRANSISTOR INTEGRATED WITH PIP CAPACITOR AND METHOD FOR MAKING THE SAME - A bipolar junction transistor (BJT) integrated with a PIP capacitor includes a substrate including a bipolarjunction transistor region and a PIP capacitor region, a bipolar junction transistor disposed in the bipolar junction transistor region and extending an isolation layer to the PIP capacitor region and a base poly layer disposed on the isolation layer, and a PIP capacitor disposed in the PIP capacitor region and including a lower poly layer, the isolation layer and the base poly layer to selectively form a PIP capacitor. | 2010-11-11 |
20100283124 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which impedances of power-supply wiring/GND wiring are matched with each other inside the semiconductor device to reduce a noise current without depending on a mounting layout of a circuit board. In a semiconductor device according to a typical embodiment of the present invention including: a package board; a semiconductor chip; a power-supply wiring; and a GND wiring, the semiconductor device includes a conductive plate, and further includes a first impedance adjusting element and a second impedance adjusting element. Parasitic capacitances of the power-supply wiring and the GND wiring are determined by the conductive plate, and the impedances of the power-supply wiring and the GND wiring are adjusted by the first impedance adjusting element and the second impedance adjusting element. | 2010-11-11 |
20100283125 | Semiconductor device and method of manufacturing the same - The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode. | 2010-11-11 |
20100283126 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate that is made of either of silicon carbide (SiC) and gallium nitride (GaN), and has a defect region containing a crystal defect; a first insulating film that coats the defect region and is arranged on the semiconductor substrate; and a conductor film that electrically connects to a principal surface of the semiconductor substrate, the principal surface being exposed to a region that is not coated with the first insulating film. | 2010-11-11 |
20100283127 | METHOD FOR PACKING SEMICONDUCTOR COMPONENTS AND PRODUCT PRODUCED ACCORDING TO THE METHOD - A method for packing semiconductor components is provided, in which a first side of a first wafer is connected to at least one further wafer, wherein at least one of the wafers has a plurality a semiconductor circuits and wherein trenches are made in the second side of the first wafer opposite to the first side and divide the first wafer into a plurality of parts, which are separated from one another by the trenches, but are connected mechanically to one another by means of the at least one further wafer, and wherein the connecting region between the first wafer and the at least one further wafer has been or will be laterally exposed in the trenches. A coating that covers the connecting region is then applied to the regions of the trenches in which the connecting region is exposed. | 2010-11-11 |
20100283128 | Dicing Structures for Semiconductor Substrates and Methods of Fabrication Thereof - Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street. | 2010-11-11 |
20100283129 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An upper surface of a semiconductor substrate includes a first portion where a dielectric film is provided, and a second portion where the dielectric film is not provided, wherein the second portion is located in the periphery of the first portion. The upper surface of the semiconductor substrate is covered with a sealing resin. | 2010-11-11 |
20100283130 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate having a first surface as a surface on which an element is formed, and a second surface opposite to the first surface; a through hole formed so as to extend through the semiconductor substrate from the first surface to the second surface; an insulating film formed on an inner wall of the through hole; and a conductive portion formed in a space surrounded by the insulating film in the through hole. The insulating film continuously extends on the inner wall of the through hole and on the second surface. | 2010-11-11 |
20100283131 | Discontinuous Thin Semiconductor Wafer Surface Features - A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers. | 2010-11-11 |
20100283132 | ECR-plasma source and methods for treatment of semiconductor structures - The invention relates to microelectronics, more particularly, to methods of manufacturing solid-state devices and integrated circuits utilizing microwave plasma enhancement under conditions of electron cyclotron resonance (ECR), as well as to use of plasma treatment technology in manufacturing of different semiconductor structures. Also proposed are semiconductor device and integrated circuit and methods for their manufacturing. Technical result consists in improvement of reproducibility parameters of semiconductor structures and devices processed, enhancement of devices parameters, elimination of possibility of defects formation in different regions, and speeding-up of the treatment process. | 2010-11-11 |
20100283133 | FILM-FORMING COMPOSITION, INSULATING FILM WITH LOW DIELECTRIC CONSTANT, FORMATION METHOD THEREOF, AND SEMICONDUCTOR DEVICE - In the invention, a silica sol prepared by hydrolyzing and condensing a silane compound represented by the following formula: Si(OR | 2010-11-11 |
20100283134 | High Power Ceramic on Copper Package - According to an embodiment of a high power package, the package includes a copper heat sink, a ceramic lead frame and a semiconductor chip. The copper heat sink has a thermal conductivity of at least 350 W/m K. The ceramic lead frame is attached to the copper heat sink with an epoxy. The semiconductor chip is attached to the copper heat sink on the same side as the lead frame with an electrically conductive material having a melting point of about 280° C. or greater. | 2010-11-11 |
20100283135 | LEAD FRAME FOR SEMICONDUCTOR DEVICE - A lead frame including a lead frame structure having a die support area and a plurality of electrical contact areas has shallow recesses formed on a surface of the lead frame structure. | 2010-11-11 |
20100283136 | QFN SEMICONDUCTOR PACKAGE - A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the extended, outer terminal lead. | 2010-11-11 |
20100283137 | QFN SEMICONDUCTOR PACKAGE - A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a trace interconnecting the intermediary terminal to the extended, outer terminal lead. | 2010-11-11 |
20100283138 | Nickel-Based Bonding of Semiconductor Wafers - A nickel-based material is used on one or both wafers to be bonded, and the two wafers are bonded at low temperature and pressure through interdiffusion of the nickel-based material with either another nickel-based material or aluminum. In various embodiments, nickel-based walls are formed on one wafer, and corresponding walls are formed on the other wafer from a nickel-based material or aluminum. The walls of the two wafers are placed in contact with one another under sufficient pressure and temperature to cause bonding of the walls through interdiffusion. | 2010-11-11 |
20100283139 | Semiconductor Device Package Having Chip With Conductive Layer - The present invention relates to a semiconductor device package having a chip with a conductive layer. The semiconductor device package includes a substrate, a chip, at least one first electrical connecting element and at least one second electrical connecting element. The substrate has a first surface and a first circuit layer. The first circuit layer is disposed adjacent to the first surface. The chip is attached to the substrate and has a surface, at least one first pad, a plurality of second pads and a conductive layer. The first pad, the second pads and the conductive layer are disposed adjacent to the surface, and the conductive layer connects the second pads. | 2010-11-11 |
20100283140 | PACKAGE ON PACKAGE TO PREVENT CIRCUIT PATTERN LIFT DEFECT AND METHOD OF FABRICATING THE SAME - A package on package includes a lower semiconductor package including a plurality of stacked semiconductor chips, a connection portion including an electrically-conductive lead having a height lower than that of an encapsulation member, and an upper semiconductor package connected to the connection portion of the lower semiconductor package via a solder ball in a fan-in structure. | 2010-11-11 |
20100283141 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package includes a chip; first and second connection pads arranged in a matrix and disposed about the chip, and the first and second connection pads have different bottom surface shapes when viewed from a bottom of the QFN package; bonding pads provided on an active surface of the chip and being electrically connected with corresponding said connection pads through bonding wires; and a package body encapsulating the chip, the bonding wires and an upper portion of each of the connection pads such that a lower portion of each of the connection pads extends outward from a bottom of the package body. | 2010-11-11 |
20100283142 | MOLD LOCK ON HEAT SPREADER - A mold lock and a method of forming the mold lock are provided. The mold lock is used in an encapsulated semiconductor device and includes a neck and a shaped head integral with the neck. The mold lock can be formed to project above a support component, such as a heat spreader, of the semiconductor device and the neck is formed from the support component. The shaped head is of a greater dimension than the neck and can present a “T” shape in side view or a “Y” shape in side view. A base portion of the neck is seated within the support component. A method is provided for forming the described mold lock. | 2010-11-11 |
20100283143 | Die Exposed Chip Package - This disclosure describes a chip package. In one embodiment, a semiconductor chip package includes a thermal dissipater placed on top of an integrated-circuit die, the thermal dissipater having a same or similar coefficient of thermal expansion as that of the integrated-circuit die. | 2010-11-11 |
20100283144 | IN-SITU CAVITY CIRCUIT PACKAGE - A flip chip semiconductor packaging device and method that incorporates in situ formation of cavities underneath selected portions of a die during a flip chip die bonding process. A method of flip chip semiconductor component packaging includes providing a die having a first surface, forming a barrier on first surface of the die, the barrier at least partially surrounding a designated location on the first surface of the die, bonding the die to a substrate in a flip chip configuration, and flowing molding compound over the die and over at least a portion of the substrate. Bonding the die to the substrate includes causing contact between the barrier and the substrate such that flow of the molding compound is blocked by the barrier to provide a cavity between the die and the substrate, the cavity being proximate the designated location on the first surface of the die. | 2010-11-11 |
20100283145 | Stack structure with copper bumps - A stack structure with copper bumps on an integrated circuit board is disclosed. The stack structure includes a plurality of insulating layers and a plurality of conductive layers which are stacked alternately. The uppermost conductive layer has copper bumps as copper pillar pins for soldering the chip pins of an integrated circuit chip. Because the copper bumps have a certain height, the distance between the copper bumps and the chip pins is shortened, and therefore the solders needed for soldering may be reduced. Also, the shape of the solders is a long strap instead of spheroid due to the cohesion force between the copper bump surfaces and the solders so that the distance between the solders is scaled down and the gaps between the pins are reduced. Thus, the entire size of the integrated circuit board may also be miniatured. | 2010-11-11 |
20100283146 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure. | 2010-11-11 |
20100283147 | METHOD FOR PRODUCING A PLURALITY OF CHIPS AND A CHIP PRODUCED ACCORDINGLY - A production method for chips, in which as many method steps as possible are carried out in the wafer composite, that is, in parallel for a plurality of chips disposed on a wafer. This is a method for producing a plurality of chips whose functionality is implemented on the basis of the surface layer of a substrate. In this method, the surface layer is patterned and at least one cavity is produced below the surface layer, so that the individual chip regions are connected to each other and/or to the rest of the substrate by suspension webs only, and/or so that the individual chip regions are connected to the substrate layer below the cavity via supporting elements in the region of the cavity. The suspension webs and/or supporting elements are cut when the chips are separated. The patterned and undercut surface layer of the substrate is embedded in a plastic mass before the chips are separated. | 2010-11-11 |
20100283148 | Bump Pad Structure - An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad. | 2010-11-11 |
20100283149 | STRUCTURE AND METHOD OF FORMING A PAD STRUCTURE HAVING ENHANCED RELIABILITY - A semiconductor substrate is provided having a first metal layer formed over a first insulating layer. A second insulating layer is formed having a first damascene opening, the first opening having a second insulating layer portion formed therein. A resist layer is deposited to fill the first opening and the resist layer is thereafter patterned to form an etching mask for etching a second damascene opening. The second opening is etched into a portion of the second insulating layer, the second opening exposing a portion of the first metal layer. A second metal layer is formed to include filling the first and second damascene openings embedding the second insulating layer portion in the second metal layer. The second metal layer is planarized and a passivation layer is formed above the second insulating layer and the second metal layer, wherein the passivation layer partially covers the second metal layer. | 2010-11-11 |
20100283150 | Semiconductor device - The present invention provides a method for forming a semiconductor device, which comprises the steps of preparing a semiconductor wafer including an electrode pad, an insulating film formed with a through hole and a bedding metal layer which are formed in a semiconductor substrate, forming a first resist mask which exposes each area for forming a redistribution wiring, over the bedding metal layer, forming a redistribution wiring connected to the electrode pad and extending in an electrode forming area for a post electrode with the first resist mask as a mask, removing the first resist mask by a dissolving solution to expose each area excluding the electrode forming area for the redistribution wiring and forming a second resist mask disposed with being separated from each side surface of the redistribution wiring, forming a redistribution wiring protective metal film over upper and side surfaces of the exposed redistribution wiring with the second resist mask as a mask, removing the second resist mask by a dissolving solution, attaching a dry film over the semiconductor wafer and exposing the electrode forming area lying over the redistribution wiring, forming a post electrode in the electrode forming area with the dry film as a mask, removing the dry film by a removal solvent, and removing the redistribution wiring protective metal film after the removal of the dry film. | 2010-11-11 |
20100283151 | TECHNIQUES FOR PACKAGING MULTIPLE DEVICE COMPONENTS - Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package. | 2010-11-11 |
20100283152 | INTEGRATED CIRCUITS INCLUDING ILD STRUCTURE, SYSTEMS, AND FABRICATION METHODS THEREOF - An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 Å or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure. | 2010-11-11 |
20100283153 | Ohmic Contact Having Silver Material - An ohmic contact is fabricated. The ohmic contact has low electric resistivity and high thermal conductivity. The materials for fabricating the ohmic contact include silver. Thus, equipments for fabricating the ohmic contact are compatible to modern generally used equipments. | 2010-11-11 |
20100283154 | SPUTTERING TARGET AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME - A sputtering target includes a tungsten (W)-nickel (Ni) alloy, wherein the nickel (Ni) is present in an amount of between about 0.01 weight % and about 1 weight %. | 2010-11-11 |
20100283155 | Methods Of Forming A Plurality Of Conductive Lines In The Fabrication Of Integrated Circuitry, Methods Of Forming An Array Of Conductive Lines, And Integrated Circuitry - A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated. | 2010-11-11 |
20100283156 | SEMICONDUCTOR DEVICE - A semiconductor device in which size reduction is possible without functional devices below pads being damaged by stress. The semiconductor device has a plurality of pads above a semiconductor substrate as terminals for external connection. A plurality of dual use pads which are used in both a probing test and assembly are provided in a first area above a main surface of the semiconductor substrate, an application of pressure by a probe during the probing test being permitted in the first area, and a plurality of assembly pads which are not used in the probing test are provided in a second area above the main surface of the semiconductor substrate, the application of pressure by the probe during the probing test being not permitted in the second area. | 2010-11-11 |
20100283157 | INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME - The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material. | 2010-11-11 |
20100283158 | STRUCTURE AND METHOD FOR FORMING A CAPACITIVELY COUPLED CHIP-TO-CHIP SIGNALING INTERFACE - A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad. | 2010-11-11 |
20100283159 | Circuit Substrate and Method for Utilizing Packaging of the Circuit Substrate - A circuit substrate and the method for fabricating a packaging of the circuit substrate are provided. A plurality of electrodes are formed on the surface of the circuit substrate, the electrodes are formed with fork structures over an connection section of the circuit substrate, so that when the circuit substrate expands/contracts due to thermal processes, the probability of alignment with electrodes of an external circuit board is increased by easily detaching the fork structure overlapping an electrode of the external circuit board which is not corresponding to the fork structure of the electrode of the circuit substrate, so as to avoid short circuit. Thus, electrode misalignment due to electrode pitch variation of the traditional circuit substrate as a result of thermal deformation can be effectively eliminated. | 2010-11-11 |
20100283160 | Panelized Backside Processing for Thin Semiconductors - A semiconductor manufacturing method includes attaching a first die to a substrate panel. The method also includes applying a mold compound after attaching the first die to the substrate panel to the first die and the substrate panel. The method further includes thinning the first die and the mold compound after applying the mold compound. Attaching the die to the substrate panel before thinning eliminates usage of a carrier wafer when processing thin semiconductors. | 2010-11-11 |
20100283161 | Carburetor for an Internal Combustion Engine - A carburetor for an internal combustion engine has a carburetor housing and a mixture forming passage provided in the carburetor housing. A throttle and a choke valve are rotatably arranged in the mixture forming passage on a throttle shaft and a choke shaft, respectively. A lever arrangement has a throttle adjusting lever mounted on the throttle shaft and a choke adjusting lever mounted on the choke shaft. The throttle valve and the choke valve are adjustable in several operating positions and the lever arrangement assumes appropriate positions corresponding to the operational positions, respectively. A release device for releasing a locking action between the throttle adjusting lever and the choke adjusting lever when an emergency stop is actuated is provided. A spring forcing the choke adjusting lever in a direction toward an engagement plane with the throttle adjusting lever. | 2010-11-11 |
20100283162 | METHOD AND APPARATUS FOR CONTROLLED AERATION OF LIQUID MEDIUM IN A PIPE - An apparatus and method for mixing gas and liquid comprising a pipe having an enclosure positioned in-line with said pipe, wherein a sealed space is defined, at least one blower, said blower regulates the barometric pressure in said sealed space at or above fluid line pressure in the pipe, wherein intermeshed rotating sets of discs operate on parallel shafts driven by variable speed drives, and strakes are radially mounted on the discs to carry liquid up into a mixing area and to carry air and liquid down into a mixing area resulting in a shear force that drives air into the oxygen depleted liquid. Strakes provide leading and trailing rotor wipes to maximize pull of liquid flow from the pipe into the mixing area and back into the pipe and acute angled energy capture strakes for capturing the energy from liquid flow exerted against the back side of strake. | 2010-11-11 |
20100283163 | FLEXIBLE AERATION PANEL AND METHODS OF USE - A flexible aeration panel is described, which does not include a rigid support plate. The flexible aeration panel can comprise a first perforated, flexible sheet sealed to a second non-perforated flexible sheet at their peripheral edges, thereby defining one or more cavities that are in fluid communication with at least one gas inlet. The flexible aeration panel can be configured to produce preferably evenly spaced bubbles of gas when positioned in a liquid body. Applications include, but are not limited to, aeration of wastewater, lakes, streams, water basins and the like. | 2010-11-11 |
20100283164 | Ocular Lens - A method of making an ocular lens device (and resulting lens device) from a polyolefin copolymer material having a crosslinking component, wherein the material is processed to remove unwanted reaction byproducts that can contribute to reduced transparency of the polyolefin copolymer material in the ocular environment of the eye. | 2010-11-11 |
20100283165 | METHOD OF FABRICATING A MOLD AND METHOD OF PRODUCING AN ANTIREFLECTION FILM USING THE MOLD - A motheye mold fabrication method of at least one embodiment of the present invention includes the steps of: (a) preparing an Al base in which an Al content is less than 99.99 mass %; (b) partially anodizing the Al base to form a porous alumina layer which has a plurality of very small recessed portions; (c) after step (b), allowing the porous alumina layer to be in contact with an etchant which contains an anodic inhibitor, thereby enlarging the plurality of very small recessed portions of the porous alumina layer; and (d) after step (c), further anodizing the Al base to grow the plurality of very small recessed portions. | 2010-11-11 |
20100283166 | Process and apparatus for the production of microcapsules - The present invention relates to an apparatus and a method for producing microcapsules. The apparatus according to the invention comprises at least one bead generator, having at least one nozzle passed by a liquid during operation, with a liquid reservoir arranged before the nozzle. The liquid reservoir comprises a membrane in the region of at least one boundary wall for generating a mechanical oscillation in the liquid. The apparatus comprises at least one reaction and transport device passed by a reaction medium, in which the beads generated in the bead generator are received. Microcapsules are formed during a predetermined reaction time period between at least one first polymeric component of the beads and at least one second polymeric component in the reaction medium and are transported along a reaction path. The apparatus is characterized in that at least one electrode, movable substantially parallel to the nozzle axis by a drive, is arranged between the bead generator and the reaction and transport device, which generates an electric field between an outlet region of the nozzle and the electrode for influencing the bead properties. The invention further includes a use of the apparatus for producing microcapsules and a method for controlling the apparatus. | 2010-11-11 |
20100283167 | METHODS OF MAKING CERAMIC FIBERS AND BEADS - Methods of making ceramic fibers and beads are disclosed. | 2010-11-11 |
20100283168 | Systems and Methods for Setting Prosthetic Posterior Teeth in Denture Production - Systems and methods for setting posterior prosthetic teeth in production of upper and lower dentures feature tooth blocks each having inner and outer bodies having upper and lower rows of recesses therein corresponding maxillary and mandibular prosthetic teeth. The recesses of the inner and outer bodies conform to lingual and buccul surfaces of the prosthetic teeth respectively and are shaped and positioned to establish proper positioning of the prosthetic teeth relative to one another when clamped between the bodies. The two tooth blocks accommodate respective ones of left and right prosthetic poster teeth sets. Connection elements between the tooth blocks allow adjustment and subsequent locking of the relative positioning between the left and right teeth sets before setting on mandibular and maxillary casts in an articulator. The two tooth blocks eliminate the need to individually position posterior teeth on each side of the jaw. | 2010-11-11 |
20100283169 | Electrolytic cell diaphragm/membrane - This invention is directed toward process and material optimization of electrolytic cell separation processes designed to generate consistent electrolytic solutions in a better salt-converting and efficient manner, as well as to increase the amount of free available chlorine generated by the electro-chemical activation of the salt. This is generally accomplished by provision of ceramic diaphragm and/or polymer membranes characterized by optimal design, construction, manufacturing, and assemblage to exacting and precise specifications with respect to chemical and material compositions, slurry formulations, ceramic mold tolerances, ceramic firing and curing conditions, dimensional measurements for thickness, dimensional measurements for gapping and placement between the anode and cathode electrodes, and machining tolerance control. | 2010-11-11 |
20100283170 | FABRICATING METHOD FOR SLEEVE-TYPE ORNAMENT OF DISPLAY DEVICE - The present invention provides a fabricating method for sleeve-type ornament of display device, comprising the steps of: a step of providing a display device, a 3D image file is provided with respect to the display device; a step of shaping an ornament, the surface of the decoration portion of the display device is shaped with a shaping material, so a layer of original ornament mold is formed on the surface of the decoration portion of the display device; a step of scanning the original ornament mold, a scanner is used to scan the shape of the original ornament mold, and the obtained data is transferred to a computer for establishing a 3D image file of the original ornament mold; a step of establishing a 3D image file of the ornament, the scanned 3D image file of the original ornament mold and the 3D image file of the display device are opened through a software in a computer, and the images of the two 3D image files are overlapped, part of the image of the display device that is overlapped within the image of the original ornament mold is removed through a command, so a 3D image file of the ornament, excluding the display device, is obtained; and a step of model fabrication, the 3D image file of the ornament is encoded to a compiler code that is recognizable for a molding machine for fabricating an ornament model. | 2010-11-11 |
20100283171 | Self-Repairing Concrete Having Carbamide Resin Polymer Micro-Capsules and Method for Fabricating Same - A self-repairing concrete includes carbamide resin polymer micro-capsules, in which the carbamide resin polymer micro-capsules are mixed for a fixed function of micro-cracks. The quality mixture ratio is: concrete/micro capsules/water=100:1-15:15-50. The manufacturing method is weighing a full amount of water in a container, adding carbamide resin polymer micro-capsules, stirring, until fully dispersed microcapsules; pouring the water into the mixing container, adding the corresponding quality of cement; stirring; adding sand and gravel filling materials, conducting worksite watering, ⅓ volume for each time, vibrating, and air exhausting; until the slurry filling mold. | 2010-11-11 |
20100283172 | CONSUMABLE ASSEMBLY FOR USE IN EXTRUSION-BASED LAYERED DEPOSITION SYSTEMS - A consumable assembly comprising a container portion configured to retain a supply of filament, a guide tube connected to the container portion, and a pump portion connected to the guide tube. | 2010-11-11 |
20100283173 | METHOD AND APPARATUS FOR EXTRUSION OF THERMOPLASTIC HANDRAIL - A method and apparatus for extrusion of an article is provided. A die assembly can apply flows of thermoplastic material to an array of reinforcing cables to form a composite extrusion. A slider fabric can be bonded to one side of the composite extrusion. After exiting the die assembly, the slider fabric can act to support the extrudate as it passes along an elongate mandrel, which can cause the base of the slider fabric to change shape from a flat profile to the final internal profile of the article. The extruded article can then be cooled to solidify the material. The die can include cooling for the slider fabric and means for promoting penetration of the thermoplastic into reinforcing cables. | 2010-11-11 |
20100283174 | Fabrication of polymer grafted carbon nanotubes/polypropylene composite bipolar plates for fuel cell - A composite bipolar plate for a proton exchange membrane fuel cell (PEMFC) is prepared as follows: a) melt compounding a polypropylene resin and graphite powder to form a melt compounding material, the graphite powder content ranging from 50 wt % to 95 wt % based on the total weight of the melt compounding material and the polypropylene resin being a homopolymer of propylene or a random copolymer of propylene and ethylene, butylenes or hexalene, wherein 0.01-15 wt % of polymer-grafted carbon nanotubes by an acyl chlorination-amidization reaction, based on the weight of the polypropylene resin, are added during the compounding; and b) molding the melt compounding material from step a) to form a bipolar plates having a desired shaped at 100-250° C. and 500-4000 psi. | 2010-11-11 |
20100283175 | COEXTRUDED POLYMER MOLDING HAVING SELECTIVELY NOTCHED CARRIER - A coextruded polymer molding product includes a notched structural carrier and a polymer seal material over the structural carrier. The structural carrier has notches along its length A first plurality of specific regions of the structural carrier have notches. A second plurality of specific regions of the structural carrier are relieved from having notches. The notched regions and relieved regions are arranged with respect to each other such that consecutive notched regions are spaced apart at non-uniform intervals to provide desired bending characteristics for conforming to a specific molding application. | 2010-11-11 |
20100283176 | FORMING HEAD FOR DRY FORMING A FIBROUS WEB - The invention relates to a forming head for dry forming a fibrous web, which forming head is positioned above a forming wire opposite a suction unit. The forming head is divided into at least two independent interconnected distribution units, each of which comprises at least one revolving roller provided with protruding spikes. By dividing the forming head into a plurality of interconnected distribution units, a more efficient disintegration of agglomerates, shadows and/or lumps in the fibre material is achieved compared to the known forming heads, thereby ensuring a more homogenous final product. | 2010-11-11 |
20100283177 | PROCESS FOR PRODUCING PRECURSOR FILM FOR RETARDATION FILM MADE OF POLYPROPYLENE RESIN - There is provided a process for producing a precursor film for a polypropylene-based resin retardation film that can yield films with almost no orientation and with high transparency. | 2010-11-11 |
20100283178 | PROCESS FOR PRODUCING SOFT CAPSULE SHELLS BASED ON POLYVINYL ALCOHOL-POLYETHYLENE GLYCOL GRAFT COPOLYMERS - A process for producing gelatin-free soft capsule shells based on polyvinyl alcohol-polyether graft copolymers as shell polymers, which comprises heating an aqueous solution comprising at least 45% by weight, based on the total weight of the solution, of a polymer component, where the polymer component consists of a polyvinyl alcohol-polyether graft copolymer or a mixture of polyvinyl alcohol-polyether graft copolymers and polyvinyl alcohol, extruding the solution at a temperature of at least 70° C., and solidifying the resulting film by cooling. | 2010-11-11 |
20100283179 | Method of Fabricating Metal Nitrogen Oxide Thin Film Structure - A TiON, TaON or ZrON thin film is fabricated through an easy process. The film is corrosion resistant, electric conductive and decorative. The process uses no chloride (Cl) and so is environmental protected. The present disclosure is fit for mass production. | 2010-11-11 |
20100283180 | APPARATUS FOR THE INFUSION OF RESIN INTO A PREFORM IN A CLOSED MOULD - A tool for the infusion of a resin into a preform made of fibre material includes a mould which can be closed around the preform and in the body of which at least one inlet duct is formed to allow resin to be injected into the mould so that the resin can be infused into the preform. At least one reservoir which can contain the resin, is also formed in the body of the mould and is connected to the at least one inlet duct. The mould can be inserted in an autoclave and the reservoir is configured to permit the transfer of the resin from the reservoir to the inlet duct under the effect of the temperature and of the pressure that are produced in the autoclave, thus allowing the resin to be injected into the mould. | 2010-11-11 |
20100283181 | MOULD SYSTEM FOR MAKING A PARTITION IN A CARDBOARD-BASED CONTAINER - The invention relates to a mould system ( | 2010-11-11 |
20100283182 | MOULD SYSTEM FOR MANUFACTURING A CONTAINER - The invention relates to a mould system ( | 2010-11-11 |
20100283183 | ENZYME-MEDICATED CROSS-LINKING OF SILICONE POLYMERS - Disclosure herein are methods of preparing cross-linked silicone polymers by contacting a silicone polymer and optionally a cross-linking agent with a hydrolytic enzyme under conditions for the cross-linking of the silicone polymer, wherein the silicone polymer has been modified to comprise functional groups that react with the hydrolytic enzyme. | 2010-11-11 |
20100283184 | PROCESS FOR PRODUCING MEDICAL IMPLANT OR MEDICAL IMPLANT PART COMPRISING POROUS UHMWPE - The invention provides a medical implant or medical implant part comprising porous ultrahigh molecular weight polyethylene having a weight average molecular weight of about 400,000 atomic mass units or more and a porosity of about 15% to about 65%. The invention further provides a process for producing a medical implant or medical implant part. | 2010-11-11 |
20100283185 | STAMPER MANUFACTURING METHOD, STAMPER, AND MOLDING MANUFACTURING METHOD - A method of manufacturing a stamper includes setting a straight plate member to a die having a cavity, the plate member having a formation surface on which a predetermined pattern structure is formed, and feeding a continuous body into the cavity and pressurizing the plate member with the continuous body, to deform an entire shape of the formation surface of the plate member set to the die into a shape corresponding to the cavity. | 2010-11-11 |
20100283186 | METHOD AND DEVICE FOR CONTROLLING A LINEAR MOTION AXIS - The invention relates to a method and device for controlling a linear motion axis, particularly of the injection screw ( | 2010-11-11 |
20100283187 | NOVEL MATERIAL FOR INFRARED LASER ABLATED ENGRAVED FLEXOGRAPHIC PRINTING PLATES - A non-photosensitive flexographic liquid or paste precursor comprising a mixture of acrylate oligomers and acrylic or methacrylate monomers, infrared absorbing material, fillers and heat decomposable peroxide, which when heated forms a non-thermoplastic elastomeric solid material in the form of a flexographic printing blank engraveable by infrared laser ablation. | 2010-11-11 |
20100283188 | METHOD AND DEVICE FOR THE GENERATIVE PRODUCTION OF A SHAPED BODY HAVING NON-PLANAR LAYERS - The present invention relates to a method for the generative production of a shaped body ( | 2010-11-11 |
20100283189 | BUBBLE LAUNCHED ELECTROSPINNING JETS - The invention relates to a novel method for electrospinning fibers wherein the fiber-spinning solution is infused with gas bubbles which travel through the electrospinning fluid, causing the bubbles to be coated with electrospinning solution. The coated bubbles, in turn, in response to an applied electrical force, generate jets of the electrospinning fluid that travel away from the bubble surface. The invention further relates to the fibers formed by this bubble-jet process and to products made therefrom. | 2010-11-11 |
20100283190 | METHOD OF CONTINUOUSLY PRODUCING ELONGATED PLASTIC SIDING PANELS - A method and an apparatus for continuously producing elongated siding panels is disclosed. The apparatus includes a conveyor, a plurality of mold plates, and a die for extruding a sheet of material onto the mold plates. The mold plates are formed of a rigid material and positioned adjacent one another and supported by the conveyor for forming the elongated siding panels. Each of the mold plates has an upper edge portion and a lower edge portion with an intermediate portion therebetween. The intermediate portion has an aesthetic pattern for imparting the pattern to the sheet of material with the adjacent mold plates having different aesthetic patterns. The lower edge portion has a lower leg extending substantially perpendicular from the intermediate portion defining a horizontal plane and a projection portion between the lower edge portion and the intermediate portion extends beyond the horizontal plane for imparting a jagged pattern to the intermediate portion. | 2010-11-11 |
20100283191 | PROCESS FOR PRODUCING RETARDATION FILM OF THERMOPLASTIC RESIN - The process has a step of longitudinally stretching a thermoplastic resin film F by heating and floating the thermoplastic resin film F by blowing hot wind supplied from slit | 2010-11-11 |