45th week of 2011 patent applcation highlights part 26 |
Patent application number | Title | Published |
20110273918 | POWER DEVICE - A power device includes two groups of diodes, a step-down circuit, and a capacitor. Each group of diodes includes a first diode and a second diode. An anode of the first diode is connected to a cathode of the second diode, a node between the first and second diode is connected to one of live lines and neutral lines of at least one alternating current source. The step-down circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first and second input terminals are respectively connected to cathodes of the first diodes and anodes of the second diodes, the first and second output terminals are respectively connected to a power terminal and a ground terminal of a load. Two terminals of the capacitor are respectively connected to the first and second input terminals of the step-down circuit. | 2011-11-10 |
20110273919 | Read-Only Memory (ROM) Bitcell, Array, and Architecture - Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines. | 2011-11-10 |
20110273920 | SWITCHING ELEMENT AND APPLICATION OF THE SAME - A micro-switching element provided with a first electrode | 2011-11-10 |
20110273921 | INTEGRATABLE PROGRAMMABLE CAPACITIVE DEVICE - A circuit with a capacitive device is disclosed. The circuit may comprise a capacitive device connected between a first conductor and a second conductor. The capacitive device may comprise a first electrode connected to the first conductor and a second electrode being connected to the second conductor. A chalcogenide layer may be connected to the first electrode and to a metal chalcogenide layer. | 2011-11-10 |
20110273922 | SENSE AMPLIFIER USING REFERENCE SIGNAL THROUGH STANDARD MOS AND DRAM CAPACITOR - A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor. | 2011-11-10 |
20110273923 | PASS-GATED BUMP SENSE AMPLIFIER FOR EMBEDDED DRAMS - A sensing circuit for use in a semiconductor memory device includes first and second conducting lines for conducting a bit signal to and from a memory cell. The circuit further includes a sense amplifier coupled to the first and second conducting lines for sensing a bit signal, a charge storing element for generating a predefined potential, and first and second switching element respectively coupled to the first and second conducting lines. The first and second switching elements are selectively controllable to connect the first and second conducting line to the charge storing element so as to induce the generated predefined voltage on the first or second conducting lines. | 2011-11-10 |
20110273924 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal voltage terminal to a first or second power supply voltage according to an operation mode in response to the detection signal, and an enable control unit configured to control the driving unit in response to a control signal corresponding to the operation mode. | 2011-11-10 |
20110273925 | NONVOLATILE SRAM/LATCH CIRCUIT USING CURRENT-INDUCED MAGNETIZATION REVERSAL MTJ - The present invention is a memory circuit that includes a bistable circuit that stores data, and a ferromagnetic tunnel junction device that nonvolatilely stores the data in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer, the data nonvolatilely stored in the ferromagnetic tunnel junction device being able to be restored in the bistable circuit. According to the present invention, writing data to and reading data from the bistable circuit can be performed at high speed. In addition, even though a power source is shut down, it is possible to restore data nonvolatilely stored in the ferromagnetic tunnel junction devices to the bistable circuit. | 2011-11-10 |
20110273926 | Method and Apparatus of Probabilistic Programming Multi-Level Memory in Cluster States Of Bi-Stable Elements - A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data. | 2011-11-10 |
20110273927 | SEMICONDUCTOR DEVICE - A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA). | 2011-11-10 |
20110273928 | METHOD AND SYSTEM FOR PROVIDING A MAGNETIC MAGNETIC FIELD ALIGNED SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY - A method and system for providing a magnetic memory are described. The method and system include providing magnetic storage cells, bit lines coupled with the magnetic storage cells, preset lines, and word lines coupled with the magnetic storage cells. Each magnetic storage cell includes magnetic element(s). The bit lines drive write current(s) through selected storage cell(s) of the magnetic storage cells to write to the selected storage cell(s). The preset lines drive preset current(s) in proximity to but not through the selected storage cell(s). The preset current(s) generate magnetic field(s) to orient the magnetic element(s) of the selected storage cell(s) in a direction. The word lines enable the selected storage cell(s) for writing. Either the bit lines reside between the preset lines and the storage cells or the preset lines reside between the storage cells and on a storage cell side of the bit lines. | 2011-11-10 |
20110273929 | SEMICONDUCTOR MAGNETIC MEMORY INTEGRATING A MAGNETIC TUNNELING JUNCTION ABOVE A FLOATING-GATE MEMORY CELL - A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate. | 2011-11-10 |
20110273930 | Diode Memory - A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal. | 2011-11-10 |
20110273931 | METHODS OF OPERATING MEMORY CELL HAVING ASYMMETRIC BAND-GAP TUNNEL INSULATOR USING DIRECT TUNNELING - Methods of operating dual-gate memory cells having asymmetric band-gap tunnel insulators using direct tunneling. The asymmetric band-gap tunnel insulators allow for low voltage direct tunneling programming and efficient erase with holes and/or electrons, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. | 2011-11-10 |
20110273932 | NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells. | 2011-11-10 |
20110273933 | ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERSION WINDOW ADJUSTMENT BASED ON REFERENCE CELLS IN A MEMORY DEVICE - An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array. | 2011-11-10 |
20110273934 | Interleaving Charge Pumps for Programmable Memories - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 2011-11-10 |
20110273935 | MITIGATING CHANNEL COUPLING EFFECTS DURING SENSING OF NON-VOLATILE STORAGE ELEMENTS - Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state. | 2011-11-10 |
20110273936 | ERASE PROCESS FOR USE IN SEMICONDUCTOR MEMORY DEVICE - A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased. | 2011-11-10 |
20110273937 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal. | 2011-11-10 |
20110273938 | CIRCUIT AND METHOD FOR CONTROLLING A CLOCK SYNCHRONIZING CIRCUIT FOR LOW POWER REFRESH OPERATION - A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete. | 2011-11-10 |
20110273939 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously. | 2011-11-10 |
20110273940 | LEVEL SHIFTING CIRCUIT - A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage level is higher than the first voltage level. Level shifting circuit embodiments having two or more parallel coupled depletion mode transistors coupled to a high voltage source and further coupled to the output by an enhancement mode transistor, and an additional transistor coupled between a first signal and the output of the level shifting circuit where the first signal has the same logic level of the input are disclosed. | 2011-11-10 |
20110273941 | TECHNIQUES FOR REFRESHING A SEMICONDUCTOR MEMORY DEVICE - Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region. | 2011-11-10 |
20110273942 | Memory Array Having a Programmable Word Length, and Method of Operating Same - A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed. | 2011-11-10 |
20110273943 | System and Method to Read a Memory Cell with a Complementary Metal-Oxide-Semiconductor (CMOS) Read Transistor - A system and method to manage leakage of a complementary metal-oxide-semiconductor (CMOS) read transistor in a memory cell. In a particular embodiment, a memory cell is disclosed that includes a storage element and a complementary metal-oxide-semiconductor (CMOS) read transistor. The CMOS read transistor includes a first terminal coupled to a read word line, a second terminal coupled to a read bit line, and a third terminal coupled to the storage element. During a non-read operating time, the read word line and the read bit line are both maintained at substantially the same voltage level. During a read operation, the read word line is maintained at a particular voltage level until after a voltage representing data stored at the storage element is sensed by the CMOS read transistor. | 2011-11-10 |
20110273944 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes first and second planes having a memory cell array that includes a plurality of memory cells coupled to bit lines, and page buffer groups that are coupled respectively to one or more of the bit lines and each include page buffers, and a common input/output circuit shared by the page buffer groups of the first and second planes for data input/output control, and coupled to data input/output pads. | 2011-11-10 |
20110273945 | TECHNIQUES TO IMPROVE THE OPERATIONS OF A MEMORY DEVICE - A method and system to improve the operations of a memory device by reducing its bit line leakage, power consumption, and read access time. The memory device has a static read word line for each of its bit cells and domino logic for each of its bit line. Each bit line of the memory device is coupled with a gating logic that is activated using a clocked signal. This eases the timing requirement of the read word lines of the memory device and the read word lines do not form the critical path of the access time of the memory device. The leakage current of the memory device in inactive mode is reduced by switching off the pre-charge circuit and/or the keeper circuit of each bit line. Each bit line is pre-charged on demand prior to the evaluation of each bit line. | 2011-11-10 |
20110273946 | UNIVERSAL TEST STRUCTURES BASED SRAM ON-CHIP PARAMETRIC TEST MODULE AND METHODS OF OPERATING AND TESTING - An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included. | 2011-11-10 |
20110273947 | TECHNIQUES FOR REFRESHING A SEMICONDUCTOR MEMORY DEVICE - Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array. Applying a plurality of voltage potentials to the memory cells may further include applying a third voltage potential to a respective word line of the array, wherein the word line may be spaced apart from and capacitively to a body region of the memory cell that may be electrically floating and disposed between the first region and the second region. Applying a plurality of voltage potentials to the memory cells may further include applying a fourth voltage potential to a third region of the memory cell via a respective carrier injection line of the array. | 2011-11-10 |
20110273948 | SEMICONDUCTOR DEVICE AND METHOD OF REFRESHING THE SAME - A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines. | 2011-11-10 |
20110273949 | ELECTRICAL FUSE PROGRAMMING TIME CONTROL SCHEME - A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse. | 2011-11-10 |
20110273950 | Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit - A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device. The voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates | 2011-11-10 |
20110273951 | MEMORY CIRCUIT AND METHOD FOR CONTROLLING MEMORY CIRCUIT - A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage, and the fourth supply voltage is coupled to a second supply voltage smaller than the first supply voltage. The switch module is coupled to the second node, the third node, the first supply voltage and the second supply voltage. When the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage, and electrically disconnects the third node from the first supply voltage. | 2011-11-10 |
20110273952 | SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE - Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented. | 2011-11-10 |
20110273953 | TANK FOR KNEADING MACHINE - A tank comprising a vessel wall and a bottom fixed to said vessel wall. The bottom comprises a portion obtained by chip-removing machining. The tank can be used for a machine for kneading foodstuff substances in which the tank can be driven in rotation by driving means of driving said machine. The aforesaid portion is prearranged for direct engagement with the aforesaid driving means of the kneading machine. | 2011-11-10 |
20110273954 | MIXING APPARATUS HAVING DISPLAY FOR PRESSURE CHANGE - A mixing apparatus for mixing at least two components comprises a mixing chamber having a first component and at least one component chamber having a further component. The component chamber is connected to the mixing chamber by a feed line. A negative pressure device generates a negative pressure in the mixing chamber in the starting position. By activating the negative pressure device, the pressure is equalized, whereby the further component is transferred into the mixing chamber. A display apparatus is provided at the component chamber to display a pressure change in the component chamber. The display apparatus is preferably formed by elastic bellows provided at one end of the component chamber, which is disposed opposite of the end of the component chamber following the feed line. | 2011-11-10 |
20110273955 | LIQUID MIXING DEVICE - Provided is a liquid mixing device capable of mixing together two or more kinds of liquids successively in an accurate ratio. The liquid mixing device includes: a first supply system for supplying a first liquid; a second supply system for supplying a second liquid; and a liquid mixing system that receives supply of the first liquid and second liquid from the first supply system and the second supply system, respectively, in which: the first supply system communicates to the liquid mixing system through a first flow rate regulation unit having a first path sectional area; the second supply system is connected to the liquid mixing system through a second flow rate regulation unit having a second path sectional area; and the first liquid in an amount corresponding to the first path sectional area and the second liquid in an amount corresponding to the second path sectional area are allowed to flow into the liquid mixing system, respectively, by making an inside pressure of the liquid mixing system negative. | 2011-11-10 |
20110273956 | DEVICE FOR DISPENSING A FILLING MASS - An apparatus for the injection of a fluid filler material includes a static mixer ( | 2011-11-10 |
20110273957 | Apparatus and Method for Decoupling a Seismic Sensor From Its Surroundings - An apparatus includes a streamer having one or more sensor holders for retaining seismic sensors therein. An elastic material is disposed about the sensor, thereby decoupling the sensor from its surroundings. The streamer is filled with a gel-like material that is in communication with the elastic material disposed about the sensor. | 2011-11-10 |
20110273958 | SYSTEM AND METHOD FOR ACCURATE DETERMINATION OF OCEAN BOTTOM SEISMOMETER POSITIONING AND TIMING - There is provided herein a system and method of seismic exploration that produces improved locations and timings for ocean bottom seismometers. The instant method utilizes linearized inversion in conjunction with a conventionally accurate clock to provide both time and positioning for each OBS unit with high accuracy as compared with the prior art approach. Inversion is one mathematical tool that effectively performs the requisite triangulation. Furthermore, the clock drift can be accounted for in the inversion scheme. The inversion not only determines the OBS position and shot timing errors, but also estimates the accuracy of the position and timing determination. | 2011-11-10 |
20110273959 | Data Acquisition and Prestack Migration Based on Seismic Visibility Analysis - Seismic visibility analysis of selected subsurface structures is employed to determine surface locations offering high visibility of target events. These locations can then be used as a basis for acquiring additional seismic survey data and/or selecting existing traces for re-migration with more sophisticated migration methods. With either usage, the newly migrated data is expected to offer enhanced images of the target event. In some embodiments, the visibility determination includes using a wave equation based propagator to find, for each of multiple simulated shots, a reflection wavefield from the target event in a seismic model; and to calculate, for each of multiple receiver positions, a contribution signal from each reflection wavefield. The visibility determination further includes converting each contribution signal into a source-receiver visibility value. Because data acquisition and/or re-migration is limited to the selected region, the imaging effort for the target event is significantly reduced. | 2011-11-10 |
20110273960 | ANTENNA FOR SEISMIC SURVEY WITH UNIFORM SPATIAL SAMPLING IN WAVELENGTH - The present invention concerns a method and an antenna for active and/or passive seismic survey, such as a particular geometric layout of a plurality of vibration sensors, each one of adequate sensitivity, to be used with signal correlation in seismic surveys with or without an artificial wave source. In particular, the invention concerns a specific geometric layout of four vibration sensors, set along an alignment at positions, with one position chosen so that the antenna covers the desired wavelength interval. The sum of the signal correlations of all possible sensor couples allows a uniform sampling of all the spatial wavelengths that such an antenna defines, producing an accurate measure of the elastic and anelastic parameters of the subsoil and of the vibrational modes of a construction with the minimum possible number of sensors and minimum physical dimensions. | 2011-11-10 |
20110273961 | Q Tomography Method - Method for reconstructing subsurface Q models ( | 2011-11-10 |
20110273962 | Transducer Array Arrangement and Operation for Sodar Applications - An array of transducers for a sodar system, and the operation of the array in a monostatic sodar system. The array is made up of a number of individual sound transducers. Each transducer emits sound into the atmosphere and senses emitted sound that has been reflected by the atmosphere. The transducers have a generally circular cross-sectional shape. The transducers are arranged in a generally planar, generally hexagonal grid packing arrangement. | 2011-11-10 |
20110273963 | DETECTION DEVICE - This disclosure provides a detection device, which includes a transceiving module for transmitting a transmission signal and receiving an echo caused by the transmission signal to output a reception signal according to an intensity of the echo, a memory module for storing the reception signals for a plurality of measurements, and an interference detecting module for detecting an interference signal from the reception signals, the interference detecting module determining that the reception signal contains the interference signal when the reception signal has an intensity difference with the previous reception signal by more than a predetermined threshold for over a reference time period in one measurement. | 2011-11-10 |
20110273964 | METHOD FOR LISTENING TO ULTRASONIC ANIMAL SOUNDS - A method for listening to ultrasonic animal sound signals comprises: obtaining a plurality of input samples at an input sample rate, the plurality of input samples including at least one sequence of samples corresponding to an instance of an intermittently occurring animal sound signal; receiving a frame including at least two of the plurality of input samples; selecting a fraction of the samples as output samples, the fraction of the samples including a sample containing the at least one sequence of samples corresponding to an instance of an intermittently occurring animal sound signal; and transmitting the output samples at an output sample rate slower than the input sample rate. | 2011-11-10 |
20110273965 | DEVICE AND METHOD FOR TRANSMITTING INFORMATION IN SOLID MEDIA - The invention relates to a device for transmitting information in solid media ( | 2011-11-10 |
20110273966 | Reducing Noise in Seismic Surveying Environment - In one embodiment of the invention a method includes (a) operating a combustion engine at a first activity level corresponding to a first noise level; (b) charging an accumulator with a first pressure input; (c) lowering engine activity level of the engine to a second activity level corresponding to a second noise level that is lower than the first noise level; and (d) seismic sweeping with the vibrator based on the first pressure input and lowering engine noise from the first noise level to the second noise level. | 2011-11-10 |
20110273967 | ULTRA HIGH RESOLUTION TIMING MEASUREMENT - A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module. | 2011-11-10 |
20110273968 | Two-Phase Detached Escapement Mechanism for Oscillators and Related Systems - An enhanced escapement mechanism provides improved isolation of energy and torque for an oscillation system, e.g. a pendulum. In an exemplary embodiment, during a first phase, a pendulum releases an impulse arm that is decoupled from a main wheel, which falls and impulses the pendulum, such as at or near the middle of the pendulum swing. In a second phase, the impulse arm continues to fall, becoming totally detached from the pendulum, wherein the falling impulse arm releases the main wheel, which restores the impulse arm to its initial position. The main wheel continues to rotate until it is no longer in contact with the impulse arm, and is captured, such that the process may be repeated. While the enhanced escapement mechanism typically provides an impulse to an oscillation system during each period, alternate embodiments provide an impulse for each of a plurality of periods, e.g. once every ten periods. | 2011-11-10 |
20110273969 | TIMEPIECE INCLUDING A PIVOTING MEMBER - A timepiece includes a frame ( | 2011-11-10 |
20110273970 | OPTICAL INFORMATION RECORDING MEDIUM, AND DEVICE FOR RECORDING/REPRODUCING INFORMATION ON/FROM OPTICAL INFORMATION RECORDING MEDIUM - An optical information recording medium ( | 2011-11-10 |
20110273971 | DATA STORAGE SYSTEM WITH POWER BACKUP MECHANISM - A data storage system with power backup mechanism includes a storage server, N pieces of power supply modules, a plurality of programmable logic devices and a control module. The storage server consumes M units of power in operation, and supports a storage bridge bay standard. The power supply modules respectively generate power for the storage server and a set of power-related signals, wherein the maximum power output of each of the power supply modules is equal to M/N−1 units. The programmable logic devices convert the power-related signals from the power supply modules to two sets of power condition signals. The control module monitors a power condition according to the power condition signals, thereby determining a power health condition of the storage server. | 2011-11-10 |
20110273972 | CODING APPARATUS, CODING METHOD, RECORDING APPARATUS, RECORDING METHOD, DECODING APPARATUS, AND DECODING METHOD - A coding apparatus includes a transform table in which with regard to data words of m bits and code words of n bits where n and m are both integers and also n>m is established, 2 | 2011-11-10 |
20110273973 | SYSTEM AND METHOD FOR IMPROVED DATA STORAGE - A method for storing data on a storage medium is provided. The method includes receiving a modulated bitstream, wherein the modulated bitstream comprises a plurality of bits comprising a bitstate of 1 and 0. The method also includes secondary modulating each of the pluality of bits comprising the bitstate of 1 to output a plurality of secondary modulated bits. The method further includes forming a plurality of marks in the storage medium, the marks indicative of each of the plurality of secondary modulated bits and the plurality of bits comprising the bitstate of 0 in the modulated bitstream. | 2011-11-10 |
20110273974 | METHOD AND APPARATUS FOR OFFSET AND GAIN CORRECTION - Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation. | 2011-11-10 |
20110273975 | SENSING DEVICE - A sensing device including a base, a pillar, an arm, a sensing element and a driving module is provided. The base has a supporting surface suitable for supporting the object. The pillar is disposed on the supporting surface. The arm has two ends and a pivot portion between the two ends. The pivot position is pivoted to the pillar along an axis substantially parallel to the supporting surface. The sensing element is disposed on the arm and located between an end and the pivot portion. The sensing element is located between the base and the object. The driving module is disposed between the arm and the base. The driving module drives the arm to pivot relatively to the pillar along the axis, and the sensing element moves toward or away from the object as the arm is pivoted. | 2011-11-10 |
20110273976 | ENCODING APPARATUS AND METHOD, RECORDING APPARATUS AND METHOD, AND DECODING APPARATUS AND METHOD - An encoding apparatus that converts m-bit data words into n-bit code words, where m and n are both integers and satisfy an expression 2 | 2011-11-10 |
20110273977 | SYSTEM AND METHOD FOR CHANNEL STATE RELATED FEEDBACK IN MULTI-USER MULTIPLE-INPUT-MULTIPLE-OUTPUT SYSTEMS - System and method for dimension reduction and for channel and interference condition feedback in a Multi-User Multiple-Input-Multiple-Output (MU MIMO) wireless communication systems. The method for dimension reduction includes determining a number of virtual antennas, v | 2011-11-10 |
20110273978 | DATA TRANSMISSION DEVICE - A data transmission device is provided including a monitoring unit | 2011-11-10 |
20110273979 | METHOD AND APPARATUS FOR PSTN-BASED IP ACTIVE CALL RECOVERY AND RE-ROUTING - A method for rerouting IP (Internet Protocol) telephony call information includes, during an active IP telephony call made by a first IP telephony phone for originating IP telephony calls over an IP network, with a boundary element, actively detecting a network failure condition in the IP network which indicates a switchover to a PSTN (Public Switched Telephone Network) network and generating a failure notification; and with a server for receiving the failure notification, generating a dynamic switchover instruction generated that is sent to the first IP telephony phone, the dynamic switchover instruction initiating automatic switchover of the active IP telephony call to a PSTN network. A method for rerouting IP (Internet Protocol) telephony call information includes, with a server, monitoring an IP network for route failures; and with the server, generating a switchover instruction when an active IP telephony call is interrupted by a route failure. The switchover instruction initiates automatic switchover of the active IP telephony call to a fallback call routed through a Public Switched Telephone Network (PSTN). The switchover instruction includes information which identifies the fallback call as a replacement for the active IP telephony call. | 2011-11-10 |
20110273980 | Distributed Failure Recovery in a Routed Etherent Network - Link identifiers such as VIDs, selected from a defined range of values, are locally assigned by each node on a link state protocol controlled Ethernet network to each of its links or adjacencies. The link identifiers are assigned by the nodes such that each link or adjacency at the node is uniquely identified by a different link identifier. A link state protocol adjacency notification mechanism or other flooding mechanism is used to disseminate the locally assigned link identifiers to other nodes on the link state protocol controlled Ethernet network. The link identifiers are added by the nodes to their topology databases to enable detour routes to be locally calculated by the nodes on the network in a distributed manner. Upon occurrence of a failure, the link identifiers are used to source route traffic around the failure so that traffic may continue to traverse the link state protocol controlled Ethernet network. | 2011-11-10 |
20110273981 | COOPERATIVE NETWORK WITH ADAPTIVE FORWARDING REQUEST POLICY - The invention relates to a packet forwarding method in a cooperative network implementing a source terminal, a destination terminal, and at least one relay terminal. In case of a packet decoding error in a node of the network, this method, depending on the outage state of a direct or relayed channel between two nodes of the network, enables a determination of the node(s) having to perform retransmission of the packet and if applicable, the transmission resource(s) to be used. | 2011-11-10 |
20110273982 | DEDUPLICATED DATA PROCESSING CONGESTION CONTROL - Various embodiments for deduplicated data processing congestion control in a computing environment are provided. In one such embodiment, a single congestion metric is determined from a sampling of a plurality of combined deduplicated data processing congestion statistics in a number of active deduplicated data processes. The congestion limit is calculated from a comparison of the single congestion metric to a congestion target setpoint, the congestion target setpoint being a virtual dimension setpoint and the congestion limit being a manipulated variable. The number of active deduplicated data processes is compared to the congestion limit. If the number of active deduplicated data processes is less than the congestion limit, a new deduplicated data process is spawned. | 2011-11-10 |
20110273983 | METHODS AND DEVICES FOR BACKWARD CONGESTION NOTIFICATION - The present invention provides improved methods and devices for managing network congestion. Preferred implementations of the invention allow congestion to be pushed from congestion points in the core of a network to reaction points, which may be edge devices, host devices or components thereof. Preferably, rate limiters shape individual flows of the reaction points that are causing congestion. Parameters of these rate limiters are preferably tuned based on feedback from congestion points, e.g., in the form of backward congestion notification (“BCN”) messages. In some implementations, such BCN messages include congestion change information and at least one instantaneous measure of congestion. The instantaneous measure(s) of congestion may be relative to a threshold of a particular queue and/or relative to a threshold of a buffer that includes a plurality of queues. | 2011-11-10 |
20110273984 | Packet Flow Processing in a Communication System - Method and apparatus for processing packet flows in a communication system. In one embodiment, a resource reservation message includes packet flow parameter information used to determine flow treatment of the associated packet flow. The packet flow mapping is based on the quality of service of the associated packet flow. In another embodiment, a bearer connection is established and monitored for information relating to flow treatment. | 2011-11-10 |
20110273985 | METHOD FOR CONTROLLING A FLOW IN A PACKET SWITCHING NETWORK - The invention is related to the field of flow control between two computing nodes over a packet switching network. Furthermore, the invention concerns a method for controlling data flow between a sending node and a receiving node over a packet switching network, data being sent with a current data rate onto a protocol-specific buffer of the receiving node, an application reading data stored in the buffer at a playback rate, | 2011-11-10 |
20110273986 | Method and System for Controlling the Restart Traffic in a Telecommunication Network - A method of regulating traffic in a telecommunications network, including the following steps: after the network receives an initial registration request, and if the network is capable of processing said initial registration request, it prescribes for the terminal that sent the request a registration refresh period randomly selected from a range defined by a predetermined minimum value (PREI | 2011-11-10 |
20110273987 | LOAD BALANCING - A method for load balancing Ethernet traffic within a fat tree network ( | 2011-11-10 |
20110273988 | Distributing decision making in a centralized flow routing system - Local rules for managing flows devolved from a central controller are received at a switch. The central controller determines a global set of rules for managing flows. The switch receives a packet from a flow from a network and determines whether a metric for the flow satisfies a dynamic condition to trigger a metric report to the central controller. In response to a determination that the metric for the flow at the switch satisfies the dynamic condition to trigger a metric report to the central controller, the switch sends a metric report to the central controller, and the switch then receives an instruction to manage the flow from the central controller. In response to a determination that the metric for the flow at the switch does not satisfy the dynamic condition to trigger the metric report to the central controller, the switch manages the flow using the local rules for managing flows. | 2011-11-10 |
20110273989 | System for mobile broadband networking using dynamic quality of service provisioning - A wireless networking system uses mobile and fixed transceivers to achieve a network with changing topology. A routing process includes quality-of-service considerations in the network to allow for features such as file or other data transfer, streaming audio and video, digital telephone communications, etc. The routing process adapts to transceiver units entering, leaving, or moving within, the network. Auxiliary networks such as the Internet, campus or corporate intranets, home networks, etc., can be accessed through the wireless network. Features, designs and user interfaces for the units are described. Security and access control of media content and other data is presented. | 2011-11-10 |
20110273990 | Per-graph link cost assignment in layer 2 multipath networks - In one embodiment, a method includes assigning at a switch in a layer 2 multipath network, costs to a link in the network, each of the link costs associated with a different graph for forwarding traffic in the network, transmitting the link costs to other switches in the layer | 2011-11-10 |
20110273991 | LOCATION OF MOBILE NETWORK NODES - The physical position of a movable node in a network is determined by sending a first signal from a first reference node to at least a second reference node and the unknown node. The unknown node receives the first signal and sends a second signal to at least the second reference node in phase with the first signal. The first signal and the second signal are received in the second reference node and the phase of the received signals is compared to determine the position of the unknown node based on the phase difference between the received first and second signals. | 2011-11-10 |
20110273992 | CARRIER PRECONFIGURATION FOR PDCCH MONITORING IN MULTI-CARRIER SYSTEMS - Certain aspects of the present disclosure relate to techniques for carrier preconfiguration for monitoring for transmissions of downlink control information (DCI), for example, conveyed in physical downlink control channel (PDCCH) transmissions utilizing multiple carriers. The methods and apparatuses described herein may be applied in both frequency division duplex (FDD) and time division duplex (TDD) systems. | 2011-11-10 |
20110273993 | System and Method for Reporting Quantized Feedback Information for Adaptive Codebooks - A system and method for reporting quantized feedback information for adaptive codebooks include generating channel state information, encoding all or part of the channel state information to produce a feedback payload and transmitting the feedback payload to a base station from a mobile station. The channel state information comprises a rank indicator, a first matrix indicator, a wideband channel quality indicator, a second matrix indicator and at least one narrowband channel quality indicator. When the rank indicator is greater than 1, the first matrix indicator is reported in a second report. On the other hand, when the rank indicator is equal to 1, the content of the first matrix indicator is split between a second report and a third report. | 2011-11-10 |
20110273994 | METHOD AND APPARATUS TO DETERMINE A CFI (CONTROL FORMAT INDICATOR) VALUE IN A WIRELESS COMMUNICATION NETWORK - A method and apparatus are disclosed determine a CFI value in a wireless communication system. In one embodiment, the method comprises configuring system devices, such as a UE or an eNB, with a plurality of component carriers for carrier aggregation. Furthermore, the method comprises receiving PDSCH on a first component carrier. The method also comprises transmitting a corresponding PDCCH on a second component carrier. In addition, the method comprises using a RRC signal to configure a CFI with an initial configured value. The method further comprises setting the CFI so that the CFI could be used to determine a starting point of the PDSCH. | 2011-11-10 |
20110273995 | REAL-TIME SERVICE MONITORING APPARATUS AND METHOD USING TIME STAMP - A real-time service monitoring apparatus and method using a time stamp is provided. The real-time service monitoring apparatus includes: a packet reception and classification block configured to generate a first time stamp whenever receiving a packet, and classify the received packet into a time synchronization packet or a real-time monitoring packet; a packet processing and switching block configured to process the classified packet depending on whether the packet is the time synchronization packet or the real-time monitoring packet, and switch the processed packet to a destination address; a packet classification and transmission block configured to classify the switched packet depending on whether the packet is the time synchronization packet or the real-time monitoring packet, generate a second time stamp for the classified packet, and transmits the packet; and a real-time monitoring block configured to compute a real-time monitoring parameters for each flow using the generated first and second time stamps, in order to monitor the real-time service. | 2011-11-10 |
20110273996 | WIRELESS APPARATUS FOR A MULTI-CARRIER SYSTEM - A wireless apparatus for a multi-carrier system is disclosed. The wireless apparatus comprises; a control channel unit which monitors a control channel transmitted via at least one carrier from among a plurality of carriers; and a data channel unit which transmits or receives data packets to or from a data channel using the resource allocation received from the control channel. The control channel unit monitors the control channel in a plurality of search space in a subframe. | 2011-11-10 |
20110273997 | RADIO COMMUNICATION SYSTEM, SCHEDULING METHOD, RADIO BASE STATION DEVICE, AND RADIO TERMINAL - A radio communication system, scheduling method, radio base station device, and radio communication terminal all enabling improvement of the system throughput. The radio base station device ( | 2011-11-10 |
20110273998 | SYSTEMS AND METHODS FOR MONITORING PARAMETERS OF A WIRELESS DEVICE - Systems and methods are provided for controlling monitoring operations, such as the monitoring of signal strength, media access control layer overhead information data, application layer overhead information, and/or data in a device, such as a battery powered, mobile, communication device. A user interface status and/or a flow status can be monitored. Based at least in part on the user interface status and/or the flow status, a determination can be made as to when and/or how often monitoring is to be performed. | 2011-11-10 |
20110273999 | DATA TRANSMISSION VIA A RELAY STATION WITH ACK/NACK FEEDBACK - Techniques for supporting communication by a relay station are described. In an aspect, the relay station may support NACK Type 1 when operating in an amplify-and-forward (AF) mode. The relay station may receive a first transmission of a packet from an upstream station, determine PAPR of the first transmission, and send NACK Type 1 to the upstream station if high PAPR is detected. In another aspect, the relay station may support NACK Type 1 and NACK Type 2 when operating in a decode-and-forward (DF) mode. The relay station may perform PAPR decoding for the first transmission, send NACK Type 1 if PAPR decoding fails, perform channel decoding if PAPR decoding passes, and send NACK Type 2 to the upstream station if channel decoding fails. In yet another aspect, the relay station may operate in the AF mode or the DF mode. | 2011-11-10 |
20110274000 | SYSTEM AND METHOD FOR DEVELOPING A WI-FI ACCESS POINT MAP USING SENSORS IN A WIRELESS MOBILE DEVICE - A wireless mobile device capable of developing a wireless fidelity (Wi-Fi) access point map. The mobile device comprises a Wi-Fi module and a processor. The Wi-Fi module is configured to communicate with a plurality of Wi-Fi access points and determine a signal strength from at least one of the Wi-Fi access points at each of a plurality of locations. The processor is configured to display a Wi-Fi access point map on a display of the mobile device, the map configured to associate the signal strength of the at least one Wi-Fi access point with each location, and direct a user of the mobile device to a location on the map, the location on the map having a stronger Wi-Fi signal that a current location of the mobile device. | 2011-11-10 |
20110274001 | Signal Measurement in TD-SCDMA Multicarrier Systems Using Downlink Synchronization Codes - Wireless communication in a multicarrier radio access network may be implemented where a user equipment (UE) maintains communication with various carrier frequencies in the multicarrier network. The UE will receive an indication from a node B to measure a signal quality on one of a number of carrier frequencies in the network. The UE will then measure the signal quality on the carrier frequency based on measurements using a downlink synchronization code transmitted by the node B on the downlink pilot channel of the carrier frequencies in the multicarrier network. The UE may then report the channel quality back to the node B. | 2011-11-10 |
20110274002 | METHOD AND SYSTEM OF OPERATING A MULTI-USER SYSTEM - A method and system is disclosed for grouping the multiple stations connected to an access point (AP). The system and method comprise sending a sounding packet to a plurality of stations, wherein the stations may be all or part of the stations that are located within the range of the AP. The stations that receive the sounding packets respond to the AP, and the AP determines the channel state information (CSI) from the responses. According to the CSI, the AP divides the multiple stations into several groups. According to an embodiment of the present invention, a confirmation step is performed to each group of stations, respectively. The AP sends a second sounding packet to each group of stations, and verifies the CSI between each station group by group. Therefore, the method and system provides for monitoring the validation of each group by periodically sending sounding packets to each group. | 2011-11-10 |
20110274003 | METHOD AND SYSTEM OF OPERATING A MULTI-USER SYSTEM - A method and system is disclosed for grouping the multiple stations connected to an access point (AP). The system and method comprise sending a sounding packet to a plurality of stations, wherein the stations may be all or part of the stations that are located within the range of the AP. The stations that receive the sounding packets respond to the AP, and the AP determines the channel state information (CSI) from the responses. According to the CSI, the AP divides the multiple stations into several groups. According to an embodiment of the present invention, a confirmation step is performed to each group of stations, respectively. The AP sends a second sounding packet to each group of stations, and verifies the CSI between each station group by group. Therefore, the method and system provides for monitoring the validation of each group by periodically sending sounding packets to each group. | 2011-11-10 |
20110274004 | SYSTEMS AND METHODS FOR SPACE-TIME DETERMINATIONS WITH REDUCED NETWORK TRAFFIC - Space-time solutions are determined by exchanging pings among nodes in a network. Each ping includes a current space-time state of the transmitting node, which includes the transmitting node's currently estimated location and corrected time (as a count stamp). A particular node in the network receives pings from the other nodes in the network and uses the data in the received pings to estimate its own current position and to correct its own free-running clock relative to a common system time. As a service to the network, the particular node then transmits its corrected time (as a count stamp) and estimated position to the other nodes. In some embodiments, the space-time solutions discussed herein are used as backup to other navigation systems, such as the Automatic Dependent Surveillance—Broadcast (ADS-B) system. | 2011-11-10 |
20110274005 | METHOD FOR TRANSMITTING AND RECEIVING CONTROL INFORMATION THROUGH PDCCH - A method for efficiently transmitting and receiving control information through a Physical Downlink Control Channel (PDCCH) is provided. When a User Equipment (UE) receives control information through a PDCCH, the received control information is set to be decoded in units of search spaces, each having a specific start position in the specific subframe. Here, a modulo operation according to a predetermined first constant value (D) is performed on an input value to calculate a first result value, and a modulo operation according to a predetermined first variable value (C) corresponding to the number of candidate start positions that can be used as the specific start position is performed on the calculated first result value to calculate a second result value and an index position corresponding to the second result value is used as the specific start position. Transmitting control information in this manner enables a plurality of UEs to efficiently receive PDCCHs without collisions. | 2011-11-10 |
20110274006 | DISTRIBUTED CACHE - ADAPTIVE MULTICAST ARCHITECTURE FOR BANDWIDTH REDUCTION - Disclosed is a method and system for maximizing the use of available bandwidth on an ISP communication system between an Internet Service Provider (ISP) and remote locations where at least one of the remote locations has a remote cache. An embodiment may create a pool of the cacheable objects being sent to the remote locations from the downstream traffic. An embodiment may determine bandwidth savings for each object in the pool of cacheable objects that would be achieved by remotely caching each object and prioritize the pool of cacheable objects based on the determined bandwidth savings for each object. An embodiment may create a queue of objects to multicast to the remote caches based on the pool of cacheable objects and the remaining multicast bandwidth and then multicast the queue to the remote caches. The remote caches may intercept and reply to requests for objects held in the remote cache without accessing the ISP communication system, thus, saving bandwidth on the ISP communication system. | 2011-11-10 |
20110274007 | Method of Handling Measurement Gap Configuration and Communication Device Thereof - A method of handling measurement gap configuration for a network in a wireless communication system comprising a mobile device capable of receiving and/or transmitting on a plurality of component carriers is disclosed. The method comprises configuring at least a measurement gap configuration each for at least a component carrier of the plurality of component carriers, to the mobile device. | 2011-11-10 |
20110274008 | Configurable switch for asymmetric communication - A networking device including at least two asymmetric communication ports. at least one of the asymmetric communication ports is a self-configurable asymmetric port and the self-configurable asymmetric port is configured automatically and able to support high throughput communications. Also disclosed a switch supporting uncompressed video comprising self-configurable asymmetric ports. The switch configured to automatically set the self-configurable asymmetric ports to support direction of communication of asymmetric end-devices coupled to the self-configurable asymmetric ports. | 2011-11-10 |
20110274009 | MANAGEMENT OF TELECOMMUNICATIONS CONNECTIONS - A network distribution, point ( | 2011-11-10 |
20110274010 | METHOD FOR ELECTING RING MANAGER OF RING TOPOLOGY NETWORK, AND NODE - A method for electing a ring manager of ring topology network and a node are disclosed, where, to this end, a node responsible for electing the ring manager periodically requests each node of diagnostic information on packet traffic and receives the diagnostic information on packet traffic from each node, newly elects a node capable of performing a ring manager role, and informs each node of information on the newly elected ring manager, whereby, the ring network can be more effectively operated because the ring manager is elected based on network load status that changes in real time even in the course of a ring network being initially set up and operated responsive to structural conditions including hop count of each nod and MAC node. | 2011-11-10 |
20110274011 | Method and Device for Data Service Provisioning - The invention refers to a method for supporting a data service provisioning, a device adapted thereto, and a corresponding computer program product. The method comprises the steps of receiving a service request for the data service, receiving a time range requirement in relation to the requested data service, wherein said time range requirement indicates a time range, in which the requested data service is to be provided, and selecting an access network that can provide the data service in the given time range. | 2011-11-10 |
20110274012 | TRANSITIONING OF A PACKET-SWITCHED EMERGENCY CALL BETWEEN FIRST AND SECOND TYPES OF WIRELESS ACCESS NETWORKS - A mobile station that is initially attached to a first type of wireless access network is involved in a packet-switched emergency call. Upon detection of transitioning of the mobile station, a message is sent indicating transitioning of the mobile station from the first type wireless access network to the second type wireless access network to cause the packet-switched emergency call to be performed over the second type wireless access network. | 2011-11-10 |
20110274013 | APPLICATION SERVER FOR DISPATCHING PHYSIOLOGICAL SIGNALS IN A HOSPITAL, IN REAL TIME - An application server (AS) for dispatching physiological signals in a hospital, in real time, this hospital comprising a local area network infrastructure (HN) with a virtual local area (VN) supporting voice over IP telephony application, comprises:—means for receiving packets containing samples of a physiological signal via a first terminal (IPP | 2011-11-10 |
20110274014 | DUAL MODE BASE STATION - The present application pertains to a dual mode radio base station that is operable to operate in either a TDD mode of operation or an FDD mode of operation. The dual mode base station may include a base-band unit (BU) and a radio unit (RU). The base-band unit may include (1) a first set of components each of which is configured to provide functionally while (a) the dual mode base station is operating in the FDD mode of operation and (b) the dual mode base station is operating in the TDD mode of operation; and (2) a second set of components each of which is configured to provide functionally (a) only while the dual mode base station is operating in the FDD mode of operation or (b) only while the dual mode base station is operating in the TDD mode of operation. | 2011-11-10 |
20110274015 | TDD Time Slot Splitting - The invention discloses a method for a cellular communications system, in which traffic is sent in frames, each frame comprising a first number of subframes, with a second number of said subframes being available for at least either uplink or downlink traffic. At least one of said second number of subframes is made to comprise at least three parts, as follows:
| 2011-11-10 |
20110274016 | UNSYNCHRONIZED SIGNALING IN RADIO SYSTEMS USING FREQUENCY DOMAIN PROCESSING - A method for unsynchronized signaling between nodes in a network is described. The method includes partitioning a message for asynchronous transmission in a network into a plurality of symbols. A symbol includes a cyclic prefix. Causing the plurality of symbols to be transmitted (for example, via a transmitter) on one or more subcarriers allocated for asynchronous transmissions is also included in the method. A given symbol is transmitted so as to reduce a discontinuity between a previous symbol and the given symbol. The method may also include applying a phase shift to one or more symbols of the plurality of symbols. Transmitting may include transmitting at a transmission frequency, where a length of a transmission cycle is determined by the transmission frequency, and where a length of the cyclic prefix is equal to an integer number of transmission cycles. Apparatus and computer readable media are also described. | 2011-11-10 |
20110274017 | VERSATILE SYSTEM FOR TRANSCEIVER NOISE REDUCTION IN A TIME-DIVISION DUPLEXING WIRELESS NETWORK - A system for suppressing transmission channel noise in a signal transmission/reception device—particularly a time division duplex (TDD) wireless communications device—is provided. The system provides one or more shunt elements, instantiated at some point along the device's signal transmission channel. One or more attenuation elements are also instantiated at some point along the signal transmission channel, as are one or more disabling elements. A trigger signal indicates when the device is shifting from signal transmission operation (or mode) to signal reception operation. Responsive to assertion of the trigger signal, the shunt, attenuation and disabling elements are activated. | 2011-11-10 |