45th week of 2011 patent applcation highlights part 14 |
Patent application number | Title | Published |
20110272717 | Light Emitting Device And Method of Manufacturing The Same - A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are seated by the first sealing material and the second sealing material. Further, reaction between electrodes of the light emitting elements (cathodes or anodes) and the sealing materials can be prevented by covering the electrodes with a transparent protective layer, for example, CaF | 2011-11-10 |
20110272718 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, typically an active matrix display device, the structure of TFTs arranged in the respective circuits are made suitable in accordance with the function of the circuit, and along with improving the operating characteristics and the reliability of the semiconductor device, the manufacturing cost is reduced and the yield is increased by reducing the number of process steps. A semiconductor device has a semiconductor layer, an insulating film formed contacting the semiconductor layer, and a gate electrode having a tapered portion on the insulating film, in the semiconductor device, the semiconductor layer has a channel forming region, a first impurity region for forming a source region or a drain region and containing a single conductivity type impurity element, and a second impurity region for forming an LDD region contacting the channel forming region, a portion of the second impurity region is formed overlapping a gate electrode, and the concentration of the single conductivity type impurity element contained in the second impurity region becomes larger with distance from the channel forming region. | 2011-11-10 |
20110272719 | LED STRUCTURE - The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula In | 2011-11-10 |
20110272720 | LIGHT EMITTING DEVICE GROWN ON WAVELENGTH CONVERTING SUBSTRATE - In some embodiments of the invention, a device includes a substrate and a semiconductor structure. The substrate includes a wavelength converting element comprising a wavelength converting material disposed in a transparent material, a seed layer comprising a material on which III-nitride material will nucleate, and a bonding layer disposed between the wavelength converting element and the seed layer. The semiconductor structure includes a III-nitride light emitting layer disposed between an n-type region and a p-type region, and is grown on the seed layer. | 2011-11-10 |
20110272721 | LED PACKAGE WITH A ROUNDED SQUARE LENS - A rounded square lens is used instead of a hemispherical lens in an LED package to produce a substantially Lambertian light emission pattern. A cross-sectional view of the rounded square lens cut along its diagonal forms a semicircular surface so as to emulate a hemispherical lens in areas close to the diagonal. A cross-sectional view of the lens cut along its width bisecting the lens forms a bullet shaped surface narrower than the semicircular surface but having the same height as the semicircular surface. The four corners of the lens are rounded. The surface of the lens smoothly transitions between the two surface shapes. Since the rounded square lens has a diagonal dimension larger than a maximum allowable diameter of a hemispherical lens in the same package body, a larger LED die may be used with the rounded square lens to output more light without increasing the size of the package while maintaining a Lambertian emission. | 2011-11-10 |
20110272722 | ENCAPSULATION STRUCTURE FOR LIGHT-EMITTING DIODE - The present invention relates to an encapsulation structure for light-emitting diode, which includes an encapsulation base, at least one light-emitting diode chip, a first encapsulation material and a second encapsulation material. The encapsulation base includes an encapsulation region, and the light-emitting diode chips are mounted on the encapsulation region. The first encapsulation material is disposed on the encapsulation region and overlays the light-emitting diode chips. The second encapsulation material is doped with a predetermined amount of phosphor (fluorescent powder), and the second encapsulation material is superposed on the first encapsulation material. Hence, according to the structure described above, the present invention effectively enables customization of products, and reduces the stockpiling of semi-finished products. | 2011-11-10 |
20110272723 | Rod Type Light Emitting Device And Method For Fabricating The Same - Disclosed herein is a rod type light emitting device and method for fabricating the same, wherein a plurality of rod structures is sequentially formed with a semiconductor layer doped with a first polarity dopant, an active layer, and a semiconductor layer doped with a second polarity dopant. | 2011-11-10 |
20110272724 | ALGAINP-BASED LIGHT-EMITTING DIODE WITH DOUBLE REFLECTIVE LAYERS AND FABRICATION METHOD THEREOF - The invention discloses an AlGaInP-based LED with double reflective layers and a fabrication method thereof. The method includes: providing a temporary substrate; forming an epitaxial layer on a front of the temporary substrate; forming a distributed Bragg reflector on the epitaxial layer; forming an some openings in the distributed Bragg reflector, such that the arrangement of the distributed Bragg reflector is grid-like and a portion of a top of the epitaxial layer is exposed; forming a reflective metal layer on the distributed Bragg reflector and on the exposed portion of the top of the epitaxial layer, to fill the openings; bonding a permanent substrate onto the reflective metal layer; removing the temporary substrate; forming a first electrode and a second electrode at a bottom of the epitaxial layer and a top of the permanent substrate, respectively; and dicing to obtain the AlGaInP-based LED chips. The AlGaInP-based LED with both the distributed Bragg reflector and the reflective metal layer according to the invention can fully utilize good reflectivity of the reflective layers to the extreme, and improve the light-emission efficiency of the AlGaInP-based LED effectively. | 2011-11-10 |
20110272725 | WAVELENGTH CONVERTING MEMBER, LIGHT-EMITTING DEVICE, AND METHOD FOR MANUFACTURING WAVELENGTH CONVERTING MEMBER - A polycrystalline sintered ceramic including (A) a garnet phase and (B) a perovskite, monoclinic or silicate phase wherein fine grains of phase (B) are included and dispersed in phase (A) is used as a wavelength converting member. Since the light transmitting through the wavelength converting member is scattered at the interface between the garnet phase and the perovskite, monoclinic or silicate phase, a light emitting device including the wavelength converting member produces light of more uniform color with a minimized loss thereof. | 2011-11-10 |
20110272726 | LUMINOUS DEVICES, PACKAGES AND SYSTEMS CONTAINING THE SAME, AND FABRICATING METHODS THEREOF - The present invention is directed to a vertical-type luminous device and high through-put methods of manufacturing the luminous device. These luminous devices can be utilized in a variety of luminous packages, which can be placed in luminous systems. The luminous devices are designed to maximize light emitting efficiency and/or thermal dissipation. Other improvements include an embedded zener diode to protect against harmful reverse bias voltages. | 2011-11-10 |
20110272727 | LIGHT-EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting diode and method for manufacturing the same are described. The light-emitting diode comprises: a conductive substrate including a first surface and a second surface opposite to the first surface; a reflector structure comprising a conductive reflector layer bonding to the first surface of the conductive substrate and a conductive distributed Bragg reflector (DBR) structure stacked on the conductive reflector layer; an illuminant epitaxial structure disposed on the reflector structure; a first electrode disposed on a portion of the illuminant epitaxial structure; and a second electrode bonded to the second surface of the conductive substrate. | 2011-11-10 |
20110272728 | Radiation-Emitting Semiconductor Chip - A radiation-emitting semiconductor chip ( | 2011-11-10 |
20110272729 | WAFER LEVEL LED INTERPOSER - A wafer level LED interposer and its manufacturing method is provided. The wafer level LED interposer includes: a LED chip of which N-type electrode and p-type electrode are formed on the upper side; an interposer substrate formed with through vias at each position corresponding to the N-type electrode and the p-type electrode and bonded to the upper side of the LED chip, wherein the N-type electrode and p-type electrode are connected to each through via; a redistribution layer formed on the upper surface of the interposer substrate and electrically connected to the through vias; a solder resist layer coated on the upper surface of the interposer substrate for a part of the redistribution layer selectively to be opened; and an external connector formed at the position where the redistribution layer is opened. | 2011-11-10 |
20110272730 | LIGHT EMITTING DEVICE - A light emitting device having an electrode structure in which resistance to electrostatic discharge (ESD) is increased, the static electricity is efficiently dispersed and a current concentration phenomenon is prevented, the light emitting device including: a substrate; a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer opposite to the first conductivity type semiconductor layer that are sequentially formed on the substrate; a first conductivity type electrode pad formed on the first conductivity type semiconductor layer; a second conductivity type electrode pad formed on the second conductivity type semiconductor layer; a first auxiliary electrode formed on the second conductivity type semiconductor layer to extend in one direction and having one end connected to the second conductivity type electrode pad and the other end formed in an opposite direction to a direction toward the first conductivity type electrode pad; and a second auxiliary electrode formed on the second conductivity type semiconductor layer to extend in one direction and including a main arm having one end connected to the second conductivity type electrode pad and the other end formed in a direction toward the first conductivity type electrode pad and a plurality of second auxiliary sub-electrodes extending from the other end of the main arm, wherein a direction in which an end of each of the second auxiliary sub-electrodes extends, is not toward the first conductivity electrode pad. | 2011-11-10 |
20110272731 | SUBSTRATE FOR LIGHT EMITTING ELEMENT PACKAGE, AND LIGHT EMITTING ELEMENT PACKAGE - This invention provides a substrate for a light emitting element package that can obtain a sufficient heat dissipation effect from a light emitting element and can also lower the costs and reduce the size as a substrate for packaging the light emitting element, as well as a light emitting element package using the same. The substrate for a light emitting element package includes an insulating layer | 2011-11-10 |
20110272732 | Element Substrate and Light Emitting Device - A light emitting device and an element substrate which are capable of suppressing variations in the luminance intensity of a light emitting element among pixels due to characteristic variations of a driving transistor without suppressing off-current of a switching transistor low and increasing storage capacity of a capacitor. According to the invention, a depletion mode transistor is used as a driving transistor. The gate of the driving transistor is fixed in its potential or connected to the source or drain thereof to operate in a saturation region with a constant current flow. A current controlling transistor which operates in a linear region is connected in series to the driving transistor, and a video signal for transmitting a light emission or non-emission of a pixel is inputted to the gate of the current controlling transistor through a switching transistor. | 2011-11-10 |
20110272733 | ENCAPSULATION STRUCTURE FOR LIGHT-EMITTING DIODE - The present invention relates to an encapsulation structure for light-emitting diode, primarily assembled from an encapsulation base, light-emitting diode chips and transparent encapsulation material, in which the light-emitting diode chips are mounted on an encapsulation region of the encapsulation base, after which the transparent encapsulation material is used to overlay the predetermined positions of the light-emitting diode chips. Accordingly, the light rays produced by the light-emitting diode chips can be emitted from the side areas, and when the light-emitting diode chips are mounted and joined to the encapsulation bases, then brightness at the connected areas can be maintained, and uneven brightness is prevented from occurring. | 2011-11-10 |
20110272734 | Light-Emitting Device Substrate - The present invention is a minimal-defect light-emitting device substrate that enables emitted light to issue from a device's substrate side, and is a light-emitting device | 2011-11-10 |
20110272735 | SEMICONDUCTOR COMPONENT WITH A TRENCH EDGE TERMINATION - A semiconductor component includes a semiconductor body having a first surface and a second surface, and having an inner region and an edge region. The semiconductor component further includes a pn-junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region. A first trench extends from the first side in the edge region into the semiconductor body. The trench has sidewalls that are arranged opposite to another and that are beveled relative to a horizontal direction of the semiconductor body. | 2011-11-10 |
20110272736 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region. | 2011-11-10 |
20110272737 | TRANSISTOR AND TRANSISTOR CONTROL SYSTEM - A transistor includes a transistor body, and a stress application section applying stress to the transistor body. The transistor body includes a formation substrate, and a first semiconductor layer and a second semiconductor layer which are sequentially stacked on the formation substrate. The second semiconductor layer having a wider bandgap than the first semiconductor layer. The stress application section applies stress to the transistor body so that tensile stress applied to the second semiconductor layer increases in accordance with an increase in a temperature. | 2011-11-10 |
20110272738 | Semiconductor Devices Including Fin Shaped Semiconductor Regions and Stress Inducing Layers - A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode. | 2011-11-10 |
20110272739 | METHOD FOR FABRICATING A STRAINED STRUCTURE - A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film. | 2011-11-10 |
20110272740 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region. | 2011-11-10 |
20110272741 | High electron mobility transistors and methods of manufacturing the same - High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a source electrode, a gate electrode, a drain electrode, a channel formation layer including at least a 2-dimensional electron gas (2DEG) channel, a channel supplying layer for forming the 2DEG channel in the channel formation layer, a portion of the channel supplying layer including a first oxygen treated region. The channel supplying layer may include a second oxygen treated region that extends from the first oxygen treated region towards the drain electrode, and the depth and concentration of oxygen of the second oxygen treated region may be less than those of the first oxygen treated region. | 2011-11-10 |
20110272742 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFCTURING SAME - A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer. | 2011-11-10 |
20110272743 | High Electron Mobility Transistors Including Lightly Doped Drain Regions And Methods Of Manufacturing The Same - High electron mobility transistors (HEMTs) including lightly doped drain (LDD) regions and methods of manufacturing the same. A HEMT includes a source, a drain, a gate, a channel supplying layer for forming at least a 2-dimensional electron gas (2DEG) channel, and a channel formation layer in which at least the 2DEG channel is formed. The channel supplying layer includes a plurality of semiconductor layers having different polarizabilities. A portion of the channel supplying layer is recessed. One of the plurality of semiconductor layers, which is positioned below an uppermost layer is an etching buffer layer, as well as a channel supplying layer. | 2011-11-10 |
20110272744 | Laterally Varying II-VI Alloys and Uses Thereof - Described herein are semiconductor structures comprising laterally varying II-VI alloy layer formed over a surface of a substrate. Further, methods are provided for preparing laterally varying II-VI alloy layers over at least a portion of a surface of a substrate comprising contacting at least a portion of a surface of a substrate within a reaction zone with a chemical vapor under suitable reaction conditions to form a laterally varying II-VI alloy layer over the portion of the surface of the substrate, wherein the chemical vapor is generated by heating at least two II-VI binary compounds; and the reaction zone has a temperature gradient of at least 50-100° C. along an extent of the reaction zone. Also described here are devices such as lasers, light emitting diodes, detectors, or solar cells that can use such semiconductor structures. In the case of lasers, spatially varying wavelength can be realized while in the case of solar cells and detectors multiple solar cells can be achieved laterally where each cell absorbs solar energy of a given wavelength range such that entire solar spectrum can be covered by the said solar cell structure. For LED applications, spatial variation of alloy composition can be used to engineer colors of light emission. | 2011-11-10 |
20110272745 | SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode. | 2011-11-10 |
20110272746 | SOLID STATE IMAGING DEVICE THAT INCLUDES A CONTACT PLUG USING TITANIUM AS A CONTACT MATERIAL, AND MANUFACTURING METHOD THEREOF - The present invention provides a solid state imaging device and a manufacturing method thereof that lowers contact resistance and suppresses dark current, even when wirings and contact plugs are reduced in size. A solid state imaging device | 2011-11-10 |
20110272747 | Electronic component - An electronic component includes a printed conductor structure on a substrate, as well as a film which contacts the printed conductor structure. The film has a smaller layer thickness than the printed conductor. The printed conductor structure has a region which is covered by the film for the purpose of contacting. | 2011-11-10 |
20110272748 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a gate electrode, a source electrode and a drain electrode, all of which are provided on top of a first surface of a substrate, and each of which includes multiple fingers; and an ohmic electrode layer. The semiconductor device includes: a gate terminal electrode connecting the fingers of the gate electrode together; a source terminal electrode connecting the fingers of the source electrode together; a drain terminal electrode connecting the fingers of the drain electrode together; and a gate pad placed on top of the ohmic electrode layer, and connecting the ohmic electrode layer to the gate terminal electrode. The semiconductor device further includes: an n type semiconductor layer formed in the substrate; a p type semiconductor layer formed in the n type semiconductor layer; and a reaction layer formed in the interface between the p type semiconductor layer substrate and the ohmic electrode layer. | 2011-11-10 |
20110272749 | LIGHT RECEIVING CIRCUIT - Provided is a light receiving circuit for detecting a change in amount of light, in which an input circuit at a subsequent stage is compact and inexpensive and current consumption is low. The light receiving circuit includes: a photoelectric conversion element for supplying a current corresponding to an amount of incident light; an N-channel MOS transistor including a drain supplied with the current from the photoelectric conversion element; and a control circuit for controlling a gate voltage of the NMOS transistor via a low pass filter so that a drain voltage of the N-channel MOS transistor becomes a desired voltage. The control circuit outputs a control state output signal, which is a GND terminal voltage when a delay amount of control on the gate voltage of the NMOS transistor performed via the low pass filter is less than a desired delay amount, and is the drain voltage of the NMOS transistor when the delay amount of control on the gate voltage of the NMOS transistor performed via the low pass filter is the desired delay amount or more. The light receiving circuit outputs the control state output signal as an output signal. | 2011-11-10 |
20110272750 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus includes a photoelectric conversion unit with a semiconductor region of a first conduction type, an amplifying transistor, and a contact. The contact supplies, via a semiconductor region of a second conduction type arranged along a side surface and a bottom surface of an element isolation region, a reference voltage to the semiconductor region of the second conduction-type arranged below source and drain regions of the amplifying transistor in a region below a gate electrode of the amplifying transistor. | 2011-11-10 |
20110272751 | SOLID-STATE IMAGING DEVICE - In each photosensitive cell, a photodiode | 2011-11-10 |
20110272752 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a semiconductor device includes, forming a first insulating film to cover a first semiconductor film and a second semiconductor film; forming a first conductive film and a second conductive film over the first semiconductor film and the second semiconductor film, respectively, with the first insulating film interposed therebetween; forming a second insulating film to cover the first conductive film; forming a third conductive film selectively over the first conductive film which is formed over the first semiconductor film, with the second insulating film interposed therebetween, and doping the first semiconductor film with an impurity element with the third conductive film serving as a mask and doping the second semiconductor film with the impurity element through the second conductive film. | 2011-11-10 |
20110272753 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film ( | 2011-11-10 |
20110272754 | MEMORIES AND THEIR FORMATION - Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array. | 2011-11-10 |
20110272755 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprising a first insulating film provided on a semiconductor substrate in a cell transistor region, a first conductive film provided on the first insulating film, an inter-electrode insulating film provided on the first conductive film, a second conductive film provided on the inter-electrode insulating film and having a first metallic silicide film on a top surface thereof, first source/drain regions formed on a surface of the semiconductor substrate, a second insulating film provided on the semiconductor substrate in at least one of a selection gate transistor region and a peripheral transistor region, a third conductive film provided on the second insulating film and having a second metallic silicide film having a thickness smaller than a thickness of the first metallic silicide film on a top surface thereof, and a second source/drain regions formed on the surface of the semiconductor substrate. | 2011-11-10 |
20110272756 | METHOD OF FORMING AN INSULATOR LAYER IN A SEMICONDUCTOR STRUCTURE AND STRUCTURES RESULTING THEREFROM - An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer. | 2011-11-10 |
20110272757 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To improve characteristics of a semiconductor device having a nonvolatile memory. | 2011-11-10 |
20110272758 | Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit - A semiconductor device comprises an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which comprises the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET. This abstract is provided to allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 2011-11-10 |
20110272759 | Vertical LDMOS device and method for fabricating same - A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further comprises diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body. | 2011-11-10 |
20110272760 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes, on a semiconductor substrate, an active region surrounded by an STI region, a gate trench formed in one direction transverse to the active region, a gate insulating film formed on a side surface of the gate trench, an insulating film formed on a bottom of the gate trench and thicker than the gate insulating film, and a gate electrode having at least a part of the gate electrode formed in the gate trench. Portions of the semiconductor substrate present in the active region and located on both sides of the gate trench in an extension direction of the gate trench function as a source region and a drain region, respectively. A portion of the semiconductor substrate located between the side surface of the active region (the side of the STI region) and the side surface of the gate trench functions as a channel region. | 2011-11-10 |
20110272761 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region. | 2011-11-10 |
20110272762 | EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR - A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region. | 2011-11-10 |
20110272763 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Extension regions ( | 2011-11-10 |
20110272764 | Semiconductor Device Having e-Fuse Structure And Method Of Fabricating The Same - A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion. | 2011-11-10 |
20110272765 | MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION - A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals. | 2011-11-10 |
20110272766 | High-K Metal Gate Device - A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F. | 2011-11-10 |
20110272767 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a semiconductor device and a method of fabricating the same. The method comprises: providing a semiconductor substrate; forming a transistor structure on the semiconductor substrate, wherein the transistor structure comprises a gate region and a source/drain region, and the gate region comprises a gate dielectric layer provided on the semiconductor substrate and a sacrificial gate formed on the gate dielectric layer; depositing a first interlayer dielectric layer, and planarizing the first interlayer dielectric layer to expose the sacrificial gate; removing the sacrificial gate to form a replacement gate hole; forming first contact holes at positions corresponding to the source/drain region in the first interlayer dielectric layer; and filling a first conductive material in the first contact holes and the replacement gate hole respectively to form first contacts and a replacement gate, wherein the first contacts come into contact with the source/drain region. Thereby, the replacement gate and the first contacts can be made in one same step of depositing the same material, and thus the process flows are simplified. | 2011-11-10 |
20110272768 | Lead Frame and Method of Producing Lead Frame - Provided is a lead frame, an electronic device provided with a lead frame, a method of producing a lead frame, and a method of producing an electronic device provided with a lead frame that has been produced by the method of producing a lead frame, in which a lead frame is not corroded, a mechanical strength of the lead frame is not lowered, it is not necessary to carry out the conventional plating processing steps composed of two stages, the processes are simple, a cost is lower, and a large amount of waste liquid such as plating processing liquid is not generated, thereby preventing an environment from being affected. The lead frame includes an outer lead part and an inner lead part, and plating is carried out on at least a part of one or both of the outer lead part or the inner lead part. | 2011-11-10 |
20110272769 | MEMS MICROPHONE PACKAGE AND PACKAGING METHOD - A MEMS microphone package having improved acoustic properties, and to a packaging method, which involve adding a vent path in the packaging process to improve equilibrium between internal and external air pressure. The MEMS microphone package includes a MEMS microphone chip, in which a back plate and a diaphragm structure are formed in a body by using MEMS process techniques; a substrate for mounting the MEMS microphone chip thereon; a vent path which is formed between the MEMS microphone chip and the substrate by applying an adhesive only to a portion of the substrate and adhering the MEMS microphone chip to the substrate; and a case which is adhered to the substrate and forms a space for accommodating the MEMS microphone chip, wherein acoustic properties of the MEMS microphone package are improved as air pressure inside the MEMS microphone chip and air pressure outside the MEMS microphone chip form air equilibrium via the vent path. | 2011-11-10 |
20110272770 | METHOD FOR MANUFACTURING MAGNETIC STORAGE DEVICE, AND MAGNETIC STORAGE DEVICE - A lower conductive film is formed over a substrate. A first insulating film is formed in the lower conductive film. An opening which reaches the lower conductive film is formed in the first insulating film. An MTJ multilayer film having a magnetization free layer, a tunnel barrier layer and a magnetization fixed layer is deposited over the lower conductive film in the opening and over the first insulating film. An upper electrode is formed over the MTJ multilayer film. By removing the portion of the MTJ multilayer film deposited over the first insulating film, an MTJ device composed of the portion of the MTJ multilayer film which has remained in the opening is formed. A lower electrode composed of the lower conductive film is formed under the MTJ device by removing at least a part of the first insulating film, and a part of the lower conductive film. | 2011-11-10 |
20110272771 | THIN FILM PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR MANUFACTURING THIN FILM PHOTOELECTRIC CONVERSION DEVICE - A thin film photoelectric conversion device for performing photoelectric conversion of a wide range of light, from the visible range to the infrared range, is provided. A plasmon resonance phenomenon, which enhances a photo-induced electric field, is caused in a wide range of light, by a metal nanostructure which is formed by annealing a substrate on which a first metal thin film layer composed of a first metal and a second metal thin film layer composed of a second metal which is partially overlapped onto the first metal thin film layer are laminated, and in which a periodic structure, wherein a number of first convex parts successively lie with a pitch of from one-tenth of a wavelength of an incident light to a wavelength equal to or shorter than the wavelength of the incident light in a planar direction along the substrate, is formed on the surface of the substrate; and a random structure, wherein a distance between any pair of a number of second convex parts formed at random positions on the substrate, or a distance between a second convex part and a first convex part is shorter than 100 nm, is formed on the substrate in a position within a region of the periodic structure or in a position adjacent to the region of the periodic structure, and as a result, high sensitivity photo-induced current is generated. | 2011-11-10 |
20110272772 | SOLID STATE IMAGING DEVICE - A solid state imaging device includes: a first photoelectric conversion layer of an organic material; a second photoelectric conversion layer of an inorganic material; a third photoelectric conversion layer of an inorganic material; a first filter of an inorganic material; a second filter of an inorganic material. The first photoelectric conversion layer photoelectrically-converts a light of a first color. The first filter is disposed between the first photoelectric conversion layer and the second photoelectric conversion layer to selectively guide a light of a second color, out of a light that passed through the first photoelectric conversion layer, to the second photoelectric conversion layer. The second filter being disposed between the first photoelectric conversion layer and the third photoelectric conversion layer to selectively guide a light of a third color, out of the light that passed through the first photoelectric conversion layer, to the third photoelectric conversion layer. | 2011-11-10 |
20110272773 | METHOD FOR MANUFACTURING SOLID-STATE IMAGE SENSING DEVICE, AND SOLID-STATE IMAGE SENSING DEVICE - A method for manufacturing a solid-state image sensing device, includes mounting a solid-state image sensor on a substrate, forming an elastic layer on a first surface of a glass lid, fixing the glass lid onto the solid-state image sensor with a bonding agent so that the glass lid covers the solid-state image sensor while a second surface opposite to the first surface of the glass lid faces the solid-state image sensor, electrically connecting a terminal provided on the solid-state image sensor, to a terminal provided on the substrate, through a wire, and encapsulating the wire and covering a side surface of the glass lid with a resin. | 2011-11-10 |
20110272774 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which has a low-profile laminate structure including an interlayer insulating film and includes an easily formed alignment mark, and a method for manufacturing the semiconductor device. The semiconductor device includes a photoelectric transducer formed in a semiconductor substrate, a stopper film in a mark area, a first interlayer insulating film formed over the stopper film and photoelectric transducer, a first metal interconnect, and a second interlayer insulating film. A through hole which penetrates the first and second interlayer insulating films and reaches the stopper film is made and a first concave is made in the upper surface of a conductive layer in the through hole. A second concave to serve as an alignment mark is made in a second metal interconnect above the first concave. | 2011-11-10 |
20110272775 | 3D INTEGRATED CIRCUIT SYSTEM AND METHOD - A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer. | 2011-11-10 |
20110272776 | STANDARD CELL, SEMICONDUCTOR DEVICE HAVING STANDARD CELLS, AND METHOD FOR LAYING OUT AND WIRING THE STANDARD CELL - The chip area of a semiconductor device having a plurality of standard cells is to be made smaller. A semiconductor device includes first and second standard cells. The first standard cell includes a diffusion region, a functional device region opposed to the diffusion region, and a metal layer. The second standard cell includes another diffusion region continuous with the diffusion region, another functional device region opposed to the other diffusion region, and further another diffusion region formed between the other diffusion region and the other functional device region. The metal layer and the other functional device region are coupled together electrically through the diffusion regions. | 2011-11-10 |
20110272777 | Manufacturing method and structure of a surface-mounting type diode co-constructed from a silicon wafer and a base plate - A manufacturing method and a structure of a surface-mounting type diode co-constructed from a silicon wafer and a base plate, in the method, a diffused wafer is stacked with a high temperature durable high strength base plate to have them sintered and molten together for connecting with each other to form a co-constructure; then the diffused wafer is processed by etching and ditching for filling with insulation material, electrodes of the diffused wafer are metalized and all on an identical plane, then production of all functional lines is completed; and then the co-constructure is cut to form a plurality of separated individuals which each forms a surface-mounting type diode to be applied straight. In comparison with the conventional techniques, manufacturing of the present invention is simplified and economic in reducing working hours, size and cost of production and the wafer is not subjected to breaking during manufacturing. | 2011-11-10 |
20110272778 | Semiconductor device - A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern. | 2011-11-10 |
20110272779 | EFUSE CONTAINING SIGE STACK - An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent. | 2011-11-10 |
20110272780 | METHOD AND STRUCTURE FOR IMPROVING THE QUALILTY FACTOR OF RF INDUCTORS - An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil. | 2011-11-10 |
20110272781 | SEMICONDUCTOR DEVICE - A package-on-package includes a semiconductor package, and a coil provided at the semiconductor package. The semiconductor package includes a bottom face, and a solder ball protruded from the bottom face. An axis of the coil is inclined with respect to the normal line of the bottom face. | 2011-11-10 |
20110272782 | POWER LAYOUT FOR INTEGRATED CIRCUITS - A power layout of an integrated circuit includes at least one power grid cell. Each power gird cell includes at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The at least one first power layer has conductive lines in at least two different directions. The at least one second power layer has conductive lines in at least two different directions. | 2011-11-10 |
20110272783 | SEMICONDUCTOR DEVICE WITH BIPOLAR TRANSISTOR AND CAPACITOR - A semiconductor device with a bipolar transistor and a capacitor that has a down-sized circuit area is presented. During the manufacture of the bipolar transistor, a polysilicon-insulator-polysilicon capacitor, a polysilicon-insulator-metal layer or a metal-insulator-metal capacitor can be formed on the isolating insulator and/or the protective insulator to achieve reduced circuit area, less manufacturing steps and lowered manufacturing cost. | 2011-11-10 |
20110272784 | SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT CYLINDRICAL CAPACITOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer. | 2011-11-10 |
20110272785 | IC PACKAGE WITH CAPACITORS DISPOSED ON AN INTERPOSAL LAYER - An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation. | 2011-11-10 |
20110272786 | ENERGY STORAGE SYSTEM - An energy storage device ( | 2011-11-10 |
20110272787 | FORMATION OF SELENIDE, SULFIDE OR MIXED SELENIDE-SULFIDE FILMS ON METAL OR METAL COATED SUBSTRATES - A composition for preventing cracking in composite structures comprising a metal coated substrate and a selenide, sulfide or mixed selenidesulfide film. Specifically, cracking is prevented in the coating of molybdenum coated substrates upon which a copper, indium-gallium diselenide (CIGS) film is deposited. Cracking is inhibited by adding a Se passivating amount of oxygen to the Mo and limiting the amount of Se deposited on the Mo coating. | 2011-11-10 |
20110272788 | Computer system wafer integrating different dies in stacked master-slave structures - A stacked 3D integrated circuit structure is manufactured with a common image design for dies which allows diced master dies to cut from the common wafer and diced slave dies cut to be cut from a wafer which has the common image design. In an embodiment is stacked to form a wafer-to-wafer 3D stack before dicing. Master and slave elements which are used for only one kind of separated individual integrated circuit dies which are located along die edges and at die centers before dicing separation of individual integrated circuit chips. A master wafer is shifted ½ way across a die to make cutting along a kerf line effective to provide both master and slave dies. Multiple slaves can be stacked and coupled to a master die which acts as a bus master when attached to a bus to which only the master die is directly connected. The use of a common wafer design minimizes cost of manufacture of chips destined to be stacked as 3D integrated circuits. | 2011-11-10 |
20110272789 | Nanochannel Device and Method for Manufacturing Thereof - The present disclosure relates to a device comprising a mono-crystalline substrate, the mono-crystalline substrate having at least one recessed region which exposes predetermined crystallographic planes of the mono-crystalline substrate, the at least one recessed region further having a recess width and comprising a filling material and an embedded nanochannel, wherein the width, the shape, and the depth of the embedded nanochannel is determined by the recess width of the at least one recessed region and by the growth rate of the growth front of the filling material in a direction perpendicular to the exposed predetermined crystallographic planes. The present disclosure is also related to a method for manufacturing a nanochannel device. | 2011-11-10 |
20110272790 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR WAFER - A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region. | 2011-11-10 |
20110272791 | METHOD FOR FORMING SEMICONDUCTOR DEVICES WITH ACTIVE SILICON HEIGHT VARIATION - A method far farming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors. | 2011-11-10 |
20110272792 | DIE BACKSIDE STANDOFF STRUCTURES FOR SEMICONDUCTOR DEVICES - Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described. | 2011-11-10 |
20110272793 | LEAD FRAME, SEMICONDUCTOR APPARATUS USING THIS LEAD FRAME, INTERMEDIATE PRODUCT THEREOF AND MANUFACTURING METHOD THEREOF - In a lead frame for a semiconductor apparatus 10, including plural terminals 13, one portions of the terminals 13 being sealed with a resin, a resin-sealed portion 16 of the terminal 13 has a polygonal columnar shape that is pentagonal or more or a deformed columnar shape having at least one notch or groove part extending vertically in a periphery. This resin-sealed portion 16 is formed by etching processing or press processing, and an exposed portion 18 of lower half of the terminal 13 is formed by the etching processing. | 2011-11-10 |
20110272794 | PRE-MOLDED CLIP STRUCTURE - A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed. | 2011-11-10 |
20110272795 | SEMICONDUCTOR DEVICE PACKAGING STRUCTURE AND PACKAGING METHOD - Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained. | 2011-11-10 |
20110272796 | Nano-structured Gasket for Cold Weld Hermetic MEMS Package and Method of Manufacture - A structure and method for cold weld compression bonding using a metallic nano-structured gasket is provided. This structure and method allows a hermetic package to be formed at lower pressures and temperatures than are possible using bulk or conventional thin-film gasket materials. | 2011-11-10 |
20110272797 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND POWER SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a casing, a semiconductor element, a terminal and a screw member. The semiconductor element is housed within the casing. The terminal is electrically connected to the semiconductor element, and has an externally projecting part extending out of the casing. The screw member is movably provided along a surface of the casing between the externally projecting part and the casing, and fixes an external terminal to the externally projecting part. | 2011-11-10 |
20110272798 | CHIP UNIT AND STACK PACKAGE HAVING THE SAME - A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other. | 2011-11-10 |
20110272799 | IC CHIP AND IC CHIP MANUFACTURING METHOD THEREOF - An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurality of protrusions and at least one conducting material. The protrusions protrude out of the conducting area and are spaced apart from each other. The conducting material covers the protrusions and electrically connects the conducting area. The method includes: (A) providing a chip body having a conducting area on its surface; (B) forming a plurality of protrusions on the chip body, wherein the protrusions protrude out of the conducting area and are spaced apart from each other; and (C) forming at least one conducting material, wherein the conducting material covers the protrusions and electrically connects the conducting area. | 2011-11-10 |
20110272800 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME - A method of manufacturing a semiconductor package includes placing a semiconductor chip in a recess provided on a surface of a supporting body so that a part of the semiconductor chip projects from the recess; forming a resin part on the surface of the supporting body, the resin part encapsulating the projecting part of the semiconductor chip; removing the supporting body; and forming an interconnection structure electrically connected to the semiconductor chip by using the resin part as a part of the base body of the semiconductor package. | 2011-11-10 |
20110272801 | SEMICONDUCTOR DEVICE WITH CONNECTION PADS PROVIDED WITH INSERTS - A semiconductor device includes an integrated circuit and external electrical connection pads. Each pad includes cavities that are at least partially filled with a material different from the material forming the pads, so as to form inserts. | 2011-11-10 |
20110272802 | BUMP, METHOD FOR FORMING THE BUMP, AND METHOD FOR MOUNTING SUBSTRATE HAVING THE BUMP THEREON - A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer. | 2011-11-10 |
20110272803 | SILICON CONTACTOR INCLUDING PLATE TYPE POWDERS FOR TESTING SEMICONDUCTOR DEVICE - A silicon contactor of which a side contacts test terminals of a semiconductor testing device and of which an other side contacts ball leads of a semiconductor device so as to be used in the semiconductor testing device, including: conductive silicon parts which are formed opposite to the ball leads and/or the test terminals and include silicon rubber and conductive powders; and an insulating silicon part which is formed by filling silicon rubber among areas of the conductive silicon parts, which do not contact the ball leads, and supports the conductive silicon parts, wherein the conductive powders of the conductive silicon parts include plate type powders. Therefore, the plate type powders are used as the conductive powders of the conductive silicon parts to improve contact characteristics between the conductive silicon parts and the semiconductor device. | 2011-11-10 |
20110272804 | SELECTING CHIPS WITHIN A STACKED SEMICONDUCTOR PACKAGE USING THROUGH-ELECTRODES - A stacked semiconductor package includes first and second semiconductor chips including semiconductor chip bodies which have circuit units, first through-electrodes which pass through the semiconductor chip bodies at first positions, and second through-electrodes which pass through the semiconductor chip bodies at second positions and provide a chip enable signal to the circuit units. A spacer including a spacer body may be interposed between the first semiconductor chip and the second semiconductor chip, with an inverter chip embedded in the spacer body. Wiring patterns formed on the spacer body may connect the first through-electrodes of the first semiconductor chip with the second through-electrodes of the second semiconductor chip, the first through-electrodes of the first semiconductor chip with input terminals of the inverter chip, and output terminals of the inverter chip with the second through-electrodes of the first semiconductor chip. | 2011-11-10 |
20110272805 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MODULE - A semiconductor package, a semiconductor device, and a semiconductor module, the semiconductor package including a substrate, the substrate having a plurality of inner pads; a semiconductor chip attached to the substrate, the semiconductor chip being electrically connected to the inner pads; a plurality of lands on the substrate, the plurality of lands being electrically connected to the inner pads; and at least one bypass interconnection on the substrate, wherein the plurality of lands includes a first land and a second land, the bypass interconnection is connected to the first land and the second land, and the first land is spaced apart from the second land by a distance of about three times or greater an average distance between adjacent lands of the plurality of lands. | 2011-11-10 |
20110272806 | SEMICONDUCTOR DICE INCLUDING AT LEAST ONE BLIND HOLE, WAFERS INCLUDING SUCH SEMICONDUCTOR DICE, AND INTERMEDIATE PRODUCTS MADE WHILE FORMING AT LEAST ONE BLIND HOLE IN A SUBSTRATE - Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material. | 2011-11-10 |
20110272807 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY - An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity. | 2011-11-10 |
20110272808 | SEMICONDUCTOR PROCESS AND STRUCTURE - A semiconductor process includes the following steps. Firstly, a conductive substrate is provided. Then, at least one insulating pattern is formed on the conductive substrate. Thereafter at least one metal pattern is formed on the insulating pattern. After that, a passivation layer is formed on the conductive substrate to cover the metal pattern by an electroplating process. | 2011-11-10 |
20110272809 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate. | 2011-11-10 |
20110272810 | STRUCTURE AND METHOD FOR AIR GAP INTERCONNECT INTEGRATION - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures. | 2011-11-10 |
20110272811 | USING UNSTABLE NITRIDES TO FORM SEMICONDUCTOR STRUCTURES - Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place. | 2011-11-10 |
20110272812 | STRUCTURE AND METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES HAVING SELF-ALIGNED DIELECTRIC CAPS - Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level. | 2011-11-10 |
20110272813 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used. | 2011-11-10 |
20110272814 | METHOD FOR ATTACHING WIDE BUS MEMORY AND SERIAL MEMORY TO A PROCESSOR WITHIN A CHIP SCALE PACKAGE FOOTPRINT - A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type. | 2011-11-10 |
20110272815 | SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD FOR THE SAME - A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features. | 2011-11-10 |
20110272816 | WIRING OVER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEREOF - A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition. | 2011-11-10 |