45th week of 2012 patent applcation highlights part 14 |
Patent application number | Title | Published |
20120280265 | LIGHT EMITTING ELEMENT AND IMAGE DISPLAY DEVICE USING THE LIGHT EMITTING ELEMENT - The present invention provides a light emitting element which emits linearly polarized light, has high efficiency, can show a higher luminance and has also adequate productivity. The light emitting element that includes an active layer composed of a semiconductor which generates light includes: a polarizer layer that allows a polarized component in a first direction among the lights generated in the active layer to pass therethrough, reflects a polarized component in a second direction which is perpendicular to the first direction, is formed on a semiconductor of the same group as the active layer, and contains a semiconductor or a metal of the same group as the active layer; a reflective layer that is provided in the opposite side of the polarizer layer with respect to the active layer, and reflects light which has been reflected by the polarizer layer; and a wavelength plate layer that is provided between the polarizer layer and the reflective layer, changes polarization states of the light which has been reflected by the polarizer layer and the light which has been reflected by the reflective layer, and contains a semiconductor of the same group as the active layer. | 2012-11-08 |
20120280266 | Light Emitting Element and Light Emitting Device Using the Same - An object of the present invention is to provide a light emitting element having slight increase in driving voltage with accumulation of light emitting time. Another object of the invention is to provide a light emitting element having slight increase in resistance with increase in film thickness. In an aspect of the invention, a light emitting element includes a first layer, a second layer and a third layer between mutually-facing first and second electrodes. The first layer is provided to be closer to the first electrode than the second layer. The third layer is provided to be closer to the second electrode than the second layer. The first layer contains a bipolar substance and a substance exhibiting an electron accepting ability with respect to the bipolar substance. The second layer contains a bipolar substance and a substance exhibiting an electron donating ability with respect to the bipolar substance. The third layer contains a light emitting substance. | 2012-11-08 |
20120280267 | LIGHTING DEVICE WITH REVERSE TAPERED HEATSINK - A solid state lighting devices includes a heatsink having a first end arranged proximate to a base end, and a second end arranged between the first end and a solid state emitter, wherein at least a portion of the heatsink is wider at point intermediate the first end and the second end than the width of the heatsink at the second end. Such reverse angled heatsink reduces obstruction of light. A heatsink may include multiple fins and a heatpipe. | 2012-11-08 |
20120280268 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed are a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a pad on the plurality of compound semiconductor layers; an electrode layer under the plurality of compound semiconductor layers; and a supporting member disposed under the plurality of compound semiconductor layers and corresponding to the pad. | 2012-11-08 |
20120280269 | LIGHT EMITTING DEVICE - A light emitting device according to the embodiment may include a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer; an electrode on the light emitting structure; a protection layer under a peripheral region of the light emitting structure; and an electrode layer under the light emitting structure, wherein the protection layer comprises a first layer, a second layer, and a third layer, wherein the first layer comprises a first metallic material, and wherein the second layer is disposed between the first layer and the third layer, the second layer has an insulating material or a conductive material. | 2012-11-08 |
20120280270 | Field Effect Transistor Devices with Low Source Resistance - A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region. | 2012-11-08 |
20120280271 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device including: an FET; a MOSFET having a drain thereof connected with a source of the FET; a resistor having one end thereof connected with a gate of the FET and having the other end thereof connected with a source of the MOSFET; and a diode having an anode thereof connected with the gate of the FET and having a cathode thereof connected with the source of the MOSFET. | 2012-11-08 |
20120280272 | PUNCH-THROUGH SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration N | 2012-11-08 |
20120280273 | METHODS AND SUBSTRATES FOR LASER ANNEALING - Methods and substrates for laser annealing are disclosed. The substrate includes a target region to be annealed and a plurality of reflective interfaces. The reflective interfaces cause energy received by the substrate to resonate within the target region. The method includes emitting energy toward the substrate with a laser, receiving the energy with the substrate, and reflecting the received energy with a plurality of reflective interfaces embedded in the substrate to generate a resonance within the target region. | 2012-11-08 |
20120280274 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure is provided, comprising: a Si substrate; a porous structure layer formed on the Si substrate, in which the porous structure layer has a flat surface and comprises a Si | 2012-11-08 |
20120280275 | SEMICONDUCTOR WAFER, ELECTRONIC DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER - Provided is a semiconductor wafer including: a base wafer whose surface is made of a silicon crystal: a Si | 2012-11-08 |
20120280276 | Single Crystal Ge On Si - A single crystal germanium-on-silicon structure includes a single crystal silicon substrate. A single crystal layer of gadolinium oxide is epitaxially grown on the substrate. The gadolinium oxide has a cubic crystal structure and a lattice spacing approximately equal to the lattice spacing or a multiple of the single crystal silicon. A single crystal layer of lanthanum oxide is epitaxially grown on the gadolinium oxide with a thickness of approximately 12 nm or less. The lanthanum oxide has a lattice spacing approximately equal to the lattice spacing or a multiple of single crystal germanium and a cubic crystal structure approximately similar to the cubic crystal structure of the gadolinium oxide. A single crystal layer of germanium with a (111) crystal orientation is epitaxially grown on the layer of lanthanum oxide. | 2012-11-08 |
20120280277 | SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION - In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions. | 2012-11-08 |
20120280278 | Normally-Off High Electron Mobility Transistors - A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage. | 2012-11-08 |
20120280279 | Field Effect Transistor Device with Shaped Conduction Channel - A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region. | 2012-11-08 |
20120280280 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The invention relates to a semiconductor device and a fabrication method thereof. A semiconductor device according to an aspect of the invention comprising: a semiconductor layer on a substrate; an isolation layer on the semiconductor layer; a source and a drain which are in contact with the semiconductor layer, each of the source and the drain comprises multiple fingers, and the multiple fingers of the source intersect the multiple fingers of the drain; and a gate on the isolation layer, the gate is located between the source and the drain and comprises a closed ring structure which encircles the multiple fingers of the source and the drain. | 2012-11-08 |
20120280281 | GALLIUM NITRIDE OR OTHER GROUP III/V-BASED SCHOTTKY DIODES WITH IMPROVED OPERATING CHARACTERISTICS - A semiconductor device includes a first Group III/V layer and a second Group III/V layer over the first Group III/V layer. The first and second Group III/V layers are configured to form an electron gas layer. The semiconductor device also includes a Schottky electrical contact having first and second portions. The first portion is in sidewall contact with the electron gas layer. The second portion is over the second Group III/V layer and is in electrical connection with the first portion of the Schottky electrical contact. The first portion of the Schottky electrical contact and the first or second Group III/V layer can form a Schottky barrier, and the second portion of the Schottky electrical contact can reduce an electron concentration near the Schottky barrier under reverse bias. | 2012-11-08 |
20120280282 | Three Dimensional Multilayer Circuit - A three dimensional multilayer circuit ( | 2012-11-08 |
20120280283 | MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER - A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed. | 2012-11-08 |
20120280284 | MICRO-FLUIDIC ELECTRONIC DEVICES AND METHOD FOR PRODUCING SUCH DEVICES - A micro-fluidic electronic device includes a micro-fluidic component and an electronic component formed on a sheet of paper. An electrically-active layer of the electronic component, such as a nano-material layer, interacts with a fluid sample deposited within a fluid reservoir of the component, and changes the electronic properties of the electronic component. This can be detected by passing an electrical signal through the electronic component. The micro-fluidic electronic device can be formed straightforwardly and inexpensively by printing or mold-casting. | 2012-11-08 |
20120280285 | CHEMICALLY SENSITIVE SENSORS WITH FEEDBACK CIRCUITS - Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis. | 2012-11-08 |
20120280286 | CHEMICALLY-SENSITIVE SAMPLE AND HOLD SENSORS - Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis. | 2012-11-08 |
20120280287 | Integrated Circuit Layouts with Power Rails under Bottom Metal Layer - A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer. | 2012-11-08 |
20120280288 | INVERSION THICKNESS REDUCTION IN HIGH-K GATE STACKS FORMED BY REPLACEMENT GATE PROCESSES - A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (Å); and forming a metal gate material over the high-k dielectric layer. | 2012-11-08 |
20120280289 | Method of Increasing the Germanium Concentration in a Silicon-Germanium Layer and Semiconductor Device Comprising Same - Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium. | 2012-11-08 |
20120280290 | LOCAL INTERCONNECT STRUCTURE SELF-ALIGNED TO GATE STRUCTURE - A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other. | 2012-11-08 |
20120280291 | SEMICONDUCTOR DEVICE INCLUDING GATE OPENINGS - According to example embodiments, a semiconductor device includes a substrate, a device isolation layer over the substrate that defines an active region of the substrate, a gate electrode crossing over the active region in between a source region and a drain region of the active region. The gate electrode defines at least one gate opening. The at least one gate opening may expose a portion of a boundary between the active region and the device isolation layer. | 2012-11-08 |
20120280292 | SEMICONDUCTOR DEVICES WITH SCREENING COATING TO INHIBIT DOPANT DEACTIVATION - A semiconductor device and a method for fabricating the semiconductor device. The device includes: a doped semiconductor having a source region, a drain region, a channel between the source and drain regions, and an extension region between the channel and each of the source and drain regions; a gate formed on the channel; and a screening coating on each of the extension regions. The screening coating includes: (i) an insulating layer that has a dielectric constant that is no greater than about half that of the extension regions and is formed directly on the extension regions, and (ii) a screening layer on the insulating layer, where the screening layer screens the dopant ionization potential in the extension regions to inhibit dopant deactivation. | 2012-11-08 |
20120280293 | STRUCTURES AND METHODS FOR REDUCING DOPANT OUT-DIFFUSION FROM IMPLANT REGIONS IN POWER DEVICES - In accordance with an embodiment, a method of forming a semiconductor structure can include forming a source region of a first conductivity type in a well region of a second conductivity type within a semiconductor region, and forming a first diffusion barrier region disposed between the source region and the well region. The method can include forming a heavy body region of the second conductivity type in the well region and forming a second diffusion bather region having a portion on a side of the heavy body region with a thickness different than a thickness of a portion on a bottom portion of the heavy body region. The method can also include forming a gate electrode, and forming a dielectric insulating the gate electrode from the semiconductor region. | 2012-11-08 |
20120280294 | METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS - An electrical device in which an interface layer comprising arsenic is disposed between and in contact with a conductor and a semiconductor. In some cases, the interface layer may be a monolayer of arsenic. | 2012-11-08 |
20120280295 | IMAGE PICKUP DEVICE - An image pickup device includes pixels, each including a photoelectric conversion unit and a transfer unit. The photoelectric conversion unit includes a first-conductivity-type first semiconductor region and a second-conductivity-type second semiconductor region. A second-conductivity-type third semiconductor region is formed on at least a part of a gap between a photoelectric conversion unit of a first pixel and a photoelectric conversion unit of a second pixel adjacent to the first pixel. A first-conductivity-type fourth semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region is formed between the photoelectric conversion unit and the third semiconductor region. A first-conductivity-type fifth semiconductor region having an impurity concentration higher than the first semiconductor region is arranged between the photoelectric conversion unit and the third semiconductor region and is arranged deeper than fourth semiconductor region. | 2012-11-08 |
20120280296 | Semiconductor Device with DRAM Bit Lines Made From Same Material as Gate Electrodes in Non-Memory Regions of the Device, and Methods of Making Same - Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array. | 2012-11-08 |
20120280297 | DRAM WITH DOPANT STOP LAYER AND METHOD OF FABRICATING THE SAME - A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br. | 2012-11-08 |
20120280298 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively. | 2012-11-08 |
20120280299 | Three-Dimensional Semiconductor Memory Devices and Method of Fabricating the Same - Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other. | 2012-11-08 |
20120280300 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates. | 2012-11-08 |
20120280301 | PHASE TRANSITION MEMORIES AND TRANSISTORS - In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region. | 2012-11-08 |
20120280302 | MEMORY CELL STRUCTURES AND METHODS - Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source region and a drain region, and a first electrode of a diode coupled to the charge storage node. | 2012-11-08 |
20120280303 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a first trench extending in a first direction is formed in a stacked structure in which a plurality of spacer films and a plurality of channel semiconductor films are alternately stacked. A first space is formed by forming a recess in the channel semiconductor films from the first trench. A tunnel dielectric film is formed in the first space, and the first space is further filled with a floating gate electrode film. Second trenches that divide the stacked structure at predetermined interval in the first direction are formed so as to divide the floating gate electrode film between memory cells adjacent to each other in the first direction but not to divide the channel semiconductor films. | 2012-11-08 |
20120280304 | NON-VOLATILE MEMORY DEVICE HAVING A VERTICAL STRUCTURE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions. | 2012-11-08 |
20120280305 | FLASH MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a flash memory device. The flash memory device comprises a semiconductor substrate and a flash memory area located on the semiconductor substrate. The flash memory area comprises a first doped well, which is divided into a first region and a second region by an isolation region, the second region being doped with an impurity having an electrical conductivity opposite to that of the first doped well; a high-k gate dielectric layer located on the first doped well; and a metal layer located on the high-k gate dielectric layer. The present invention enables compatibility between the high-k dielectric metal gate and the erasable flash memory and increases the operation performance of the flash memory. The present invention also provides a manufacturing method of the flash memory device, which greatly increases the production efficiency and yield of flash memory devices. | 2012-11-08 |
20120280306 | ONE-TRANSISTOR COMPOSITE-GATE MEMORY - One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies. | 2012-11-08 |
20120280307 | INTEGRATING SCHOTTKY DIODE INTO POWER MOSFET - A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa. | 2012-11-08 |
20120280308 | VERTICAL POWER TRANSISTOR DIE PACKAGES AND ASSOCIATED METHODS OF MANUFACTURING - The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the first vertical transistor is stacked on top of the second vertical transistor. The first vertical transistor is mounted on a lead frame with the source electrode of the first vertical transistor coupled to the lead frame. The second vertical transistor is stacked on the first vertical transistor with the source electrode of the second vertical transistor coupled to the drain electrode of the first vertical transistor. | 2012-11-08 |
20120280309 | MOS TRANSISTOR SUPPRESSING SHORT CHANNEL EFFECT AND METHOD OF FABRICATING THE SAME - A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer. | 2012-11-08 |
20120280310 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including an isolation layer structure including a doped polysilicon layer pattern doped with first and second impurities of first and second conductivity types at lower and upper portions thereof, the doped polysilicon layer pattern being on an inner wall of a first trench on a substrate including an active region in which the first trench is not formed and a field region including the first trench, and an insulation structure filling a remaining portion of the first trench; a gate structure on the active region; a well region at a portion of the active region adjacent to lower portions of the doped polysilicon layer pattern and being doped with third impurities of the second conductivity type; and a source/drain at a portion of the active region adjacent to upper portions of the doped polysilicon layer pattern and being doped with fourth impurities of the first conductivity type. | 2012-11-08 |
20120280311 | TRENCH-GATE MOSFET DEVICE AND METHOD FOR MAKING THE SAME - The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device. | 2012-11-08 |
20120280312 | STRUCTURE AND METHOD FOR FORMING SHIELDED GATE TRENCH FET WITH MULTIPLE CHANNELS - In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region. | 2012-11-08 |
20120280313 | SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs. | 2012-11-08 |
20120280314 | Gate Pullback at Ends of High-Voltage Vertical Transistor Structure - In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 2012-11-08 |
20120280315 | SEMICONDUCTOR DEVICE - A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes. | 2012-11-08 |
20120280316 | Semiconductor Structure and Manufacturing Method for the Same - A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a first doped well, a first doped electrode, a second doped electrode, doped strips and a doped top region. The doped strips are on the first doped well between the first doped electrode and the second doped electrode. The doped strips are separated from each other. The doped top region is on the doped strips and extended on the first doped well between the doped strips. The first doped well and the doped top region have a first conductivity type. The doped strips have a second conductivity type opposite to the first conductivity type. | 2012-11-08 |
20120280317 | RESURF STRUCTURE AND LDMOS DEVICE - A reduced surface field (RESURF) structure and a lateral diffused metal oxide semiconductor (LDMOS) device including the same are provided. The RESURF structure includes a substrate of a first conductivity type, a deep well region of a second conductivity type, an isolation structure, at least one trench insulating structure, and at least one doped region of the first conductivity type. The deep well region is disposed in the substrate. The isolation structure is disposed on the substrate. The trench insulating structure is disposed in the deep well region below the isolation structure. The doped region is disposed in the deep well region and surrounds a sidewall and a bottom of the trench insulating structure. | 2012-11-08 |
20120280318 | HIGH VOLTAGE DEVICE - A device is disclosed. The device includes s substrate prepared with an active device region. The active device region includes a gate. The device also includes a doped channel well disposed in the substrate adjacent to a first edge of the gate. The first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate. The first edge of the gate and channel edge defines an effective channel length of the device. The effective channel length is self-aligned to the gate. A doped drift well adjacent to a second edge of the gate is also included. | 2012-11-08 |
20120280319 | High-Voltage Transistor having Multiple Dielectrics and Production Method - On a doped well ( | 2012-11-08 |
20120280320 | High voltage device and manufacturing method thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions. | 2012-11-08 |
20120280321 | SEMICONDUCTOR DEVICE - A field-effect transistor ( | 2012-11-08 |
20120280322 | Self-Aligned Contacts for Field Effect Transistor Devices - A field effect transistor device includes a gate stack disposed on a substrate a first contact portion disposed on a first distal end of the gate stack, a second contact portion disposed on a second distal end of the gate stack, the first contact portion disposed a distance (d) from the second contact portion, and a third contact portion having a width (w) disposed in a source region of the device, the distance (d) is greater than the width (w). | 2012-11-08 |
20120280323 | DEVICE HAVING A GATE STACK - A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a second gate layer that are immediately on top of the gate conductive layer. The first gate layer has a first resistance higher than a second resistance of the second gate layer. The second gate layer is conductive, is electrically coupled with the gate conductive layer, and has a contact terminal configured to serve as a gate contact terminal for the device. Fabrication methods of the gate stack are also disclosed. | 2012-11-08 |
20120280324 | SRAM STRUCTURE AND PROCESS WITH IMPROVED STABILITY - An SRAM memory cell with reduced SiGe formation area using a gate extension ( | 2012-11-08 |
20120280325 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes first gate lines arranged at a first interval over a substrate and each configured to have a silicide layer as a highest layer, second gate lines arranged at a second interval greater than the first interval over the substrate and each configured to have the silicide layer as the highest layer, a first insulating layer formed between the first gate lines over the substrate and includes a gap; a second insulating layer formed on the sidewalls of the second gate lines, an etch-stop layer adjacent the second insulating layer, a third insulating layer located over and between the first gate lines and over and between the second gate lines, a capping layer over the third insulating layer, and a contact plug adjacent to the capping layer and the third insulating layer and coupled to a junction, the junction adjacent the substrate between the second gate lines. | 2012-11-08 |
20120280326 | Method for Manufacturing a Hybrid MOSFET Device and Hybrid MOSFET Obtainable Thereby - Disclosed are methods for forming hybrid metal-oxide-semiconductor field effect transistors (MOSFETs) and the hybrid MOSFETS thus obtained. In one embodiment, a method is disclosed that includes providing a first substrate comprising a first region and a second region, providing a second substrate comprising a second semiconductor layer and an insulating layer overlaying the second semiconductor layer, and direct substrate bonding the second substrate to the first substrate, thereby contacting the first region and the second region with the insulating layer. The method further includes selectively removing the second semiconductor layer and the insulating layer in the first region, thereby exposing the first semiconductor layer in the first region, forming a first gate stack of a first MOSFET on the exposed first semiconductor layer in the first region, and forming a second gate stack of a second MOSFET on the second semiconductor layer in the second region. | 2012-11-08 |
20120280327 | Interface device with programmable voltage gain and/or input impedance having an analog switch comprising N and P field effect transistors connected in series - An interface device for connection between two electronic components of an electronic circuit, includes:
| 2012-11-08 |
20120280328 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d | 2012-11-08 |
20120280329 | SEMICONDUCTOR DEVICE - A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode. | 2012-11-08 |
20120280330 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - Semiconductor devices including first and second fin active regions protruding vertically from a substrate and integrally formed with the substrate, a gate insulation layer formed on the first and second fin active regions, a first gate metal contacting the gate insulation layer on the first fin active region, and a second gate metal contacting the first gate metal on the first fin active region and contacting the gate insulation layer on the second fin active region. | 2012-11-08 |
20120280331 | Adaptive Fin Design for FinFETs - A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer. | 2012-11-08 |
20120280332 | PIXEL STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a pixel structure is provided. A patterned semiconductor layer including a lower electrode, a doped source region, a doped drain region and a channel region is formed on a substrate. A gate dielectric layer is formed on the patterned semiconductor layer. A patterned first metal layer including a gate electrode, a scan line and a common electrode is formed on the gate dielectric layer, wherein the channel region is disposed below the gate electrode. A first dielectric layer and a first passivation layer are sequentially formed on the patterned first metal layer. A patterned second metal layer including a source, a drain and a data line is formed on the first passivation layer, wherein the data line is disposed above the common electrode, and the first dielectric layer and the first passivation layer are disposed between the data line and the common electrode. | 2012-11-08 |
20120280333 | MULTI-NANOMETER-PROJECTION APPARATUS FOR LITHOGRAPHY, OXIDATION, INSPECTION, AND MEASUREMENT - An apparatus, method for manufacturing the apparatus, and method for processing a substrate using the apparatus are disclosed. An exemplary apparatus includes a substrate having a plurality of cells, wherein each cell includes a cell structure. The cell structure includes a piezoelectric film portion and a tip disposed over the piezoelectric film portion. The tip is physically coupled with the piezoelectric film portion. | 2012-11-08 |
20120280334 | ACCELERATION SENSOR - In an acceleration sensor, a sensor unit includes a weight portion having a recess section with one open surface and a solid section one-piece formed with the recess section, beam portions for rotatably supporting the weight portion such that the recess section and the solid section are arranged along a rotation direction, a movable electrode, fixed electrodes, detection electrodes electrically connected to the fixed electrodes to detect a capacitance between the movable electrode and the fixed electrodes. A fixed plate is arranged in a spaced-apart relationship with a surface of the weight portion on which the movable electrode is provided, and embedment electrodes are embedded in the fixed plate to extend along a thickness direction of the fixed plate, the embedment electrodes having one end portions facing the movable electrode to serve as the fixed electrodes and the other end portions configured to serve as the detection electrodes. | 2012-11-08 |
20120280335 | COMPONENT - A component includes at least one MEMS component and at least one additional semiconductor component in a common housing having at least one access opening. On the front side of the MEMS component, at least one diaphragm structure is provided, which spans a cavity on the backside of the MEMS component. The housing includes a carrier, on which the MEMS component is mounted. The MEMS component is mounted, using its front side, on the carrier, so that there is a standoff between the diaphragm structure and the carrier surface. The at least one additional semiconductor component is connected to the backside of the MEMS component, so that the MEMS component and the semiconductor component form a chip stack. | 2012-11-08 |
20120280336 | Multilayers having reduced perpendicular demagnetizing field using moment dilution for spintronic applications - A magnetic element is disclosed that has a composite free layer with a FM1/moment diluting/FM2 configuration wherein FM1 and FM2 are magnetic layers made of one or more of Co, Fe, Ni, and B and the moment diluting layer is used to reduce the perpendicular demagnetizing field. As a result, lower resistance x area product and higher thermal stability are realized when perpendicular surface anisotropy dominates shape anisotropy to give a magnetization perpendicular to the planes of the FM1, FM2 layers. The moment diluting layer may be a non-magnetic metal like Ta or a CoFe alloy with a doped non-magnetic metal. A perpendicular Hk enhancing layer interfaces with the FM2 layer and may be an oxide to increase the perpendicular anisotropy field in the FM2 layer. The magnetic element may be part of a spintronic device or serve as a propagation medium in a domain wall motion device. | 2012-11-08 |
20120280337 | Composite free layer within magnetic tunnel junction for MRAM applications - A MTJ in an MRAM array is disclosed with a composite free layer having a FL1/FL2/FL3 configuration where FL1 and FL2 are crystalline magnetic layers and FL3 is an amorphous NiFeX layer for improved bit switching performance. FL1 layer is CoFe which affords a high magnetoresistive (MR) ratio when forming an interface with a MgO tunnel barrier. FL2 is Fe to improve switching performance. NiFeX thickness where X is Hf is preferably between 20 to 40 Angstroms to substantially reduce bit line switching current and number of shorted bits. Annealing at 330° C. to 360° C. provides a high MR ratio of 190%. Furthermore, low Hc and Hk are simultaneously achieved with improved bit switching performance and fewer shorts without compromising other MTJ properties such as MR ratio. As a result of high MR ratio and lower bit-to-bit resistance variation, higher reading margin is realized. | 2012-11-08 |
20120280338 | SPIN TORQUE MRAM USING BIDIRECTIONAL MAGNONIC WRITING - An apparatus is provided for bidirectional writing. A stack includes a reference layer on a tunnel barrier, the tunnel barrier on a free layer, and the free layer on a metal spacer. The apparatus includes an insulating magnet. A Peltier material is thermally coupled to the insulating magnet and the stack. When the Peltier/insulating magnet interface is cooled, the insulating magnet is configured to transfer a spin torque to rotate a magnetization of the free layer in a first direction. When the Peltier/insulating magnet interface is heated, the insulating magnet is configured to transfer the spin torque to rotate the magnetization of the free layer in a second direction. | 2012-11-08 |
20120280339 | PERPENDICULAR MAGNETIC TUNNEL JUNCTION (pMTJ) WITH IN-PLANE MAGNETO-STATIC SWITCHING-ENHANCING LAYER - A STTMRAM element includes a magnetic tunnel junction (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current. | 2012-11-08 |
20120280340 | MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A memory device includes a lower electrode formed on a substrate, and an information storage unit formed on the lower electrode. The information storage unit includes a plurality of information storage layers spaced apart from one another. Each of the plurality of information storage layers is an information unit. A method of manufacturing a memory device uses a porous film to form the plurality of information storage layers. | 2012-11-08 |
20120280341 | INTEGRATED PASSIVE COMPONENT - An integrated passive component having a semiconductor body, arranged on a metal substrate and having a first surface, and a plurality of metal surfaces formed on the surface, a passivation layer formed on the surface, an integrated circuit formed near the surface of the semiconductor body, whereby the integrated circuit is connected to metal surfaces via traces formed below the passivation layer, a part of the metal surfaces is connected to pins via bonding wires, a first part of a first coil, the part formed in part above the semiconductor body, whereby the first coil with a plurality of turns has a longitudinal axis formed substantially parallel to the surface of the semiconductor body, and a second part of the first coil is formed below the semiconductor body. | 2012-11-08 |
20120280342 | INTEGRATED PASSIVE COMPONENT - An integrated passive component having a semiconductor body, arranged on a metal substrate and having a first surface, and a plurality of metal surfaces formed on the surface, a passivation layer formed on the surface, an integrated circuit formed near the surface of the semiconductor body, whereby the integrated circuit is connected to metal surfaces via traces formed below the passivation layer, a part of the metal surfaces is connected to pins via bonding wires, and a first coil formed above the passivation layer, whereby the first coil with a plurality of turns has a longitudinal axis formed substantially parallel to the surface of the semiconductor body, and in a lower part of the first coil, said part which is formed substantially parallel to the longitudinal axis of the coil on the surface of the semiconductor body, parts of a plurality of turns are formed as sections of traces. | 2012-11-08 |
20120280343 | BACK-SIDE ILLUMINATION IMAGE SENSOR AND METHOD FOR FABRICATING BACK-SIDE ILLUMINATION IMAGE SENSOR - A method for fabricating a back-side illumination image sensor includes: implanting a first type of dopant into an epitaxial layer disposed over a first side of a substrate layer to form a first dopant layer in a first side of the epitaxial layer; adhering a carry layer over the first dopant layer for carrying the substrate layer; grinding a second side of the substrate layer for exposing a second side of the epitaxial layer; implanting the first type of dopant into the epitaxial layer from the second side of the epitaxial layer to form a second dopant layer in the second side of the epitaxial layer; forming at least one metal layer over the second dopant layer after forming the second dopant layer in the second side of the epitaxial layer; removing the carry layer; and forming a color filtering module over the first dopant layer. | 2012-11-08 |
20120280344 | Wafer Scale Packaging Platform For Transceivers - A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules. | 2012-11-08 |
20120280345 | PHOTODETECTOR AND A METHOD OF FORMING THE SAME - According to embodiments of the present invention, a photodetector is provided. The photodetector includes a substrate, a waveguide formed on a surface of the substrate, a first metal layer formed on a first side of the waveguide, wherein a first interface is defined between the waveguide and the first metal layer, and a silicide layer formed on a second side of the waveguide, wherein a second interface is defined between the waveguide and the silicide layer, and wherein the second side is opposite to the first side, and wherein at least one of the first interface and the second interface is at least substantially perpendicular to the surface of the substrate. Various embodiments further provide a method of forming the photodetector. | 2012-11-08 |
20120280346 | SENSOR STRUCTURE FOR OPTICAL PERFORMANCE ENHANCEMENT - The present disclosure provides various embodiments of an image sensor device. An exemplary image sensor device includes an image sensing region disposed in a substrate; a multilayer interconnection structure disposed over the substrate; and a color filter formed in the multilayer interconnection structure and aligned with the image sensing region. The color filter has a length and a width, where the length is greater than the width. | 2012-11-08 |
20120280347 | WAVEGUIDE PHOTO-DETECTOR - Provided is a waveguide photodetector that may improve an operation speed and increase or maximize productivity. The waveguide photodetector includes a waveguide layer extending in a first direction, an absorption layer disposed on the waveguide layer, a first electrode disposed on the absorption layer, a second electrode disposed on the waveguide layer, the second electrode being spaced from the first electrode and the absorption layer in a second direction crossing the first direction, and at least one bridge electrically connecting the absorption layer to the second electrode. | 2012-11-08 |
20120280348 | BACK SIDE ILLUMINATED IMAGE SENSOR WITH IMPROVED STRESS IMMUNITY - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side opposite the first side. The substrate has a pixel region and a periphery region. The image sensor device includes a plurality of radiation-sensing regions disposed in the pixel region of the substrate. Each of the radiation-sensing regions is operable to sense radiation projected toward the radiation-sensing region through the back side. The image sensor device includes a reference pixel disposed in the periphery region. The image sensor device includes an interconnect structure that is coupled to the front side of the substrate. The interconnect structure includes a plurality of interconnect layers. The image sensor device includes a film formed over the back side of the substrate. The film causes the substrate to experience a tensile stress. The image sensor device includes a radiation-blocking device disposed over the film. | 2012-11-08 |
20120280349 | PHOTOVOLTAIC MODULE STRUCTURE AND METHOD FOR PRODUCING AN ELECTRICALLY CONDUCTIVE CONNECTION BETWEEN TWO CONTACT LAYERS SPACED APART FROM ONE ANOTHER, IN PARTICULAR IN THE PHOTOVOLTAIC MODULE STRUCTURE - The present invention relates to a photovoltaic module structure | 2012-11-08 |
20120280350 | BARRIER DEVICE POSITION SENSITIVE DETECTOR - According to one embodiment, a position sensitive detector (PSD) comprises a plurality of layers, including a substrate layer, an absorber layer, a barrier layer, a sheet layer, and a contact layer. The absorber layer absorbs incident photons such that the absorbed photons excite positive charges and negative charges in the absorber layer. The barrier layer collects a photocurrent from the absorber layer, the photocurrent comprising either the positive charges or the negative charges. The sheet layer provides resistance to control the flow of the photocurrent between a point of incidence of the photons and a plurality of interconnect contacts. The contact layer comprises the interconnect contacts, each interconnect contact operable to conduct the photocurrent to one or more electrical components external to the PSD. The position sensitive detector facilitates determining the point of incidence of the photons according to a relative amount of photocurrent associated with each interconnect contact. | 2012-11-08 |
20120280351 | ALIGNMENT FOR BACKSIDE ILLUMINATION SENSOR - Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces. | 2012-11-08 |
20120280352 | SEMICONDUCTOR STRUCTURE WITH HEAT SPREADER AND METHOD OF ITS MANUFACTURE - A semiconductor structure is provided and a method for manufacturing said structure. The semiconductor structure includes a thin film semiconductor having an active region and placed on a diamond substrate. The thin film semiconductor is preferably directly bonded to the diamond layer, or may be adhered thereto by a dielectric adhesion. | 2012-11-08 |
20120280353 | PROTECTIVE ELEMENT FOR ELECTRONIC CIRCUITS - A protective element for electronics has at least one Schottky diode and at least one Zener diode which are located between a power supply and the electronics, the anode of the Schottky diode being connected to the power supply and the cathode of the Schottky diode being connected to the electronics, and the cathode and the anode of the Zener diode are connected to ground. The Schottky diode is a trench MOS barrier junction diode or trench MOS barrier Schottky (TMBS) diode or a trench junction barrier Schottky (TJBS) diode and includes an integrated semiconductor arrangement, which has at least one trench MOS barrier Schottky diode and a p-doped substrate, which is used as the anode of the Zener diode. | 2012-11-08 |
20120280354 | METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES - An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process. | 2012-11-08 |
20120280355 | SOS SUBSTRATE WITH REDUCED STRESS - There is provided an SOS substrate with reduced stress. The SOS substrate is a silicon-on-sapphire (SOS) substrate comprising a sapphire substrate and a monocrystalline silicon film on or above the sapphire substrate. The stress of the silicon film of the SOS substrate as measured by a Raman shift method is 2.5×10 | 2012-11-08 |
20120280356 | UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND RESULTING STRUCTURE - A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region. | 2012-11-08 |
20120280357 | Method of Forming an Isolation Structure - Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit. | 2012-11-08 |
20120280358 | INTEGRATED CIRCUITS INCLUDING METAL-INSULATOR-METAL CAPACITORS AND METHODS OF FORMING THE SAME - An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer. | 2012-11-08 |
20120280359 | SEMICONDUCTOR DEVICE - Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film. | 2012-11-08 |
20120280360 | Semiconductor Device and Method for Low Resistive Thin Film Resistor Interconnect - The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction. | 2012-11-08 |
20120280361 | HIGH VOLTAGE RESISTOR WITH BIASED-WELL - Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L. | 2012-11-08 |
20120280362 | SIMPLE ROUTE FOR ALKALI METAL INCORPORATION IN SOLUTION-PROCESSED CRYSTALLINE SEMICONDUCTORS - A precursor solution for producing a semiconductor includes at least one of an alkali metal or an alkali metal compound dissolved in a solvent, and a metal chalcogenide dissolved in the solvent. A method of producing a precursor solution for a semiconductor includes preparing a first precursor solution that has at least one of an alkali metal or an alkali metal compound dissolved in a first solvent, preparing a second precursor solution that has a metal chalcogenide dissolved in a second solvent, and combining the first and second precursor solutions to obtain the precursor solution for producing the semiconductor. A method of producing a semiconductor device includes providing a precursor solution for producing a semiconductor layer on a substructure, and forming a layer of the precursor solution on the substructure. The precursor solution includes at least one of an alkali metal or an alkali metal compound dissolved in a solvent, and a metal chalcogenide dissolved in the solvent. | 2012-11-08 |
20120280363 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - The method for manufacturing a semiconductor device comprises steps of: forming a growth mask with a plurality of openings directly or indirectly upon a substrate that comprises a material differing from GaN-based semiconductor; and growing a plurality of island-like GaN-based semiconductor layers upon the substrate using the growth mask in the (0001) plane orientation in a manner such that the | 2012-11-08 |
20120280364 | SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING PATTERN PEELING - A semiconductor device includes a first pattern and a plurality of second patterns arranged at equal intervals. When the distance of the space between the first pattern and the second pattern closet to the first pattern is larger than a first distance, a plurality of dummy patterns are arranged in the space with shapes and intervals similar to those of the second patterns. When the distance of the space is equal to or less than the first distance and larger than a second distance, the dummy pattern is spaced from the second pattern closest to the first pattern, and extends toward the first pattern to be brought into contact with the first pattern. When the distance of the space is equal to or less than the second distance, the dummy pattern is spaced from the second pattern closest to the first pattern, and is connected to the first pattern. | 2012-11-08 |