45th week of 2012 patent applcation highlights part 13 |
Patent application number | Title | Published |
20120280165 | PIEZOELECTRIC FILM AND METHOD OF MANUFACTURING THE SAME, INK JET HEAD, METHOD OF FORMING IMAGE BY THE INK JET HEAD, ANGULAR VELOCITY SENSOR, METHOD OF MEASURING ANGULAR VELOCITY BY THE ANGULAR VELOCITY SENSOR, PIEZOELECTRIC GENERATING ELEMENT, AND METHOD OF GENERATING ELECTRIC POWER USING THE PIEZOELECTRIC GENERATING ELEMENT - It is an object of the present invention to provide a lead-free piezoelectric film including a lead-free ferroelectric material and having low dielectric loss and high piezoelectric performance comparable to that of PZT, and a method of manufacturing the lead-free piezoelectric film. | 2012-11-08 |
20120280166 | Quasicrystalline Structures and Uses Thereof - This invention relates generally to the field of quasicrystalline structures. In preferred embodiments, the stopgap structure is more spherically symmetric than periodic structures facilitating the formation of stopgaps in nearly all directions because of higher rotational symmetries. More particularly, the invention relates to the use of quasicrystalline structures for optical, mechanical, electrical and magnetic purposes. In some embodiments, the invention relates to manipulating, controlling, modulating and directing waves including electromagnetic, sound, spin, and surface waves, for a pre-selected range of wavelengths propagating in multiple directions. | 2012-11-08 |
20120280167 | FERRITE MAGNETIC MATERIAL, FERRITE MAGNET, AND FERRITE SINTERED MAGNET - A ferrite magnet and a ferrite sintered magnet including a ferrite magnetic material are provided. A main phase of the ferrite magnetic material includes a ferrite phase having a hexagonal crystal structure, and metal element composition expressed by Ca1-w-x-yR wSr xBayFezMm wherein 0.252012-11-08 | |
20120280168 | Silver-nanowire thermo-interface material composite - A thermo-interface material composite uses a thermo-interface material containing silver nanowires. The silver nanowires have high aspect ratios, high thermo-conductivity coefficients and good anti-oxidation capabilities. Hence, an amount of silver nanowires can be added fewer than that of a traditional metal or ceramic powder. In this way, defects on device surface can be speckled during a dispersal process for improving adhesion between devices. Thus, a thermo-interface material is fabricated to obtain a high thermo-conductivity coefficient for further forming a thermo-channel. | 2012-11-08 |
20120280169 | Thermally Conductive Silicone Grease Composition - A thermally conductive silicone grease composition comprises: (A) an organopolysiloxane represented by the following general formula: wherein each R | 2012-11-08 |
20120280170 | COMPOSITIONS FOR POLISHING SILICON-CONTAINING SUBSTRATES - The invention provides chemical-mechanical polishing (CMP) compositions and methods for polishing a silicon-containing substrate. A method of the invention comprises the steps of contacting a silicon-containing substrate with a polishing pad and an aqueous CMP composition, and causing relative motion between the polishing pad and the substrate while maintaining a portion of the CMP composition in contact with the surface of the substrate to abrade at least a portion of the substrate. The CMP composition comprises a ceria abrasive, a polishing additive bearing a functional group with a pK | 2012-11-08 |
20120280171 | PRODUCTION OF BATTERY GRADE MATERIALS VIA AN OXALATE METHOD - An active electrode material for electrochemical devices such as lithium ion batteries includes a lithium transition metal oxide which is free of sodium and sulfur contaminants. The lithium transition metal oxide is prepared by calcining a mixture of a lithium precursor and a transition metal oxalate. Electrochemical devices use such active electrodes. | 2012-11-08 |
20120280172 | METHOD FOR PRODUCING POSITIVE ELECTRODE FOR NON-AQUEOUS ELECTROLYTE SECONDARY CELL AND METHOD FOR PRODUCING NON-AQUEOUS ELECTROLYTE SECONDARY CELL - A method for producing a non-aqueous electrolyte secondary cell by preparing a positive electrode by applying a positive electrode mixture onto a positive electrode core material, the mixture containing a positive electrode active material mainly made of a lithium nickel composite oxide and a binding agent containing polyvinylidene fluoride; measuring the amount of carbon dioxide gas generated when a layer of the positive electrode mixture is removed out of the positive electrode and the layer is heated to 200° C. or higher and 400° C. or lower in an inactive gas atmosphere; selecting a positive electrode satisfying the following formulas: | 2012-11-08 |
20120280173 | PRODUCTION METHOD OF POSITIVE ELECTRODE ACTIVE MATERIAL FOR LITHIUM SECONDARY BATTERY - The production method for a positive electrode active material according to the present invention is a method of producing a positive electrode active material for a lithium secondary battery mainly composed of an olivine-type lithium manganese phosphate compound, wherein the olivine-type lithium manganese phosphate compound is a compound represented by the general formula Li(Mn | 2012-11-08 |
20120280174 | METHOD OF INHIBITING FREE RADICAL POLYMERIZATION OF STYRENE - The method of inhibiting free radical polymerization of styrene includes adding multi-walled carbon nanotubes are added to the styrene monomer. The addition of the multi-walled carbon nanotubes at a concentration of 5% by weight is found to provide effective inhibition of the polymerization of the styrene. Greater decreases in the conversion rate of styrene to polystyrene are found through the addition of multi-walled carbon nanotubes functionalized with a carboxylic group (COOH). Still greater decreases in the conversion rate of styrene to polystyrene are found through the addition of multi-walled carbon nanotubes functionalized with octadecylamine (C | 2012-11-08 |
20120280175 | Apparatus and Method for Converting Biomass to Feedstock for Biofuel and Biochemical Manufacturing Processes - Improved systems and methods for producing feedstock for biofuel and biochemical manufacturing processes are disclosed. Some systems and methods use components that are capable of transferring relatively high concentrations of solid biomass. Some systems and methods recycle a deconstruction catalyst. | 2012-11-08 |
20120280176 | Method and Composition for Removal of Mercaptans from Gas Streams - A composition for removing mercaptan from a gas stream containing at least one acid gas in addition to a mercaptan, the composition comprising a physical and/or chemical solvent for H | 2012-11-08 |
20120280177 | ORGANIC FIBER FOR SOLAR PANEL AND PHOTOLUMINESCENT ELEMENT AND MATERIAL FOR PREPARING THE SAME - An organic fiber for a solar panel and a photoluminescent element and a material for preparing the same are provided. An organic conjugated polymer is dissolved in a solvent and is used to prepare an organic conjugated polymer fiber directly in an electrospinning process. The organic conjugated polymer fiber is applied in an organic photoluminescent base material with a high luminous efficiency or an organic solar panel with a high absorption efficiency. The organic conjugated polymer fiber is prepared directly by using the electrospinning process, and a diameter of the organic conjugated polymer fiber is between about 10 nm and 100 μm. The organic conjugated polymer fiber prepared by the present invention has the characteristics of polymer orientation and high specific surface area, thereby improving the light absorption efficiency, and further has the properties of high crystallinity and continuity, thereby improving the light transmission efficiency and photovoltaic conversion efficiency of the organic solar panel. | 2012-11-08 |
20120280178 | PHOTOLUMINESCENT GRANULATE AND METHOD FOR PRODUCTION THEREOF - A granulate made of a cured mixture comprising a transparent true light matrix in which at least one photoluminescent luminous pigment and a transparent filler material are present, wherein the filler material comprises a grain size of less than 30μ and/or a grain size between 70μ and 1.2 mm. The granulate may be produced by producing a hardenable binder mixture, introducing and mixing a photoluminescent luminous pigment into the hardenable binder mixture, dispersing a filler in the mixture, and milling the hardened mixture to form the granulate. | 2012-11-08 |
20120280179 | Self-Regulating Gas Generator and Method - A self-regulating gas generator that, in response to gas demand, supplies and automatically adjusts the amount of gas (e.g., hydrogen or oxygen) catalytically generated in a chemical supply chamber from an appropriate chemical supply, such as a chemical solution, gas dissolved in liquid, or mixture. In some embodiments, the gas generator may employ a piston, rotating rod, or other element(s) to expose the chemical supply to the catalyst in controlled amounts. In another embodiment, the self-regulating gas generator uses bang-bang control, with the element(s) exposing a catalyst, contained within the chemical supply chamber, to the chemical supply in ON and OFF states according to a self-adjusting duty cycle, thereby generating and outputting the gas in an orientation-independent manner. The gas generator may be used to provide gas for various gas consuming devices, such as a fuel cell, torch, or oxygen respiratory devices. | 2012-11-08 |
20120280180 | Methods for Sulfate Removal in Liquid-Phase Catalytic Hydrothermal Gasification of Biomass - Processing of wet biomass feedstock by liquid-phase catalytic hydrothermal gasification must address catalyst fouling and poisoning. One solution can involve heating the wet biomass with a heating unit to a pre-treatment temperature sufficient for organic constituents in the feedstock to decompose, for precipitates of inorganic wastes to form, for preheating the wet feedstock in preparation for subsequent removal of soluble sulfate contaminants, or combinations thereof. Processing further includes reacting the soluble sulfate contaminants with cations present in the feedstock material to yield a sulfate-containing precipitate and separating the inorganic precipitates and/or the sulfate-containing precipitates out of the wet feedstock. Having removed much of the inorganic wastes and the sulfate contaminants that can cause poisoning and fouling, the wet biomass feedstock can be exposed to the heterogeneous catalyst for gasification. | 2012-11-08 |
20120280181 | DEVICE AND METHOD FOR GENERATING A SYNTHESIS GAS FROM PROCESSED BIOMASS BY ENTRAINED-FLOW GASIFICATION - The present invention relates to a device for generating a synthesis gas (SG) from biomass (BM) by entrained-flow gasification. The device comprises a treatment plant ( | 2012-11-08 |
20120280182 | METHOD FOR HEATING A FIBER-REINFORCED POLYMER ARTICLE - The present invention concerns a method for heating a polymer article reinforced with electrically conductive embedded fibers, comprising the steps of applying an outer, electrically non-conductive coating so as to cover exposed electrically conductive fibers, and irradiating the coated, fiber-reinforced thermosetting polymer article with microwaves within a predetermined frequency range so as to heat up the coated, fiber-reinforced thermosetting polymer article by dielectric heating. | 2012-11-08 |
20120280183 | CERAMIC BORON-CONTAINING DOPING PASTE AND METHODS THEREFOR - A ceramic boron-containing dopant paste is disclosed. The ceramic boron-containing dopant paste further comprising a set of solvents, a set of ceramic particles dispersed in the set of solvents, a set of boron compound particles dispersed in the set of solvents, a set of binder molecules dissolved in the set of solvents. Wherein, the ceramic boron-containing dopant paste has a shear thinning power law index n between about 0.01 and about 1. | 2012-11-08 |
20120280184 | Composite Material of Electroconductor Having Controlled Coefficient of Thermical Expansion - The present invention relates to a composite material comprising a ceramic component, characterized in that it has a negative coefficient of thermal expansion, and carbon nanofilaments, to its obtainment process and to its uses as electrical conductor in microelectronics, precision optics, aeronautics and aerospace. | 2012-11-08 |
20120280185 | Method for Forming an Ink - A method for forming an ink is disclosed. The method includes steps of forming at least one of metal ions and metal complex ions, forming metal chalcogenide nanoparticles, forming a first solution to include the metal chalcogenide nanoparticles and the at least one of metal ions and metal complex ions, wherein metals of the metal chalcogenide nanoparticles, the metal ions and the metal complex ions are selected from group I, group II, group III or group IV of periodic table and repeating at least one forming step of the metal chalcogenide nanoparticles, the metal ions and the metal complex ions, and forming the first solution as the ink if metals of the metal chalcogenide nanoparticles, the metal ions and the metal complex ions do not include all metal elements of a chalcogenide semiconductor material. | 2012-11-08 |
20120280186 | METAL-NANOPARTICLE-CONTAINING COMPOSITE, DISPERSION LIQUID THEREOF, AND METHODS FOR PRODUCING THE METAL-NANOPARTICLE-CONTAINING COMPOSITE AND THE DISPERSION LIQUID - Provided are a composite of nanoparticles of a metal such as gold, silver, a platinum metal, or copper, and a polymer, the composite allowing formation of a metal film having a sufficiently low resistivity in terms of practicality simply by drying at room temperature without requiring any special heating-baking step or any step of removing a protective agent with a solvent; a dispersion liquid of the composite; methods for producing the foregoing; and a plastic substrate formed from the dispersion liquid. When a dispersion liquid of a metal-nanoparticle-containing composite that is prepared by reducing metal ions in an aqueous medium in the presence of a (meth)acrylic-based copolymer having, as side chains, a polyethylene glycol chain and a phosphate residue represented by —OP(O)(OH) | 2012-11-08 |
20120280187 | FINE METAL PARTICLE-CONTAINING COMPOSITION - A fine silver particle-containing composition includes a large number of fine silver particles | 2012-11-08 |
20120280188 | TRANSPARENT CONDUCTIVE THIN FILM AND METHOD OF MANUFACTURING THE SAME - An embodiment of the disclosed technology discloses a transparent conductive thin film and a method of manufacturing the same. The embodiment of the disclosed technology employs tin (II) oxalate (Sn | 2012-11-08 |
20120280189 | PERFLUOROKETONES AS GASEOUS DIELECTRICS - A gaseous dielectric comprising a perfluoroketone of the formula R | 2012-11-08 |
20120280190 | BASE FRAME FOR A LIFTING APPARATUS, ESPECIALLY A CABLE TRACTION MECHANISM, COMPRISING CONNECTING POSSIBILITIES - A lifting apparatus, especially a cable traction mechanism, comprises a base frame that has at least two base plates and at least two longitudinal beams that interconnect the base plates and are spaced apart from each other. Attachment elements are mounted on the base plates by means of holding parts. The lifting apparatus, especially a cable traction mechanism, is characterized by a modular design, where the holding parts are arranged as extensions of the longitudinal beams. | 2012-11-08 |
20120280191 | LIFT ASSIST DEVICE - A lift assist device for assisting a user in lifting an item includes a base having a center portion and a side portion that is angled relative to said center portion, a support shaft extending upward from the center portion of the base, and a support platform rotatably attached at an upper end of the support shaft and rotatable about an axis that is generally parallel to a longitudinal axis of the support shaft. The lift assist device is tiltable between a loading position, where the side portion of the base rests on a floor or support surface and the support shaft is in a tilted orientation, and a lifting position, where the center portion of the base rests on the floor or support surface and the support shaft is in a generally vertical orientation. | 2012-11-08 |
20120280192 | FURCATED COMPOSITE POST - A method of manufacturing a furcated composite post ( | 2012-11-08 |
20120280193 | TERMINAL ARRANGEMENT FOR A ROAD RAIL - In a terminal arrangement for a road rail with a rail profile ( | 2012-11-08 |
20120280194 | FENCE WITH PIVOTABLE PANELS - A partition fence comprises two posts and a panel, pivotally connected between said posts by rotary joints. At least one of the rotary joints has a first joint member, connected to the post and comprising a first rotary bearing unit, and a second joint member, connected to the panel and comprising a second rotary bearing unit. One of the two rotary bearing units radially surrounds the other. Stop faces of the second joint member stop against stop faces of a first joint member when the second joint member is rotated relative to the first joint member. | 2012-11-08 |
20120280195 | RESISTANCE VARIABLE MEMORY CELLS AND METHODS - Resistance variable memory cells and methods are described herein. One or more methods of forming a resistance variable memory cell include forming a silicide material on a terminal of a select device associated with the resistance variable memory cell, forming a modified region of the silicide material by modifying a resistivity of a region of the silicide material, forming a conductive element on at least a portion of the modified region, and forming a resistance variable material on the conductive element. | 2012-11-08 |
20120280196 | ELECTROFORMING FREE MEMRISTOR - An electroforming free memristor ( | 2012-11-08 |
20120280197 | FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL - A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts. | 2012-11-08 |
20120280198 | GCIB-TREATED RESISTIVE DEVICE - The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion. | 2012-11-08 |
20120280199 | NONVOLATILE MEMORY ELEMENT, METHOD OF MANUFACTURING THE SAME, AND NONVOLATILE MEMORY DEVICE - Provided is a nonvolatile memory element achieving a stable resistance change and miniaturization, and a method of manufacturing the same. The nonvolatile memory element includes: a first electrode formed above a substrate; an interlayer insulating layer formed above the substrate including the first electrode and having a memory cell hole reaching the first electrode; a barrier layer formed in the memory cell hole and composed of a semiconductor layer or an insulating layer connected to the first electrode; a second electrode formed in the memory cell hole and connected to the barrier layer; a variable resistance layer formed on the second electrode and having a stacked structure whose resistance value changes based on electric signals; and a third electrode connected to the variable resistance layer and formed on the interlayer insulating layer to cover the memory cell hole. | 2012-11-08 |
20120280200 | RESISTANCE CHANGING ELEMENT, SEMICONDUCTOR DEVICE, AND METHOD FOR FORMING RESISTANCE CHANGE ELEMENT - A resistance changing element according to the present invention comprises a first electrode ( | 2012-11-08 |
20120280201 | OPTIMIZED ELECTRODES FOR RE-RAM - Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element. | 2012-11-08 |
20120280202 | HETEROJUNCTION DEVICE COMPRISING A SEMICONDUCTOR AND A RESISTIVITY-SWITCHING OXIDE OR NITRIDE - A monolithic three dimensional memory array is provided that includes a first memory level formed above a substrate, and a second memory level monolithically formed above the first memory level. The first memory level includes a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction, a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction, the second direction different from the first direction, the second conductors above the first conductors, and a first plurality of devices. Each of the first plurality of devices is disposed between one of the first conductors and one of the second conductors, and includes a resistivity-switching binary metal oxide or nitride compound and a silicon, germanium, or silicon-germanium alloy resistor of a single conductivity type. Numerous other aspects are provided. | 2012-11-08 |
20120280203 | TRANSPARENT PHOTODETECTOR - A transparent photodetector. The transparent photodetector includes a substrate; a waveguide on the substrate; a displaceable structure that can be displaced with respect to the substrate, the displaceable structure in proximity to the waveguide; and a silicon nanowire array suspended with respect to the substrate and mechanically linked to the displaceable structure, the silicon nanowire array comprising a plurality of silicon nanowires having piezoresistance. In operation, a light source propagating through the waveguide results in an optical force on the displaceable structure which further results in a strain on the nanowires to cause,a change in electrical resistance of the nanowires. The substrate may be a semiconductor on insulator substrate. | 2012-11-08 |
20120280204 | DIRECTIONALLY ETCHED NANOWIRE FIELD EFFECT TRANSISTORS - A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. | 2012-11-08 |
20120280205 | Contacts for Nanowire Field Effect Transistors - A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region. | 2012-11-08 |
20120280206 | Nanowire Circuits in Matched Devices - A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire. | 2012-11-08 |
20120280207 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip comprises the following sequence of regions in a growth direction (c) of the semiconductor chip ( | 2012-11-08 |
20120280208 | QUANTUM DOT CHANNEL (QDC) QUANTUM DOT GATE TRANSISTORS, MEMORIES AND OTHER DEVICES - This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories. | 2012-11-08 |
20120280209 | OPTOELECTRONIC DEVICES EMPLOYING PLASMON INDUCED CURRENTS - An electro-optical device includes a substrate on which first and second electrodes are formed. A plurality of nanoparticles are arrayed on the surface of the substrate between the first and second electrodes. The arrayed nanoparticles exhibit plasmonic activity in at least one wavelength band. A plurality of linking molecules are coupled between respective adjacent ones of the nanoparticles and between each of the electrodes and nanoparticles that are adjacent to the electrodes. The linking molecules are selected to exhibit photo-activity that is complementary to the arrayed nanoparticles. | 2012-11-08 |
20120280210 | VERTICAL TUNNELING NEGATIVE DIFFERENTIAL RESISTANCE DEVICES - The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry. | 2012-11-08 |
20120280211 | A p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors - Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET. | 2012-11-08 |
20120280212 | Semi-Polar Nitride-Based Light Emitting Structure and Method of Forming Same - A structure and method for producing same provides a solid-state light emitting device with suppressed lattice defects in epitaxially formed nitride layers over a non-c-plane oriented (e.g., semi-polar) template or substrate. A dielectric layer with “window” openings or trenches provides significant suppression of all diagonally running defects during growth. Posts of appropriate height and spacing may further provide suppression of vertically running defects. A layer including gallium nitride is formed over the dielectric layer, and polished to provide a planar growth surface with desired roughness. A tri-layer indium gallium nitride active region is employed. For laser diode embodiments, a relatively thick aluminum gallium nitride cladding layer is provided over the gallium nitride layer. | 2012-11-08 |
20120280213 | Method of Fabricating Thin Film Transistor and Top-gate Type Thin Film Transistor - A method of fabricating a thin film transistor (TFT) and a top-gate type thin film transistor are disclosed, the method of fabricating a TFT of the present invention comprises steps: (A) providing a substrate; (B) forming a source electrode, a drain electrode, and SWCNT (singled-walled carbon nanotubes) layer on the substrate, in which the source electrode and the drain electrode are spaced in a distance and the SWCNT layer is located between the source electrode and the drain electrode; (C) forming a gate oxide layer on the SWCNT layer; (D) annealing the gate oxide layer with oxygen or nitrogen gas; and (E) forming a gate electrode on the gate oxide layer; wherein the temperature used in the step (D) for annealing is a 500° C. to 600° C. | 2012-11-08 |
20120280214 | ORGANIC EL ELEMENT HAVING CATHODE BUFFER LAYER - An organic EL element having at least a cathode, a cathode buffer layer comprising a HAT derivative, an electron injection transport layer and a light-emitting layer in that order from a substrate side. The organic EL element of the present invention provides the particular advantages of (1) preventing damage to the electron injection transport performance of the electron injection transport layer due to oxygen and/or moisture adsorbed on the cathode, thereby ensuring a supply of electrons to the light-emitting layer, (2) reducing the drive voltage of the organic EL element, (3) preventing an increase in the drive voltage to provide the same current density over the course of the drive time, and (4) controlling the occurrence of current leaks and pixel defects, thereby improving the quality and manufacturing yield of the organic EL element. | 2012-11-08 |
20120280215 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An organic light-emitting display apparatus including: a substrate; a plurality of pixels on a first surface of the substrate, each pixel of the pixels having a first region in which visible rays are emitted and a second region through which external light penetrates, such that the plurality of pixels provide a plurality of first and second regions; a plurality of pixel circuit units in the first region of each pixel, each pixel circuit unit of the pixel circuit units including at least one thin film transistor (TFT); a plurality of first electrodes independently disposed in the first region of each pixel, each first electrode of the first electrodes being electrically connected to each pixel circuit unit; a second electrode facing the first electrodes, the second electrode being electrically connected throughout the pixels; and an intermediate layer including an organic emitting layer between the first electrodes and the second electrode. | 2012-11-08 |
20120280216 | PATTERNING - The present invention provides a method of patterning an electronic or photonic material on a substrate comprising: forming a film (polymer A) of said electronic or photonic material on said substrate; and using a fluoropolymer (e.g. cytop) to protect regions of said electronic or photonic material during a patterning process. | 2012-11-08 |
20120280217 | ELECTRODE FOIL AND ORGANIC DEVICE - There are provided an electrode foil which has both the functions of a supporting base material and a reflective electrode and also has a superior thermal conductivity and heat resistance; and an organic device using the same. The electrode foil comprises a metal foil; a diffusion prevention layer for preventing diffusion of metal derived from the metal foil, the diffusion prevention layer being provided directly on the metal foil; and a reflective layer provided directly on the diffusion prevention layer. | 2012-11-08 |
20120280218 | ORGANIC ELECTROLUMINESCENCE DEVICE - As an organic electroluminescence device that exhibits superior external quantum efficiency and durability during driving at high temperature, and small variation in chromaticity and small increase in voltage after driving at high temperatures and has long lifespan, it is provided that the organic electroluminescence device including on a substrate a pair of electrodes and at least one layer of an organic layer including a light emitting layer disposed between the electrodes, wherein the light emitting layer contains at least one specific iridium complex and any layer of the at least one layer of an organic layer contains at least one compound represented by Formula (1): | 2012-11-08 |
20120280219 | LIGHT EMITTING ELEMENT - An object of the present invention is to provide a material which does not substantially have a hole injection barrier from an electrode. A composite material containing an organic compound and an inorganic compound, in which measured current-voltage characteristics of a thin-film layer formed from the composite material which is sandwiched between a pair of electrodes each having a work function of 3.5 eV to 5.5 eV follow Formula (1) below, is manufactured. | 2012-11-08 |
20120280220 | Organometallic Complex, and Light-Emitting Element, Light-Emitting Device, Electronic Device, and Lighting Device Using the Organometallic Complex - To provide a novel organometallic complex capable of emitting phosphorescence by using an organic compound with which a variety of derivatives can be easily synthesized as a ligand. In addition, to provide an organometallic complex which exhibits red emission. To provide an organometallic complex formed by ortho-metalation of an m-alkoxyphenyl pyrazine derivative represented by General Formula (G0) below with respect to an ion of a metal belonging to Group 9 or Group 10. In addition, to provide an organometallic complex which exhibits red emission formed by ortho-metalation of an m-alkoxyphenyl pyrazine derivative represented by General Formula (G0) below with respect to an ion of a metal belonging to Group 9 or Group 10. | 2012-11-08 |
20120280221 | MATERIAL FOR ORGANIC PHOTOELECTRIC DEVICE INCLUDING ELECTRON TRANSPORTING UNIT AND HOLE TRANSPORTING UNIT, AND ORGANIC PHOTOELECTRIC DEVICE INCLUDING THE SAME - A material for an organic photoelectric device, the material including a compound including a pyridine ( | 2012-11-08 |
20120280222 | FABRICATION METHOD FOR ORGANIC ELECTRONIC DEVICE AND ORGANIC ELECTRONIC DEVICE FABRICATED BY THE SAME METHOD - The present invention provides a fabrication method for an organic electronic device comprising a step of stacking sequentially a first electrode made of a metal, one or more organic material layers, and a second electrode on a substrate, wherein the method comprises the steps of: 1) forming a layer on the first electrode using a metal having a higher oxidation rate than the first electrode before forming the organic material layer, 2) treating the layer formed using a metal having a higher oxidation rate than the first electrode with oxygen plasma to form a metal oxide layer, and 3) treating the metal oxide layer with inert gas plasma to remove a native oxide layer on the first electrode, and an organic electronic device fabricated by the same method. | 2012-11-08 |
20120280223 | OXIDE SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING OXIDE SEMICONDUCTOR DEVICES AND DISPLAY DEVICES HAVING OXIDE SEMICONDUCTOR DEVICES - An oxide semiconductor device may include a gate electrode formed on a substrate, and a gate insulation layer formed on the substrate to cover the gate electrode. A channel protection structure may be disposed on the gate insulation layer to expose a portion of the gate insulation layer. A source electrode may be located on a first portion of the channel protection structure. A drain electrode may be disposed on a second portion of the channel protection structure. An active pattern may be positioned on the exposed portion of the gate insulation layer, the source electrode, and the drain electrode. | 2012-11-08 |
20120280224 | METAL OXIDE STRUCTURES, DEVICES, AND FABRICATION METHODS - Metal oxide structures, devices, and fabrication methods are provided. In addition, applications of such structures, devices, and methods are provided. In some embodiments, an oxide material can include a substrate and a single-crystal epitaxial layer of an oxide composition disposed on a surface of the substrate, where the oxide composition is represented by ABO | 2012-11-08 |
20120280225 | SEMICONDUCTOR DEVICE, MEMORY DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - An oxide semiconductor is used for a semiconductor layer of a transistor included in a semiconductor device, whereby leakage current between a source and a drain can be reduced, so that reduction in power consumption of a semiconductor device and a memory device including the semiconductor device and an improvement in characteristics of retaining stored data (electric charge) in the semiconductor device and the memory device can be achieved. Further, a drain electrode of the transistor, the semiconductor layer, and a first electrode which overlaps with the drain electrode form a capacitor, and a gate electrode is led to an overlying layer at a position which overlaps with the capacitor. Thus, the semiconductor device and the memory device including the semiconductor device can be miniaturized. | 2012-11-08 |
20120280226 | MATERIALS, FABRICATION EQUIPMENT, AND METHODS FOR STABLE, SENSITIVE PHOTODETECTORS AND IMAGE SENSORS MADE THEREFROM - Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s. | 2012-11-08 |
20120280227 | OXIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Features are forming a gate electrode on an insulating substrate; forming a first semiconducting layer mainly composed of an indium oxide and having a film thickness of 5 nm or more onto the gate electrode interposing a gate insulating film; forming a second semiconducting layer mainly composed of zinc and tin oxides without containing indium and having a film thickness of 5 to 50 nm on the first semiconducting layer, and including a step of forming a source electrode and a drain electrode on the second semiconducting layer. In this manner, by combining the materials of the first semiconducting layer and the second semiconducting layer with each other, a semiconductor device with a reduced dependency on the film thickness of the semiconducting layer, little characteristic variations on a large area substrate is provided. | 2012-11-08 |
20120280228 | METAL OXIDE FIELD EFFECT TRANSISTORS ON A MECHANICALLY FLEXIBLE POLYMER SUBSTRATE HAVING A DIE-LECTRIC THAT CAN BE PROCESSED FROM SOLUTION AT LOW TEMPERATURES - The present invention relates to a method for producing an electronic component, in particular a field-effect transistor (FET), comprising at least one substrate, at least one dielectric, and at least one semiconducting metal oxide, wherein the dielectric or a precursor compound thereof based on organically modified silicon oxide compounds, in particular based on silsequioxanes and/or siloxanes, can be processed out of solution, and is thermally treated at a low temperature from room temperature to 350° C., and the semiconductive metal oxide, in particular ZnO or a precursor compound thereof, can also be processed from solution at a low temperature from room temperature to 350° C. | 2012-11-08 |
20120280229 | FLEXIBLE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME AND IMAGE DISPLAY DEVICE - There is provided a method for manufacturing a flexible semiconductor device. The method of the present invention comprises the steps of: (A) providing a metal foil; (B) forming an insulating layer on the metal foil, the insulating layer having a portion serving as a gate insulating film; (C) forming a supporting substrate on the insulating layer; (D) etching away a part of the metal foil to form a source electrode and a drain electrode therefrom; (E) forming a semiconductor layer in a clearance portion located between the source electrode and the drain electrode by making use of the source and drain electrodes as a bank member; and (F) forming a resin film layer over the insulating layer such that the resin film layer covers the semiconductor layer, the source electrode and the drain electrode. In the step (F), a part of the resin film layer interfits with the clearance portion located between the source and drain electrodes. | 2012-11-08 |
20120280230 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THE SAME - An object is to provide a method for manufacturing a highly reliable semiconductor device including thin film transistors which have stable electric characteristics and are formed using an oxide semiconductor. A method for manufacturing a semiconductor device includes the steps of: forming an oxide semiconductor film over a gate electrode with a gate insulating film interposed between the oxide semiconductor film and the gate electrode, over an insulating surface; forming a first conductive film including at least one of titanium, molybdenum, and tungsten, over the oxide semiconductor film; forming a second conductive film including a metal having lower electronegativity than hydrogen, over the first conductive film; forming a source electrode and a drain electrode by etching of the first conductive film and the second conductive film; and forming an insulating film in contact with the oxide semiconductor film, over the oxide semiconductor film, the source electrode, and the drain electrode. | 2012-11-08 |
20120280231 | SEMICONDUCTOR DEVICE, AND TEST METHOD FOR SAME - It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop ( | 2012-11-08 |
20120280232 | PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device includes a first photoelectric conversion unit on a substrate and having a first energy bandgap, a second photoelectric conversion unit having a second energy bandgap that is different from the first energy bandgap, the second photoelectric conversion unit being on the first photoelectric conversion unit, and an intermediate unit between the first and second photoelectric conversion units, the intermediate unit including a stack of a first intermediate layer and a second intermediate layer, each of the first intermediate layer and the second intermediate layer having a refractive index that is smaller than that of the first photoelectric conversion unit, the first intermediate layer having a first refractive index, and the second intermediate layer having a second refractive index that is smaller than the first refractive index. | 2012-11-08 |
20120280233 | NITRIDE-BASED HETEROSTRUCTURE FIELD EFFECT TRANSISTOR HAVING HIGH EFFICIENCY - A high efficiency heterostructure field effect transistor (HFET) capable of suppressing a leakage current and enhancing a current density by lowering a barrier between an electrode and a semiconductor layer is provided. The high efficiency HFET may include a substrate, a semi-insulating gallium nitride (GaN) layer formed on the substrate, an aluminum gallium nitride (AlGaN) layer formed on the GaN layer, and a silicon carbide (Si | 2012-11-08 |
20120280234 | SEMICONDUCTOR DEVICE - A highly reliable semiconductor device which is formed using an oxide semiconductor and has stable electric characteristics is provided. A semiconductor device which includes an amorphous oxide semiconductor layer including a region containing oxygen in a proportion higher than that in the stoichiometric composition, and an aluminum oxide film provided over the amorphous oxide semiconductor layer is provided. The amorphous oxide semiconductor layer is formed as follows: oxygen implantation treatment is performed on a crystalline or amorphous oxide semiconductor layer which has been subjected to dehydration or dehydrogenation treatment, and then thermal treatment is performed on the oxide semiconductor layer provided with an aluminum oxide film at a temperature lower than or equal to 450° C. | 2012-11-08 |
20120280235 | THIN FILM FET DEVICE AND METHOD FOR FORMING THE SAME - A thin film FET device and a method of forming the same are disclosed. The method comprises: etching a single crystal silicon thin film layer on an insulating thin film layer of an SOI substrate, wherein the etched single crystal silicon thin film layer is used as a channel; forming a gate insulating layer on the SOI substrate that has the single crystal silicon channel formed thereon; and forming a gate electrode, a drain electrode, and a source electrode. | 2012-11-08 |
20120280236 | DISPLAY DEVICES AND METHODS OF MANUFACTURING THE DISPLAY DEVICES - A display device includes a switching device, a first pixel electrode, a dielectric layer and a second pixel electrode. The switching device is provided on the lower substrate. The organic layer pattern is disposed on the lower substrate. The organic layer pattern includes a plurality of stepped portions in a pixel region. The first pixel electrode is disposed on the organic layer pattern in the pixel region. The dielectric layer is disposed on the first pixel electrode. A plurality of the second pixel electrodes is disposed on the dielectric layer. The second pixel electrodes are partially superimposed over the first pixel electrode. Non-uniform vertical fields may be minimized by the morphology of the first pixel electrode, so that the display device may have excellent brightness and transmittance. | 2012-11-08 |
20120280237 | Thin Film Transistor Substrate and Method for Fabricating the Same - The present invention relates to a thin film transistor substrate and a method for fabricating the same which can reduce a number of steps. The method for fabricating a thin film transistor substrate includes the steps of a first mask step forming a first conductive pattern on a substrate to include a gate electrode and a gate line, a second mask step depositing a gate insulating film on the substrate having the first conductive pattern formed thereon and forming a second conductive pattern on the gate insulating film to include a semiconductor pattern, source and drain electrodes and data line, a third mask step depositing a first protective film on the substrate having the second conductive pattern formed thereon and forming a pixel contact hole for exposing the drain electrode passed through the first protective film, a fourth mask step forming a third conductive pattern on the first protective films to have a common electrode and a common line and a second protective film to form an undercut with the common electrode and to include a pixel contact hole which exposes the drain electrode on the common electrode, and a fifth mask step forming a fourth conductive pattern to include a pixel electrode spaced from the common electrode by a space provided by the undercut. | 2012-11-08 |
20120280238 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region. | 2012-11-08 |
20120280239 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE THIN FILM TRANSISTOR ARRAY SUBSTRATE - The present disclosed technology is related to a TFT array substrate and a method for fabricating the TFT array substrate. The method may comprise: depositing a transparent conductive film layer and a source-drain metal layer in this order on a base substrate, and forming source electrodes, drain electrodes, data scan lines and transparent pixel electrodes by a first pattering process, with the transparent conductive film layer being left under the source electrodes, the drain electrodes and the data scan lines; on the resultant substrate, depositing a semiconductor layer and forming a patterned semiconductor layer by a second pattering process; and on the resultant substrate, depositing a gate insulator and a gate metal film in this order, and forming gate electrodes and gate scan lines by a third pattering process, the gate electrodes being located over the patterned semiconductor layer. | 2012-11-08 |
20120280240 | LIQUID CRYSTAL DISPLAY DEVICE HAVING FIRST, SECOND, AND THIRD TRANSPARENT ELECTRODES WHEREIN A SECOND REGION OF THE SECOND ELECTRODE PROTRUDES FROM A FIRST REGION - To form a sufficiently large storage capacitor, a liquid crystal display device includes a liquid crystal display panel having a first substrate, a second substrate, and a liquid crystal held between the first substrate and the second substrate, the liquid crystal display panel having multiple pixels arranged in matrix. The first substrate has, in a transmissive display area provided in each of the pixels, a laminated structure containing a first transparent electrode, a first insulating film, a second transparent electrode, a second insulating film, and a third transparent electrode which are laminated in this order. The first transparent electrode and the second transparent electrode are electrically insulated from each other and together form a first storage capacitor through the first insulating film, and the second transparent electrode and the third transparent electrode are electrically insulated from each other and together form a second storage capacitor through the second insulating film. | 2012-11-08 |
20120280241 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE - A thin film transistor substrate with reduced interlayer short-circuit defects in a capacitor, and a display device having the thin film transistor substrate. The thin film transistor substrate includes: a substrate; a thin film transistor having, over the substrate, a gate electrode, a gate insulating film, an oxide semiconductor layer, and a source-drain electrode in order; and a capacitor having, over the substrate, a bottom electrode, a capacitor insulating film, and a top electrode made of oxide semiconductor in order. | 2012-11-08 |
20120280242 | SEMICONDUCTOR FILM AND PHOTOELECTRIC CONVERSION DEVICE - There is provided a semiconductor film formed on a surface of a substrate and containing a crystalline substance, wherein the semiconductor film has a central region including a center of a surface of the semiconductor film and a peripheral region located around the central region, and a crystallization ratio in the peripheral region of the semiconductor film is higher than a crystallization ratio in the central region. There is also provided a photoelectric conversion device including the semiconductor film. | 2012-11-08 |
20120280243 | SEMICONDUCTOR SUBSTRATE AND FABRICATING METHOD THEREOF - A fabricating method of a semiconductor substrate is provided. A patterned mask layer is formed on a substrate base. The patterned mask layer includes a plurality of apertures, and each aperture exposes a portion of the substrate base. A plurality of nano-pillars is formed on the substrate base, wherein each nano-pillar is grown on the portion of the substrate base exposed by each aperture. An insulating layer is formed on a sidewall of each nano-pillar. An epitaxial lateral overgrowth process is performed on a top portion of each nano-pillar, so as to form a semiconductor layer on the nano-pillars, wherein the semiconductor layer is exposed by a plurality of gaps disposed between the nano-pillars. | 2012-11-08 |
20120280244 | High Electron Mobility Transistors And Methods Of Manufacturing The Same - High electron mobility transistors (HEMTs) and methods of manufacturing the same. A HEMT may include a channel layer and a channel supply layer, and the channel supply layer may be a multilayer structure. The channel supply layer may include an etch stop layer and an upper layer on the etch stop layer. A recess region may be in the upper layer. The recess region may be a region recessed to an interface between the upper layer and the etch stop layer. A gate electrode may be on the recess region. | 2012-11-08 |
20120280245 | High Voltage Cascoded III-Nitride Rectifier Package with Stamped Leadframe - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts. | 2012-11-08 |
20120280246 | High Voltage Cascoded III-Nitride Rectifier Package with Etched Leadframe - Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts. | 2012-11-08 |
20120280247 | High Voltage Cascoded III-Nitride Rectifier Package Utilizing Clips on Package Support Surface - Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing. | 2012-11-08 |
20120280248 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a first thin insulating layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive type semiconductor layer. The first thin insulating layer is formed on the active layer. The second conductive type semiconductor layer is formed on the thin insulating layer. | 2012-11-08 |
20120280249 | METHODS FOR IMPROVING THE QUALITY OF STRUCTURES COMPRISING SEMICONDUCTOR MATERIALS - Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods. | 2012-11-08 |
20120280250 | SPACER AS HARD MASK SCHEME FOR IN-SITU DOPING IN CMOS FINFETS - A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described. | 2012-11-08 |
20120280251 | CAVITY-FREE INTERFACE BETWEEN EXTENSION REGIONS AND EMBEDDED SILICON-CARBON ALLOY SOURCE/DRAIN REGIONS - A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor. | 2012-11-08 |
20120280252 | Field Effect Transistor Devices with Low Source Resistance - A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region. | 2012-11-08 |
20120280253 | Stress Regulated Semiconductor Devices and Associated Methods - Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C. | 2012-11-08 |
20120280254 | SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME - According to the present invention, there is provided an SiC epitaxial wafer which reduces triangular defects and stacking faults, which is highly uniform in carrier concentration and film thickness, and which is free of step bunching, and its method of manufacture. The SiC epitaxial wafer of the present invention is an SiC epitaxial wafer in which an SiC epitaxial layer is formed on a 4H—SiC single crystal substrate that is tilted at an off angle of 0.4°-5°, wherein the density of triangular-shaped defects of said SiC epitaxial layer is 1 defect/cm | 2012-11-08 |
20120280255 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region. | 2012-11-08 |
20120280256 | REMOTE PHOSPHOR LIGHT EMITTING DEVICES, COMPONENTS AND FABRICATION - A substrate including phosphor is remotely illuminated by an LED. Optical radiation that emerges through the substrate is measured. Portions of the substrate, such as raised features on the substrate, are then selectively removed responsive to the measuring, so as to obtain a desired optical radiation. In removing portions of the substrate, holes may be drilled through the substrate to provide a separate path for light from the LED that does not pass through the phosphor. Alternatively, a separate LED may be provided outside the dome. | 2012-11-08 |
20120280257 | TFT ARRAY SUBSTRATE AND MANUFACTURING AND REPAIRING METHODS OF THE SAME - An embodiment of the disclosed provides a TFT-LCD array substrate is provided, comprising a base substrate; a first transparent conductive film, a gate layer, a gate insulating layer, a semiconductor layer, and a source/drain electrode layer sequentially formed on the base substrate from the bottom up, wherein for each pixel unit of the array substrate the first transparent conductive film comprises at least a first part and a second part that do not contact with each other, and the first part is located under an area of the data line, without contacting the gate line and the common electrode line. When a data line in the array substrate has an open failure, this part of the transparent conductive film can be welded together with the data line using laser welding so as to repaire the data line. | 2012-11-08 |
20120280258 | Nitride Light-Emitting Diode with a Current Spreading Layer - A nitride light-emitting diode is provided including a current spreading layer. The current spreading layer includes a first layer having a plurality of distributed insulating portions configured to have electrical current flow therebetween; and a second layer including interlaced at least one substantially undoped nitride semiconductor layer and at least one n-type nitride semiconductor layer configured to spread laterally the electrical current from the first layer | 2012-11-08 |
20120280259 | SYSTEM FOR DISPLAYING IMAGES - A system for displaying images is provided. The system includes an emissive display device including a plurality of pixel elements arranged in an array. Each pixel element includes a first substrate and a second substrate disposed thereunder, wherein the first substrate includes at least three subpixel regions. An organic light-emitting device is disposed between the first and second substrates and on the second substrate. At least one patterned polarizer film is disposed between the first and second substrates to be correspondingly located at one of the subpixel regions. At least one retarder film is disposed between the first and second substrates and affixed to the patterned polarizer film. | 2012-11-08 |
20120280260 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided are a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a first electrode on an region of top surface of a first conductive semiconductor layer; a second electrode layer under a second conductive semiconductor layer; and a conductive support member under the second electrode layer, wherein the second conductive semiconductor layer includes a plurality of recesses on a lower portion of the second conductive semiconductor layer, wherein the second electrode layer has an uneven structure corresponding to the plurality of recesses. | 2012-11-08 |
20120280261 | LIGHT-EMITTING DIODE (LED) FOR ACHIEVING AN ASYMMETRIC LIGHT OUTPUT - A light emitting diode (LED) for achieving an asymmetric light output includes a multilayered structure comprising a p-n junction, where at least one layer of the multilayered structure comprises a surface configured to provide a peak emission in a direction away from a normal to a mounting surface, the surface being a top or bottom surface of the layer. | 2012-11-08 |
20120280262 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor light emitting device comprises a circuit, a reflector, an LED chip, an encapsulation layer and a luminescent conversion layer. The encapsulation layer comprises an annular projection formed outside the encapsulation layer. The circuit and the LED chip are covered by the encapsulation layer, wherein the annular projection of the encapsulation layer is inside the reflector; the encapsulation layer also fills in an interspace between two electrodes of the circuit. Therefore the semiconductor light emitting device is rigid and strongly resistant to water vapor and similar contaminants. | 2012-11-08 |
20120280263 | COMPOSITE HIGH REFLECTIVITY LAYER - A high efficiency light emitting diode with a composite high reflectivity layer integral to said LED or package to improve emission efficiency. One embodiment of a light emitting diode (LED) chip comprises a LED and a composite high reflectivity layer integral to the LED to reflect light emitted from the active region. One embodiment of a LED package comprises a LED mounted on a substrate with an encapsulant over said LED and a composite high reflectivity layer arranged to reflect emitted light. The composite layer comprises a plurality of layers such that at least one of said plurality of layers has an index of refraction lower than the encapsulant and a reflective layer on a side of said plurality of layers opposite the LED. In some embodiments, conductive vias are included through the composite layer to allow an electrical signal to pass through the layer to the LED. | 2012-11-08 |
20120280264 | Wavelength conversion chip for use with light emitting diodes and method for making same - A solid-state light source has a wavelength conversion chip affixed to a light emitting diode. Optical coatings, vias, light extraction elements, electrical connections or electrical bond pads can be fabricated on the wavelength conversion chips. | 2012-11-08 |