| 45th week of 2009 patent applcation highlights (11-05-09/11-05-09_15) part 15 |
| Patent application number | Title | Published |
|---|
| 20090273303 | Synchronous light emitting diode lamp string controller - The present invention discloses a synchronous LED lamp string controller, comprising a clock synchronous circuit to receive a reference signal with a constant frequency, and based on which, to generate a system clock; a counter circuit to counter the system clock and generate a clock signal; a control logic circuit to receive said clock signal to generate a control signal; and a driver circuit to receive said control signal to drive at least a light emitting diode. | 11-05-2009 |
| 20090273304 | APPARATUS AND METHOD FOR TRIMMING AN OUTPUT PARAMETER OF AN ELECTRONIC BALLAST - An electronic ballast includes a microprocessor which is programmed to read an external voltage value, output a signal which controls an amount of power outputted by the electronic ballast, and adjust the signal based upon a difference between the external voltage value and an internal reference value. | 11-05-2009 |
| 20090273305 | CONTROL SYSTEM FOR FLUORESCENT LIGHT FIXTURE - A ballast module regulates power output to a fluorescent light. The ballast module includes a component. A temperature sensor senses temperature of the component. A control module adjusts power output to the fluorescent light based on the temperature of the component sensed by the temperature sensor. The control module adjusts power to the fluorescent light by reducing the power output to the fluorescent light or increasing the power output to the fluorescent light. | 11-05-2009 |
| 20090273306 | FAN SPEED CONTROL CIRCUIT - The fan speed control circuit and system of the present invention includes a capacitor or internally triggered triac to enable current to flow across the terminals of an electrical switch for a fan motor when the switch is in the open and OFF position to permit continued operation of a fan so that the system complies with the ASHRAE 62.2 standard. The capacitor may be of a fixed value so that the speed of the fan motor is reduced to a fixed level when the switch is open and OFF. Alternatively, a potentiometer and internally triggered triac arrangement may be used to permit adjustment of the level to which the speed of the fan drops to when the switch is actuated to the open and OFF position. The present invention is a viable less expensive option to prior art microprocessor based fan speed control circuits. | 11-05-2009 |
| 20090273307 | Remote vertical blind opening and closing system - A remote blind actuating system for use in opening and closing blinds with a string incorporates a motor, a pulley, a receiver, and a housing. The motor, the pulley, and the receiver are disposed within the housing. The motor is connected with the pulley and is in communication with the receiver. The pulley is an cylindrical member with a first distal end and a second distal end. The pulley is rotatably affixed to the motor about an axis. The first distal end of the pulley is connected with the motor and the second distal end is connected with the string. | 11-05-2009 |
| 20090273308 | POSITION SENSORLESS CONTROL OF PERMANENT MAGNET MOTOR - Systems and methods of controlling a permanent magnet motor without a mechanical position sensor are provided. In accordance with one embodiment, a motor control system includes an inverter configured to receive direct current (DC) power and output a power waveform to a permanent magnet motor, driver circuitry configured to receive control signals and drive the inverter based upon the control signals, a current sensor configured to determine a sampled current value associated with the power waveform, and control circuitry configured to generate the control signals based at least in part upon a comparison of a flux-producing component of the sampled current value and a flux-producing component of a command reference current value. | 11-05-2009 |
| 20090273309 | PHOTOVOLTAIC CHARGING SYSTEM - A modular charging unit that allows efficient charging of a rechargeable battery with a charging station and during use away from the charging system uses ambient energy to extend battery life of the device. | 11-05-2009 |
| 20090273310 | Concentric connector for electric vehicles - An electrical connection system including a triaxial socket and a triaxial plug, each having three concentric contacts—an inner, an intermediate and an outer contact. In the process of connecting, the outer contacts connect first, the inner contacts connect second, and the intermediate contacts connect third. All contacts except the plug inner contact are connected to an insulator that covers one radial side of the contact, and extends past and over the end of the contact. Two of the insulators isolate the inner contacts from the intermediate contacts prior to either of their connections being made. | 11-05-2009 |
| 20090273311 | Charging System for an Article of Footwear - An article of footwear and a footwear housing is disclosed. The footwear housing includes a charging station that can be used to charge a battery in the footwear housing. | 11-05-2009 |
| 20090273312 | System and Method for Reliable Information Handling System and Battery Communication - Communication between an information handling system and battery has improved reliability by repeated communications of information from the battery using different commands from the information handling system. A battery management unit responds to a first command from an information handling system by sending information stored at a first address associated with the command and then saving the first address at second address. A power manager of the information handling system sends a second command having the second address to the battery management unit. The battery management unit responds to the second command by retrieving the first address stored at the second address, retrieving information stored at the first address and sending the information to the power manager. The power manager restricts operations of the battery, such as charges or discharges, unless the information received in response to the first and second commands matches. | 11-05-2009 |
| 20090273313 | CAPACITY FADE ADJUSTED CHARGE LEVEL OR RECHARGE INTERVAL OF A RECHARGEABLE POWER SOURCE OF AN IMPLANTABLE MEDICAL DEVICE, SYSTEM AND METHOD - System and method for estimating the time before recharging the rechargeable power source of an implantable medical device. In a method, the present charge level of the power source is determined by determining the percentage of total charge consumed over a period of time. The present charge level is then divided by the expected power use to determine time remaining before recharging. Another method utilizes a model to determine the faded capacity of the rechargeable power source based on the number of times the rechargeable power source has been charged and the duration of the rechargeable power source's life. | 11-05-2009 |
| 20090273314 | BATTERY PACK AND CONTROL METHOD - A battery pack includes at least one secondary battery, a fuse, and a control section. The fuse is configured to cut off charge or discharge current of the secondary battery upon detection of an abnormality of the secondary battery. The control section is configured to detect the abnormality of the secondary battery, and to perform a fusion-cutting process of fusion-cutting the fuse in accordance with the result of the detection. Upon detection of the abnormality, the control section measures a first potential being the potential of a subsequent stage of the fuse and a second potential being the potential of the secondary battery. If it is found from the result of the measurement that the first potential and the second potential are equal, the control section determines that the fuse has not been fusion-cut by the fusion-cutting process, and stops the fusion-cutting process. | 11-05-2009 |
| 20090273315 | Method and apparatus for battery pre-check at system power-on - A system including at least one electronic component and a battery check circuit. When a power consumption level of the at least one electronic component is increased, the battery check circuit determines whether to provide power from a battery to the at least one electronic component by comparing a power level of the battery to a first power level. | 11-05-2009 |
| 20090273316 | Method and Device for Recharging a Mobile Device Such As a Headset - A recharging system for recharging a rechargeable battery of a mobile device such as a headset is disclosed. The recharging system includes a rechargeable system battery, a first connector configured to connect the recharging system to the mobile device, a second connector configured to connect the recharging system to a source of electrical power, and a controller configured to direct electrical power as required. | 11-05-2009 |
| 20090273317 | INTELLIGENTIZED HIGH-FREQUENCY CHARGER FOR BATTERIES - An intelligentized high-frequency charger for batteries includes a monolithic processor control circuit, a charging control circuit and a detection circuit electrically connected to the said monolithic processor control circuit respectively. The said monolithic processor control circuit includes a monolithic processor, an auxiliary power supply circuit and a key display circuit electrically connected to the said monolithic processor respectively. The said charging control circuit includes a PWM circuit, a drive circuit, a rectifier and filter circuit, an output control circuit and a current sampling circuit. The detection circuit includes a cell detection circuit, a reverse connection detection circuit, a cell voltage detection circuit and an auto pole circuit. | 11-05-2009 |
| 20090273318 | TIME REMAINING TO CHARGE AN IMPLANTABLE MEDICAL DEVICE, CHARGER INDICATOR, SYSTEM AND METHOD THEREFORE - System and method for estimating a time to recharge a rechargeable power source of an implantable medical device. A plurality of measured parameters relating to the implantable medical device and an external charging device are applied to a model of recharging performance and an estimate is provided to a patient, perhaps in advance of charging. Once charging has begun, updated estimates can be provided until charging is complete. Once charging is complete, the model may be updated to reflect any differences in the estimated time to complete charging and the actual time required to complete charging. The model may be based on limitations to the rate at which charge may be transferred to the rechargeable power source over a plurality of intervals. | 11-05-2009 |
| 20090273319 | HANDHELD DEVICE WITH FAST-CHARGING CAPABILITY - A handheld device with a fast-charging capability is adapted to be connected to a charger to obtain an electric power. The handheld device includes a battery, a charging circuit, a safety circuit, a control unit, and an input module. The charging circuit is electrically connected to the charger and transfers an electric power to the battery. The safety circuit is used for restricting an upper limit of the electric power transferred by the charging circuit. The input module is provided for a user to input an emergency charge command. Upon receiving the emergency charge command, the control unit instructs the safety circuit to lower the restriction on the charging circuit, so as to raise the upper limit of the electric power that can be obtained by the charging circuit, thereby accelerating the charging of the battery. | 11-05-2009 |
| 20090273320 | CONTROLLING BATTERY CHARGING BASED ON CURRENT, VOLTAGE AND TEMPERATURE - Some embodiments of the present invention provide a system that charges a lithium-ion battery. During operation, the system monitors: a current through the battery, a voltage of the battery, and a temperature of the battery. Next, the system uses the monitored current, voltage and temperature to control a charging process for the battery. In some embodiments, controlling the charging process involves: inferring electrode lithium surface concentrations for the battery from the monitored current, voltage and temperature; and applying the charging current and/or the charging voltage in a manner that maintains the inferred electrode lithium surface concentrations for the battery within set limits. | 11-05-2009 |
| 20090273321 | DEVICE AND METHOD FOR CHARGING AN ENERGY STORE - The energy required for equilibrating the charges of at least two cells in series in an energy storage device is introduced by way of a first charge path via an alternating voltage bus to the cell with the lowest cell voltage (U | 11-05-2009 |
| 20090273322 | APPARATUS AND METHOD FOR GENERATING POWER FOR A LOW CURRENT DEVICE - A method for providing power to a low current electronic device includes pivotably coupling a door to a door frame. A rotating member of an alternating current generator is coupled to either the edge surface of the door or the door-facing surface of the door frame. A stationary member of an alternating current generator is coupled to an other of the edge surface of the door and the door-facing surface of the door frame. The door is pivoted toward an open position to thereby rotate the rotating member and generate an alternating current. The door is pivoted toward a closed position to thereby rotate the rotating member and generate an alternating current. | 11-05-2009 |
| 20090273323 | SERIES REGULATOR WITH OVER CURRENT PROTECTION CIRCUIT - A series regulator with an over current protection circuit regulates output current at an output terminal by controlling an output transistor. There is a current sense transistor with a conductivity that is dependent on the conductivity of the output transistor. A current limiting transistor is connected between an input power supply terminal and a differential amplifier output that controls the conductivity of the output transistor. A current supply source provides current to a constant current source and a converter output of a current to voltage converter. The converter output is connected to a control electrode of the current limiting transistor. A first differential transistor couples the current sense transistor to the constant current source and a second differential transistor couples the current supply source to the constant current source. In operation, the current sense transistor controls the conductivity of the second differential transistor thereby varying a control current supplied from the current supply source to the constant current source. When the control current matches a limiting threshold value, a voltage control signal at the converter output controls the current limiting transistor to thereby limit maximum current flow through the output transistor. | 11-05-2009 |
| 20090273324 | SWITCHING REGULATOR - A switching regulator which does not require a capacitor having large time constant as a soft start circuit, reduces variation of the soft start time and the time until a start of a power source voltage stabilizing control | 11-05-2009 |
| 20090273325 | CURRENT NEGATIVE-FEEDBACK CIRCUIT AND DC-DC CONVERTER USING THE CIRCUIT - A current negative-feedback circuit comprises a current detection unit and a sawtooth-shaped waveform generation unit. The current detection unit comprises a first P-ch MOSFET Q | 11-05-2009 |
| 20090273326 | SYSTEMS AND METHODS FOR CONTROLLING OUTPUT CURRENTS OF POWER CONVERTERS - A power converter can include a high-side switch coupled to a power supply terminal and selectively coupled to ground via a conduction path. During an on state duration, the high-side switch can be enabled and the conduction path can be disabled. During an off state duration, the high-side switch can be disabled and the conduction path can be enabled. During a skip state duration, the high-side switch and the conduction path both can be disabled. A controller coupled to the high-side switch can control the on state duration and the skip state duration based on a current reference. The controller can further generate a first control signal for controlling the high-side switch and the conduction path according to the on state duration and the skip state duration, and adjust an output current of the power converter to the current reference according to the first control signal. | 11-05-2009 |
| 20090273327 | POWER SUPPLY DEVICE, ELECTRONIC DEVICE USING THE SAME, AND SEMICONDUCTOR DEVICE - A linear regulator is provided which stabilizes an input voltage based on a reference voltage source that generates a reference voltage, and the reference voltage generated by the reference voltage. An output voltage of the linear regulator is supplied as a power supply voltage of a switching controller and the reference voltage source. The linear regulator is configured to enable switching of a regulation mode in which voltage is outputted according to the reference voltage, and a bypass mode in which an input voltage is outputted as it is, with no relation to the reference voltage. When a power supply apparatus is started up, during a time period until the input voltage reaches a predetermined threshold voltage, the linear regulator operates in the bypass mode, and when the input voltage exceeds the threshold voltage, operates in the regulation mode. | 11-05-2009 |
| 20090273328 | VOLTAGE/CURRENT CONTROL APPARATUS AND METHOD - A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET “on” and the gate of the low-side FET “off”. | 11-05-2009 |
| 20090273329 | STEP-DOWN TYPE SWITCHING REGULATOR - A pulse signal generating circuit generates a pulse signal having a duty ratio controlled such that the output voltage approaches a reference voltage. A driver circuit generates first and second gate voltages, which are to be respectively applied to the gates of a switching transistor and a synchronous rectifier transistor, based upon the pulse signal. A threshold voltage generating unit generates a threshold voltage which is synchronous with the second gate voltage, and which is in the high-level state during a period when the synchronous rectifier transistor is to be turned off and in the low-level state during a period when the synchronous rectifier transistor is to be turned on. A light-load detection comparator compares a switching voltage with the threshold voltage, and outputs a light-load detection signal. | 11-05-2009 |
| 20090273330 | MERGED RAMP/OSCILLATOR FOR PRECISE RAMP CONTROL IN ONE CYCLE PFC CONVERTER - A one cycle power factor correction converter circuit comprising a switch for controlling a DC output voltage of the converter circuit, the switch being switched by a drive signal having a frequency determined by a clock signal; the converter circuit being provided with a DC input voltage and producing the DC output voltage, the DC input voltage being rectified from an AC input; a controller circuit for controlling an on-time or off-time of the switch to set the output voltage and to achieve power factor correction at the AC input; the controller circuit comprising an error amplifier receiving a feedback voltage from the output of the converter circuit and a reference voltage and producing an error signal; a ramp generator receiving the error signal and generating a first ramp signal by integrating a signal related to the error signal; a pulse width modulation circuit receiving the first ramp signal and a signal related to the error signal and producing a pulse width modulated signal by comparing the first ramp signal and the signal related to the error signal; the pulse width modulated signal determining the on-time or off-time of the switch to control the output voltage with power factor correction; further comprising a circuit for terminating the first ramp signal when a predetermined inequality exists between the first ramp signal and a reference signal and for developing the clock signal from the first ramp signal. | 11-05-2009 |
| 20090273331 | REGULATOR CIRCUIT AND CAR PROVIDED WITH THE SAME - An output transistor is provided between an input terminal and an output terminal. An error amplifier adjusts the gate voltage of the output transistor such that the voltage that corresponds to the output voltage approaches a predetermined reference voltage. A fluctuation detection capacitor is provided on a path from the input terminal to a grounded terminal, which sets one terminal thereof to a fixed voltage. A current feedback circuit supplies, to the gate of the output transistor, the current that corresponds to the current that flows through the fluctuation detection capacitor. A clamp circuit clamps the gate voltage of the output transistor. The clamp circuit | 11-05-2009 |
| 20090273332 | FAST, EFFICIENT REFERENCE NETWORKS FOR PROVIDING LOW-IMPEDANCE REFERENCE SIGNALS TO SIGNAL PROCESSING SYSTEMS - Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of a complimentary common-drain output stage, at least one diode-coupled transistor inserted between transistors of the output stage, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide gate voltages to the output stage to establish top and bottom reference voltages about the diode-coupled transistor that are spaced from a common-mode voltage. This reference structure maintains a constant output current as the span between the top and bottom reference voltages is selectively altered. In different embodiments, the diode-coupled transistor is replaced with a bipolar junction transistor. | 11-05-2009 |
| 20090273333 | POWER SUPPLY WITH ADJUSTABLE OUTPUTTED VOLTAGE - A power supply with adjustable outputted voltage includes a casing, a circuit board, a voltage-adjusting knob and a rotary wheel. The casing is provided thereon with a window, and the circuit board is disposed in the casing. The circuit board is electrically connected to AC/DC power input processing circuit in which only AC (or DC) exists or both AC and DC exist simultaneously. The voltage-adjusting knob is electrically connected on the circuit board. The rotary wheel is provided thereon with a plurality of voltage-adjusting numerals. The voltage-adjusting numerals are located to correspond to the window of the casing and are displayed in the window. | 11-05-2009 |
| 20090273334 | System and Method for Efficient Association of a Power Outlet and Device - A system and method for providing automatic or semi-automatic identity association between an outlet of an intelligent power distribution unit and a target device, such as a computer server, which is powered by that outlet. The association is accomplished by enabling identification information to be transmitted between a memory device near or within the target device and the intelligent power distribution unit via a power cable. The power cable may include a specialized interface for mating with the power distribution unit and/or providing the identification information. | 11-05-2009 |
| 20090273335 | Sensing instrument - In adopting a structure in which an oscillator circuit unit and an instrument main body including a measuring unit are separately formed in a sensing instrument measuring the concentration of or determining the presence/absence of a substance to be sensed by using a quartz sensor, the present invention has an object to enable the instrument main body side to know an oscillation frequency of the connected oscillator circuit unit. | 11-05-2009 |
| 20090273336 | Upgradable Test Set - An upgradeable test set is that includes a stimulator circuit to transmit test signals to an electrical equipment under test, a coupling to removeably couple at least the stimulator circuit to one of a plurality of front-end interfaces. The plurality of front-end interfaces include a first front-end interface having a first display and a first input device and a second front-end interface having a second display and a second input device. The first display and the second display have different display characteristics, and the first input device and the second input device have different characteristics. The one of the front-end interfaces communicates a test control parameter to the stimulator circuit and a response of the electrical equipment under test is communicated to the one of the front-end interfaces. The case is configured to enclose the stimulator circuit, the one of the front-end interfaces, and the coupling. | 11-05-2009 |
| 20090273337 | ELECTRIC FIELD SENSOR WITH ELECTRODE INTERLEAVING VIBRATION - An electric field sensor comprising: a substrate having a hole; a shielding electrode and a sensing electrode, disposed in the hole of the substrate; a piezoelectric bar having one end connected to the center of the shielding electrode, the other end fixed on the substrate. Present invention provides several electric field sensors, which have the same feature of utilizing electrodes interleaving vibration to modulate external electric field. They have IC-compatible operation voltage and small volume. | 11-05-2009 |
| 20090273338 | ACTIVE AUTORANGING CURRENT SENSING CIRCUIT - A range-changing circuit for a measurement device having a desirable range includes an array of graduated impedances. And amplifier supplies an electrical voltage to at least one of the impedances of the array. A voltage sensing and limiting switch is provided in a feedback path of the amplifier. The switch limits said electrical voltage supplied to said at least one of the impedances in response to a sensed voltage that is sensed by the switch. An electrical voltage in the desirable range is developed across a different one of the impedances of the array based on an operation of the switch. | 11-05-2009 |
| 20090273339 | CALIBRATION METHOD AND CALIBRATION APPARATUS FOR A HAND-HELD LOCATING DEVICE - A calibration apparatus for a hand-held locating device ( | 11-05-2009 |
| 20090273340 | SELF-CALIBRATING MAGNETIC FIELD MONITOR - A self-calibrating magnetic field monitor is disclosed. In one embodiment, a magnetic field sensor repeatedly generates an electronic signal related to the magnetic field. In addition, a calibration module generates a relative baseline signal based on an average value of the electronic signals for a given time period. A comparator compares the electronic signal with the relative baseline signal and generating an output signal if a difference in the comparing is greater than or equal to a threshold. | 11-05-2009 |
| 20090273341 | SYSTEM INCLUDING SIGNAL OFFSET ESTIMATION - A system includes a first circuit configured to convert a first analog signal to a first digital signal. The system includes a second circuit configured to determine an area of the first digital signal above a set value and an area of the first digital signal below the set value to provide a second digital signal indicating an offset of the first analog signal. | 11-05-2009 |
| 20090273342 | ENHANCED WIRELESS EDDY CURRENT PROBE FOR A NON-DESTRUCTIVE INSPECTION SYSTEM - An enhanced wireless eddy current probe is disclosed which has means to wirelessly couple to a non-destructive inspection (NDI) system situated some distance away from an inspection point on a material under inspection. The disclosed enhanced wireless eddy current probe provides means for executing advanced functions necessary for a complex eddy current inspection operation. These functions include, but are not limited to, storing, loading, and executing a predetermined firing sequence on an array of coil elements, probe balancing, probe calibration, and providing bibliographic information specific to said probe to a wirelessly coupled NDI system. | 11-05-2009 |
| 20090273343 | REDUCING IMAGING-SCAN TIMES FOR MRI SYSTEMS - Provided are methods and systems for rapid MRI imaging-scanning that provides 2D or 3D coverage, high precision, and high-temporal efficiency, without exceeding SAR limits. In one embodiment, a pulse sequence process is performed that includes a T | 11-05-2009 |
| 20090273344 | METHOD FOR SIMULTANEOUSLY MEASURING T2* AND DIFFUSION WITH MAGNETIC RESONANCE IMAGING - A method for measuring the apparent transverse relaxation time (“T | 11-05-2009 |
| 20090273345 | Method for determining the spatial distribution of magnetic resonance signals with use of local spatially encoding magnetic fields - A method for determining the spatial distribution of magnetic resonance (MR) signals from an imaging region within MSEM regions of a local gradient system, wherein, in a preparatory step, a spatial encoding scheme is defined; in an execution step, nuclear spins are repeatedly excited with RF pulses, and thereafter spatially encoded according to the spatial encoding scheme, in at least one dimension by means of the local gradient system, and MR signals are acquired, from which the spatial distribution is calculated, visualized and/or stored, | 11-05-2009 |
| 20090273346 | APPARATUS AND METHOD FOR OPTIMIZING THE SPECTRA OF PARALLEL EXCITATION PULSES - An MRI apparatus includes a magnetic resonance imaging (MRI) system having a magnet to impress a polarizing magnetic field, a plurality of gradient coils positioned about the bore of the magnet to impose a magnetic field gradient, and an RF transceiver system and an RF switch controlled by a pulse module to transmit RF pulses to an RF coil assembly and to acquire MR images, and a computer programmed to apply a plurality of RF pulses configured to control RF excitation by a transmit coil array such that a waveform shape of each of the plurality of RF pulses is based on optimizing a spatial spectrum. | 11-05-2009 |
| 20090273347 | TILED RECEIVER COIL ARRAY WITH IMPROVED SPATIAL COVERAGE - A phased array for a magnetic resonance (MR) imaging apparatus is disclosed that includes a plurality of receiver coils arranged to form a staggered hexagonal coil array, with the staggered hexagonal coil array being rectangular in shape. Included in the plurality of receiver coils are a plurality of standard coils and a plurality of filler coils differing in shape from the standard coils. The shape of the filler coils is such that no more than negligible mutual inductance between the filler coils and all adjacent overlapping standard coils is present. | 11-05-2009 |
| 20090273348 | CHAMBER APPARATUS AND METHOD OF MANUFACTURE THEREOF - A chamber apparatus comprises a chamber housing for maintaining a vacuum. The housing has a bore tube bounded by a substantially cylindrical wall formed at least in part from a coil suspended in a substantially non-metallic material. | 11-05-2009 |
| 20090273349 | SYSTEM AND METHOD FOR MONITORING A POWER SOURCE OF AN IMPLANTABLE MEDICAL DEVICE - Techniques for monitoring a battery of an implantable medical device are disclosed. First and second current sources are provided to draw currents having amplitudes of I | 11-05-2009 |
| 20090273350 | Systems and Methods for Detecting Wire Breaks - A circuit is provided that includes a power source and a sensor circuit electrically coupled by a switch to the power source. The circuit further includes an A/D converter electrically coupled to the sensor circuit and adapted to read a voltage difference across a resistive element to determine an impedance of the sensor circuit. A method is provided that includes closing a switch electrically coupling a power source to a sensor circuit and measuring a voltage difference across a resistive element at an A/D converter electrically coupled to the sensor circuit. The method further includes determining an impedance of the sensor circuit based on the voltage difference. | 11-05-2009 |
| 20090273351 | Electronic element testing and supporting apparatus - An electronic element testing and supporting apparatus includes a circuit board, an outer frame, an inner frame, a plate and two locking devices. The outer frame is assembled on a second surface of the circuit board and has a plurality of outer frame. Two opposing outer frame rims are provided respectively with a slot having an accommodating opening and an accommodating hole. The inner frame is lodged in the outer frame. The plate is inserted into the slots via the accommodating openings of the two opposing outer frame rims. The locking device includes an elastic element disposed in the accommodating hole of the outer frame rim and a stopper. The elastic element abuts against the stopper, so that the stopper can be movably extended into the corresponding slot to stop the plate. Via this arrangement, the present invention avoids using screws to lock the plate and the inner frame. | 11-05-2009 |
| 20090273352 | SENSOR APPARATUS AND SYSTEM FOR TIME DOMAIN REFLECTOMETRY - A sensor probe for time domain reflectometry may include a plurality of flexible elongated strips of an electrically conductive material extending from a proximal end portion of the probe to a distal end portion thereof. Each of the elongated strips can be substantially coplanar relative to each other along a path that is transverse to a longitudinal axis of the probe, and the plurality of elongated strips also being in a substantially parallel arrangement along the length of the probe. A flexible substrate of an insulating material can be attached to the sheets to maintain the sheets in the substantially parallel and coplanar arrangement. A connector is electrically coupled to the strips for providing communication of electrical signals relative to the strips. | 11-05-2009 |
| 20090273353 | STRAIN MONITORING SYSTEM AND APPARATUS - This application relates to an apparatus and system for sensing strain on a portion of an implant positioned in a living being. In one aspect, the apparatus has at least one sensor assembly that can be mountable thereon a portion of the implant and that has a passive electrical resonant circuit that can be configured to be selectively electromagnetically coupled to an ex-vivo source of RF energy. Each sensor assembly, in response to the electromagnetic coupling, can be configured to generate an output signal characterized by a frequency that is dependent upon urged movement of a portion of the passive electrical resonant circuit and is indicative of strain applied thereon a portion of the respective sensor assembly. | 11-05-2009 |
| 20090273354 | Dielectric Sensing Method and System - Sensing device and method for detecting presence and concentration of generic target analytes of interest. The device and method are based on detecting changes in effective dielectric induced by the target analytes of interest. Applications of the invention include, but are not restricted to, detecting and characterizing the presence of chemical and/or biological target analytes of interest as well as detecting and characterizing target analytes of interest from a separation apparatus. In one embodiment of the invention, the device comprises at least two electrodes in a rigid architecture such as a solid surface, where the electrodes have sizes and inter-electrode spacings that are on the order of sizes of target analytes of interest to improve sensitivity of the device. Changes in effective dielectric and, therefore, capacitance induced by a presence of the target analytes of interest are measured electronically. The changes are used to detect the presence of the target analytes of interest and to characterize their presence. | 11-05-2009 |
| 20090273355 | CAPACITIVE SENSING SLIDE DETECTION - A circuit includes a first capacitor having first and second capacitive sensing strips positioned on first and second sliding portions of the slider type mobile device. In the closed position, the first and second capacitive sensing strips overlap one another and in an open position the first and second capacitive sensing strips have no overlap with one another. A voltage divider having a voltage V | 11-05-2009 |
| 20090273356 | INSULATED SUBSTRATE IMPEDANCE TRANSDUCERS - The present invention provides an electronic transducer ( | 11-05-2009 |
| 20090273357 | CONTACT FOR ELECTRICAL TEST OF ELECTRONIC DEVICES, METHOD FOR MANUFACTURING THE SAME, AND PROBE ASSEMBLY - A contact for an electrical test comprises a first area to be bonded to a board, a second area extending in the right-left direction from the lower end portion of the first area, a third area projecting downward from the tip end portion of the second area, and a low light reflective film having lower light reflectance than that of the first area. The third area has a probe tip to be contacted an electrode of an electronic device. The low light reflective film is formed on a surface of at least the bonding part of the first area to the board and its proximity. | 11-05-2009 |
| 20090273358 | METHOD AND APPARATUS FOR ENHANCED PROBE CARD ARCHITECTURE - A technique for distributing power to a plurality of dies uses a probe card. The probe card can include a plurality of regulators, each regulator accepting a bulk power input and producing a regulated output. The regulated output can be controlled by a programmable controller that accepts a tester-controlled power input and adjusts the regulated outputs as a function of the tester-controlled power input. | 11-05-2009 |
| 20090273359 | ELECTRICAL TESTING APPARATUS HAVING MASKED SOCKETS AND ASSOCIATED SYSTEMS AND METHODS - An apparatus for forming a temporary electrical connection with a microelectronic component and associated systems and methods are disclosed herein. Embodiments of the apparatus can include a base, a plurality of electrical contacts coupled to the base, and a nest attached to the base. The nest includes a plurality of contact compartments aligned with peripheral leads of the microelectronic component and at least partially covering the contacts. Individual contact compartments are masked to prevent a corresponding contact from electrically contacting the peripheral leads of the microelectronic component. In one embodiment, the masked contact compartments are used as a guide zone to guide individual peripheral leads when the microelectronic component is seated at or unseated from the support surface. In an additional or alternative embodiment, the masked contact compartments are used to selectively isolate contacts, for example, from supply or ground electrical potentials. | 11-05-2009 |
| 20090273360 | SYSTEM FOR ISOLATING A SHORT-CIRCUITED INTEGRATED CIRCUIT (IC) FROM OTHER ICs ON A SEMICONDUCTOR WAFER - A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated. | 11-05-2009 |
| 20090273361 | LOCALIZED CALIBRATION OF PROGRAMMABLE DIGITAL LOGIC CELLS - An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit configurations or (ii) a voltage level controller. A self-calibration system is provided that includes at least one reference device, a measurement device for measuring at least one electrical performance parameter that can affect a processing speed of the first programmable digital logic cell or at least one parameter that can affect the electrical performance parameter using the reference device to obtain calibration data. A processing device maps the calibration data or a parameter derived therefrom to generate a control signal that is operable to select from the plurality of different accessible circuit configurations or a voltage level output to change the processing speed of the programmable digital logic cell. | 11-05-2009 |
| 20090273362 | BOOSTER CIRCUITS FOR REDUCING LATENCY - A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition. | 11-05-2009 |
| 20090273363 | OUTPUT DRIVER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OUTPUT DRIVER CIRCUIT, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE - Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal. | 11-05-2009 |
| 20090273364 | CALIBRATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE CALIBRATION CIRCUIT - Calibration circuit, semiconductor memory device including the same, and operation method of the calibration circuit includes a calibration unit configured to generate a calibration code for controlling a termination resistance value, a calibration control unit configured to count a clock and allow the calibration unit to be enabled during a predetermined clock and a clock control unit configured to selectively supply the clock to the calibration control unit according to an operation mode of a semiconductor device employing the calibration circuit. | 11-05-2009 |
| 20090273365 | DATA INPUT/OUTPUT MULTIPLEXER OF SEMICONDUCTOR DEVICE - There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line. | 11-05-2009 |
| 20090273366 | SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT CONTROL METHOD, AND TERMINAL SYSTEM - A semiconductor integrated circuit | 11-05-2009 |
| 20090273367 | IC HAVING PROGRAMMABLE DIGITAL LOGIC CELLS - An integrated circuit (IC) includes at least one programmable digital logic cell that includes first dedicated digital logic cell having a plurality of transistors including at least one PMOS transistor and at least one NMOS transistor configured to perform at least one digital logical function. The first dedicated digital logic cell includes a plurality of nodes including at least one input node and at least one output node that reflects performance of a digital logical function. Programmable tuning circuitry includes at least one tuning input and at least one tuning circuit output. Circuitry for coupling or decoupling the tuning input or tuning circuit output to at least one of the plurality of nodes of the first dedicated digital logical cell is provided, wherein the coupling or decoupling is operable to change the processing speed for the first reprogrammable digital logic cell. | 11-05-2009 |
| 20090273368 | SCALABLE NON-BLOCKING SWITCHING NETWORK FOR PROGRAMMABLE LOGIC - A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits. | 11-05-2009 |
| 20090273369 | GTL BACKPLANE BUS WITH IMPROVED RELIABILITY - Isolation components such as p-n junction or Schottky diodes are provided at pull-up resistors of each signal line of a Gunning Transceiver Logic (GTL) backplane bus in an electronic system for improved reliability, specifically to prevent momentary termination of the bus to ground when a circuit card incorporating the pull-up resistors is inserted into the system. | 11-05-2009 |
| 20090273370 | Muller-C Element - The invention relates to an electronic device that includes an MCML Muller-c element. The MCML Muller-c element has a first differential stage for operating in a trans-conductance state converting the differential input to a differential output current implementing the logical behavior of the MCML Muller-c element and a second stage operating as a trans-impedance stage being coupled to the first stage. Further, the MCML Muller-c element has peaking circuitry being coupled to the first stage, such that the peaking circuitry and the first stage provide a negative capacitance to the MCML Muller-c element for reducing the damping factor of the MCML Muller-c element. | 11-05-2009 |
| 20090273371 | PHASE COMPARATOR, PHASE SYNCHRONIZING CIRCUIT, AND PHASE-COMPARISON CONTROL METHOD - A phase comparator includes an edge detecting unit to which a reference signal is input and to which a referred signal based on the reference signal is input as a feedback signal. The edge detecting unit detects an edge of the reference signal and an edge of the referred signal. The phase comparator also includes a phase-difference detecting unit that detects a phase difference between the edge of the reference signal and the edge of the referred signal. The phase comparator also includes a phase-difference-signal output unit that outputs a phase-difference signal for current control based on the phase difference. The phase comparator also includes an input-break detecting unit that detects an input break of the reference signal when an edge of the referred signal is again detected after an edge of the referred signal is detected and before an edge of the reference signal is detected. | 11-05-2009 |
| 20090273372 | HALF BIN LINEAR FREQUENCY DISCRIMINATOR - Frequency discriminator based on a variant of the DFT transform in which the usual twiddle factors are replaced with twiddle factors as for a DFT on a number of points which is the double as the actual number of sample points. The DFT so modified allows half-bin frequency discrimination, with few added computational burden. Two DFT shifted of half bin with respect to the zero frequency provide a linear response of the discrimination and good immunity to noise. The discriminator is particularly useful in FLL for tracking signals in a GPS receiver. | 11-05-2009 |
| 20090273373 | SEMICONDUCTOR DEVICE HAVING RECEIVING CIRCUIT USING INTERNAL REFERENCE VOLTAGE - A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage. | 11-05-2009 |
| 20090273374 | HIGH LINEARITY VOLTAGE TO CURRENT CONVERSION - A system and method for performing voltage to current conversion, the system comprising of a first set of devices that senses the input voltage signal through its input terminal and replicates said input voltage across a second set of devices which then converts said replicated input voltage signal to an output current signal; a third set of devices that transfers the output current signal to output terminals; a differential feedback loop comprising an amplifier positioned between a first one of the first set of devices and a first one of the third set of devices; and a common mode feedback loop that regulates the output average voltage to a reference voltage. | 11-05-2009 |
| 20090273375 | Low-noise LVDS output driver - An LVDS output is described herein that has wideband operation down to 2.5V without degrading spur performance or dramatically increasing die are. A current mirror used in a conventional LVDS output is eliminated in such as way as to reduce noise coupling and produce especially clean output signals. | 11-05-2009 |
| 20090273376 | AC/DC CONVERTERS AND METHODS OF MANUFACTURING SAME - The present invention discloses AC/DC converters and methods of manufacturing the same. The method includes providing a substrate; forming an oxide layer on a top surface of the substrate; applying a photo-resist layer on the oxide layer to define a well region; performing an ion-implantation in the well region using a dopant; and driving in atoms of the dopant to a depth in the well region through a thermal treatment, wherein the driving in process provides a concentration profile of the dopant in the well region such that the semiconductor structure has a high breakdown voltage. | 11-05-2009 |
| 20090273377 | THRESHOLD DITHERING FOR TIME-TO-DIGITAL CONVERTERS - Techniques for dithering quantization thresholds of time-to-digital converters (TDC's) in all-digital phase-locked loops (ADPLL's) are disclosed. In an embodiment, the delay introduced by an individual buffer in a TDC delay line may be dithered. In another embodiment, the delay associated with the TDC delay line may be extended by a fixed amount to accommodate dithering of the zero-delay threshold. | 11-05-2009 |
| 20090273378 | CLOCK CONFIGURATION - A circuit and method for determining the frequency of a first oscillating reference signal generated by a first reference oscillator. The circuit comprises: a second reference oscillator arranged to generate a second oscillating reference signal having a known frequency, a boot memory storing boot code comprising clock configuration code, and a processor coupled to the boot memory and the second reference oscillator. The processor is arranged to execute the boot code from the boot memory upon booting, wherein when executed the clock configuration code operates the processor to determine the frequency of the first reference signal by reference to the second reference signal. | 11-05-2009 |
| 20090273379 | Self-Biased Phase Locked Loop and Phase Locking Method - The present invention discloses a self-bias phase locked loop including a phase frequency detector, a charge pump, a loop filter, a voltage control oscillator, a divider and a bias current converter. A charging or discharging current output from the charge pump equals to a first control current. A resistor of the loop filter is controlled by a first control voltage a second control voltage which is adjusted according to the first control voltage and a second control current. The loop filter boosts or lowers the first control voltage according to the charging or discharging current output from the charge pump. The voltage control oscillator generates a bias current according to the first control voltage and increases or decreases an oscillation frequency according to the boosted or lowered first control voltage, and symmetric loads of the voltage control oscillator are controlled by the first control voltage. The first control current output from the bias current converter equals to the ratio of the bias current to a constant, and the second control current output from the bias current converter equals to the ratio of the bias current to a frequency division factor. The circuit of the self-bias phase locked loop is simple and a low jitter. | 11-05-2009 |
| 20090273380 | DELAY LOCKED LOOP CIRCUIT AND METHOD THEREOF - A delayed locked loop (DLL) circuit for reducing power consumption in updating a delay value of an external clock after locking. The DLL circuit includes a phase comparator for comparing a phase of a feedback clock and a phase of an external clock, and a delay unit for delaying an external clock in response to a comparison signal from the phase comparison. A replica unit receives the delayed external clock and outputs the feedback clock. A toggling controller disables toggling of the delayed external clock that is inputted to the replica unit for a predetermined time at a regular interval after locking. | 11-05-2009 |
| 20090273381 | DELAYED LOCKED LOOP CIRCUIT - A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device. | 11-05-2009 |
| 20090273382 | CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE - A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal. | 11-05-2009 |
| 20090273383 | Logic circuit having gated clock buffer - A logic circuit includes a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state, a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain, and a combinational logic circuit coupled to at least one of the plurality of scan flip-flops. | 11-05-2009 |
| 20090273384 | VERNIER DELAY CIRCUIT - A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted. | 11-05-2009 |
| 20090273385 | OUTPUT CIRCUIT OF SEMICONDUCTOR DEVICE - An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals. | 11-05-2009 |
| 20090273386 | APPARATUS FOR CURRENT-TO-VOLTAGE INTEGRATION FOR CURRENT-TO-DIGITAL CONVERTER - Methods and apparatus for improved current-to-voltage integrators reducing charge injection and kT/C errors from capacitor switching and intrinsic operational amplifier noise (i.e., offset, 1/f noise, thermal noise) during the reset cycle of the integrator, simultaneously reducing demands on the reference voltage source, using correlated double sampling to compensate for DC offset and low frequency op-amp noises, and “fake” integration and a capacitor divider to eliminate or significantly reduce kT/C noise and charge injection. | 11-05-2009 |
| 20090273387 | Bypassing Amplification - An integrated circuit includes a power amplification circuit and a switch circuit wherein the switch circuit is coupled to an output of the power amplification circuit, a bypass input, and a control input, such that the switch selectively couples the power amplification circuit output or the bypass input to an output of the integrated circuit. | 11-05-2009 |
| 20090273388 | MINIATURIZED DEMULTIPLEXER AND ELECTRONIC DEVICE USING SAME - A demultiplexer includes an input terminal for providing an input signal, a plurality of output terminals for outputting the input signal, and a switching circuit coupled among the input terminal and the plurality of output terminals, and outputting the input signal selectively from the plurality of output terminals according to a plurality of control signals provided to a plurality of control terminals. For miniaturizing the demultiplexer, the switching circuit includes one or more switch elements connected between the input terminal and each of the output terminals in series, wherein at least two of the switch elements coupled to different output terminals are simultaneously switched in response to one control signal from the plurality of control terminals. | 11-05-2009 |
| 20090273389 | Integrated Circuit Having Temperature Based Clock Filter - An integrated circuit is provided having a system clock and a clock filter. The clock filter has a temperature sensor for sensing a temperature of the integrated circuit and for causing the clock filter to block output of the system clock if the sensed temperature is below or above a predetermined temperature. | 11-05-2009 |
| 20090273390 | METHOD OF MEDIATING FORWARD VOLTAGE DRIFT IN A SIC DEVICE - A method of reversing Shockley stacking fault expansion includes providing a bipolar or a unipolar SiC device exhibiting forward voltage drift caused by Shockley stacking fault nucleation and expansion. The SiC device is heated to a temperature above 150° C. A current is passed via forward bias operation through the SiC device sufficient to induce at least a partial recovery of the forward bias drift. | 11-05-2009 |
| 20090273391 | FLASH MEMORIES AND REGULATED VOLTAGE GENERATORS THEREOF - A flash memory and a regulated voltage generator thereof. The regulated voltage generator includes a charge pump having an output terminal outputting a first voltage, a control circuit coupled to the output terminal of the charge pump and having first and second output terminals outputting a second voltage and a charge pump control signal, respectively, and a Field Effect Transistor (FET) in diode mode. The FET is coupled between the output terminal of the charge pump and the first output terminal of the control circuit. The charge pump adjusts the first voltage according to the charge pump control signal. | 11-05-2009 |
| 20090273392 | METHODS AND APPARATUS FOR REDUCING NON-IDEAL EFFECTS IN CORRELATED DOUBLE SAMPLING COMPENSATED CIRCUITS - Embodiments of the present invention address kT/C noise, sampled high frequency operational amplifier noise, and charge injection errors sampled on switching capacitors and introduced due to internal switching. Correlated double sampling compensates for DC offset and low frequency operational amplifier noise, and the use of fake integration and a capacitor divider eliminate or significantly reduce kT/C noise, sampled high frequency operational amplifier noise, and charge injection errors. | 11-05-2009 |
| 20090273393 | SUBSTRATE STRESS MEASURING TECHNIQUE - A system, including: a first current mirror having a first current, formed of multiple devices disposed on a substrate, where, when a stress is present, a behavior of a device of the multiple devices forming the first current mirror depends on a direction in which the device of the multiple devices forming the first current mirror is disposed on the substrate; a second current mirror having a second current, formed of multiple devices disposed on the substrate, where, when the stress is present, a behavior of a device of the multiple devices forming the second current mirror depends on a direction in which the device of the multiple devices forming the second current mirror is disposed on the substrate; and a device for measuring a ratio of a difference between the first current and the second current to a sum of the first current and the second current. | 11-05-2009 |
| 20090273394 | ADJUSTABLE CAPACITY DEVICE AND PROCESS THEREOF - The invention specifically concerns a device for varying the apparent level of a capacity, said device being characterized in that it compromises: —a dipole ( | 11-05-2009 |
| 20090273395 | PREAMPLIFIER AND METHOD FOR CALIBRATING OFFSET VOLTAGES THEREIN - A preamplifier includes cascade-connected amplifying circuits, and at least one of the cascade-connected amplifying circuits includes a differential switch pair circuit, a comparator and current sources. The differential switch pair circuit has a pair of differential inputs and a pair of differential outputs. The comparator outputs a comparison signal by comparing the differential outputs. The current sources are respectively and selectively coupled to one of the differential outputs based on the comparison signal to adjust voltages of the differential outputs. A method for calibrating offset voltages in a preamplifier is also disclosed herein. | 11-05-2009 |
| 20090273396 | Pulse Area Modulation and High-Efficiency Linear Power Amplifier System Using the Same - A linear power amplifier system using pulse area modulation includes: an envelop/phase decomposer for decomposing an input signal into an envelop signal and a phase signal; a pulse area modulator for modulating the envelop signal such that an area of the modulated envelop signal is proportional to an amplitude of the envelop signal; a control signal generator for converting the modulated envelop signal into a control signal; an automatic gain adjuster for equalizing pulse height of the modulated envelop signal; a mixer for mixing the phase signal with the output of the automatic gain adjustor to produce a RF pulse train; a power amplifier for amplifying the RF pulse train, to generate an amplified RF pulse train; and a band pass filter for restoring the original input signal from the amplified RF pulse train. The output level of the power amplifier is controlled by the control signal. | 11-05-2009 |
| 20090273397 | Controlling power with an output network - In one embodiment, the present invention includes multiple gain stages and an output network coupled to the gain stages. Each of the gain stages can be independently controlled to amplify a radio frequency (RF) signal to an output power level for transmission from a mobile wireless device. When controlled to be inactive, at least one of the gain stages can be placed into a low impedance state. | 11-05-2009 |
| 20090273398 | DOHERTY POWER AMPLIFIER - The present invention relates to a power amplifier; and, more particularly, to a Doherty power amplifier. The power amplifier includes at least one carrier amplifier; at least one peaking amplifier arranged in parallel with the carrier amplifier in such a manner that the carrier amplifier and the peaking amplifier collectively operate as a Doherty amplifier; a plurality of input matching circuits, at least one of which is respectively connected to an input ends of the carrier amplifier and the peaking amplifier; at least one impedance control circuit, each of which is connected to an output end of each carrier amplifier for controlling a load line impedance of the said each carrier amplifier; at least one output matching circuit directly or indirectly connected to output ends of the impedance control circuit and the peaking amplifier; and at least one first delay circuit for matching delays between the carrier amplifier and the peaking amplifier. The present invention provides an improved Doherty power amplifier capable of achieving a further miniaturization and integration while maintaining an advantage in terms of efficiency and linearity of a Doherty power amplifier by employing an improved output and input matching method, and capable of operating more similar to the ideal operation of a Doherty power amplifier by applying an improved input power division method thereto. | 11-05-2009 |
| 20090273399 | Power amplifier, power amplifier circuit and power amplifying method - The present invention discloses a power amplifier, comprising: a first transistor having a gate receiving an input signal; a second transistor coupled to the first transistor in a cascode configuration, in which a source of the second transistor is coupled to a drain of the first transistor, and a drain of the second transistor outputs an amplified signal; and a dynamic biasing circuit having two input terminals, one of which receiving the input signal, and the other one coupled to the drain of the first transistor, and an output terminal being coupled to a gate of the second transistor, thereby modulating the voltage at the drain of the first transistor. | 11-05-2009 |
| 20090273400 | DEVICE AND METHOD FOR GENERATING AN OUTPUT SIGNAL - An embodiment provides a device for generating an output signal as a function of an input signal, wherein a plurality of circuit sections generate partial signals and the output signal is composed from the partial signals. | 11-05-2009 |
| 20090273401 | Method and System for Multiple Tuner Application Using a Low Noise Broadband Distribution Amplifier - An active splitter circuit arrangement includes a first amplification module having a number of first input ports and first output ports. The first amplification module is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals, each substantially matching the input signal. Also included is a first gain control device having a number of gain input ports respectively coupled to the first output ports and a gain output port coupled to at least one of the first input ports. The first gain control device is configured to control a gain of the first amplification module. Next, a number of second amplification modules corresponding to the number of output signals has a number of second input ports respectively coupled to the first output ports. Each second amplification module is configured to receive a control signal from the second gain control device, provide second stage amplification to a corresponding one of the number of output signals based upon the control signal and produce an amplified output signal. | 11-05-2009 |
| 20090273402 | PHASE-LOCKED LOOP - The present invention concerns a phase-locked loop comprising:
| 11-05-2009 |
