45th week of 2009 patent applcation highlights part 12 |
Patent application number | Title | Published |
20090273006 | Bidirectional silicon-controlled rectifier - The present invention discloses a bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss. | 2009-11-05 |
20090273007 | Method Of Testing An Integrated Circuit Die, And An Integrated Circuit Die - In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing. | 2009-11-05 |
20090273008 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - In a solid state imaging device, and a method of manufacture thereof, the efficiency of the transfer of available photons to the photo-receiving elements is increased beyond that which is currently available. Enhanced anti-reflection layer configurations, and methods of manufacture thereof, are provided that allow for such increased efficiency. They are applicable to contemporary imaging devices, such as charge-coupled devices (CCDs) and CMOS image sensors (CISs). In one embodiment, a photosensitive device is formed in a semiconductor substrate. The photosensitive device includes a photosensitive region. An anti-reflection layer comprising silicon oxynitride is formed on the photosensitive region. The silicon oxynitride layer is heat treated to increase a refractive index of the silicon oxynitride layer, and to thereby decrease reflectivity of incident light at the junction of the photosensitive region. | 2009-11-05 |
20090273009 | Integrated CMOS porous sensor - A single chip wireless sensor ( | 2009-11-05 |
20090273010 | REMOVAL OF IMPURITIES FROM SEMICONDUCTOR DEVICE LAYERS - A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has a low thermal budget determined by temperatures equal to or lower than about 900° C. and time periods equal to or lower than about 5 minutes. In one aspect, the method includes providing a germanium gettering layer with a higher solubility for the impurities than the semiconductor device layer. The germanium gettering layer is provided at least partly in direct or indirect contact with the at least one semiconductor device layer, such that impurities can diffuse from the at least one semiconductor device layer to the germanium gettering layer. | 2009-11-05 |
20090273011 | Metal-Oxide-Semiconductor Device Including an Energy Filter - A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel. | 2009-11-05 |
20090273012 | High Voltage Tolerant Metal-Oxide-Semiconductor Device - A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values. | 2009-11-05 |
20090273013 | METHOD OF FORMING A SPLIT GATE MEMORY DEVICE AND APPARATUS - A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity. | 2009-11-05 |
20090273014 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Each of a memory gate, a control gate, a source diffusion layer, and a drain diffusion layer is connected to a control circuit for controlling potential, and the control circuit operates so as to supply a first potential to the memory gate, a second potential to the control gate, a third potential to the drain diffusion layer, and a fourth potential to the source diffusion layer. Here, after setting the memory gate to be in a floating state by shifting a switch transistor from an ON state to an OFF state, the control circuit operates so as to supply a sixth potential which is higher than the second potential to the control gate to make the memory gate have a fifth potential which is higher than the first potential, thereby boosting the memory gate. | 2009-11-05 |
20090273015 | NON-VOLATILE MEMORY CELL - This document discloses non-volatile memory cells and methods of manufacturing the same. The non-volatile memory cells are self-aligned and have a reduced tunnel window area that is within an active region of a substrate. The tunnel window area can be reduced using mask openings without optical proximity correction that define tunnels having one or more curvatures. | 2009-11-05 |
20090273016 | NANOCRYSTAL FORMATION USING ATOMIC LAYER DEPOSITION AND RESULTING APPARATUS - Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures. | 2009-11-05 |
20090273017 | Method for Forming Trenches on a Surface of a Semiconductor Substrate - A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described. | 2009-11-05 |
20090273018 | NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer. | 2009-11-05 |
20090273019 | MEMORY DEVICE TRANSISTORS - Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors. | 2009-11-05 |
20090273020 | SONOS Flash Memory - A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, comprising: preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first polysilicon layer with the first etch stop layer as a mask, till the silicon oxide-silicon nitride-silicon oxide (ONO) layer is exposed, the etched first polysilicon layer having an inverse trapezia section along a direction of word line; filling a dielectic layer between portions of the first polysilicon layer, the dielectric layer having a trapezia section along the direction of word line. After the above steps, it becomes easy to remove the portion of the first polysilicon layer on a sidewall of the dielectric layer by vertical etching. Thus, no polysilicon residue will be formed on the sidewall of the dielectric layer. Thereby, the short circuit between different memory cells may be avoided. | 2009-11-05 |
20090273021 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a charge storage layer on the tunnel insulating film, a block insulating film on the charge storage layer, and a control gate electrode on the block insulating film, the charge storage layer including a plurality of layers including first and second charge storage layers, the second charge storage layer being provided on a nearest side of the block insulating film, the first charge storage layer being provided between the tunnel insulating film and the second charge storage layer, the second charge storage layer having a higher trap density than the first charge storage layer, the second charge storage layer having a smaller band gap than the first charge storage layer, and the second charge storage layer having a higher permittivity than the first charge storage layer and a silicon nitride film. | 2009-11-05 |
20090273022 | CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH - A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors extending in a first direction, ii) forming first pillars above the first conductors, each first pillar comprising a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, iii) depositing a first dielectric layer above the first pillars, and iv) etching a plurality of substantially parallel first trenches in the first dielectric layer, the first trenches extending in a second direction, wherein, after the etching step, the lowest point in the trenches is above the lowest point of the first conductive layer or layerstack, wherein the first conductive layer or layerstack does not comprise a resistivity-switching metal oxide or nitride. The method also includes monolithically forming a second memory level above the first memory level. Other aspects are also described. | 2009-11-05 |
20090273023 | Segmented pillar layout for a high-voltage vertical transistor - In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. | 2009-11-05 |
20090273024 | METHOD FOR PRODUCING A TRANSISTOR COMPONENT HAVING A FIELD PLATE - A method for producing a transistor component having a field plate. One embodiment includes providing a semiconductor body having a first side, and including a first trench extending into the semiconductor body. A field plate dielectric layer is produced on the first side and at uncovered areas of the first trench such that a residual trench remains. A field plate layer is produced in the residual trench. The first side of the semiconductor body is uncovered using a polishing method. The field plate dielectric layer is partially removed from the at least one first trench proceeding from the first side. | 2009-11-05 |
20090273025 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a semiconductor device and a method for manufacturing the same. The method includes forming a gate structure using a carbon nano tube (CNT). In order to prevent reduction of the gate resistance and the short channel effect, a CNT gate having a grown CNT pattern with a half-cylinder shape is formed over a recess of a semiconductor substrate. The CNT gate has the same effect as a recess gate, and can prevent the short channel effect, improve the speed, and the lower power characteristic of semiconductor devices. | 2009-11-05 |
20090273026 | TRENCH-GATE LDMOS STRUCTURES - MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias. | 2009-11-05 |
20090273027 | Power IC Device and Method for Manufacturing Same - In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel CMOS transistor. Thus, the power IC device and a method for manufacturing the power IC device are provided for reducing manufacturing cost in the case of forming the trench power MOS transistor and the surface layer channel CMOS transistor on the same chip. | 2009-11-05 |
20090273028 | Short Channel Lateral MOSFET and Method - A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes:
| 2009-11-05 |
20090273029 | High Voltage LDMOS Transistor and Method - An LDMOS transistor structure and methods of making the same are provided. The structure includes a gate electrode extended on an upper boundary of an extension dielectric region that separates the gate electrode from the drain region of the LDMOS transistor. Moreover, at an area close to an edge of the extended gate electrode portion, the gate electrode further projects downwards into a convex-shaped recess or groove in the upper boundary of the extension dielectric region, forming a tongue. LDMOS transistors with this structure may provide improved suppression of hot carrier effects. | 2009-11-05 |
20090273030 | Semiconductor Device with a Trench Isolation and Method of Manufacturing Trenches in a Semiconductor Body - A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower. | 2009-11-05 |
20090273031 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a major surface of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the major surface of the first semiconductor layer, the third semiconductor layer forming a structure of periodical arrangement with the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided above the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively provided on a surface of the fourth semiconductor layer; a first main electrode electrically connected to the first semiconductor layer; a second main electrode provided to contact a surface of the fifth semiconductor layer and a surface of the fourth semiconductor layer; and a control electrode provided above the fifth semiconductor layer, the fourth semiconductor layer, and the second semiconductor layer via an insulative film. A portion is provided locally in the third semiconductor layer, the portion depleting at a voltage not more than one third of a voltage at which the second semiconductor layer and the third semiconductor layer completely deplete. | 2009-11-05 |
20090273032 | LDMOS Device and Method for Manufacturing the Same - Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate. | 2009-11-05 |
20090273033 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate. The first regions are disposed in the substrate and surrounded by the annular well region. The at least one transistor is disposed on the substrate between the first regions and including a source, a gate, and a drain. The annular well region and the drain are coupled to a first voltage source. The source and one of the first regions are coupled to a second voltage source, and the other of the first regions is coupled to a substrate triggering circuit. | 2009-11-05 |
20090273034 | Source/Drain Carbon Implant and RTA Anneal, Pre-SiGe Deposition - A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain. | 2009-11-05 |
20090273035 | METHOD FOR SELECTIVELY REMOVING A SPACER IN A DUAL STRESS LINER APPROACH - By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps. | 2009-11-05 |
20090273036 | METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING PROCESSES BY MODIFYING A PARASITIC PN JUNCTION - By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced. | 2009-11-05 |
20090273037 | Semiconductor Integrated Circuit Device and Manufacturing Method Thereof - After silicon oxide film ( | 2009-11-05 |
20090273038 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique is provided which permits formation within a single chip both a field effect transistor of high reliability capable of suppressing the occurrence of a crystal defect and a field effect transistor of a high integration degree. In a mask ROM section having an element isolation region with an isolation width of smaller than 0.3 μm, a planar shape of each active region ACT is made polygonal by cutting off the corners of a quadrangle, thereby suppressing the occurrence of a crystal defect in the active region ACT and diminishing a leakage current flowing between the source and drain of a field effect transistor. In a sense amplifier data latch section which is required to have a layout of a small margin in the alignment between a gate G of a field effect transistor and the active region ACT, the field effect transistor is disposed at a narrow pitch by making the active region ACT quadrangular. | 2009-11-05 |
20090273039 | SEMICONDUCTOR DEVICE - A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the p-type Si substrate so that it surrounds the p-type well region. A plurality of conductive regions which pierce through the n-type well region are formed at regular intervals. By doing so, parasitic resistance from the p-type Si substrate, through the plurality of conductive regions, to the n-type MOS transistors becomes low. Accordingly, when back bias is applied to a contact region, the back bias potential of the n-type MOS transistors can be controlled uniformly. As a result, the influence of noise from the p-type Si substrate or the p-type well region can be reduced. | 2009-11-05 |
20090273040 | HIGH PERFORMANCE SCHOTTKY-BARRIER-SOURCE ASYMMETRIC MOSFETS - The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain dopant region at the second end of the semiconducting body, and a channel positioned between the schottky barrier region and the drain dopant region. The semiconducting device may further include a gate structure overlying the channel of the semiconducting body. Further, a drain contact may be present to the drain dopant region of the semiconducting body, the drain contact being composed of a conductive material and in direct physical contact with a portion of a sidewall of the semiconducting body having a dimension that is less than a thickness of the semiconducting body in which the drain dopant region is positioned. | 2009-11-05 |
20090273041 | TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER - A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor. | 2009-11-05 |
20090273042 | METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor. | 2009-11-05 |
20090273043 | Micro-electro-mechanical system device and method for making same - According to the present invention, a micro-electro-mechanical system (MEMS) device comprises: a thin film structure including at least a metal layer and a protection layer deposited in any order; and a protrusion connected under the thin film structure. A preferred thin film structure includes at least a lower protection layer, a metal layer and an upper protection layer. The MEMS device for example is a capacitive MEMS acoustical sensor. | 2009-11-05 |
20090273044 | Semiconductor Device, Memory Module, and Method of Manufacturing a Semiconductor Device - According to one embodiment of the present invention, a semiconductor device is provided including a semiconductor chip. The semiconductor chip is at least partly surrounded by a surrounding structure. The semiconductor chip further includes a magneto-resistive memory cell. A shielding layer is disposed between the semiconductor chip and the surrounding structure, wherein the shielding layer is configured to shield the magneto-resistive memory cell from external magnetic fields. | 2009-11-05 |
20090273045 | MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively. | 2009-11-05 |
20090273046 | Process for Producing Solid-State Image Sensing Device, Solid-State Image Sensing Device and Camera - In the formation of a multilayer interference filter that is included in a solid-state imaging device, at the outset, a titanium dioxide layer ( | 2009-11-05 |
20090273047 | SOLID STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - To a transparent substrate ( | 2009-11-05 |
20090273048 | IMAGE-SENSING CHIP PACKAGE MODULE ADAPTED TO DUAL-SIDE SOLDERING - An image-sensing chip package module adapted to dual-side soldering includes three substrates, an image-sensing chip and a filter lens. The three substrates are stacked together by pressing (using adhesive as adhesion medium), and the image-sensing chip is electrically connected to the top side of the top substrate and the bottom side of the bottom substrate via conductive bodies that are formed on inner surfaces of through holes passing through the three substrates. Hence, the image-sensing chip package module can use the conductive bodies formed on the bottom side of the bottom substrate (positive face electrical conduction) or the conductive bodies formed on the top side of the top substrate (negative face electrical conduction) to electrically connect with a main PCB. Furthermore, the filter lens is received and hidden in an opening of the top substrate in order to prevent the filter lens from being slid, collided and destroyed. | 2009-11-05 |
20090273049 | WDM Signal Detector - A detector includes a light detecting layer and a grating structure. The light detecting layer, which can be a photodiode, has an optical mode that resonates in the light detecting layer, and the grating structure is positioned to interact with the optical mode. The grating structure further couples incident light having a resonant frequency into the optical mode, and causes destructive interference to prevent light having the resonant frequency from escaping the detecting layer. The light detecting layer can be made transparent to light having other frequencies, so that a stack of such detectors, each having a different resonant frequency, can be integrated into a WDM detector that is compact and efficient. | 2009-11-05 |
20090273050 | Photoelectric Conversion Device and Method of Producing the Same, and Method of Producing Line Image Sensor IC - A plurality of line image sensor ICs | 2009-11-05 |
20090273051 | METHODS OF FORMING ISOLATED ACTIVE AREAS, TRENCHES, AND CONDUCTIVE LINES IN SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES INCLUDING THE SAME - Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed. | 2009-11-05 |
20090273052 | Reducing Device Performance Drift Caused by Large Spacings Between Action Regions - A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting. | 2009-11-05 |
20090273053 | SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUITRY HAVING A PLURALITY OF DEVICES OF REDUCED MISMATCH - In an analog circuit portion, a systematic mismatch between a plurality of circuit elements may be reduced in view of a technology gradient by appropriately positioning the unit devices of the circuit elements so as to obtain a similar response of the circuit elements with respect to the gradient. For example, the spatial relationship of adjacent unit devices belonging to the same circuit element along an arbitrary lateral direction may be the same as the spatial relationship of adjacent unit devices of another circuit element. | 2009-11-05 |
20090273054 | Non-volatile memory device and method of fabricating the same - A non-volatile memory device and methods of fabricating the device according to example embodiments involve a stacked layer structure. The non-volatile memory device may include at least one first horizontal electrode including a first sidewall and a second sidewall; at least one second horizontal electrode including a third sidewall and a fourth sidewall; wherein the third sidewall may be disposed to face the first sidewall; at least one vertical electrode may be interposed between the first sidewall and the third sidewall, in such a way as to cross or intersect each of the at least one first and second horizontal electrodes, and; at least one data storage layer that may be capable of locally storing a change of electrical resistance may be interposed where the at least one first horizontal electrode and the at least one vertical electrode cross or intersect and where the at least one horizontal electrode and the at least one vertical electrodes cross or intersect. | 2009-11-05 |
20090273055 | Fuse Structure - An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer. | 2009-11-05 |
20090273056 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrates. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided at an end and the other end of the first fuse link, and a third current inlet/outlet terminal (second terminal) and a fourth current inlet/outlet terminal (third terminal) provided at an end and the other end of the second fuse link. | 2009-11-05 |
20090273057 | METHOD, APPARATUS, AND SYSTEM FOR LOW TEMPERATURE DEPOSITION AND IRRADIATION ANNEALING OF THIN FILM CAPACITOR - Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed. | 2009-11-05 |
20090273058 | ELECTRICAL COMPONENTS FOR MICROELECTRONIC DEVICES AND METHODS OF FORMING THE SAME - Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process. | 2009-11-05 |
20090273059 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING POLYSILICON MEMBERS - A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members, and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix. | 2009-11-05 |
20090273060 | GROUP III NITRIDE CRYSTAL AND METHOD FOR SURFACE TREATMENT THEREOF, GROUP III NITRIDE STACK AND MANUFACTURING METHOD THEREOF, AND GROUP III NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for surface treatment of a group III nitride crystal includes the steps of lapping a surface of a group III nitride crystal using a hard abrasive grain with a Mohs hardness higher than 7, and abrasive-grain-free polishing the lapped surface of the group III nitride crystal using a polishing solution without containing abrasive grain, and the polishing solution without containing abrasive grain has a pH of not less than 1 and not more than 6, or not less than 8.5 and not more than 14. Accordingly, the method for surface treatment of a group III nitride crystal can be provided according to which hard abrasive grains remaining at the lapped crystal can be removed to reduce impurities at the crystal surface. | 2009-11-05 |
20090273061 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR SUBSTRATE - A double-structure silicon on insulator (SOI) substrate with a silicon layer, an insulation film (silicon oxide film), a silicon layer, and an insulation film in this order from the side of the surface. The upper-layer insulation film is formed so as to have a uniform distribution of depth while the lower-layer insulation film is formed so as to have a non-uniform distribution of depth so that a thick portion may be formed in the silicon layer along a predetermined path. The refractive index of Si is 3.5 and the refractive index of SiO | 2009-11-05 |
20090273062 | SEMICONDUCTOR PACKAGE HEAT SPREADER - A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate. | 2009-11-05 |
20090273063 | SEMICONDUCTOR DEVICE - One embodiment provides a semiconductor device including a carrier, a first chip attached to the carrier, a structured dielectric coupled to the chip and to the carrier, and a conducting element electrically connected with the chip and extending over a portion of the structured dielectric. The conducting element includes a sintered region. | 2009-11-05 |
20090273064 | Semiconductor device and inspection method therefor - A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and electrically connected to a lead frame by a bonding wire, the laterally offset bonding pad thereby functioning as a substitute wire bonding pad for the circuit block. | 2009-11-05 |
20090273065 | INTERCONNECTION OF LEAD FRAME TO DIE UTILIZING FLIP CHIP PROCESS - Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby maintain the vertical profile of the solder. Examples of such a solder-repellent surface include an oxide (such as Brown Oxide) of the lead frame, or a tape (such as Kapton) which is used as a dam bar to control/constrain the solder flow on the leads prior to the encapsulation step. In another embodiment, the solder connection may be formed from at least two components. The first component may reflow at high temperatures to provide the necessary adhesion between solder ball and the die, with the second component reflowing at a lower temperature to provide the necessary adhesion between the solder ball and the leads. An example of such multi-component connections include a first high temperature reflow solder ball paired with a second low temperature reflow solder. Another example includes a solder ball with a hard core (such as Cu, stainless steel, or a plastic material stable at high temperatures) coated with a lower temperature reflow material. | 2009-11-05 |
20090273066 | SEMICONDUCTOR DEVICE AND METHOD - An electronic device and fabrication of an electronic device. One embodiment provides applying a paste including electrically conductive particles to a surface of a semiconductor wafer. The semiconductor wafer is singulated with the electrically conductive particles for obtaining a plurality of semiconductor chips. At least one of the plurality of semiconductor chips is placed over a carrier with the electrically conductive particles facing the carrier. The electrically conductive particles are heated until the at least one semiconductor chip adheres to the carrier. | 2009-11-05 |
20090273067 | MULTI-CHIP DISCRETE DEVICES IN SEMICONDUCTOR PACKAGES - Semiconductor packages that contain multiple dies containing discrete devices and methods for making such devices are described. The semiconductor package contains both a first die containing transistor and second die containing a diode. The interconnect lead of the semiconductor package is connected to the bond pad of the transistor. At the same time, the interconnect lead contains a die attach pad for the diode. The result of this configuration is an integrated functional semiconductor device with a diminished footprint and decreased cost of manufacture. By using more than a single die containing a discrete device in a single semiconductor package, the device can also provide a wider variety of functions. Other embodiments are also described. | 2009-11-05 |
20090273068 | 3-D Integrated Circuit Lateral Heat Dissipation - By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations. | 2009-11-05 |
20090273069 | LOW PROFILE CHIP SCALE STACKING SYSTEM AND METHOD - The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material. | 2009-11-05 |
20090273070 | Liquid Resin Composition for Electronic Components and Electronic Component Device - The invention relates to a liquid resin composition for electronic components which is used in sealing of electronic components, comprising a liquid epoxy resin, a curing agent containing a liquid aromatic amine, and an inorganic filler, and further comprising at least one member selected from a hardening accelerator, silicone polymer particles, and a nonionic surfactant. There is thereby provided a liquid resin composition for electronic components, which is excellent in fluidity in narrow gaps, is free of void generation, is excellent in adhesiveness and low-stress characteristic and is excellent in fillet formation, as well as an electronic component device having high reliability (moisture resistance, thermal shock resistance), which is sealed therewith. | 2009-11-05 |
20090273071 | IC CHIP MOUNTING PACKAGE AND PROCESS FOR MANUFACTURING THE SAME - In one embodiment of the present invention, an IC chip mounting package is arranged such that an IC chip and a film base member are connected via an interposer, and a section in which the IC chip, the film base member, and the interposer are connected is sealed with sealing resin. The sealing resin is provided by potting sealing resin around the interposer via a potting nozzle, or is provided by potting the sealing resin around the IC chip, that is, via a device hole. Moreover, the sealing resin has a coefficient of linear expansion of not more than 80 ppm/° C., a viscosity of not less than 0.05 Pa·s but not more than 0.25 Pa·s, and also includes filler having a particle size of not more than 1 μm. | 2009-11-05 |
20090273072 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a semiconductor device eliminated of the effect of an adhesive used in assembling upon the semiconductor chip. According to the semiconductor device, the semiconductor device includes a board, a semiconductor chip provided on and contacting with the board, and a plurality of wires each having both ends firmly fixed to a point close to a peripheral edge of the semiconductor chip and a point on the board close to a peripheral edge respectively. The semiconductor chip is fixed on the board by means of the wires. | 2009-11-05 |
20090273073 | CONNECTING STRUCTURE FOR FLIP-CHIP SEMICONDUCTOR PACKAGE, BUILD-UP LAYER MATERIAL, SEALING RESIN COMPOSITION, AND CIRCUIT BOARD - The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting structure for a flip-chip semiconductor package, including: a circuit board having a core layer and at least one build-up layer; a semiconductor element connected via metal bumps to the circuit board; and a sealing resin composition with which gaps between the semiconductor element and circuit board are filled, wherein a cured product of the sealing resin composition has a glass transition temperature between 60° C. and 150° C. and a coefficient of linear expansion from room temperature to the glass transition temperature being between 15 ppm/° C. and 35 ppm/° C., a cured product of the build-up layer has a the glass transition temperature of at least 170° C. and a coefficient of linear expansion in the in-plane direction up to the glass transition temperature being not more than 40 ppm/° C., and stacked vias are provided in the build-up layer on at least one side of the core layer. | 2009-11-05 |
20090273074 | Bond wire loop for high speed noise isolation - Semiconductor dies embodying electronic circuits are enclosed and protected within a package. To electrically access the die, the package includes external electrical leads which in turn connect to internal bond wires. The bond wires electrically connect the package to the die. As die density and circuit complexity increase, bond wire are placed in greater proximity. As a result, signal coupling between adjacent bond wires also increases and this coupling reduces circuit performance and input/output rates. A dissipation bond wire is provided adjacent the signal or supply bond wire acting as an aggressor. The dissipation bond wire has a first end connecting to the package and the second end connecting to the die or the package to form a conductive loop which dissipates unwanted coupling from an aggressor bond wire before the coupling couples into victim bond wire. The dissipation bond wire may be grounded. | 2009-11-05 |
20090273075 | SEMICONDUCTOR DEVICE AND MANUFACTURING OF THE SEMICONDUCTOR DEVICE - A semiconductor device. In one embodiment the device includes a carrier. A first material is deposited on the carrier. The first material has an elastic modulus of less than 100 MPa. A semiconductor chip is placed over the first material. A second material is deposited on the semiconductor chip, the second material being electrically insulating. A metal layer is placed over the second material. | 2009-11-05 |
20090273076 | Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and elctronic apparatus including the same - Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component. | 2009-11-05 |
20090273077 | MULTI-LID SEMICONDUCTOR PACKAGE - A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may include one or more discrete surface mount components disposed on the substrate. The multi-lid semiconductor package may include a sealant between the one or more die lids and the one or more substrate lids and the substrate. The one or more die lids and the one or more substrate lids may differ in construction, design, placement, and/or thermal performance. | 2009-11-05 |
20090273078 | Electronic packages - Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics. | 2009-11-05 |
20090273079 | SEMICONDUCTOR PACKAGE HAVING PASSIVE COMPONENT BUMPS - A semiconductor package includes contact bumps configured as passive circuit components. One or more contact bumps of the semiconductor package may be formed or configured as pull-up resistors, pull-down resistors, capacitors or inductors. | 2009-11-05 |
20090273080 | DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME - A display device includes a drive circuit chip, and a substrate on which the drive circuit chip is mounted. The drive circuit chip includes a semiconductor substrate, an insulation layer, a first conductive layer and a second conductive layer formed of metal between the semiconductor substrate and the insulation layer, and a first bump and a second bump formed over the insulation layer. The first bump is superposed with the first conductive layer, and a profile of the first bump in plan view is within a profile of the first conductive layer in plan view. The second bump is superposed with the second conductive layer, and a profile of the second pump in plan view is beyond a profile of the second conductive layer in plan view. | 2009-11-05 |
20090273081 | PAD CUSHION STRUCTURE AND METHOD OF FABRICATION FOR Pb-FREE C4 INTEGRATED CIRCUIT CHIP JOINING - A controlled collapse chip connection (C4) method and integrated circuit structure for lead (Pb)-free solder balls with stress relief to the underlying insulating layers of the integrated circuit chip by deposing soft thick insulating cushions beneath the solder balls and connecting the metallization of the integrated circuit out-of-contact of the cushions but within the pitch of the solder balls. | 2009-11-05 |
20090273082 | METHODS AND DESIGNS FOR LOCALIZED WAFER THINNING - Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described. | 2009-11-05 |
20090273083 | ELECTRICALLY CONDUCTIVE FLUID INTERCONNECTS FOR INTEGRATED CIRCUIT DEVICES - Disclosed are embodiments of an electrically conductive fluid interconnect for coupling an integrated circuit (IC) device to a substrate. The IC device may be coupled to the substrate in a socketless manner or using a socket. The electrically conductive fluid interconnect may include, for example, a metal, an electrically conductive paste, or an electrically conductive polymer material. The fluid may be in a liquid or paste state over at least part of an operating temperature range of the IC device, and in other embodiments the fluid may be in the liquid or paste state at room temperature. Other embodiments are described and claimed. | 2009-11-05 |
20090273084 | OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME - A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy. | 2009-11-05 |
20090273085 | CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES - The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the Copper-containing feature to the dielectric layer, a CuSiN layer and a SiN layer. This layer combination provides an efficient barrier for suppressing Copper diffusion from the feature into the dielectric layer. Furthermore, a CuSiN/SiN layer sequence provides an improved adhesion between the layers of the diffusion-barrier layer stack and the dielectric layer, and thus improves the electromigration performance of the integrated-circuit device during operation. Therefore, the reliability of device operation and the lifetime of the integrate-circuit device are improved in comparison with prior-art devices. The invention further relates to a method for fabricating such an integrated-circuit device. | 2009-11-05 |
20090273086 | METHOD OF REDUCING EROSION OF A METAL CAP LAYER DURING VIA PATTERNING IN SEMICONDUCTOR DEVICES - During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced. | 2009-11-05 |
20090273087 | CLOSED-LOOP SPUTTERING CONTROLLED TO ENHANCE ELECTRICAL CHARACTERISTICS IN DEPOSITED LAYER - This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or “off” current characteristics (I | 2009-11-05 |
20090273088 | Semiconductor Device and Method for Fabricating the Same - A method for fabricating a semiconductor device includes forming a metal word line additionally over a vertical transistor to obtain a multi-layered structure, thereby preventing degradation of the operating speed of the semiconductor device by preventing an increase of resistance of a damascene word line that connects a surrounding gate of a vertical transistor. As a result, the yield and reliability of the semiconductor device can be improved. | 2009-11-05 |
20090273089 | Method for manufacturing semiconductor device and semiconductor device - A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated in it, and a second interlayer film. The second interlayer film includes a trench, and is deposited on the first interlayer film. The semiconductor device also includes a metal conductor filled in and protruding above the trench, and a hard mask film deposited on the metal conductor. The semiconductor device also includes sidewalls formed on lateral surfaces of the hard mask film and the metal conductor for overlying the second interlayer film, and a third interlayer film formed above the second interlayer film inclusive of the hard mask film and the sidewalls. The device also includes a contact hole opened through the third interlayer film and the second interlayer film and in the first interlayer film to expose the first contact metal part between the sidewalls. The device further includes a second contact metal part | 2009-11-05 |
20090273090 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a semiconductor device and a method for manufacturing the same. Embodiments may include forming a lower porous oxide layer on a semiconductor substrate having a conductive layer, forming a pyrolytic polymer layer on the lower porous oxide layer, forming an upper porous oxide layer on the pyrolytic polymer layer, forming a via hole by sequentially etching the upper porous oxide layer, the pyrolytic polymer layer, and the lower porous oxide layer, forming a trench having a width larger than a width of the via hole by sequentially etching the upper porous oxide layer and the pyrolytic polymer layer in such a manner that the trench is connected with the via hole, forming metal interconnections by filling the via hole and the trench with a metal thin film, and forming a vacuum between the upper and lower porous oxide layers by removing the pyrolytic polymer layer. | 2009-11-05 |
20090273091 | SEMICONDUCTOR DEVICE AND METAL LINE FABRICATION METHOD OF THE SAME - Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern. | 2009-11-05 |
20090273092 | SEMICONDUCTOR MODULE HAVING AN INTERCONNECTION STRUCTURE - In a method for manufacturing a semiconductor module, a metal layer is formed on a support substrate. Then, first conductive posts and a first insulating layer are formed on the metal layer. The first insulating layer surrounds the sides of the first conductive posts. Then, second conductive posts are formed above the first conductive posts. The second conductive posts are electrically connected to the first conductive posts. Then, a second insulating layer is formed so as to cover the second conductive posts. The second insulating layer is made of adhesive resin. Finally, a semiconductor device is adhered to the second conductive posts by the second insulating layer while a gap between the first semiconductor device and the first insulating layer is sealed by the second insulating layer. | 2009-11-05 |
20090273093 | PLANAR PACKAGELESS SEMICONDUCTOR STRUCTURE WITH VIA AND COPLANAR CONTACTS - A semiconductor device includes a substrate having a first side and a second side and an epitaxial layer disposed over the second side. The device also includes a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and a bond pad disposed over the epitaxial layer and comprising a conductive material, wherein the semiconductor is not provided in a package. | 2009-11-05 |
20090273094 | INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM - An integrated circuit package on package system including: forming a first substrate assembly; forming a second substrate, having an auxiliary access port, supported by the first substrate assembly; exposing an integrated circuit die through the auxiliary access port; and coupling an external integrated circuit on the second substrate. | 2009-11-05 |
20090273095 | Rectangular-Shaped Controlled Collapse Chip Connection - A rectangular-shaped controlled collapse chip connection (C | 2009-11-05 |
20090273096 | High Density Memory Device Manufacturing Using Isolated Step Pads - An electronic device includes multiple IC dies stacked in an offset stacking arrangement on a substrate. Each IC die includes electrically isolated step pads that facilitates transmitting a dedicated signal between a (beginning) substrate bonding pad and a selected (terminal) contact pad of any die by way of short bonding wires that extend up the stack between the electrically isolated step pads. A memory devices includes stacked memory IC die, wherein “shared” signal transmission paths are formed by associated bonding wires that link corresponding contact pads of each memory die, and dedicated select/control signals are transmitted to each memory die by separate transmission paths formed in part by associated electrically isolated step pads. Substrate space overhung by the stack is used for passive components and IC dies. Memory controller die may be mounted on the stack and connected by dedicated transmission paths utilizing the electrically isolated step pads. | 2009-11-05 |
20090273097 | Semiconductor Component with Contact Pad - A structure and method of forming low cost bond pads is described. In one embodiment, the invention includes depositing an insulating layer over a last metal line of a substrate and forming an opening in the insulating layer. A colloid is printed over the insulating layer and fills the opening in the insulating layer. A conductive via and bond pads are formed by heating the colloid. | 2009-11-05 |
20090273098 | Enhanced Architectural Interconnect Options Enabled With Flipped Die on a Multi-Chip Package - A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the first variant of the chip. The first and second variants of the chip are attached to the carrier such that a vertical surface (side) of the first variant of the chip faces a corresponding vertical surface of the second variant of the chip. A circuit on the first variant of the chip is electrically connected to a corresponding circuit on the second variant of the chip. | 2009-11-05 |
20090273099 | SEMICONDUCTOR INTEGRATED CIRCUIT - On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end portion on the first chip side are arranged having a steplike shift in a direction apart from the first chip side with decreasing distance from the center portion to the end portion on the first chip side. | 2009-11-05 |
20090273100 | INTEGRATED CIRCUIT HAVING INTERLEAVED GRIDDED FEATURES, MASK SET AND METHOD FOR PRINTING | 2009-11-05 |
20090273101 | Apparatus and Method for Preventing Configurable System-on-a-Chip Integrated Circuits from Becoming I/O Limited - An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal determines which module or clock circuit is coupled by the multiplexer. A common buffer may be coupled between the multiplexer and the pad to save substrate space. An analog circuit may be coupled to the pad to provide a signal path minimizing signal distortion. The integrated circuit's clock may be coupled via the multiplexer to an off-substrate circuit. Selective module coupling improves the integrated circuit's testing speed, may salvage an integrated circuit containing a malfunctioning module, and provides for signal loopback during testing. | 2009-11-05 |
20090273102 | Semiconductor Substrate and Method for Manufacturing the Same - A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. | 2009-11-05 |
20090273103 | Nanofluid Production Apparatus and Method - The present invention provides a nanofluid generating apparatus and method of use thereof that is capable of efficiently generating nanofluid by having relatively simple and inexpensive construction, being capable of continuously and stably generating nanofluid, being easy to handle, dramatically reducing manufacturing costs, and being able to generate and select nanofluids according to various usages. An apparatus for generating nanofluid containing nanobubbles, wherein the nanobubbles are gas bubbles with diameter less than 1 μm, comprising: a gas-liquid mixing chamber | 2009-11-05 |
20090273104 | PRODUCING METHOD OF POLYMER FILM - A casting dope ( | 2009-11-05 |
20090273105 | METHOD AND SYSTEM FOR PERFORMING AN INTERFACIAL REACTION IN A MICROFLUIDIC DEVICE - A microfluidic system for performing interfacial reactions can comprise at least one pump in fluid communication with a tube. A first fluid is injected into the tube so that its flow is laminar and continuous. A second fluid is injected in discrete amounts into the tube into the stream or flow of the first fluid. In other embodiments, discrete amounts of the second fluid are introduced into the channel first, then the first fluid is injected so that it creates a region of substantially laminar fluid flow around the discrete amounts of the second fluid. After the two fluids are in contact, a reaction occurs. The system can be configured so that the second fluid solidifies to form a capsule around the first fluid or vice versa. Other interfacial reactions also can be accomplished using the disclosed microfluidic systems and methods. | 2009-11-05 |