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Last week patent highlights (11-05-09):
1. LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME
2. CHIP PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME
3. OPTO-ELECTRONIC PACKAGE STRUCTURE HAVING SILICON-SUBSTRATE AND METHOD OF FORMING THE SAME
4. Bidirectional silicon-controlled rectifier
5. Method Of Testing An Integrated Circuit Die, And An Integrated Circuit Die
6. IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME
7. Integrated CMOS porous sensor - single chip wireless sensor comprises a microcontroller connected by a transmit/receive interface to a wireless antenna
8. REMOVAL OF IMPURITIES FROM SEMICONDUCTOR DEVICE LAYERS
9. Metal-Oxide-Semiconductor Device Including an Energy Filter
10. High Voltage Tolerant Metal-Oxide-Semiconductor Device
11. METHOD OF FORMING A SPLIT GATE MEMORY DEVICE AND APPARATUS
12. NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Each of a memory gate a control gate a source diffusion layer
13. NON-VOLATILE MEMORY CELL - This document discloses non-volatile memory cells and methods of manufacturing the same
14. NANOCRYSTAL FORMATION USING ATOMIC LAYER DEPOSITION AND RESULTING APPARATUS
15. Method for Forming Trenches on a Surface of a Semiconductor Substrate
16. NONVOLATILE MEMORY DEVICE WITH MULTIPLE BLOCKING LAYERS AND METHOD OF FABRICATING THE SAME
17. MEMORY DEVICE TRANSISTORS - Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing
18. SONOS Flash Memory - method for fabricating a silicon-oxide-nitride-oxide-silicon flash memory comprising: preparing a silicon substrate including a
19. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
20. CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH
21. Segmented pillar layout for a high-voltage vertical transistor
22. METHOD FOR PRODUCING A TRANSISTOR COMPONENT HAVING A FIELD PLATE
23. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
24. TRENCH-GATE LDMOS STRUCTURES - MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral
25. Power IC Device and Method for Manufacturing Same
26. Short Channel Lateral MOSFET and Method - are disclosed with interpenetrating drain-body protrusions for reducing channel-on resistance while
27. High Voltage LDMOS Transistor and Method
28. Semiconductor Device with a Trench Isolation and Method of Manufacturing Trenches in a Semiconductor Body
29. SEMICONDUCTOR DEVICE - includes: a first semiconductor layer of a first conductivity type
30. LDMOS Device and Method for Manufacturing the Same
31. ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
32. Source/Drain Carbon Implant and RTA Anneal, Pre-SiGe Deposition
33. METHOD FOR SELECTIVELY REMOVING A SPACER IN A DUAL STRESS LINER APPROACH
34. METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING PROCESSES BY MODIFYING A PARASITIC PN JUNCTION
35. Semiconductor Integrated Circuit Device and Manufacturing Method Thereof
36. SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
37. SEMICONDUCTOR DEVICE - in which potential is uniformly controlled and in which the influence of noise is reduced
38. HIGH PERFORMANCE SCHOTTKY-BARRIER-SOURCE ASYMMETRIC MOSFETS
39. TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER
40. METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE
41. Micro-electro-mechanical system device and method for making same
42. Semiconductor Device, Memory Module, and Method of Manufacturing a Semiconductor Device
43. MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
44. Process for Producing Solid-State Image Sensing Device, Solid-State Image Sensing Device and Camera
45. SOLID STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF
46. IMAGE-SENSING CHIP PACKAGE MODULE ADAPTED TO DUAL-SIDE SOLDERING
47. WDM Signal Detector - detector includes a light detecting layer and a grating structure
48. Photoelectric Conversion Device and Method of Producing the Same, and Method of Producing Line Image Sensor IC
49. METHODS OF FORMING ISOLATED ACTIVE AREAS, TRENCHES, AND CONDUCTIVE LINES IN SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES INCLUDING THE SAME
50. Reducing Device Performance Drift Caused by Large Spacings Between Action Regions
51. SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUITRY HAVING A PLURALITY OF DEVICES OF REDUCED MISMATCH
52. Non-volatile memory device and method of fabricating the same
53. Fuse Structure - electrical fuse and a method of forming the same are presented
54. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
55. METHOD, APPARATUS, AND SYSTEM FOR LOW TEMPERATURE DEPOSITION AND IRRADIATION ANNEALING OF THIN FILM CAPACITOR
56. ELECTRICAL COMPONENTS FOR MICROELECTRONIC DEVICES AND METHODS OF FORMING THE SAME
57. SEMICONDUCTOR INTEGRATED CIRCUIT HAVING POLYSILICON MEMBERS
58. GROUP III NITRIDE CRYSTAL AND METHOD FOR SURFACE TREATMENT THEREOF, GROUP III NITRIDE STACK AND MANUFACTURING METHOD THEREOF, AND GROUP III NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
59. SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR SUBSTRATE
60. SEMICONDUCTOR PACKAGE HEAT SPREADER - semiconductor heat spreader from a unitary metallic plate is provided
61. SEMICONDUCTOR DEVICE - One embodiment provides a semiconductor device including a carrier a first chip attached to the carrier
62. Semiconductor device and inspection method therefor
63. INTERCONNECTION OF LEAD FRAME TO DIE UTILIZING FLIP CHIP PROCESS
64. SEMICONDUCTOR DEVICE AND METHOD - electronic device and fabrication of an electronic device
65. MULTI-CHIP DISCRETE DEVICES IN SEMICONDUCTOR PACKAGES
66. 3-D Integrated Circuit Lateral Heat Dissipation
67. LOW PROFILE CHIP SCALE STACKING SYSTEM AND METHOD
68. Liquid Resin Composition for Electronic Components and Electronic Component Device
69. IC CHIP MOUNTING PACKAGE AND PROCESS FOR MANUFACTURING THE SAME
70. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
71. CONNECTING STRUCTURE FOR FLIP-CHIP SEMICONDUCTOR PACKAGE, BUILD-UP LAYER MATERIAL, SEALING RESIN COMPOSITION, AND CIRCUIT BOARD
72. Bond wire loop for high speed noise isolation
73. SEMICONDUCTOR DEVICE AND MANUFACTURING OF THE SEMICONDUCTOR DEVICE
74. Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and elctronic apparatus including the same
75. MULTI-LID SEMICONDUCTOR PACKAGE - includes one or more die disposed on a substrate an interconnect disposed on the substrate
76. Electronic packages - Assemblies involving integrated circuit dies and packaged dies electrically connected to circuit boards at times mechanically fail
77. SEMICONDUCTOR PACKAGE HAVING PASSIVE COMPONENT BUMPS
78. DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME
79. PAD CUSHION STRUCTURE AND METHOD OF FABRICATION FOR Pb-FREE C4 INTEGRATED CIRCUIT CHIP JOINING
80. METHODS AND DESIGNS FOR LOCALIZED WAFER THINNING
81. ELECTRICALLY CONDUCTIVE FLUID INTERCONNECTS FOR INTEGRATED CIRCUIT DEVICES
82. OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME
83. CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES
84. METHOD OF REDUCING EROSION OF A METAL CAP LAYER DURING VIA PATTERNING IN SEMICONDUCTOR DEVICES
85. CLOSED-LOOP SPUTTERING CONTROLLED TO ENHANCE ELECTRICAL CHARACTERISTICS IN DEPOSITED LAYER
86. Semiconductor Device and Method for Fabricating the Same
87. Method for manufacturing semiconductor device and semiconductor device
88. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
89. SEMICONDUCTOR DEVICE AND METAL LINE FABRICATION METHOD OF THE SAME
90. SEMICONDUCTOR MODULE HAVING AN INTERCONNECTION STRUCTURE
91. PLANAR PACKAGELESS SEMICONDUCTOR STRUCTURE WITH VIA AND COPLANAR CONTACTS
92. INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
93. Rectangular-Shaped Controlled Collapse Chip Connection
94. High Density Memory Device Manufacturing Using Isolated Step Pads
95. Semiconductor Component with Contact Pad
96. Enhanced Architectural Interconnect Options Enabled With Flipped Die on a Multi-Chip Package
97. SEMICONDUCTOR INTEGRATED CIRCUIT - On a semiconductor chip in a semiconductor integrated circuit a plurality of circuit cells each of which has a pad
98. INTEGRATED CIRCUIT HAVING INTERLEAVED GRIDDED FEATURES, MASK SET AND METHOD FOR PRINTING
99. Apparatus and Method for Preventing Configurable System-on-a-Chip Integrated Circuits from Becoming I/O Limited
100. Semiconductor Substrate and Method for Manufacturing the Same
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