44th week of 2010 patent applcation highlights part 27 |
Patent application number | Title | Published |
20100277944 | Interchangeable attachments for accessories - An interchangeable attachment modifies the look and feel of an article, such as a hair accessory (head bands, barrettes), hand bag and clutch, belt, and cap. The article comprises a proximal end, distal end and a central section having at least one connection means appointed to receive the interchangeable attachment. The interchangeable attachment includes a top wall having a show surface and a back wall having a securing member adapted to engage with the connection means of the article for removably attaching the interchangeable attachment to the article. In one embodiment the interchangeable attachment is provided as a plurality of appliqué, swatch or patch attachments. In another embodiment, the interchangeable attachment is provided as an elongated attachment portion appointed to substantially cover the central section of the article. The interchangeable attachments have a plethora of designs and may include LED, fiber optic and/or reflective properties. Advantageously, the interchangeable attachments provide aesthetic appeal and allow the ability to design one's own accessory. They also afford, enhanced visibility, and/or increased safety during dusk or nighttime hours. | 2010-11-04 |
20100277945 | Interchangeable attachments for accessories for pets - An article forming pet gear appointed to be worn by a pet, including pet coats, jackets, shirts or sweaters, has a plurality of interchangeable attachments appointed to modify the article's look, feel and function. The article comprises a proximal end, distal end and a central section having at least one connection means appointed to receive the interchangeable attachment. The interchangeable attachment includes a top wall having a show surface and a back wall having a securing member adapted to engage with the connection means of the article for removably attaching the interchangeable attachment to the article. The interchangeable attachments have a plethora of designs and may include LED, fiber optic and/or reflective properties to provide aesthetic appeal, the ability to design one's own accessory, enhanced visibility, and/or increased safety of the pet during nighttime or dusk hours. They may also be treated with insect repellent, fragrance enhancers, and/or water repellant agents; and layered to provide increased warmth or a cooling effect to accommodate for changes in weather conditions. | 2010-11-04 |
20100277946 | Illuminated Vehicle Trim Panel - A trim panel for a vehicle interior provides a distinctive ambient lighting effect. The trim panel has an opening therein and an illuminated insert panel is mounted on the trim panel within the opening. The insert panel is molded of a clear plastic material and has a front face located in the opening and a painted or other rear reflective surface. The insert panel has a clear plastic edge wall located beyond the opening of the trim panel. A light pipe extends alongside the clear plastic edge wall and directs light into the clear plastic edge wall so that the light reflects within the clear plastic material and onto the rear reflective surface of the insert panel to illuminate the insert panel over its entire surface area facing through the opening of the interior trim panel. | 2010-11-04 |
20100277947 | Light Source Device and Display Device - A light guide body of a light source device includes a first portion where a low intensity distribution area of one light source and another low intensity distribution area of another light source overlap each other, a second portion positioned closer to the one light source than a boundary line connecting boundaries, each of the boundaries being between the first portion and an overlapping portion where a high intensity distribution area of the one light source overlaps with high intensity distribution areas of the light sources, and a third portion other than the second portion. The prism includes a first prism pattern in which a component reflecting the light in the second portion to a side of the first portion is larger than a component reflecting the light in the second portion to a side of the third portion. | 2010-11-04 |
20100277948 | LIGHT EMITTING DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A light emitting device package and a method of manufacturing the light emitting device package are provided. A base is first provided and a hole is formed on the base. After a light emitting portion is formed on the base, a mold die is placed on the light emitting portion and a molding material is injected through the hole. The mold die is removed to complete the package. | 2010-11-04 |
20100277949 | Light guide plate and backlight module - A light guide plate adapted to guide a beam emitted from at least one light emitting device and including a light transmissive substrate and a plurality of optical structures is provided. The light transmissive substrate has a light emitting surface, a bottom surface opposite to the light emitting surface, and a light incident surface connecting the light emitting surface and the bottom surface. The beam from the light emitting device enters the light transmissive substrate through the light incident surface and is emitted out. The optical structures are disposed on the bottom surface and each of the optical structures has a first total internal reflection (TIR) surface and a second TIR surface. A part of the beam from the light incident surface is totally internally reflected by the first TIR surface and the second TIR surface in sequence. A backlight module using the light guide plate is also provided. | 2010-11-04 |
20100277950 | REMOTE WAVELENGTH CONVERTING MATERIAL CONFIGURATION FOR LIGHTING - A device includes a reflector and a wavelength converting material disposed on the reflector. A backlight is disposed between the reflector and a surface to be illuminated, such as a liquid crystal display panel. The backlight includes a light source and a waveguide. The waveguide is configured to direct a majority of light from the light source toward the reflector. At least a portion of the light is converted by the wavelength converted material, reflected by the reflector, and incident on the surface to be illuminated. | 2010-11-04 |
20100277951 | LIGHT GUIDE PLATE, METHOD OF MANUFACTURING THE SAME, AND LIQUID CRYSTAL DISPLAY DEVICE INCLUDING THE SAME - A light guide plate includes a light incident surface to which light is incident as incident light, an opposite surface formed opposite to the light incident surface, a light emitting surface through which the incident light is emitted, a rear surface formed opposite to the light emitting surface and including a prism pattern which reflects the incident light to the light emitting surface, and lateral surfaces, wherein a diffuse reflection pattern is formed on at least any one of the light emitting surface and the lateral surfaces to diffuse-reflect light incident to the lateral surfaces, thus rendering a brightness at both the opposite surface and the light incident surface substantially uniform. | 2010-11-04 |
20100277952 | LED NIGHT LIGHT HAS PROJECTION OR IMAGE FEATURE - An LED night light for night time or dark area use, such as a plug-in wall outlet night light or direct current (DC) operated night light, includes projection or image features to project or present an image, message, data, logo, or time on a ceiling, walls, floor, or other desired surface, or an optics element surface. The optics means may include an optics-lens, slide, convex lens, concave lens, openings, cut-outs, film, grating, or holographic element to create an image at a desired location. The night light may have an adjustable angle or distance between light source and optics-means, as well as other adjustable position, location, or orientation features. | 2010-11-04 |
20100277953 | SWITCHING POWER SUPPLY - A switching power supply includes a switching unit, a driving signal generator, and a control circuit. The driving signal generator is configured for providing a driving signal including a plurality of acting voltage parts. The plurality of acting voltage parts is used to turn on the switching unit. Each of the acting voltage parts may be one of a high level voltage and a low level voltage. The control circuit is connected between the driving signal generator and the switching unit. The control circuit turns off the switching unit when a duration of one of the plurality of acting voltage parts is longer than a preset time period. | 2010-11-04 |
20100277954 | ACTIVE CENTERPOINT POWER BUS BALANCING SYSTEM - An active centerpoint bus balancing system which actively maintains centerpoint voltage balance of the output capacitors in a power supply having a multi-level voltage output. The centerpoint voltage balance is maintained by a novel control circuit which efficiently transfers charge from one capacitor to the other capacitor so as to maintain the same voltage on each output capacitor. The centerpoint voltage balance minimizes the effect of loading conditions. It operates even with no load, and allows severe load unbalance on the two output capacitors without creating voltage unbalance. | 2010-11-04 |
20100277955 | Boost Device For Voltage Boosting - A boost device boosts an input voltage to an output voltage across an output capacitor, and includes an output diode coupled to the output capacitor, and a transformer coupled to a first switch, a clamp circuit and a boost circuit. The clamp circuit is coupled across a first winding of the transformer, and includes a clamp capacitor coupled in series to a second switch. The output capacitor is capable of being charged through the output diode with an induced voltage across a second winding of the transformer. The boost circuit is capable of being charged with the induced voltage across the second winding, and of charging the output capacitor so as to boost the output voltage across the output capacitor. | 2010-11-04 |
20100277956 | CONTROL APPARATUS OF POWER CONVERTER CIRCUIT - To detect a peak time of an exciting current of a transformer, a primary current corresponding to the peak time, or a variation time of the primary voltage, and to switch a switch after expiration of a predetermined period from the peak time, after the peak time occurs. A control apparatus | 2010-11-04 |
20100277957 | POWER SYSTEM HAVING A POWER SAVING MECHANISM - A power system having a power saving mechanism includes a voltage regulator, a power input module, and a switching signal generation unit. The voltage regulator performs a regulation operation on a first voltage for generating a second voltage. The power input module includes a transformer, a rectifying unit, a switch, and a switch control unit. The rectifying unit together with the transformer is put in use for converting an input voltage into the first voltage. The switch is employed to control a current flowing through the primary winding of the transformer. The switch control unit generates a control signal for controlling the switch according to a switching signal. The switching signal generation unit is utilized for generating the switching signal to disable the switch control unit during an energy transfer disable interval so as to decrease the first voltage from a first predetermined voltage to a second predetermined voltage. | 2010-11-04 |
20100277958 | POWER MODULE ASSEMBLY - A power module assembly of the type suitable for deployment in a vehicular power inverter, wherein the power inverter has a grounded chassis, is provided. The power module assembly comprises a conductive base layer electrically coupled to the chassis, an insulating layer disposed on the conductive base layer, a first conductive node disposed on the insulating layer, a second conductive node disposed on the insulating layer, wherein the first and second conductive nodes are electrically isolated from each other. The power module assembly also comprises a first capacitor having a first electrode electrically connected to the conductive base layer, and a second electrode electrically connected to the first conductive node, and further comprises a second capacitor having a first electrode electrically connected to the conductive base layer, and a second electrode electrically connected to the second conductive node. | 2010-11-04 |
20100277959 | POWER SUPPLY MODULE - A power supply module includes a rectifying and filtering unit, a pulse width modulation (PWM) unit, a voltage transforming unit, a sampling and comparing unit, and an overvoltage protection unit. The rectifying and filtering unit receives an alternating current (AC) voltage, and generates a filtered primary DC voltage. The PWM unit is configured for generating pulses. The voltage transforming unit transforms the filtered primary DC voltage into the DC voltage according to the pulses. The sampling and comparing unit samples the DC voltage, and generates an overvoltage signal when the sampled DC voltage exceeds a predetermined DC voltage. The overvoltage protection unit is coupled between the sampling and comparing unit and the PWM unit. According to the overvoltage signal, the overvoltage protection unit generates a first control signal to disable the PWM unit, and the overvoltage protection unit is self-locked. | 2010-11-04 |
20100277960 | AIRCRAFT POWER SUPPLY AND METHOD OF OPERATING THE SAME - An aircraft power supply for providing DC power with improved power quality characteristics. The aircraft power supply includes a transformer control system that can use closed-loop feedback from a DC power output to control switches that can short primary windings turns of a step-down transformer. By shorting turns in the primary, the transformer control system can control or manipulate the turns ratio in the transformer and compensate for decreases in the DC power output. | 2010-11-04 |
20100277961 | METHOD FOR INHIBITING THERMAL RUN-AWAY - A method for mitigating aliasing effects in a single phase power converter and mitigating aliasing effects and inhibiting thermal run-away in a multi-phase power converter at varying load transition rates. A single phase or multi-phase power converter having an on-time is provided and the frequency of the power converter is adjusted so that a load step period and the on time of the single phase power converter are in a temporal relationship. Alternatively, a load step rate is inhibited from locking onto a phase current of the single phase power converter by suspending an oscillator signal. In accordance with another alternative, a load step rate is inhibited from locking onto a phase current of the single phase power converter by suspending an oscillator signal and dithering an input signal to the oscillator. | 2010-11-04 |
20100277962 | Media player with non-volatile memory - A media player is provided that includes a processor configured to execute a media player program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device, and an analog/digital module electrically coupled with the processor and the non-volatile memory, the analog/digital module configured to output a media signal. The input/output module may be in electrical communication with the input/output device (e.g., electrically coupled) and/or signal communication with the input/output device (e.g., wireless and/or optical communication). | 2010-11-04 |
20100277963 | IC CARD - An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip ( | 2010-11-04 |
20100277964 | MULTI-BANK MEMORY - A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed. | 2010-11-04 |
20100277965 | Memory System Having Multiple Vias at Junctions Between Traces - An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces connected by the vias includes a widened portion that provides sufficient overlap with the other trace to allow the two or more vias to be formed between the traces at the overlap. Parallel traces for global write lines that carry a write signal and its inverse may be positioned more than one maximum-density grid space apart to allow the widened portions to be formed between the traces. A global read line that is formed in a different metal layer from the global write line traces may be positioned in a grid space between the global write line traces to reduce the capacitance of this line. | 2010-11-04 |
20100277966 | Memory Array and Storage Method - A memory arrangement comprises a first memory transistor ( | 2010-11-04 |
20100277967 | GRADED METAL OXIDE RESISTANCE BASED SEMICONDUCTOR MEMORY DEVICE - Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells. | 2010-11-04 |
20100277968 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array configured of at least a first portion and a second portion each including a plurality of memory cells each with a variable resistor which stores an electrically rewritable resistance value as a data, and a control circuit which controls a first operation including selected one of operations to erase, write and read the data in the first portion and a second operation including selected one of operations to erase, write and read the data in the second portion, the first operation and the second operation being performed in temporally overlapped relation with each other. | 2010-11-04 |
20100277969 | STRUCTURES FOR RESISTIVE RANDOM ACCESS MEMORY CELLS - A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; a resistive layer having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; and a second electrode having a lower portion, an upper portion and an outer surface; wherein the outer surface of the resistive layer directly contacts the inner surface of the first electrode. | 2010-11-04 |
20100277970 | Static random accee memory device - Additional transistors P | 2010-11-04 |
20100277971 | METHOD FOR REDUCING CURRENT DENSITY IN A MAGNETOELECTRONIC DEVICE - A method for reducing spin-torque current density needed to switch a magnetoelectronic device ( | 2010-11-04 |
20100277972 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELL ARRAYS - First and second memory cell arrays are adjacent in a first direction. First and second areas are positioned adjacent to one and the other side of the first memory array in a second direction. Third and fourth areas are positioned adjacent to one and the other side of the second memory array in a second direction. A sense amplifier is arranged in the first area and a current sink is arranged in the fourth area. The sense amplifier compares a read current which flows into the current sink via a memory cell in the first memory cell array and the second area from the sense amplifier with a reference current which flows into the current sink via the third area and a reference memory cell in the second memory cell array from the sense amplifier. | 2010-11-04 |
20100277973 | Metallic-Glass-Based Phase-Change Memory - A phase-change material for use in a phase-change memory device is provided. The phase-change material includes at least one metal and is reversibly phase-changeable, switchable, to a detectable metallic glass state or to a detectable crystalline state thereof. There is also provided a phase-change memory, that includes at least one phase change memory cell comprising the phase change material whereby the phase-change material and thereby the phase-change memory cell is reversibly programmable to one of these states. A method of fabricating the phase-change memory is also provided. | 2010-11-04 |
20100277974 | Single bit line SMT MRAM array architecture and the programming method - An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal. Out-of-phase switching devices are connected to the source lines for selectively transferring the out-of-phase signal to the at least one source lines. Column select transistors are connected to the single bit lines for transferring an in-phase data signal to a selected column of the SMT MRAM cells. A precharge circuit selectively charges or discharges the single bit lines. Ground switching devices selectively connect to the source lines to a ground reference voltage source. A method for programming a selected SMT MRAM cell within a provided SMT MRAM device is described. | 2010-11-04 |
20100277975 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate a reference current corresponding to each of the memory cells; and a sense amplification unit configured to sense and amplify the reference current and a data current corresponding to a memory cell connected to an activated word line among the word lines. | 2010-11-04 |
20100277976 | MAGNETIC MEMORY DEVICES INCLUDING MAGNETIC LAYERS HAVING DIFFERENT PRODUCTS OF SATURATED MAGNETIZATION AND THICKNESS AND RELATED METHODS - A magnetic memory device may include a tunnel barrier, a reference layer on a first side of the tunnel barrier, and a free layer on a second side of the tunnel barrier so that the tunnel barrier is between the reference and free layers. The free layer may include a first magnetic layer adjacent the tunnel barrier, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer. More particularly, the nonmagnetic layer may be between the first and second magnetic layers, and the first magnetic layer may be between the tunnel barrier and the second magnetic layer. A product of a saturated magnetization of the first magnetic layer and a thickness of the first magnetic layer may be less than a product of a saturated magnetization of the second magnetic layer and a thickness of the second magnetic layer. Related methods are also discussed. | 2010-11-04 |
20100277977 | NAND FLASH MEMORY - A NAND flash memory includes a semiconductor substrate, a well region in the semiconductor substrate, memory cells connected in series in the well region, a discharge circuit connected to the well region, a word line connected to the memory cells, and a control circuit which controls potentials of the well region and the word line. The control circuit set the well region to a first potential, and set the word line to a second potential lower than the first potential, in an erase operation. The discharge circuit comprises a constant current source with a constant discharge speed independent on a temperature, and discharges the well region after the erase operation. | 2010-11-04 |
20100277978 | FLASH MEMORY DEVICE HAVING IMPROVED READ OPERATION SPEED - Provided is a flash memory device. The flash memory device includes: a memory cell storing multi-bit data; a reference bias voltage supply circuit generating a reference bias voltage; an sense amplifier sensing the multi-bit data stored in the memory cell using the reference bias voltage; and a control circuit controlling the reference bias voltage supply circuit. The control circuit controls the reference bias voltage supply circuit to allow the reference bias voltage to be developed according to a change of a main word line voltage applied to the memory cell during a read operation. | 2010-11-04 |
20100277979 | MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM - A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result. | 2010-11-04 |
20100277980 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 2010-11-04 |
20100277981 | NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells. | 2010-11-04 |
20100277982 | SEMICONDUCTOR DEVICE WITH FLOATING GATE AND ELECTRICALLY FLOATING BODY - Techniques for providing floating body memory devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor device comprising a floating gate, a control gate disposed over the floating gate, a body region that is electrically floating, wherein the body region is configured so that material forming the body region is contained under at least one lateral boundary of the floating gate, and a source region and a drain region adjacent the body region. | 2010-11-04 |
20100277983 | Two Pass Erase For Non-Volatile Storage - Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing. | 2010-11-04 |
20100277984 | NONVOLATILE SEMICONDUCTOR MEMORY - In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage V | 2010-11-04 |
20100277985 | Verification Method for Nonvolatile Semiconductor Memory Device - The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used. | 2010-11-04 |
20100277986 | NON-VOLATILE FIELD PROGRAMMABLE GATE ARRAY - A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful. | 2010-11-04 |
20100277987 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - Systems and methods for programming data to a memory device (MD). The methods involve receiving the data at MD ( | 2010-11-04 |
20100277988 | INTERNAL SOURCE VOLTAGE GENERATION CIRCUIT AND GENERATION METHOD THEREOF - An internal source voltage generation circuit includes main source voltage driving means configured to drive an internal source voltage terminal to a predetermined voltage level; and additional source voltage driving means configured to additionally drive the internal source voltage terminal in response to a data strobe signal. | 2010-11-04 |
20100277989 | INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data. | 2010-11-04 |
20100277990 | INTEGRATED CIRCUIT HAVING MEMORY REPAIR INFORMATION STORAGE AND METHOD THEREFOR - A storage unit on an integrated circuit stores information that identifies a circuit on the integrated circuit, a selected operating condition, and a required operating configuration for the circuit for the selected operating condition. The manner of operating the circuit is changed to the required operating configuration in response to an operating condition of the circuit changing to the selected operating condition. This allows for efficiently identifying the few circuits that do not meet specified requirements based on a reduction in, for example, operating voltage, and altering their operation in order to meet the specified requirements relative to the reduced operating voltage without having to do so for the vast majority of the circuits that are able to meet the requirements at the lowered operating voltage. | 2010-11-04 |
20100277991 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors | 2010-11-04 |
20100277992 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes output enable signal generation means configured to be reset in response to an output enable reset signal, count a DLL clock signal and an external clock signal, and generate an output enable signal in correspondence to a read command and an operating frequency; and activation signal generation means configured to generate an activation signal for inactivating the output enable signal generation means during a write operation interval. | 2010-11-04 |
20100277993 | Method for Tuning Control Signal Associated with at Least One Memory Device - Disclosed is a method for tuning control signals associated with one or more memory devices. The method includes performing a number of memory access operations on at least one memory device and recording results of the memory access operations. Specifically, the memory access operations are performed with different time delays for a first edge of a control signal. The control signal used for capturing data is provided by the at least one memory device. The method further includes selecting a time delay from the time delays used in the memory access operations. Moreover, the method includes utilizing the selected time delay in performing subsequent memory access operations on the at least one memory device. Also disclosed is a system including at least one memory device and an integrated circuit operatively coupled to the at least one memory device. The system incorporates the method for tuning control signals. | 2010-11-04 |
20100277994 | Semiconductor Memory Device and Operating Method Thereof - A semiconductor memory device and an operating method thereof prevent the mal-operation of the semiconductor memory device induced by misrecognizing addresses or data as commands. The semiconductor memory device includes a plurality of input pads, a data information path, a command path, a transfer block configured to transmit signals coupled through the input pads to the data information path and the command path, a command decoding block configured to decode signals transmitted through the command path to verify an inputting of a command, and a transmission control block configured to generate a control signal for controlling the signal transmission from the transfer block to the command path according to the verified result of the command decoding block. | 2010-11-04 |
20100277995 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF OPTIMIZING SIGNAL TRANSMISSION POWER AND POWER INITIALIZING METHOD THEREOF - A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first chip, checking whether the test signal provided to the first chip has an error, providing the checking result to the signal-providing chip, setting the power of a first signal provided to the first chip according to the checking result, and setting the power of a signal provided to a second chip adjacent to the first chip and close to the signal-providing chip using the power of the first signal. | 2010-11-04 |
20100277996 | SEMICONDUCTOR DEVICE - A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers. | 2010-11-04 |
20100277997 | Semiconductor memory device - The semiconductor memory device includes a first memory cell connected between a first word line and a bit line. The semiconductor memory device may also include a second memory cell connected between a second word line and an inverted bit line. Additionally, the memory device may include a precharger configured to charge the bit line and the inverted bit line to a first voltage before a read operation, a first sense amplifier having a first transistor connected between to the bit line and a first node, the first transistor including a gate to which a signal of the inverted bit line is applied. The semiconductor memory device may have a second transistor connected between the inverted bit line and a second node, the second transistor including a gate to which a signal of the bit line is applied, and the first sense amplifier configured to amplify a voltage of the bit line or the inverted bit line to a second voltage based on to the second voltage applied to one of the first node and the second nodes during the read operation. The semiconductor memory device may also have a bias unit configured to generate a voltage difference between the first node and the second node, and a sense amplifier driver configured to apply the second voltage to one of the first and second nodes based on one of the first and second selected word lines during the read operation. | 2010-11-04 |
20100277998 | MAINTENANCE OF AMPLIFIED SIGNALS USING HIGH-VOLATAGE-THRESHOLD TRANSISTORS - Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated. | 2010-11-04 |
20100277999 | FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A fuse circuit includes a fuse unit configured to drive an output terminal via a current path including a fuse in response to a fuse enable signal; and a comparison unit configured to be activated in response to an activation signal for comparing a reference voltage having a predetermined level with a voltage level of the output terminal to generate a fuse state signal. | 2010-11-04 |
20100278000 | MEMORY DEVICE CONTROL FOR SELF-REFRESH MODE - In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off. | 2010-11-04 |
20100278001 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory core; a charge pump circuit providing a high voltage to the memory core; and a charge pump control circuit operating the charge pump circuit by a standby mode and measuring an operation time value of the standby mode. The charge pump control circuit controls the standby mode of the charge pump circuit using the time value. | 2010-11-04 |
20100278002 | CIRCUIT AND METHOD OF PROVIDING CURRENT COMPENSATION - Some embodiments regard a method comprising: during a leakage sampling phase, recognizing a voltage level dropped due to a leakage current associated with a signal linestoring the voltage level; and during a reading phase, using the voltage level to provide an amount of compensation current to the signal line. | 2010-11-04 |
20100278003 | ADDRESS DECODER AND/OR ACCESS LINE DRIVER AND METHOD FOR MEMORY DEVICES - Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in the decoder and driver. The row decoder and a latch in the driver are powered by a first supply voltage, and an output stage in the access line driver is powered by a second supply voltage. The first and second supply voltages are maintained at a relatively low level during standby before an address is decoded. Only after an address is decoded to set the latch are the supply voltages increased to levels needed to drive the access line. Further, before resetting the latch, the first and power supply voltages are decreased to their standby levels. By maintaining the first and second voltages relatively low until after the latch is set and reset, GIDL currents may be avoided and CHC damage may be prevented. | 2010-11-04 |
20100278004 | ADDRESS RECEIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS - An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal. | 2010-11-04 |
20100278005 | Magnetic bubble mixer forming plate assembly - An improved bubble forming plate for a mixer employing large bubbles to mix liquids in a tank, comprising a gas injector, a bubble-forming undersurface and at least one permanent magnet affixed to the plate, the magnet providing sufficient magnetic force to retain the plate against the inner surface of the tank. | 2010-11-04 |
20100278006 | DEVICE FOR MIXING POWDER WITH A LIQUID, THE DEVICE INCLUDING A DISPERSION TUBE - A device for mixing powder or the like with a liquid, the device comprising both a dispersion tube having its bottom portion open and designed to be in the liquid and having a delivery orifice for powder or the like in its top portion, and mixer means located in the dispersion tube and comprising a first rotary stirrer disposed in the vicinity of the bottom end of the dispersion tube and suitable for creating a first downward stream in said dispersion tube. The mixer means further comprise a second rotary stirrer disposed between the delivery orifice for powder or the like and the first rotary stirrer, and suitable for creating a second downward stream in said dispersion tube. | 2010-11-04 |
20100278007 | Stirring Apparatus - It is an object of the present invention to provide a stirring apparatus which can exhibit excellent stirring characteristics in a wide range of viscous regions and which can reduce the mixing time. A stirring apparatus includes a stirred tank having a bottomed cylinder shape, a rotation shaft concentrically or substantially concentrically disposed inside the stirred tank, and a bottom blade that extends from the rotation shaft so as to extend in a radial direction and a vertical direction, of the stirred tank, and a lower edge of the bottom blade has a shape conforming to a bottom wall surface of the stirred tank. Here, a clearance is formed between the lower edge of the bottom blade and the lower wall surface and the clearance satisfies the following condition: 1% of the inner diameter of the stirred tank2010-11-04 | |
20100278008 | ACOUSTIC AND ULTRASONIC CONCEALED OBJECT DETECTION - An acoustic/ultrasonic detection system can detect, for example, an object concealed under the clothing of a subject. The system includes a signal generator configured to output an electrical signal. An acoustic/ultrasonic transducer can be configured to convert the electrical signal into an acoustic/ultrasonic signal, transmit the acoustic/ultrasonic signal, receive a reflected acoustic/ultrasonic signal from an object in the target area and convert the reflected acoustic/ultrasonic signal into a received electrical signal. The transducer is at least one of an air-coupled transducer and an electro-magnetic acoustic transducer. The system can also include an acoustic/ultrasonic antenna aperture operatively connected to the transducer and configured to focus the transmitted acoustic/ultrasonic signal to create a narrow beam in the target area, a processor configured to extract object information from the received electrical signal and an object indication device to provide an indication of a detected object based on the extracted object information. | 2010-11-04 |
20100278009 | Storage and Management System for Seismic Data Acquisition Units - A configuration for the deck of a marine vessel, wherein parallel and perpendicular travel paths, for movement of individual OBS unit storage baskets, are formed along a deck utilizing, in part, the storage baskets themselves. A portion of the deck is divided into a grid defined by a series of low-to-the-deck perpendicular and parallel rails and each square in the grid is configured to hold an OBS unit storage basket. Around the perimeter of the grid is an external containment wall which has a greater height than the rails. Storage baskets seated within the grid are configured to selectively form internal containment walls. Opposing internal and external containment walls define travel paths along which a storage basket can be moved utilizing a low, overhead gantry. A basket need only be lifted a minimal height above the deck in order to be moved along a path. The containment walls and the deck itself constraining uncontrolled swinging of baskets, even in onerous weather or sea conditions. The system is flexible to meet the needs of a desired operation since the internal walls of the grid can be reconfigured as desired in order to free up a particular storage basket or define a particular travel path. | 2010-11-04 |
20100278010 | Method and system for passive acoustic monitoring in seismic survey operations - A system for passive acoustic monitoring in connection with seismic surveying includes a survey vessel having a recording system thereon. At least one seismic energy source is coupled to the vessel by a first towing cable. The towing cable includes at least one conductor therein. At least one seismic sensor streamer is coupled to the vessel by a lead in cable. At least one acoustic sensor is coupled to the at least one source by a second towing cable. The second towing cable includes at least one signal conductor configured to transmit signals from the acoustic sensor to the at least one conductor in the first towing cable. The at least one acoustic sensor is configured to detect marine mammal vocalization. | 2010-11-04 |
20100278011 | System and method for towed marine geophysical equipment - A system comprises towed marine geophysical equipment, adapted for towing through a body of water; and a surface covering, comprising a textural attribute of shark skin, attached to the marine geophysical equipment. A method comprises towing marine geophysical equipment having a surface covering, comprising a textural attribute of shark skin, attached thereto. | 2010-11-04 |
20100278012 | Human echolocation system - A human echolocation system emits toward a target a series of sound pulses beginning at a low frequency and progressing stepwise to a high frequency. Echoes of the pulses enable the user to estimate location, distance and dimensions of the target. Target location and distance are estimated based on a stretched echo delay, while target dimensions are estimated based on a musical pitch corresponding to the echo frequency. | 2010-11-04 |
20100278013 | System and method for precision acoustic event detection - Systems and methods of providing precision locations for sensors which make up an array of sensors in a gunshot detection system. Consistent with some exemplary implementations, sensors may employ a commercial GPS which reports a sensor position or a group of pseudoranges to GPS satellites. A server may collect differential information from a differential node and, in one exemplary implementation, may calculate a precision position for each sensor by adjusting the reported position or pseudoranges with the differential information. In other exemplary implementations, differential information may be sent from the host to individual sensors which calculate their own precision positions. Exemplary differential information may include latitude and longitude corrections, pseudorange corrections, ionospheric delay, GPS satellite clock drift, or other corrective term which will improve the accuracy of a sensor position. | 2010-11-04 |
20100278014 | Underwater synchronisation system - An underwater system ( | 2010-11-04 |
20100278015 | Variable Operating Voltage in Micromachined Ultrasonic Transducer - A cMUT and a cMUT operation method use an input signal that has two components with different frequency characteristics. The first component has primarily acoustic frequencies within a frequency response band of the cMUT, while the second component has primarily frequencies out of the frequency response band. The bias signal and the second component of the input signal together apply an operation voltage on the cMUT. The operation voltage is variable between operation modes, such as transmission and reception modes. The cMUT allows variable operation voltage by requiring only one AC component. This allows the bias signal to be commonly shared by multiple cMUT elements, and simplifies fabrication. The implementations of the cMUT and the operation method are particularly suitable for ultrasonic harmonic imaging in which the reception mode receives higher harmonic frequencies. | 2010-11-04 |
20100278016 | WAKE UP STIMULUS CONTROL SYSTEM - The invention relates to a wake up stimulus control system, comprising a control unit ( | 2010-11-04 |
20100278017 | TOURBILLON WITHOUT THE WEIGHT OF THE BALANCE - Tourbillon mechanism for a watch having a turning cage mounted in pivoting manner in a first and second cage bearing lodged in fixed elements of the watch; an escapement mobile integral with the cage; and a regulating element in the form of a spiral balance capable of oscillating around a balance staff according to pulses received from the escapement mobile. The balance staff is mounted in pivoting manner in the balance bearings lodged outside the cage. The outer extremity of the spiral hairspring is fastened to the cage through a hairspring stud. | 2010-11-04 |
20100278018 | TIMEPIECE HAVING AN AUTOMATIC WINDING MECHANISM - A timepiece has a basic movement including at least one barrel ( | 2010-11-04 |
20100278019 | RECORDING APPARATUS - A recording apparatus having a reproduction means to play digital data from a recording medium recorded with that digital data and retrieval information, a recording means to write the digital data reproduced by the reproduction means and record the retrieval information on a control table, and a control circuit to search the control table by using the retrieval information when the digital data from the reproduction means is written by the recording means, to permit the writing of digital data recorded on the medium with the recording means when the retrieval information is not recorded on the control table, and to prohibit the writing of digital data recorded on the medium with the recording means when the retrieval information is already recorded on the control table, and also prevent the mistaken duplicate copying of the digital data with the recording means. | 2010-11-04 |
20100278020 | Recording Method and Apparatus for Optical Disk Drive - A recording apparatus for an optical disk drive is provided. The recording apparatus includes a driver, a servo signal generator, a filter, and a counter. The driver controls a recording speed of the optical disk drive. The servo signal generator generates at least a servo signal. The filter with a specific bandwidth filters the servo signal to generate a filtered servo signal. The counter generate a count value according to the filtered servo signal and instructs the driver to decrease the recording speed of the optical disk drive when the count value exceeds a trigger value, so as to record with the decreased recording speed. | 2010-11-04 |
20100278021 | CONTROLLING AN OPTICAL-DISC READER USING SURFACE MARKS - An optical-disc player having a reader and a controller. The reader derives out-of-band information from surface marks of an optical disc, where the controller controls operations of the reader based on the derived information. The controlled operations may involve the reading and rendering of embedded data of the optical disc. For example, a person writes the words “Spanish” and “widescreen” on the surface of a DVD with a marker and inserts the DVD in a DVD player. The DVD player scans the surface of the DVD and sends the resulting image data to an optical character recognition (OCR) module. The OCR module outputs a text file containing the words “Spanish” and “widescreen” to a controller (e.g., Microsoft HDi runtime). In response, the controller sets the playback language to Spanish and the screen format to widescreen. | 2010-11-04 |
20100278022 | METHOD AND APPARATUS FOR ACQUIRING AND DISPLAYING IMAGE DATA CORRESPONDING TO CONTENT DATA - An information reproducing apparatus and method thereof. The information reproducing apparatus includes a storage unit, communication unit, controller, and display unit. The storage unit stores music data and at least one first string of characters corresponding to the music data. The reproducing unit reproduces the music data from the storage unit. The communication unit communicates with an image data storage unit, which stores a plurality of image data each corresponding to at least one second string of characters. The controller controls acquisition of one image data from the image data storage unit via the communication unit. The one image data is acquired based on a comparison between the at least one first string of characters and the plurality of the at least one second string of characters. Further, the display unit is configured to display the acquired image data when the reproducing unit is reproducing the music data. | 2010-11-04 |
20100278023 | SYSTEMS FOR OBTAINING WRITE STRATEGY PARAMETERS UTILIZING DATA-TO-CLOCK EDGE DEVIATIONS, AND RELATED METHOD AND OPTICAL STORAGE DEVICE THEREOF - A system in an optical storage device has a controller which obtains a plurality of write strategy parameters for the optical storage device to write data on an optical storage medium. The write strategy parameters are derived from data-to-clock edge deviations respectively corresponding to a plurality of data set types. Each of the data set types corresponds to a combination of at least a specific target pit length and a specific target land length, or a combination of at least a specific target land length and a specific target pit length. | 2010-11-04 |
20100278024 | OPTICAL DISC DRIVE AND HIBERNATION RECOVERY METHOD FOR AN OPTICAL DISC DRIVE - Provided is a technology in which a controller for controlling read/write performed to/from an optical disc includes a processor for controlling an interface, a temporary memory unit, a rotation control unit, and an optical control unit. The controller causes the processor to shift to a hibernate state when a predetermined condition is satisfied, and causes the processor to recover from the hibernate state into an active state when the interface receives a first command. The processor receives the first command from the interface, instructs the rotation control unit to drive the optical disc at a predetermined target rotational speed, instructs the optical control unit to perform a processing specified by the first command, transmits a completion notification of the first command to the interface with a delay, receives a second command after transmitting the completion notification of the first command, and executes the processing of the second command. | 2010-11-04 |
20100278025 | OPTICAL DISC DEVICE, OPTICAL DISC RECORDING METHOD, AND REPRODUCTION METHOD - Even when recording data which is continuously inputted at a high speed, it is possible to correct a recording error and reproduce preferable AV data without a noise upon reproduction. A recording error detection circuit ( | 2010-11-04 |
20100278026 | OPTICAL INFORMATION RECORDING MEDIUM REPRODUCING DEVICE, AND OPTICAL INFORMATION RECORDING MEDIUM - An optical information recording medium reproducing device ( | 2010-11-04 |
20100278027 | APPARATUS AND METHOD FOR MEASURING SIGNAL QUALITY - An apparatus and method for measuring the quality of a signal on an optical disc based on level information of a viterbi decoder are provided. The signal quality measuring apparatus includes: a binary unit that generates binary signals from input RF signals; a channel identifier that receives the input RF signals and the binary signals output from the binary unit and outputs reference level values corresponding to the binary signals; and an information calculator that receives the reference level values and detects a signal quality value. | 2010-11-04 |
20100278028 | RECORDING APPARATUS - A recording apparatus having a reproduction means to play digital data from a recording medium recorded with that digital data and retrieval information, a recording means to write the digital data reproduced by the reproduction means and record the retrieval information on a control table, and a control circuit to search the control table by using the retrieval information when the digital data from the reproduction means is written by the recording means, to permit the writing of digital data recorded on the medium with the recording means when the retrieval information is not recorded on the control table, and to prohibit the writing of digital data recorded on the medium with the recording means when the retrieval information is already recorded on the control table, and also prevent the mistaken duplicate copying of the digital data with the recording means. | 2010-11-04 |
20100278029 | REFLECTING WAVELENGTH PLATE AND OPTICAL PICKUP USING REFLECTING WAVELENGTH PLATE - Disclosed is a reflecting wavelength plate that deflects and reflects a light path and adds a phase difference with respect to plural incident light having different wavelengths. The reflecting wavelength plate includes a substrate; a reflecting film laminated on the substrate; and a sub-wavelength concavo-convex structure that is laminated on the reflecting film and has a pitch less than or equal to the shortest wavelength of the plural incident light. The filling factor and the groove depth of the sub-wavelength concavo-convex structure are determined so as to add the phase difference obtained by (kπ)/8, where k is an integer, to the plural incident light having the different wavelengths. | 2010-11-04 |
20100278030 | OPTICAL PICKUP OPTICAL SYSTEM AND OPTICAL PICKUP DEVICE HAVING THE SAME - An optical system for optical pickup, which optical system is used for performing recording, reproducing, and/or erasing of information on an optical recording medium and has a simple configuration, is provided. An optical pickup device | 2010-11-04 |
20100278031 | ULTRAVIOLET-CURABLE COMPOSITION FOR OPTICAL DISK AND OPTICAL DISK - With branched epoxy(meth)acrylate which comprises a phenyl skeleton serving as a stiff molecular skeleton, and which comprises in the molecular skeleton a number of branched structures capable of forming a coating structure at a high crosslinking density after ultraviolet curing, it becomes possible to design the coating hardness to be high even if the content of an acryloyl group is designed to be low to effect less crosslinking reaction induced by ultraviolet curing, and it becomes possible to relax distortions inside a cured film due to cure shrinkage which occurs at the time of ultraviolet curing. As a result, there can be realized an ultraviolet-curable composition for an optical disk which has a high elastic modulus and is less tilted at the time of curing even if the coating hardness is designed to be high. | 2010-11-04 |
20100278032 | OPTICAL INFORMATION RECORDING MEDIUM AND RECORDING/REPRODUCING METHOD THEREFOR - An optical information recording medium in which recorded information is stably stored for long time in the initial state, signals are not deteriorated by a laser beam for reproduction at the time of signal reproduction, the quality does not change in normal long-term storage, the write characteristic is held, a manufacturing cost is reduced, a margin in the manufacture process is assured, and excellent recording/reproducing characteristics are obtained in the wide range of linear speeds and recording powers is provided. An optical information recording medium | 2010-11-04 |
20100278033 | Method, Apparatus and System for Estimating Channel Transfer Matrices - A method, system and device for use in conjunction with Digital Subscriber Line (DSL) transmission systems, including Far-End Crosstalk (FEXT) cancellation circuitry. According to embodiments of the invention there is provided a system including a central office having a plurality of central modems, and at least one remote modem in communication with the plurality of central modems, the remote modem capable of automatic channel adjustment, and further capable of providing to the central office a channel adjustment parameter, wherein the central office includes a precoder to selectively precode symbols prior to transmission by each of the central modems with an estimation precoding matrix, and a controller to receive from the at least one remote modem respective channel adjustment parameters in response to transmitted symbols precoded with said estimation precoding matrix. | 2010-11-04 |
20100278034 | Efficient signal transmission methods and apparatus using a shared transmission resource - A device includes a zero symbol rate (ZSR) coding/modulation module and a second type coding/modulation module. Both modules generate modulation symbols to be conveyed using the same air link resources but with the non-zero ZSR symbols having a higher power level. The ZSR module generates a mixture of zero and non-zero modulation symbols. A ZSR modulation scheme communicates information using both the position of the non-zero modulation symbols and the phase and/or amplitude of the non-zero modulation symbols. Different ZSR schemes, implementing different ratios relating the number of zero symbols to the total number of symbols, can be associated with different low data rates while second module modulation schemes can be associated with different high data rates. Modulation symbols from two modules are in some embodiments, superimposed. In some embodiments, non-zero ZSR modulation symbols punch out second module modulation symbols which occupy the same air link resource. | 2010-11-04 |
20100278035 | METHOD AND SYSTEM FOR MULTI-USER DETECTION USING TWO-STAGE PROCESSING - Systems and methods for multi-user detection in a multiple access system are provided. In one aspect, an apparatus is provided. The apparatus comprises a processing unit configured to process received chips into received symbols for a plurality of users and a computation unit configured to compute a multi-user matrix using a Hadamard matrix, wherein the multi-user matrix relates user symbols for the plurality of users to the received symbols. The apparatus further comprises a detection unit configured to detect the user symbols for the plurality of users using the received symbols and the computed multi-user matrix. | 2010-11-04 |
20100278036 | METHOD AND DEVICE FOR USER COOPERATIVE COMMUNICATION - A wireless network system and corresponding methodologiesthat operates in a user cooperative communication system is provided. In operation, the system either combines packets transmitted from a direct channel with packets transmitted from and a relay channel, or uses erroneously relayed packets to assist decoding a direct packet. | 2010-11-04 |
20100278037 | Method of Handling Identity Confusion and Related Communication Device - A method of handling identity confusion for a network in a wireless communication system is disclosed. The method includes receiving from a first mobile device a radio resource control (RRC) connection reestablishment request message including a physical cell identity corresponding to a source cell of the first mobile device, and sending a RRC connection reestablishment reject message in response to the RRC connection reestablishment request message and a RRC connection release message according to a cell-level identity of the mobile device corresponding to the source cell. | 2010-11-04 |
20100278038 | Method and Apparatus for Mitigating Cell Outage - Cell outage within a wireless communication network is automatically mitigated. This way, neither manual operator intervention nor manual base station reconfiguration is needed to cover problematic cells. Quality of wireless services provided by the network improves when cell outage is automatically mitigated. In one embodiment, cell outage is mitigated in a wireless communication network by automatically communicating cell status messages between radio base stations or within a node that controls the radio base stations ( | 2010-11-04 |
20100278039 | METHOD TO BLOCK SPLIT PHONE AND GATEWAY REGISTRATION - The present disclosure is directed to a method and system to forcibly unregister and/or prevent registration of a gateway and/or other endpoint in a network region in response to a survivable gatekeeper servicing the network region becoming active. | 2010-11-04 |
20100278040 | PROTECTION METHOD, SYSTEM, AND DEVICE IN PACKET TRANSPORT NETWORK - A protection method in a packet transport network is provided. A protection path is established for a service data flow borne on a shared protection ring in the method, where the protection path includes a wrapping protection path and a steering protection path. Firstly, a first service data flow is sent through the wrapping protection path. Then, a service data flow node stops sending a second service data flow subsequent to the first service data flow to the wrapping protection path, and buffers the second service data flow. When the first service data flow completely passes by the service data flow node again, the buffered second service data flow is switched from the wrapping protection path to the steering protection path. | 2010-11-04 |
20100278041 | METHOD AND DEVICE FOR PROVIDING SERVICES FOR USER - A method and a device for providing services for a user are provided. The method includes receiving, by an interrogating call session control function (I-CSCF), a failure response returned by a first serving call session control function (S-CSCF) after the I-CSCF selects the first S-CSCF for the user according to a capability set of an S-CSCF returned by a home subscriber server (HSS) and forwards a service request to the first S-CSCF; obtaining, by the I-CSCF, information of a second S-CSCF, and forwarding the service request from the user to the second S-CSCF. Therefore, when multiple identities of the user simultaneously generate unregistered services, when they generate registration requests at the time of generating unregistered services, or when they simultaneously generate registration requests, the I-CSCF forwards the service request from the user to a corresponding S-CSCF for processing, thus enabling a network to normally provide services for the user. | 2010-11-04 |
20100278042 | SYSTEM AND METHOD FOR CONTROLLING CONGESTION IN CELLS WITHIN A CELLULAR COMMUNICATION SYSTEM - Systems and methods for controlling congestion in a cellular communication system ( | 2010-11-04 |
20100278043 | METHOD AND SYSTEM FOR IDENTIFYING DEGRADATION OF A MEDIA SERVICE - A method and device for identifying degradation in service quality for a wireless media service. The wireless media service has a known expected packet generation rate, which may be determined by the device based upon the codec and payload size selected on initiating the media service. At a receiving device, the packets actually received by the device from the other termination point are counted over a time period, and this number is compared with the number of packets that were expected based upon the known packet generation rate. From this comparison a packet loss rate may be determined. If the packet loss rate exceeds a threshold level, then the device may issue a user alert, terminate the service, or take other action. The threshold level may be established based upon a packet loss rate corresponding to a significant degree of service quality degradation. | 2010-11-04 |