44th week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100276742 | RANDOM ACCESS MEMORY DEVICE UTILIZING A VERTICALLY ORIENTED SELECT TRANSISTOR - A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell. | 2010-11-04 |
20100276743 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film. | 2010-11-04 |
20100276744 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region. | 2010-11-04 |
20100276745 | ELECTRICALLY PROGRAMMABLE DEVICE WITH EMBEDDED EEPROM AND METHOD FOR MAKING THEREOF - A semiconductor device includes a substrate and a first gate oxide layer overlying a first device region and a second device region in the substrate, a first gate in the first device region, and a second gate and a third gate in the second device region. The device also has a first dielectric layer with a first portion disposed on the first gate, a second portion disposed adjacent a sidewall of the first gate, and a third portion disposed over the third gate. An inter-gate oxide layer is disposed on the first gate and between the first portion and the second portion of the first dielectric layer. A fourth gate overlies the second gate oxide layer, the inter-gate oxide layer, and the first portion and the second portion of the first dielectric layer in the first device region. A fifth gate overlies the third portion of the first dielectric layer which is disposed over the third gate in the second device region. | 2010-11-04 |
20100276746 | SONOS MEMORY CELLS HAVING NON-UNIFORM TUNNEL OXIDE AND METHODS FOR FABRICATING SAME - Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure. | 2010-11-04 |
20100276747 | Charge trapping layer, method of forming the charge trapping layer, non-volatile memory device using the same and method of fabricating the non-volatile memory device - Provided is a charge trapping layer which has excellent memory characteristics, a method of forming the charge trapping layer, a nonvolatile memory device using the charge trapping layer, and a method of fabricating the nonvolatile memory device, in which a hybrid nanoparticle which is obtained by mixing a nanoparticle having an excellent programming characteristic with a nanoparticle having an excellent erasing characteristic is used as the charge trapping layer. The charge trapping layer for use in the nanoparticle is discontinuously formed between a tunneling oxide film and a control oxide film, and includes at least two different kinds of numerous nanoparticles. | 2010-11-04 |
20100276748 | METHOD OF FORMING LUTETIUM AND LANTHANUM DIELECTRIC STRUCTURES - Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control. | 2010-11-04 |
20100276749 | VERTICAL TRANSISTORS - The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures. | 2010-11-04 |
20100276750 | Metal Oxide Semiconductor (MOS) Structure and Manufacturing Method Thereof - The manufacturing method includes the steps of: providing a semiconductor base of a first conduction type; forming a first epitaxial layer with a plurality of epitaxial pillars of therein on a first surface of the semiconductor base, wherein the epitaxial pillars have a conduction type opposite to the first epitaxial layer; forming a plurality of first shallow trenches and a plurality of second shallow trenches alternately on the epitaxial pillars and the first epitaxial layer, wherein the first shallow trench has a width greater than the width of the second shallow trench and the first shallow trench is extended downward to the epitaxial pillar; and forming a plurality of gate regions in the first shallow trenches respectively; forming a plurality of source regions on both sides of the first shallow trench; and forming a source metal conducting wire to connect the source regions. | 2010-11-04 |
20100276751 | INTEGRATED CIRCUIT UTILIZING TRENCH-TYPE POWER MOS TRANSISTOR - An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region. | 2010-11-04 |
20100276752 | MONOLITHIC OUTPUT STAGE WITH VERTICLE HIGH-SIDE PMOS AND VERTICLE LOW-SIDE NMOS INTERCONNECTED USING BURIED METAL, STRUCTURE AND METHOD - A voltage converter can include an output circuit having a vertical high-side device and a vertical low-side device which can be formed on a single die (i.e. a “PowerDie”). The high side device can be a PMOS transistor, while the low side device can be an NMOS transistor. The source of the PMOS transistor and the source of the NMOS transistor can be formed from the same metal structure, with the source of the high side device electrically connected to V | 2010-11-04 |
20100276753 | Threshold Voltage Adjustment Through Gate Dielectric Stack Modification - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 2010-11-04 |
20100276754 | THIN-FILM SEMICONDUCTOR DEVICE AND FIELD-EFFECT TRANSISTOR - A semiconductor thin film ( | 2010-11-04 |
20100276755 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD FOR FABRICATING THE SAME - An electrostatic discharge protection device includes a substrate where an active region is defined by an isolation layer, a gate electrode simultaneously crossing both the isolation layer and the active region, and a junction region formed in the active region at both sides of the gate electrode and separated from the isolation layer by a certain distance in a direction where the gate electrode is extended. The electrostatic discharge protection device is able to prevent the increase of a leakage current while securing an electrostatic discharge protection property that a semiconductor device requires. | 2010-11-04 |
20100276756 | SUBSTRATE FINS WITH DIFFERENT HEIGHTS - A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas. | 2010-11-04 |
20100276757 | RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) IN REPLACEMENT METAL GATE (RMG) LOGIC FLOW - Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal. | 2010-11-04 |
20100276758 | STRESSED SEMICONDUCTOR USING CARBON AND METHOD FOR PRODUCING THE SAME - A stressed semiconductor using carbon is provided. At least one carbon layer containing diamond is formed either below a semiconductor layer or above a semiconductor device. The carbon layer induces stress in the semiconductor layer, thereby increasing carrier mobility in the device channel region. The carbon layer may be selectively formed or patterned to localize the induced stress. | 2010-11-04 |
20100276759 | Integrated Circuits and Methods of Design and Manufacture Thereof - Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives. | 2010-11-04 |
20100276760 | SEMICONDUCTOR DEVICE WITH METAL GATE - Gate electrode structures having a thin layer of ReO | 2010-11-04 |
20100276761 | Non-Planar Transistors and Methods of Fabrication Thereof - Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region. | 2010-11-04 |
20100276762 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side. | 2010-11-04 |
20100276763 | LGA SUBSTRATE AND METHOD OF MAKING SAME - A transistor comprises a gate ( | 2010-11-04 |
20100276764 | SEMICONDUCTOR STRUCTURE WITH SELECTIVELY DEPOSITED TUNGSTEN FILM AND METHOD FOR MAKING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer overlying the substrate; a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and a conformal metal layer selectively deposited on the top surface and sidewalls, but without deposited on the main surface of the dielectric layer substantially. | 2010-11-04 |
20100276765 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes: a bonding step of bonding a first substrate with optical transparency and a second substrate having a surface on which a functional element is provided to each other such that the functional element faces the first substrate; a thinning step of thinning at least one of the first and second substrates; and a through-hole forming step of forming a cavity and a through-hole communicated with the cavity in at least part of a bonding portion between the first and second substrates. According to the present invention, it is possible to prevent irregularities or cracks caused by the presence or absence of the cavity and more regularly thin the substrate. In addition, it is possible to manufacture a semiconductor device capable of contributing to the miniaturization of devices and electronic equipment having the devices, using a more convenient process. | 2010-11-04 |
20100276766 | SHIELDING FOR A MICRO ELECTRO-MECHANICAL DEVICE AND METHOD THEREFOR - A device comprises a conductive substrate, a micro electromechanical systems (MEMS) structure, and a plurality of bond pads. The conductive substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed over the first side of the conductive substrate. The plurality of bond pads are formed over the first side of the conductive substrate and electrically coupled to the first side of the conductive substrate. The conductive substrate and plurality of bond pads function to provide electrostatic shielding to the MEMS structure. | 2010-11-04 |
20100276767 | MEMS MICROPHONE WITH CAVITY AND METHOD THEREFOR - A device comprises a substrate, a micro electro-mechanical systems (MEMS) structure, and a dielectric film. The substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed on the first side of the substrate. The cavity is formed in the substrate directly opposite the MEMS structure. The cavity has an opening formed on the second side. The dielectric film is attached to the second side of the substrate and completely covering the opening. In one embodiment, the MEMS structure is a diaphragm for a microphone. Another embodiment includes a method for forming the device. | 2010-11-04 |
20100276768 | SIDEWALL COATING FOR NON-UNIFORM SPIN MOMENTUM-TRANSFER MAGNETIC TUNNEL JUNCTION CURRENT FLOW - A magnetic tunnel junction device comprises a substrate including a patterned wiring layer. A magnetic tunnel junction (MTJ) stack is formed over the wiring layer. A low-conductivity layer is formed over the MTJ stack and a conductive hard mask is formed thereon. A spacer material is then deposited that includes a different electrical conductivity than the low conductivity layer. The spacer material is etched from horizontal surfaces so that the spacer material remains only on sidewalls of the hard mask and a stud. A further etch process leaves behind the sidewall-spacer material as a conductive link between a free magnetic layer and the conductive hard mask, around the low-conductivity layer. A difference in electrical conductivity between the stud and the spacer material enhances current flow along the edges of the free layer within the MTJ stack and through the spacer material formed on the sidewalls. | 2010-11-04 |
20100276769 | SEMICONDUCTOR DEVICE - A semiconductor device includes a magnetic sensor chip, an electrically conducting layer wafer-level patterned in contact with the magnetic sensor chip, encapsulation material disposed on the magnetic sensor chip, and an array of external contact elements electrically coupled with the magnetic sensor chip through the electrically conducting layer. | 2010-11-04 |
20100276770 | SPIN CURRENT THERMAL CONVERSION DEVICE AND THERMOELECTRIC CONVERSION DEVICE - The invention relates to a spin current thermal conversion device and a thermoelectric conversion device, with which a spin current is thermally generated, and its concrete application is realized. | 2010-11-04 |
20100276771 | MAGNETORESISTANCE DEVICE INCLUDING LAYERED FERROMAGNETIC STRUCTURE, AND METHOD OF MANUFACTURING THE SAME - A layered ferromagnetic structure is composed of a first ferromagnetic layer positioned over a substrate; a second ferromagnetic layer positioned over the first ferromagnetic layer; and a first non-magnetic layer placed between the first and second ferromagnetic layers. The top surface of the first ferromagnetic layer is in contact with the first non-magnetic layer. The first ferromagnetic layer includes a first orientation control buffer that exhibits an effect of enhancing crystalline orientation of a film formed thereon. | 2010-11-04 |
20100276772 | PHOTOELECTRIC CONVERSION DEVICE AND METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - Provided are a photoelectric conversion device ( | 2010-11-04 |
20100276773 | PHOTOELECTRIC CONVERSION ELEMENT AND MANUFACTURING METHOD OF PHOTOELECTRIC CONVERSION ELEMENT - An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane. | 2010-11-04 |
20100276774 | INTEGRATED CIRCUIT PACKAGE AND METHOD FOR FABRICATION THEREOF - The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package. | 2010-11-04 |
20100276775 | SEMICONDUCTOR LIGHT RECEIVING ELEMENT - The semiconductor light receiving element | 2010-11-04 |
20100276776 | Germanium Film Optical Device Fabricated on a Glass Substrate - A germanium (Ge) photodiode array on a glass substrate is provided with a corresponding fabrication method. A Ge substrate is provided that is either not doped or lightly doped with a first dopant. The first dopant can be either an n or p type dopant. A first surface of the Ge substrate is moderately doped with the first dopant and bonded to a glass substrate top surface. Then, a first region of a Ge substrate second surface is heavily doped with the first dopant. A second region of the Ge substrate second surface is heavily doped with a second dopant, having the opposite electron affinity than the first dopant, forming a pn junction. An interlevel dielectric (ILD) layer is formed overlying the Ge substrate second surface and contact holes are etched in the ILD layer overlying the first and second regions of the Ge substrate second surface. The contact holes are filled with metal and metal pads are formed overlying the contact holes. | 2010-11-04 |
20100276777 | LOW CAPACITANCE PHOTODIODE ELEMENT AND COMPUTED TOMOGRAPHY DETECTOR - A photodiode element includes a first layer of a first diffusion type and a second layer. The second layer defines a charge-collecting area. The charge-collecting area includes an active region of a second diffusion type and an inactive region. The active region surrounds the inactive region. The photodiode element also includes an intrinsic semiconductor layer between the first layer and the second layer. | 2010-11-04 |
20100276778 | Image sensor - A buried oxide is provided in a substrate of a photodiode so as to be opposed to a cathode and is in contact with a lower end of a depletion layer. The buried oxide is polarized owing to charges forming the depletion layer and thus works as a capacitor. A capacitor formed in the depletion layer and the additional capacitor made by the buried oxide are, therefore, connected in series, which reduces a total junction capacitance Cs. Increase in photo-detection voltage Vs results in according to an equation, Vs=Qp/Ct, since an amount of photocharge Qp is constant. The increase in the photo-detection voltage Vs allows an improvement in the SN ratio of the photodiode. Further, easy formation of the buried oxide, for example, by implanting oxygen ions, permits low-cost manufacturing of the photodiode. | 2010-11-04 |
20100276779 | Transient Voltage Suppressor Having Symmetrical Breakdown Voltages - A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS. | 2010-11-04 |
20100276780 | Memory Arrays - The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions. | 2010-11-04 |
20100276781 | Semiconductor Constructions - The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H | 2010-11-04 |
20100276782 | SEMICONDUCTOR DEVICE MOUNTED WITH FUSE MEMORY - A fuse element utilizing a reaction between two layers by feeding current is manufactured. A fuse element including a first layer formed of an oxide or a nitride and a second layer that becomes high resistant by nitridation or oxidation, in which the first layer and the second layer are in contact with each other, is manufactured. For example, the fuse element is manufactured by using indium tin oxide for the first layer and aluminum for the second layer. By generating joule heat by applying voltage to the first layer and the second layer, oxygen in the indium tin oxide enters the aluminum, which changes the aluminum into aluminum oxide that presents an insulating property. The fuse element can be manufactured by a similar process as that of forming a TFT. | 2010-11-04 |
20100276783 | SELECTIVE PLASMA ETCH OF TOP ELECTRODES FOR METAL-INSULATOR-METAL (MIM) CAPACITORS - A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ≦100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas. | 2010-11-04 |
20100276784 | ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - An electronic module including a substrate having at least one structure that reduces stress flow through the substrate, wherein the structure comprises at least one trench in a surface of the substrate. | 2010-11-04 |
20100276785 | DOPING OF SEMICONDUCTOR LAYER FOR IMPROVED EFFICIENCY OF SEMICONDUCTOR STRUCTURES - A system and method for variable doping within a semiconductor structure for improved efficiency is described. One embodiment includes a semiconductor structure comprising a first semiconductor layer comprising a first semiconductor material, and a second semiconductor layer comprising a second semiconductor material, wherein the second semiconductor material is an oppositely-typed semiconductor material from the first semiconductor material, and wherein the second semiconductor layer comprises a first region adjacent to the first semiconductor layer, wherein the first region comprises low-doped second semiconductor material, and a second region adjacent to the first region, wherein the second region comprises highly-doped second semiconductor material to increase a built-in potential of the semiconductor structure. | 2010-11-04 |
20100276786 | Through Substrate Vias - Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal. | 2010-11-04 |
20100276787 | Wafer Backside Structures Having Copper Pillars - An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL. | 2010-11-04 |
20100276788 | METHOD AND DEVICE OF PREVENTING DELAMINATION OF SEMICONDUCTOR LAYERS - Embodiments of the present invention describe a method and device of preventing delamination of semiconductor layers in a semiconductor device. The semiconductor device comprises a substrate with an interlayer dielectric (ILD). A protection layer is deposited on the ILD. Next, a getter layer is formed on the protection layer to remove any native oxides on the protection layer. A capping layer is then deposited on the getter layer to prevent oxidation of the getter layer. Next, a semiconductor layer is formed on the capping layer. An oxide layer is then deposited on the semiconductor layer. Subsequently, a buffered oxide etch solution is used to remove the oxide layer. By removing the native oxides on the protection layer, the getter layer prevents the reaction between the buffered oxide etch solution and the native oxides which may cause delamination of the semiconductor layer and protection layer. | 2010-11-04 |
20100276789 | SEMICONDUCTOR DEVICE HAVING MULTIPLE-LAYER HARD MASK WITH OPPOSITE STRESSES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress. | 2010-11-04 |
20100276790 | INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL - A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased. | 2010-11-04 |
20100276791 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on a principal surface of the semiconductor substrate and having a multiple-layered interconnect layer; and a heterostructure magnetic shield covering the semiconductor element. The heterostructure magnetic shield includes a first magnetic shield layered structure and a second magnetic shield layered structure that covers the first magnetic shield layered structure. Each of a first and a second magnetic shield layered structures includes a magnetic shielding film composed of a magnetic substance and covering the semiconductor element and a buffer film disposed between the semiconductor element and the magnetic shield films and preventing a diffusion of the magnetic substance. | 2010-11-04 |
20100276792 | Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure - A semiconductor device has a substrate containing a conductive layer. An interconnect structure is formed over the substrate and electrically connected to the conductive layer. A semiconductor component is mounted to the substrate. An encapsulant is deposited over the semiconductor component and interconnect structure. A channel is formed in the encapsulant to expose the interconnect structure. Solder paste is deposited in the channel prior to forming the shielding layer. A shielding layer is formed over the encapsulant and semiconductor component. The shielding layer can be conformally applied over the encapsulant and semiconductor die and into the channel. The shielding layer extends into the channel and electrically connects to the interconnect structure. A docking pin is formed on the shielding layer, which extends into the channel and electrically connects to the interconnect structure. A chamfer area is formed around a perimeter of the shielding layer. | 2010-11-04 |
20100276793 | HIGH PIN DENSITY SEMICONDUCTOR SYSTEM-IN-A-PACKAGE - Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The packages also contain multiple chips that are stacked vertically. The chips are connected through stud bumps, printed interconnect structures, and conductive pillars formed with the package. The packages also contain two different moldings layers that together operate as an encapsulation material. The semiconductor packages contain a full land pad array at both the bottom and the top of the package, allowing the packages to be used in a package-on-package configuration. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described. | 2010-11-04 |
20100276794 | SYSTEM AND METHOD FOR MULTI-CHIP MODULE DIE EXTRACTION AND REPLACEMENT - A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another. | 2010-11-04 |
20100276795 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package capable of being efficiently stacked and a method of manufacturing the same is presented. The semiconductor package includes a semiconductor chip, an insulation layer, and a through-electrode. The semiconductor chip has a first surface and a second surface, a circuit section in the semiconductor chip, an internal circuit pattern electrically connected to the circuit section, and a through-hole that passes through the internal circuit pattern and through the first and second surfaces. The insulation layer is on a through-hole of the semiconductor chip and has an opening which exposes the internal circuit pattern which was exposed by the through-hole. The through-electrode is in the through-hole and electrically coupled to the internal circuit pattern which is exposed through the opening of the insulation layer. | 2010-11-04 |
20100276796 | REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD - An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts. | 2010-11-04 |
20100276797 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a chip island, a chip attached to the chip island, and encapsulation material deposited on the chip and part of the chip island. The chip island includes a first main face to which the chip is attached opposite a second main face, with the second main face of the chip island defining at least one cavity. | 2010-11-04 |
20100276798 | Semiconductor device - A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad. | 2010-11-04 |
20100276799 | Semiconductor Chip Package with Stiffener Frame and Configured Lid - Various semiconductor chip packages and methods of assembling and making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a stiffener frame to a first side of a substrate. The stiffener frame has a central opening to accommodate a semiconductor chip and an outer edge surface. A semiconductor chip is coupled to the first side in the opening. A lid is coupled to the stiffener frame with an adhesive. The lid has a first edge surface set back from the outer edge surface of the stiffener frame. The adhesive is set back from the outer edge surface of the stiffener frame. | 2010-11-04 |
20100276800 | SEMICONDUCTOR MODULE - A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding. | 2010-11-04 |
20100276801 | SEMICONDUCTOR DEVICE AND METHOD TO MANUFACTURE THEREOF - A semiconductor device | 2010-11-04 |
20100276802 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire. | 2010-11-04 |
20100276803 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor element ( | 2010-11-04 |
20100276804 | SEMICONDUCTOR DEVICE INCLUDING RUTHENIUM ELECTRODE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug fainted on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug. | 2010-11-04 |
20100276805 | INTEGRATED CIRCUIT CHIP WITH REDUCED IR DROP - An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion. | 2010-11-04 |
20100276806 | Plastic package and method of fabricating the same - A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals. | 2010-11-04 |
20100276807 | FABRICATION OF METAL FILM STACKS HAVING IMPROVED BOTTOM CRITICAL DIMENSION - A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a bottom titanium nitride barrier. | 2010-11-04 |
20100276808 | SURFACE MOUNTING ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - The electric component includes at least a set of electrode terminals | 2010-11-04 |
20100276809 | T-CONNECTIONS, METHODOLOGY FOR DESIGNING T-CONNECTIONS, AND COMPACT MODELING OF T-CONNECTIONS - T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar. | 2010-11-04 |
20100276810 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device is provided. A substrate is provided. A buried layer is formed in the substrate. The buried layer comprises an insulating region. A deep trench contact structure is formed in the substrate. The deep trench contact structure comprises a conductive material and a liner layer formed on a side wall of the conductive material. The conductive material is electrically connected with the substrate. | 2010-11-04 |
20100276811 | Semiconductor Component with Terminal Contact Surface - At least one terminal contact surface ( | 2010-11-04 |
20100276812 | EPITAXIAL WAFER AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a substrate, a conductive layer deposited on a substrate and an epitaxial layer deposited on the conductive layer. The conductive layer is patterned to include a first pattern. The first pattern includes a major surface and a plurality of grids defined in the major surface. The major surface includes a plurality of first lines and a connecting portion. The connecting portion is connected to an electrode. The epitaxial layer covers the grids and the first lines between the adjacent grids. | 2010-11-04 |
20100276813 | INJECTION MOLDED SOLDERING PROCESS AND ARRANGEMENT FOR THREE-DIMENSIONAL STRUCTURES - A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips. In accordance with a further aspect, it is possible to derive a unique design for an IMS mold structure, which contains cavities for forming the columnar fill of solder, and which also incorporates further cavities acting as cutouts for dies or the positioning of other electronic packages or modules. | 2010-11-04 |
20100276814 | METHODS FOR PACKAGING MICROELECTRONIC DEVICES AND MICROELECTRONIC DEVICES FORMED USING SUCH METHODS - Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is directed toward a method for packaging a microelectronic device that includes coupling an active side of a microelectronic die to a surface of a support member. The microelectronic die can have a backside opposite the active side, a peripheral side extending at least part way between the active side and the backside, and at least one through-wafer interconnect. The method can further include applying an encapsulant to cover a portion of the surface of the support member so that a portion of the encapsulant is laterally adjacent to the peripheral side, removing material from a backside of the microelectronic die to expose a portion of at least one through-wafer interconnect, and applying a redistribution structure to the backside of the microelectronic die. | 2010-11-04 |
20100276815 | INTEGRATED CIRCUIT COMMUNICATION SYSTEM WITH DIFFERENTIAL SIGNAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit communication system including providing a semiconductor wafer; and fabricating a cross-over current mirror driver on the semiconductor wafer for generating a crossing point at a reference voltage. | 2010-11-04 |
20100276816 | SEPARATE PROBE AND BOND REGIONS OF AN INTEGRATED CIRCUIT - Disclosed are a system and method of separate probe and bond regions of an integrated circuit (IC). An IC, an I/O region adjacent to the core region to enable the core region, and a die metal interconnect separating a bond pad area in the I/O region from a probe pad area outside the I/O region of the IC are disclosed. The die metal interconnect may have a length that is greater than the bond pad area length and/or the probe pad area length, and a width that is less than the bond pad area width and/or the probe pad area width. An in-front staggering technique may be used at a die corner of the IC to maintain the bond pad area in the I/O region, and a side staggering technique may be used at the die corner of the IC to maintain the bond pad area in the I/O region. | 2010-11-04 |
20100276817 | SEMICONDUCTOR DEVICE - A protective coating is formed on the surface of a semiconductor device. The surface is located on the side to which an extension portion of a wire connected to a pad of the semiconductor device is pulled. The protective coating is formed such that its height decreases toward the pad. | 2010-11-04 |
20100276818 | DEVICE COMPRISING AN ORGANIC COMPONENT AND AN ENCAPSULATION LAYER WITH A MOISTURE-REACTIVE MATERIAL - The device includes at least one optoelectronic component positioned on a substrate and at least one transparent face. The component is covered by a packaging layer which includes at least one barrier layer and a moisture-reactive layer. The reactive layer includes a moisture-reactive material chosen from alkaline-earth metals, alkali metals and organo-metallic derivatives. The material can be positioned in the moisture-reactive layer in the form of a continuous layer or in the form of a plurality of nodules dispersed in an organic matrix. | 2010-11-04 |
20100276819 | Microbubble gas-liquid mixing device - A microbubble gas-liquid mixing device is fitted and disposed in a sanitary fixture, wherein the sanitary fixture has at least one faucet and the water source treated by the microbubble gas-liquid mixing device is introduced into the faucet. The microbubble gas-liquid mixing device comprises a pump and a spiral tube, and air enters the pump and spiral tube through a first gas inlet valve disposed at the front end of the pump and is therein mixed with the water source in a gas-liquid phase to form a large amount of fine bubbles, thereby achieving the effect of increasing the oxygen content in water. | 2010-11-04 |
20100276820 | STATIC FLUID MIXER - A static fluid mixer which can perform processing such as generation of ultrafine uniform bubbles and has small pressure loss. A static fluid mixer has mixing units having outflow openings for allowing fluid having passed through mixing flow paths to flow through the outflow openings. The mixing units are arranged in a tubular casing body at intervals in the axis direction of the casing body. Adjacent mixing units and the casing body forma flow path forming space. Each mixing unit has an annular outflow path communicating with the end of each mixing flow path. The annular outflow path is open in a ring-like form having a substantially constant width along the entire circumference. The opening at the end of the annular outflow path functions as an outflow opening connecting to the flow path forming space. In the outflow path forming space is formed a collection flow path into which liquid having passed through the mixing flow path collects after flowing from the entire circumference of the outflow opening which is open in the ring-like form and moving toward the axis of the casing body. | 2010-11-04 |
20100276821 | VAPOR DISTRIBUTOR FOR GAS-LIQUID CONTACTING COLUMNS - A vapor distributor for use in atmospheric or vacuum columns includes a new design of vapor inlet device, or vapor horn, to provide superior mixing and distribution of a tangential first feed and a vertical second feed. New vapor inlet device has an inlet dividing the first feed into two portions, each flowing in respective housings in opposed circulation directions, and a plurality of vanes for redirection of vapor. Mixing and distribution of feeds by the vapor distributor is further enhanced by inclusion in vapor distributor of a mixer and vapor directing plates. | 2010-11-04 |
20100276822 | RARE EARTH-DOPED CORE OPTICAL FIBER AND MANUFACTURING METHOD THEREOF - A rare earth-doped core optical fiber of the present invention includes a core comprising a silica glass containing at least aluminum and ytterbium, and a clad provided around the core and comprising a silica glass having a lower refraction index than that of the core, wherein the core has an aluminum concentration of 2% by mass or more, and ytterbium is doped into the core at such a concentration that the absorption band which appears around a wavelength of 976 nm in the absorption band by ytterbium contained in the core shows a peak absorption coefficient of 800 dB/m or less. | 2010-11-04 |
20100276823 | METHOD FOR MAKING CONTACT LENSES - The instant invention pertains to a method and a fluid composition for producing contact lenses with improved lens quality and with increased product yield. The method of the invention involves adding a phospholipid into a fluid composition including a lens-forming material in an amount sufficient to reduce an averaged mold separation force by at least about 40% in comparison with that without the phospholipids. | 2010-11-04 |
20100276824 | METHOD FOR MAKING CONTACT LENSES - The instant invention pertains to a method and a fluid composition for producing contact lenses with improved lens quality and with increased product yield. The method of the invention involves adding a phospholipid into a fluid composition including a lens-forming material in an amount sufficient to reduce an averaged mold separation force by at least about 40% in comparison with that without the phospholipids. | 2010-11-04 |
20100276825 | METHOD FOR MANUFACTURING LENS MOLD - In a method for manufacturing a lens mold, a raw mold is provided. The raw mold defines a cavity therein. The cavity defines a raw molding surface. The raw molding surface includes a molding surface portion. The molding surface portion includes a center. Photoresist material is filled in the cavity, covering the molding surface portion. A photo mask is provided. The photo mask defines a through hole. The size through hole is the same as the molding surface portion of the lens mold. The photo mask is placed above the photoresist material with the through hole aligned with the center. The photoresist material is exposed and developed to form a photoresist portion. A rigid molding material is filled in the cavity. The resist portion is removed to expose the molding surface. | 2010-11-04 |
20100276826 | PROCESS FOR PRODUCING RETARDATION FILM - A method for producing a retardation film by a tenter method, in which a thermoplastic resin film | 2010-11-04 |
20100276827 | Method for Producing Nanoparticles - A method for producing nanoparticles which includes dissolving a solute into a solvent forming a solution, feeding the solution through a liquid entrance port of a convergent-divergent nozzle; feeding a carrier gas into a gas entrance port of the nozzle, mixing the solution and the carrier gas prior to entering the nozzle, upon exiting the nozzle the solution is atomized to micron sized droplets, and the evaporating the solvent and leaving behind solid state nanoparticles of the solute. | 2010-11-04 |
20100276828 | Resin Infusion Mold Tool System And Vacuum Assisted Resin Transfer Molding With Subsequent Pressure Bleed - A resin infusion mold tool system for use in a vacuum assisted resin transfer molding process with a subsequent pressure bleed step. The mold tool system includes a mold assembly having an outer mold line tool connected to resin supply lines and supplying resin to the preform. A plurality of inner mold line tools form a hard interface with the inner mold line of the fiber preform and are held to within tight tolerances by an external locating fixture. Excess resin is drawn out of the fiber preform using a vacuum bag connected to vacuum lines and disposed over the inner mold line tools but not between the tools and the fiber preform. The mold assembly is placed in an autoclave, the resin supply lines are detached and the autoclave pressurized to bleed additional resin out of the preform to raise the fiber volume of the composite structure. | 2010-11-04 |
20100276829 | High Aspect Ratio Microstructures and Method for Fabricating High Aspect Ratio Microstructures From Powder Composites - Methods to fabricate high aspect ratio powder composite microstructures is provided by filling a molding composition containing a powdered material and a binder into a patterned mold, and releasing the cured composite microstructures from the mold. An alternate method is by filling a mix of powdered dense metals and low-melt alloys into a patterned mold, and releasing the melted and solidified composite microstructures from the mold. The mold is derived from lithographically defined parent mold. One example of the application is in the field of x-ray anti-scatter grids and nuclear collimators. | 2010-11-04 |
20100276830 | Method For Manufacturing A Fiber-Reinforced Composite Sabot By Using Resin-Injection Vacuum Assisted Resin Transfer Molding After Stitching - Disclosed is a method for manufacturing a fiber-reinforced composite sabot for use in APFSDS (Armor Piercing Fin Stabilized Discarding Sabot) wherein a plurality of fiber mats are laminated instead of one-directional prepreg ply and whole part is reinforced by stitching through long fiber bundle in order to enhance circumferential shear strength, and high quality fiber-reinforced composite sabot is manufactured in a short time using resin-injection vacuum assisted resin transfer molding after stitching. | 2010-11-04 |
20100276831 | COLD-SHRINKABLE TYPE RUBBER INSULATION SLEEVE AND METHOD OF MANUFACTURING - A cold-shrinkable type rubber insulation sleeve includes a reinforced insulation sleeve, a semiconductive stress-relief cone, an internal semiconductive layer, and an external semiconductive layer. The reinforced insulation sleeve, the semiconductive stress-relief cone, and the internal semiconductive layer are formed by molding, and the external semiconductive layer is formed by coating. | 2010-11-04 |
20100276832 | COMPOSITE METAL MOLDING AND METHOD FOR MANUFACTURING THEREOF - A compression molding which is high in both dimensional accuracy and mechanical strength is difficult to manufacture by a powder molding process. Especially, a molding including a soft magnetic material with high soft magnetic properties is difficult to manufacture. A composite metal molding according to the present invention includes metal particles and the carbide of a resin intervening among the particles. It is manufactured by coating metal particles with a resin, molding the prepared molding material under pressure into a predetermined shape, and heating the prepared pressurized preform to calcine the resin and weld mutually the particles. The carbide of the resin has a weight ratio of 0.001 to 2% to the metal particles when the particles have their proportion expressed as 100. The particles have a weld ratio of 10 to 80%. The particles preferably contain a soft magnetic material and the resin is preferably a furan resin. | 2010-11-04 |
20100276833 | CONTINUOUS RESIN FABRIC - A decorative surface covering includes a fabric; and a layer of molded resin disposed on said fabric, where the resin is molded into decorative features of the covering. A method of forming a decorative surface covering includes molding resin disposed on a fabric to produce decorative features, the resin adhering to the fabric. | 2010-11-04 |
20100276834 | DEVICE FOR GRANULATING PLASTIC STRANDS - The invention relates to a device for granulating plastic strands having a cutting wheel ( | 2010-11-04 |
20100276835 | Method of Manufacturing an Air Hole of Hollow Fiber Membrane Module for Water Treatment - The present invention relates to a method of forming air holes in a hollow fiber membrane module for water treatment. A main object of the present invention is to easily form air holes in the potting material injected into the module housing to prevent contamination of the hollow fiber membranes in the module housing. Accordingly, the present invention provides a method of forming air holes in a hollow fiber membrane module for water treatment, in which a plurality of pins and a disc-like plate, to which distal ends of the pins are fit, are disposed at one end portion of the inside of the module housing, the pins and the plate are immersed in the potting material (adhesive agent) during the potting process, the bonding mold is first removed from the module housing after the potting process and the plate is separated from the pins, and simultaneously the rear ends of the pins exposed to the outside are pulled outwardly to be removed from the potting material such that a plurality of air holes are formed at the corresponding empty positions of the potting material from which the pins are removed. | 2010-11-04 |
20100276836 | Transfer System for Multicomponent Injection Molding - The invention relates to a method and a device for producing parts that are made up of more than one component. The first part ( | 2010-11-04 |
20100276837 | Lightweight construction material and methods and device for fabrication thereof - A lightweight construction material, a method of fabricating building panels utilizing said material and device therefore. The formulation utilizes silicone-treated expanded perlite in combination with cement, alpha gypsum, polyvinyl alcohol fibers and powder, and water. Building panels are formed utilizing fiber mesh to reinforce them while minimizing their weight. The building panel may be formed with one layer or two layers of different formulations. | 2010-11-04 |
20100276838 | STEERING WHEEL AND METHOD OF MANUFACTURING THE SAME - A steering wheel includes a rim that is rotatable around a steering shaft. The rim includes an armature; a first rim portion surrounding the armature; and a second rim portion, covering part of the surface of the first rim portion. A method of manufacturing a steering wheel includes providing an armature; injection molding a first rim portion such that the it surrounds the armature; injection molding a second rim portion; and attaching the first and second rim portions such that the second rim portion covers part of the surface of the first rim portion. | 2010-11-04 |
20100276839 | WASTE CONTAINER AND RELATED METHOD OF MANUFACTURE - A method of forming a container includes providing a mold including at least one bulbous protrusion. The mold is closed to form a mold cavity corresponding to the shape of the container, with the bulbous protrusion being positioned in the mold cavity. Material is injected into the mold cavity to form the container, and the material envelopes the bulbous protrusion to create an undercut slot. The container is removed from the mold and the bulbous protrusion is withdrawn from the slot. | 2010-11-04 |
20100276840 | APPARATUS AND METHOD FOR MAKING SUTURE PACKAGES - Apparatus and method for making a plurality of different types of suture packages employ a mold with first and second opposing mold parts partially defining a mold cavity, at least one of the opposing mold parts has an opening therein communicating with the mold cavity. An insert is removeably inserted into the opening, to complete the mold cavity in a form suitable for molding a first type of suture package. An alternative insert is interchangeable with the first insert for completing the mold cavity in a form suitable for molding a second type of suture package. To make different suture packages, the mold is initially configured and used with one of the inserts to thereby make one type of suture package. The first insert is then replaced with the second, changing the mold cavity to form another type of suture package. | 2010-11-04 |
20100276841 | INJECTION MOLDING DEVICE WITH A ROTATABLE CENTRAL PART - The present disclosure relates to an injection moulding device with a first mould half and a second mould half, arranged movably with respect to said first half, and a central mould half arranged between said first and second halves and rotatable about an axis of rotation. Arranged to the side of the central mould half is a further processing device. | 2010-11-04 |