| 44th week of 2011 patent applcation highlights part 59 |
| Patent application number | Title | Published |
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| 20110271034 | MULTIPLE PARTITIONED EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY AND METHOD OF OPERATION - A method and system wherein a volatile memory is partitioned to have a first percentage of address space dedicated to a first classification of data which is data that is expected to have greater than a predetermined number of times of being modified and a second percentage of address space dedicated to a second classification of data which is data that is expected to have less than the predetermined probability of being modified. Address assignment of data to be stored in the volatile memory is made on a basis of predicted change of the data. Memory addresses of the first and second percentages of address space are respectively assigned to first and second sections of nonvolatile memory. The memory addresses of the first percentage initially consume a smaller percentage of an address map of the first section than the memory addresses of the second percentage of the second section. | 2011-11-03 |
| 20110271035 | EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY AND METHOD OF OPERATION - A system has an emulation memory having a plurality of sectors for storing information. A controller calculates a number of addresses used divided by a number of valid records in a predetermined address range of the emulation memory. An amount of remaining addresses in a currently used space of the emulation memory which have not been used to store information is calculated. A determination is made whether the calculation is greater than a first predetermined number and whether the amount of remaining addresses is greater than a second predetermined number. If both the fraction is greater than the first predetermined number and the amount of remaining addresses is greater than the second predetermined number, any subsequent update requests are responded to using the currently used space of the emulation memory. Otherwise a compression of the emulation memory is required by copying valid data to an available sector. | 2011-11-03 |
| 20110271036 | PHASED NAND POWER-ON RESET - A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold. | 2011-11-03 |
| 20110271037 | STORAGE DEVICE PERFORMING DATA INVALIDATION OPERATION AND DATA INVALIDATION METHOD THEREOF - A storage device of one aspect includes a data storage medium including a plurality of memory blocks, and a storage controller which outputs a free memory block signal to a host device, and which is responsive to an externally received invalidation command from the host device to selectively invalidate data stored in the memory blocks of the storage medium. The free memory block signal is in accordance with a free memory block status of the data storage medium. | 2011-11-03 |
| 20110271038 | INDEXED REGISTER ACCESS FOR MEMORY DEVICE - Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain. | 2011-11-03 |
| 20110271039 | APPARATUS AND METHOD FOR FLASH MEMORY ADDRESS TRANSLATION - Provided is a flash memory address translation method that may maintain at least one chip that may be divided based on at least one horizontal bank and at least one vertical channel, and may divide the at least one bank by at least one stripe partition, managing an error of a chip without deterioration in a performance of a small writing. | 2011-11-03 |
| 20110271040 | MEMORY SYSTEM HAVING NONVOLATILE SEMICONDUCTOR STORAGE DEVICES - According to an embodiment, a memory system includes a memory unit, a memory controller, a timer and a timer control unit. The memory unit has nonvolatile first and second chips capable of holding data. The memory controller transfers data received from host equipment simultaneously to the first and second chips. The timer measures a lapse of preset shift time. The timer control unit starts writing of data into the second chip immediately after the lapse of the shift time. | 2011-11-03 |
| 20110271041 | ELECTRONIC DEVICE COMPRISING FLASH MEMORY AND RELATED METHOD OF HANDLING PROGRAM FAILURES - A storage device performs a program operation to store program data in a selected memory block of a flash memory. The storage device allocates a reserved area of the flash memory as a free block upon detecting that a program failure has occurred in the program operation, reads the program data from a cache latch in a page buffer of the flash memory, copies valid data stored in the selected memory block to a first area of the free block, and reprograms the program data read from the cache latch to a second area of the free block. | 2011-11-03 |
| 20110271042 | METHOD FOR WRITING INTO AND READING FROM AN ATOMICITY MEMORY - A method for writing data into a reprogrammable non-volatile memory, wherein a marking pattern including several bits is added at the beginning of the data and the set formed of the marking pattern and of the data is written from an address in the memory varying from one write operation to another, the marking pattern being identical for each write operation. | 2011-11-03 |
| 20110271043 | SYSTEM AND METHOD FOR ALLOCATING AND USING SPARE BLOCKS IN A FLASH MEMORY - A method for using a single spare block pool in flash memory comprising: allocating a plurality of flash memory arrays, wherein each flash memory array comprises a plurality of flash memory blocks; within a main flash memory array: allocating a used block pool comprising a plurality of used blocks and allocating a main spare block pool comprising a plurality of spare blocks; within each of the other flash memory arrays: allocating a used block pool comprising multiple used blocks; allocating a minimum spare block pool comprising a minimum number of spare blocks; allocating the main spare block pool and each of the minimum spare block pools to a single spare block pool; transferring a spare block from the main spare block pool to one of the minimum spare block pools; and transferring a spare block from a first minimum spare block pool to a second minimum spare block pool. | 2011-11-03 |
| 20110271044 | MEMORY CARD HAVING ONE OR MORE SECURE ELEMENTS ACCESSED WITH HIDDEN COMMANDS - A memory card compatible token includes one or more secure elements accessed using secure element commands hidden in a memory card access command. A mobile computing device such as a mobile phone accesses the non-memory components by including a hidden command value as part of the memory card access command. Any set or subset of all possible secure element commands may be routed to one or more secure elements based on the hidden command value. | 2011-11-03 |
| 20110271045 | Controller for One Type of NAND Flash Memory for Emulating Another Type of NAND Flash Memory - A method of executing an erasing instruction to erase host data from a flash memory device is provided. The method initiates with receiving from a host device an erase instruction to erase host data from an array of NAND flash memory cells grouped into separately-erasable device blocks, each device block including multiple device pages, the host data being a portion of device data that is stored in a device block. The host data is marked as erased, and a message is sent to the host device indicating that the host data has been erased. | 2011-11-03 |
| 20110271046 | WEAR LEVELING FOR LOW-WEAR AREAS OF LOW-LATENCY RANDOM READ MEMORY - Described herein are method and apparatus for performing wear leveling of erase-units of an LLRRM device that considers all active erase-units. Wear counts of all active erase-units (containing client data) and free erase-units (not containing client data) are tracked. Wear counts are used to determine low-wear active erase-units having relatively low wear counts and high-wear free erase-units having relatively high wear counts. In some embodiments, data contents of low-wear active erase-units are transferred to high-wear free erase-units, whereby the low-wear active erase-units are converted to free erase-units and may later store different client data which may increase the current rate of wear for the erase-unit. The high-wear free erase-units are converted to active erase-units that store client data that is infrequently erased/written, which may reduce the current rate of wear for the erase-unit. As such, wear is spread more evenly among erase-units of the LLRRM device. | 2011-11-03 |
| 20110271047 | STORAGE DEVICE IN COMPUTER SYSTEM AND METHOD FOR CONTROLLING THE SAME - A storage device of a computer system including a first storage portion having a first capacity and a second storage portion having a second capacity is disclosed. A virtual storage unit is installed in an operating system of the computer system, and the operating system directly accesses data in the first capacity of the storage device. The operating system accesses the data in the second capacity via the virtual storage unit mapped to the second capacity of the storage device. The invention may be adapted to the storage device which uses a MBR partition table scheme and has a capacity larger than 2.2 TB which is the maximum supportive capacity of the MBR partition table scheme. | 2011-11-03 |
| 20110271048 | STORAGE APAPRATUS AND ITS CONTROL METHOD - A storage apparatus and its control method capable of shortening data save time at the time of power shutdown are suggested. | 2011-11-03 |
| 20110271049 | STORAGE SYSTEM HAVING POWER SAVING FUNCTION - A data element that is identical to a part of a plurality of data elements stored in a logical storage device (LU hereinbelow) is stored in a storage area (pool hereinbelow) separate from the LU. A first PDEV (physical storage device) that stores the data element stored in the LU may be placed in a power saving state while the storage system is operating (in periods when a read command can be received), and a second PDEV which stores the data element stored in the pool is not placed in a power saving state during operation. When the storage system receives a read command which is received from the host apparatus, and if the first PDEV is in the power saving state and a data element identical to the data element which is the target of the read command is stored in the pool, the storage system reads the identical data element from the pool without canceling the power saving state of the first PDEV, and sends the read data element to the host apparatus. | 2011-11-03 |
| 20110271050 | STORAGE SYSTEM - A storage system includes: a plurality of storing means and a data processing means that stores data into the plurality of storing means and retrieves the data stored in the storing means. The data processing means includes: a data set generating means that generates division data by dividing storage target data into a plurality of pieces and also generates redundant data for restoring the storage target data, thereby generating a data set composed of a plurality of fragment data that are the division data and the redundant data; and a distribution storage controlling means that distributes and stores the fragment data into the respective storing means. The distribution storage controlling means stores the fragment data composing the data set in same positions within storage regions formed in the respective storing means, respectively. | 2011-11-03 |
| 20110271051 | ARRAY TYPE DISK DEVICE, AND CONTROL METHOD FOR ARRAY TYPE DISK DEVICE - For the purpose of reducing the time for information processing in an array type disk device provided with a plurality of optical disk devices, when a beginning address is notified from any one of the optical disk devices to a main control device of the array type disk device, the main control device determines the beginning address notified first as a writing start address, without waiting for a notification of a beginning address from any other optical disk devices. Then, the main control device notifies the determined writing start address to the respective optical disk devices. Accordingly, even if search times for the writing start address are different among the optical disk devices, all the optical disk devices can start the writing of information based on which optical disk device has most quickly notified the beginning address. | 2011-11-03 |
| 20110271052 | RAID SYSTEM INCLUDING SEMICONDUCTOR STORAGE UNIT AND CONTROL METHOD OF THE SAME - A RAID system to transfer data to and from host equipment includes a semiconductor storage unit, a semiconductor-memory selector, and a memory controller. The semiconductor storage unit includes two or more semiconductor memories, a mounting board, and solder joints. The semiconductor memories are mounted on the mounting board. The solder joints are between the semiconductor memories and the mounting board. The semiconductor-memory selector selects a combination of the semiconductor memories to dispersively record the data in the semiconductor storage unit. The memory controller accesses the combination in response to a request of the host equipment. In addition, the selector selects the combination so that mechanical loads received by the semiconductor memories are averaged. | 2011-11-03 |
| 20110271053 | MOBILE DATA MEMORY WITH AUTOMATIC DELETE FUNCTION - The invention relates to a mobile data memory ( | 2011-11-03 |
| 20110271054 | Mobile Network Access Device, System and Method - A mobile network access device, system and method are disclosed. The method includes sending data or a command to a storing unit or a baseband processing unit according to a logical address in a Secure Digital (SD) command, where the SD command is a result of converting a Small Computer System Interface (SCSI) Command Descriptor Block (CDB) after a terminal device encapsulates the received data or command into the SCSI CDB. In the embodiments of the present invention, the wireless Internet access function is integrated into an SD card. The mobile network access device determines to send the data or command to the baseband processing unit or storing unit according to the logical address in the SD command, which reduces the size of the mobile network access device and enables developers to design smaller terminal products. | 2011-11-03 |
| 20110271055 | SYSTEM AND METHOD FOR LOW-LATENCY DATA COMPRESSION/DECOMPRESSION - A compression technique includes storing respective fixed-size symbols for each of a plurality of words in a data block, e.g., a cache line, into a symbol portion of a compressed data block, e.g., a compressed cache line, where each of the symbols provides information about a corresponding one of the words in the data block. Up to a first plurality of data segments are stored in a data portion of the compressed data block, each data segment corresponds to a unique one of the symbols in the compressed data block and a unique one of the words in the cache line. Up to a second plurality of dictionary entries are stored in the data portion of the compressed cache line. The dictionary entries can correspond to multiple ones of the symbols. | 2011-11-03 |
| 20110271056 | MULTITHREADED CLUSTERED MICROARCHITECTURE WITH DYNAMIC BACK-END ASSIGNMENT - A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units. | 2011-11-03 |
| 20110271057 | CACHE ACCESS FILTERING FOR PROCESSORS WITHOUT SECONDARY MISS DETECTION - The disclosed embodiments provide a system that filters duplicate requests from an L | 2011-11-03 |
| 20110271058 | Method, system and apparatus for identifying a cache line - A method of identifying a cache line of a cache memory ( | 2011-11-03 |
| 20110271059 | REDUCING REMOTE READS OF MEMORY IN A HYBRID COMPUTING ENVIRONMENT - A hybrid computing environment in which the host computer allocates, in the shadow memory area of the host computer, a memory region for a packet to be written to the shared memory of an accelerator; writes packet data to the accelerator's shared memory in a memory region corresponding to the allocated memory region; inserts, in a next available element of the accelerator's descriptor array, a descriptor identifying the written packet data; increments the copy of the head pointer of the accelerator's descriptor array maintained on the host computer; and updates a copy of the head pointer of the accelerator's descriptor array maintained on the accelerator with the incremented copy. | 2011-11-03 |
| 20110271060 | Method And System For Lockless Interprocessor Communication - A computer readable storage medium storing a set of instructions executable by a processor. The set of instructions is operable to receive, from a first processor, a message to be sent to a second processor; store the message in a portion of a shared memory, the shared memory being shared by the first processor and the second processor; store, in an instruction list stored in a further portion of the shared memory, an instruction corresponding to the message; and prompt the second processor to read the message list. | 2011-11-03 |
| 20110271061 | STORAGE CONTROLLER AND STORAGE SUBSYSTEM - Some functions of multiple structural elements are integrated into a specific structural element and the specific structural element controls transmission/reception of signals to/from the respective structural elements. | 2011-11-03 |
| 20110271062 | INTEGRATED STORAGE CONTROLLER AND APPLIANCE METHOD AND SYSTEM - An integrated data center method and system combines a storage controller and one or more appliances onto a computer platform. Storage controller component executes on the hardware of a computer platform and has exclusive access to a first storage controller host bus adapter coupled to a storage shelf having one or more storage devices. The method and system provisions a virtualized instance of the hardware from the computer platform to deliver application services from an appliance component. The appliance component may share the processing resources from the computer platform through multiple different virtual machines. With respect to storage, aspects of the present invention exclusively associates an appliance host bus adapter from the computer platform to the appliance component. In addition, aspects of the present invention also provide control of the appliance host bus adapter to the appliance component passing through the virtualized instance of the hardware. To access the storage devices, the appliance host bus adapter and corresponding appliance component are coupled with a second storage controller host bus adapter associated with the storage controller component. Aspects of the present invention enable the access to the storage controller component and storage devices from each appliance host bus adapter. This enables applications associated with the appliance component to perform storage operations on the storage devices at a high throughput even though the applications are executing within a virtualized instance of the hardware. | 2011-11-03 |
| 20110271063 | SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT AND OUTPUT METHOD THEREOF - A semiconductor memory apparatus includes an input data bus inversion unit configured to determine whether or not to invert a plurality of input data depending upon levels of the plurality of input data, and generate a plurality of conversion data; data input lines configured to transmit the plurality of conversion data; a data recovery unit configured to receive the plurality of conversion data and generate a plurality of storage data; and a memory bank configured to store the plurality of storage data. | 2011-11-03 |
| 20110271064 | STORAGE DEVICE AND METHOD FOR ACCESSING THE SAME - The present invention provides a storage device, which includes: a storage medium including a data address table, the data address table recording addresses for data stored in the storage medium; and a control module for receiving an external operation instruction and determining whether the operation instruction is an acceptable instruction, wherein if the operation instruction is the acceptable instruction, the control module determines an operation address corresponding to the operation instruction according to the data address table and executes the operation instruction in the storage medium according to the determined operation address, and if the operation instruction is not the acceptable instruction, the control module rejects the operation instruction. | 2011-11-03 |
| 20110271065 | STORAGE SYSTEM FRONT END WITH PROTOCOL TRANSLATION - A storage system may include a first storage device and a protocol translator. The protocol translator may be programmed to receive a storage-access command formatted in a first protocol format. The protocol translator may also be programmed to translate the storage-access command into a second protocol format. The storage system may include a pseudo-target-module coupled to the protocol translator. The pseudo-target module may be programmed to send the command to the first storage device after the command is translated into the second protocol format. A virtualization engine may provide an interface to the first storage device, and the storage-access command may be sent to the first storage device through the virtualization engine. The pseudo-target module may be programmed to receive data from both storage-area-network devices and network-attached-storage devices. | 2011-11-03 |
| 20110271066 | STORAGE SYSTEM AND DATA MANAGEMENT METHOD - The present invention comprises a CHA | 2011-11-03 |
| 20110271067 | Efficient Cloud Network Attached Storage - Snapshots of data and metadata associated with the data are created. The snapshot of the data is separate from the snapshot of the associated metadata. The snapshot of metadata is maintained locally in a cloud network attached storage (NAS) and globally. The snapshot of data is maintained according to an accessibility metric. | 2011-11-03 |
| 20110271068 | METHOD AND APPARATUS FOR SYNCHRONIZING APPLICATIONS FOR DATA RECOVERY USING STORAGE BASED JOURNALING - Disclosed is a method to synchronize the state of an application and an application's objects with data stored on the storage system. The storage system provides API's to create special data, called a marker journal, and stores it on a journal volume. The marker contains application information, e.g. file name, operation on the file, timestamp, etc. Since the journal volume contains markers as well as any changed data in the chronological order, IO activities to the storage system and application activities can be synchronized. | 2011-11-03 |
| 20110271069 | DISMOUNTING A STORAGE VOLUME - In response to an instruction to dismount a storage volume, for example, an object in the storage volume is identified and a handle that references the object is closed. Once an exclusive lock on the storage volume is acquired, the storage volume can be dismounted. The storage volume can then remounted. | 2011-11-03 |
| 20110271070 | MEMORY USAGE SCANNING - A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption. | 2011-11-03 |
| 20110271071 | STORAGE APPARATUS AND HIERARCHICAL DATA MANAGEMENT METHOD FOR STORAGE APPARATUS - Proposed are a storage apparatus and hierarchical data management method for promoting the effective usage of memory apparatuses while suppressing maintenance-related costs and work. The storage apparatus comprises a plurality of memory apparatuses of a plurality of types, and a control unit for executing required data migration by monitoring an access frequency to each of the unit areas of the virtual volume and by controlling the corresponding memory apparatuses so that the storage area provided by the memory apparatus with a superior response performance is allocated to unit areas for which the access frequency is higher. The control unit controls the corresponding memory apparatuses so that when data is migrated from a first storage area, provided by a first memory apparatus which can be rewritten a limited number of times, to a second storage area provided by another second memory apparatus, the data is migrated to the second storage area without being deleted from the first storage area, manages updated parts of the data migrated from the first storage area to the second storage area after the data is migrated to the second storage area, and controls the corresponding memory apparatuses so that, when data which has been migrated from the first storage area to the second storage area is restored from the second storage area to the first storage area, the corresponding data still remaining in the first storage area is overwritten with the updated parts of the data which are updated after being migrated to the second storage area. | 2011-11-03 |
| 20110271072 | DATA MIGRATION METHOD AND INFORMATION PROCESSING SYSTEM - A volume group comprising one or a plurality of logical volumes is set. A coexistence avoidance volume group having different array groups can be set to the volume group. Upon execution of preset volume search criteria, a logical volume is specified by carrying out a search in which are excluded array groups to which logical volumes in the coexistence avoidance volume belong. | 2011-11-03 |
| 20110271073 | COMPUTER SYSTEM AND CONTROL METHOD OF THE SAME - Summary Problem | 2011-11-03 |
| 20110271074 | Method for memory management to reduce memory fragments - Provided is a method and apparatus for managing a memory. The method and apparatus may allocate or release a memory larger than N bytes through a heap; and the performance of allocating or releasing a memory smaller than or equal to N bytes through a fragless module, wherein the memory smaller than or equal to N bytes is allocated or released at a first region of a memory pool without passing through the heap. | 2011-11-03 |
| 20110271075 | SYSTEM ON CHIP INCLUDING UNIFIED INPUT/OUTPUT MEMORY MANAGEMENT UNIT - A system on chip, includes a memory, a bus, a plurality of intellectual property (IP) blocks, and a unified input/output memory management unit (IOMMU) connected between the memory and the bus and configured to determine whether to perform address conversion for a transaction transferred from the bus based on transaction information. | 2011-11-03 |
| 20110271076 | Optimizing Task Management - An electronic device includes a processing component and a task manager. The processing component is configurable for one of a single-core processing mode and a multi-core processing mode. The task manager determines a number of tasks running on the electronic device. The processor is configured to one of the single-core processing mode and the multi-core processing mode as a function of the number of tasks. | 2011-11-03 |
| 20110271077 | PROCESSOR AND DATA COLLECTION METHOD - A processor has a plurality of PEs (processing elements) that operate in parallel based on operation commands and an information collection unit that collects the data of the plurality of PEs, wherein each of the plurality of PEs holds data and a condition flag, supplies the data and the condition flag to the information collection unit upon receiving an operation command, and upon receiving an update request for updating the condition flag, updates the condition flag in accordance with the update request that was received; and the information collection unit, upon receiving the data and the condition flags, selects one PE based on a predetermined order of priority from among the PEs for which the received condition flags are active and both supplies the data of the selected PE as collection result data and supplies an update request for updating the condition flag of the PE that was selected. | 2011-11-03 |
| 20110271078 | PROCESSOR STRUCTURE OF INTEGRATED CIRCUIT - A processor structure of integrated circuit is provided. The processor structure comprises at least one processor capable of configuring an operation component and at least one processor capable of configuring a storage component. The processor capable of configuring an operation component or the processor capable of configuring a storage component cascades the processor capable of configuring an operation component and the processor capable of configuring a storage component. The processor capable of configuring an operation component includes a first arithmetic data control component and at least one operation component, and the first arithmetic data control component executes a configuration instruction to configure the operation function of the operation component. The processor capable of configuring a storage component includes a second arithmetic data control component and at least one memory component, and the second arithmetic data control component executes a configuration instruction to configure the storage function of the memory component. | 2011-11-03 |
| 20110271079 | MULTIPLE-CORE PROCESSOR SUPPORTING MULTIPLE INSTRUCTION SET ARCHITECTURES - A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. | 2011-11-03 |
| 20110271080 | COMPUTER SYSTEM AND METHOD OF ADAPTING A COMPUTER SYSTEM TO SUPPORT A REGISTER WINDOW ARCHITECTURE - A target computing system | 2011-11-03 |
| 20110271081 | MULTIMEDIA PLATFORM - A multimedia platform is discussed, which includes a first stacking unit including a first substrate and a multimedia processor, wherein the first substrate and the multimedia processor are stacked on the first stacking unit, a pattern and a via hole are formed on the first substrate, and the multimedia processor is mounted on top of the first substrate; a second stacking unit including a second substrate and a plurality of storage devices, wherein the second substrate and the plurality of storage devices are stacked on the second stacking unit, a pattern and a via hole being formed on the second substrate, and the plurality of storage devices are mounted on top of the second substrate; and at least one solder ball arranged on the first stacking unit, the at least one solder ball allowing the first substrate to be coupled to the second substrate. | 2011-11-03 |
| 20110271082 | PERFORMING ACTIONS ON FRAME ENTRIES IN RESPONSE TO RECEIVING BULK INSTRUCTION - Various example embodiments are disclosed. According to an example embodiment, a switch may comprise an instruction decode stage and a lookup stage. The instruction decode stage may be configured to receive a bulk instruction identifying an action to perform on frame entries of the lookup stage, and in response to receiving the bulk instruction, send, to the lookup stage, at least first and second frame entry instructions, each of the first and second frame entry instructions identifying the action and identifying a unique frame entry in the lookup stage upon which to perform the action. The lookup stage may be configured to receive the first and second frame entry instructions from the instruction decode stage, and in response to receiving each of the first and second frame entry instructions, perform the identified action on the frame entry identified by the respective frame entry instruction. | 2011-11-03 |
| 20110271083 | MICROPROCESSOR ARCHITECTURE AND METHOD OF INSTRUCTION DECODING - A microprocessor architecture comprises an instruction decoding network for decoding in a first mode partially suppressed opcodes of a sequence of instructions, the opcodes comprising a first part containing parameters being invariant for each opcode of the sequence and a second part comprising a flag indicating an end of the sequence, the first part being suppressed for all opcodes of the sequence except a first opcode of the sequence. Further, a method of instruction decoding in a microprocessor architecture comprising an instruction decoding network for decoding in a first mode partially suppressed opcodes of a sequence of instructions, and in a second mode uncompressed instructions comprises decoding an opcode of an instruction in the second mode when the instruction is not compressible; and decoding an opcode of an instruction in the first mode when the instruction is compressible. | 2011-11-03 |
| 20110271084 | Information processing system and information processing method - A disclosed information processing system includes a receiving node and a storing node, the receiving node includes an order information adding unit that adds first order information to operation instructions included in an operation instruction sequence, the first order information indicating an order among the operation instruction sequences and an operation instruction transmission unit that transmits the one or more operation instructions to the storing node, the storing node includes an operation instruction execution unit that executes the operation instructions. Further, upon a receipt of a second operation instruction having the first order information indicating that the second operation instruction is earlier than the one or more first operation instructions, which was already executed, in the first order relationship, the storing node re-executes the first operation instruction after the second operation instruction is executed. | 2011-11-03 |
| 20110271085 | PARSING-ENHACEMENT FACILITY - An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure. | 2011-11-03 |
| 20110271086 | SYSTEMS AND METHODS TO CONTROL MULTIPLE PERIPHERALS WITH A SINGLE-PERIPHERAL APPLICATION CODE - Methods and apparatus are provided for enhancing the BIOS of a hardware peripheral device to manage multiple peripheral devices simultaneously without modifying the application software of the peripheral device. The apparatus comprises a logic control unit and a memory in communication with the logic control unit. The memory is partitioned into a plurality of ranges, each range comprising one or more blocks of memory, one range being associated with each instance of the peripheral application and one range being reserved for storage of a data pointer related to each peripheral application of the plurality. The logic control unit is configured to operate multiple instances of the control application by duplicating one instance of the peripheral application for each peripheral device of the plurality and partitioning a memory device into partitions comprising one or more blocks of memory, one partition being associated with each instance of the peripheral application. The method then reserves a range of memory addresses for storage of a data pointer related to each peripheral device of the plurality, and initializes each of the plurality of peripheral devices. | 2011-11-03 |
| 20110271087 | EMBEDDING PROCESS IDENTIFICATION INFORMATION IN A PATHNAME TO INDICATE PROCESS STATUS - The method determines whether a particular process is currently executing or not executing. The method embeds process identification information and a process name in a process pathname that binds to a socket. The method creates a socket and binds to the socket a process name and associated process identifier if that process is currently executing. A status file may store the socket pathnames of those processes currently executing. A socket pathname appears in the status file if a corresponding process is executing, but does not appear in the status file if the process is not executing. To determine if a particular process is currently executing, the method tests the status file to determine if the status file contains a match for the socket pathname associated with the particular process under test. The presence of a match for the socket pathname in the status file indicates that the particular process associated therewith is currently executing. | 2011-11-03 |
| 20110271088 | OPERATING SYSTEM CONTEXT SWITCHING - A technique for quickly switching between a first operating system (OS) and a second OS involves deactivating the first OS and booting the second OS from memory. The technique can include inserting a context switching layer between the first OS and a hardware layer to facilitate context switching. It may be desirable to allocate memory for the second OS and preserve state of the first OS before deactivating the first OS and booting the second OS from memory. | 2011-11-03 |
| 20110271089 | Server Apparatus and Startup Control Method - According to one embodiment, a server apparatus includes a communication processor, a database and a controller. The communication processor starts up based on a startup program recorded in a processing memory, and performs a communication processing based on a service program recorded in the processing memory, after startup. The database stores the startup program in association with a first directory for specifying a first memory area, and stores the service program in association with a second directory for specifying a second memory area different from the first directory, The controller refers to the second directory stored in the database after the startup program starts, and reads the service program from the database based on the referred result, and further, records the read program in second memory area of the processing memory. | 2011-11-03 |
| 20110271090 | Providing a secure execution mode in a pre-boot environment - In one embodiment, the present invention includes a method to establish a secure pre-boot environment in a computer system; and perform at least one secure operation in the secure environment. In one embodiment, the secure operation may be storage of a secret in the secure pre-boot environment. | 2011-11-03 |
| 20110271091 | INTELLIGENT ROLLING UPGRADE FOR DATA STORAGE SYSTEMS - Various method, system, and computer program product embodiments for facilitating upgrades in a computing storage environment are provided. In one such embodiment, one of an available plurality of rolling upgrade policies registering at least one selectable upgrade parameter for an upgrade window is selected. A node down tolerance factor is set for at least one node in the computing storage environment. The node down tolerance factor specifies a percentage of elements of the at least one node taken offline to apply the selected one of the available plurality of rolling upgrade policies during the upgrade window. | 2011-11-03 |
| 20110271092 | METHODS & APPARATUSES FOR A PROJECTED PVR EXPERIENCE - Exemplary embodiments of methods and apparatuses to project personal video recorder (“PVR”) trick mode operations over a network are described. A first content stream may be at a first speed. A request to access the first content stream at a second speed can be received. A second content stream can be generated based on a second speed. The second content stream can be send over a network to be rendered at the first speed by a client device. One or more anchor frames in the first content stream are selected. The second content stream is generated based on the one or more anchor frames. One or more dummy frames can be inserted into the second content stream. Indexing information can be generated to create a second content stream to send over the network. | 2011-11-03 |
| 20110271093 | SECURE DATA EXCHANGE TECHNIQUE - Techniques utilizing common encryption approaches for data from multiple parties enable those parties to discover information that is held in common by the parties without disclosing to any party information that is not held in common by the parties. Encrypted information for each party can be compared to determine which encrypted values match, and those encrypted values can be returned to any of the parties such that a party can determine which corresponding data the parties have in common without having access to any other data of any other parties. | 2011-11-03 |
| 20110271094 | PEER-TO-PEER IDENTITY MANAGEMENT INTERFACES AND METHODS - Peer-to-peer (P2P) application programming interfaces (APIs) that allow an application to create, import, export, manage, enumerate, and delete P2P identities are presented. Further, the management of group identity information is provided. APIs abstract away from low level credential and cryptographic functions required to create and manage P2P identities. This management includes retrieval and setting of a friendly name, generation of a cryptographic public/private key pair, retrieval of security information in the form of an XML fragment, and creation of a new name based on an existing identity. | 2011-11-03 |
| 20110271095 | Embedded Communication of Link Information - A method of processing documents is described. The method includes the operation of receiving a document in a search engine crawler. The document includes an embedded first link tag. The first link tag includes one or more information pairs. A respective information pair includes a respective parameter and a corresponding value. The parameters in the one or more information pairs may correspond to content at one or more content locations or one or more document locations. The method also includes selecting a method of processing content associated with the first link tag in accordance with one or more of the information pairs. | 2011-11-03 |
| 20110271096 | Loosely-Coupled Encryption Functionality for Operating Systems - Described are computer-based methods and apparatuses, including computer program products, for loosely-coupled encryption functionality for operating systems. A data packet is processed through one or more internet protocol stack layers to generate a processed data packet. Encryption information is determined that includes parameters for encrypting and decrypting data packets transmitted between the first computing device and the remote computer. A message comprising data indicative of the encryption information is transmitted to a second computing device, wherein an operating system being executed is unaware of a security nature of the transmission. A bypass encryption routine is executed to generate a unencrypted data packet, wherein the bypass encryption routine does not encrypt the processed data packet. The unencrypted data packet is transmitted to the second computing device. The unencrypted data packet is encrypted based on the message transmitted from the first computing device to generate an encrypted data packet. | 2011-11-03 |
| 20110271097 | Loosely-Coupled Encryption Functionality for Operating Systems - Described are computer-based methods and apparatuses, including computer program products, for loosely-coupled encryption functionality for operating systems. A data packet is processed through one or more internet protocol stack layers to generate a processed data packet. Modified encryption information is determined that does not comprise a desired security policy for the data packet and comprises null parameter(s) and is based on encryption information that comprises the desired security policy. A message comprising data indicative of the encryption information is transmitted. An operating system is unaware of a security nature of the transmission. A null-encryption routine is executed to generate an unencrypted data packet, wherein the null-encryption routine does not encrypt the processed data packet. The unencrypted data packet is transmitted to the second computing device. The unencrypted data packet is encrypted based on the message transmitted from the first computing device to generate an encrypted data packet. | 2011-11-03 |
| 20110271098 | SYSTEM AND METHOD FOR SECURING DATA THROUGH A PDA PORTAL - Consumers may utilize computing devices to assist in the purchase and/or loyalty process, and in particular, the consumer may utilize a PDA to facilitate the purchase and/or loyalty process. During the purchase and/or loyalty process, the consumer may need to insure that any content downloaded or used in association with the PDA is secure in how it is collected, assembled, and delivered to the PDA device. This system and method secures the data from its source to when it is actually viewed or used by the authorized user. The exemplary system and method may establish a PDA portal link to the web site for collecting specified information for a user and transmitting the information to the remote device. To receive the information, the PDA contacts the portal and establishes a connection, authenticates itself to the network and allows the user to complete secured transactions or transmissions over the network. | 2011-11-03 |
| 20110271099 | AUTHENTICATION SERVER AND METHOD FOR GRANTING TOKENS - An authentication server and method are provided for generating tokens for use by a mobile electronic device for accessing a service. Communications between the device and the authentication server are through a relay. A memory stores a secret shared with a service server from which the service is provided. A processor is configured to generate the token using the shared secret and based on a reliance on the relay to ensure that the device has authorization to access the service. One or more computer readable medium having computer readable instructions stored thereon that cause the device to obtain proof of authorization to access the service is also provided. The instructions implement a method comprising: outputting via a wireless connection to a relay a request addressed to an authentication server for a token and receiving the token from the authentication server via the relay. | 2011-11-03 |
| 20110271100 | UNATTENDED CODE UPDATE OF STORAGE FACILITY - Various embodiments for providing an update to at least one storage facility in a computing storage environment are provided. In one embodiment, a security verification is performed on the update via a certificate authentication mechanism to confirm a validity of the update. Subsequent to confirming the validity of the update, a safety verification on the update is performed to confirm a suitability of the update to the at least one storage facility. If the security and safety verifications are validated, the update is provided and installed in the at least one storage facility. | 2011-11-03 |
| 20110271101 | Method, system and terminal device for realizing locking network by terminal device - A method, system and terminal device implement locking a terminal device onto a network. This method comprises a procedure of locking onto the network during accessing the network, namely performing locking-onto-network configuration verification in a network accessing authentication process, and if the locking-onto-network configuration verification is successful, allowing for verification for an authentication certificate, or else refusing the terminal device of access to the network. The method, system and terminal device in the present invention perform locking-onto-network configuration verification when performing authentication, and the terminal device and server uniformly configure a locking-onto-network character string, and thus it has a great security. Besides, the present invention also can implement unlocking and locking again after accessing the network via an air interface management in the OTA way, and thus it has high flexibility and applicability, and can satisfy the requirements of 4G networks such as the WiMAX network and LTE network. | 2011-11-03 |
| 20110271102 | METHOD AND APPARATUS FOR INGRESS FILTERING USING SECURITY GROUP INFORMATION - A method and apparatus for ingress filtering using security group information are disclosed. The method includes performing access control processing on a packet and sending access control information to an ingress node of the packet in response to the access control processing. The access control information includes security group information and an address of a network node. The security group information identifies a security group. The network node is a member of the security group and is a destination of the packet. | 2011-11-03 |
| 20110271103 | Generic File Protection Format - A file may contain an unencrypted and an encrypted portion. The unencrypted portion may contain a layout section that may point to a published license, metadata, and a contents section, where the contents section is in the encrypted portion. The encrypted portion may contain the contents section which may act as a directory for one or more included files that may be compressed and stored in the encrypted portion. When the file is opened by a receiver, the receiver may read the published license and communicate with a security server to establish access rights and receive at least one key for decrypting at least a portion of the encrypted portion of the file. The receiver may then gain access to the included files. | 2011-11-03 |
| 20110271104 | Security device and building block functions - A method and system of securing content is described, the method including establishing communication between a secure module source and a content rendering device, loading a dynamically generated pseudo-unique secure module to the content rendering device from the secure module source, establishing communication between the secure module source and the dynamically generated pseudo-unique secure module, and transferring a decryption key from the secure module source to the dynamically generated pseudo-unique secure module, thereby enabling decryption of encrypted content, the encrypted content being encrypted according to the decryption key. Related methods and apparatus are also described. | 2011-11-03 |
| 20110271105 | METHOD AND APPARATUS FOR IMPLEMENTING A NOVEL ONE-WAY HASH FUNCTION ON HIGHLY CONSTRAINED DEVICES SUCH AS RFID TAGS - A method and apparatus for implementing a novel one-way hash function with provable security properties for authentication and non-authentication applications on highly constrained devices, with particular application to RFID tags. | 2011-11-03 |
| 20110271106 | Communication Channel of a Device - A method including transferring a device ID through a first communication channel between a device and a transaction device, configuring the device to send secured information in response to receiving a transaction request and sending user information to a service provider through a second communication channel in response to receiving a request to authenticate the secured information. | 2011-11-03 |
| 20110271107 | System and Method for Comparing Private Data - The present disclosure is directed to systems and methods including accessing a first private value, generating a first intermediate value based on the first private value, receiving a second intermediate value that is based on a second private value, generating a first comparison value based on the second intermediate value, receiving over the network a second comparison value that is based on the first intermediate value, comparing the first comparison value and the second comparison value to generate a result, and displaying the result, the result indicating that the first private is greater than the second private value when the first comparison value is less than the second comparison value, and the result indicating that the first private value is less than or equal to the second private value when the first comparison value is greater than the second comparison value. | 2011-11-03 |
| 20110271108 | METHOD AND SYSTEM FOR SECURE EXCHANGE AND USE OF ELECTRONIC BUSINESS CARDS - Some embodiments provide a system that facilitates the use of an electronic business card. During operation, the system obtains one or more permissions for the electronic business card. Next, the system manages use of the electronic business card by a recipient of the electronic business card based on the permissions. | 2011-11-03 |
| 20110271109 | SYSTEMS AND METHODS OF REMOTE DEVICE AUTHENTICATION - Methods and systems are provided herein that allow for a first device to remotely authenticate a particular software or hardware feature of a second device with which the first device is communicating. More specifically, the teachings herein allow for a server to verify that a particular application running on a client machine is an authentic application, as opposed to an application developed by a rogue element disguising itself as a authentic application. In a broader sense the teachings herein allow a server to initiate a sequence of instructions on the remote machine, and for which assurance is needed that the intended instructions were executed on the remote machine. Additionally methods and systems are provided that generate and update client registration certificates that are tightly bound to both client and server. | 2011-11-03 |
| 20110271110 | KEY MANAGEMENT DEVICE, SYSTEM AND METHOD HAVING A REKEY MECHANISM - According to some embodiments, a key management apparatus for deploying in a smart grid system adapted to receive metering data from smart meters connected to at least one relay via a network, includes: a key control mechanism that derives a key array of individual purpose specific keys from one master key such that the purpose specific key in the key array are each independent cryptographic keys for each specific usage in an application or for each application if there is only one specific usage in an application. | 2011-11-03 |
| 20110271111 | Systems and Methods For Providing Security to Different Functions - Methods and systems are provided that use smartcards, such as subscriber identity module (SIM) cards to provide secure functions for a mobile client. One embodiment of the invention provides a mobile communication network system that includes a mobile network, a mobile terminal, a server coupled to the mobile terminal via the mobile network, and a subscriber identity module (SIM) card coupled to the mobile terminal. The SIM card includes a first key and a second key. The first key is used to authenticate an intended user of the mobile terminal to the mobile network. Upon successful authentication of the intended user to the mobile network, the mobile terminal downloads a function offered from the server through the mobile network. The second key is then used by the mobile terminal to authenticate the intended user to the downloaded function so that the intended user can utilize the function. | 2011-11-03 |
| 20110271112 | METHODS, APPARATUSES, AND COMPUTER PROGRAM PRODUCTS FOR FACILITATING RANDOMIZED PORT ALLOCATION - A method, apparatus, and computer program product are provided for facilitating randomized port allocation. An apparatus may include a processor configured to receive a port allocation message from a network management entity. The port allocation message may comprise an encryption key, an initial input value, and a value indicating a number of ports allocated to the apparatus for communication on a network. The processor may be further configured to calculate at least one port allocated to the apparatus with an encryption function based at least in part upon the encryption key and initial input value. Corresponding methods and computer program products are also provided. | 2011-11-03 |
| 20110271113 | SECURE STREAMING CONTAINER - A system and method for securely streaming encrypted digital media content out of a digital container to a user's media player. This streaming occurs after the digital container has been delivered to the user's machine and after the user has been authorized to access the encrypted content. The user's operating system and media player treat the data stream as if it were a being delivered over the Internet (or other network) from a streaming web server. However, no Internet connection is required after the container has been delivered to the user and the data stream suffers no quality loss due to network traffic or web server access problems. In this process of the invention, the encrypted content files are decrypted and fed to the user's media player in real time and are never written to the user's hard drive or storage device. This process makes unauthorized copying of the digital content contained in the digital container virtually impossible. | 2011-11-03 |
| 20110271114 | SYSTEM AND METHOD FOR AUTHENTICATING REMOTE SERVER ACCESS - A system and method for providing secure authentication for website access or other secure transaction. In one embodiment, when a user accesses a website, the web server identifies the user, and sends an authentication request to the user's mobile device. The mobile device receives the authentication requests and sends back authentication key to the web server. Upon verifying the authentication key, the web server grants access to the user. | 2011-11-03 |
| 20110271115 | CERTIFICATE INFORMATION STORAGE SYSTEM AND METHOD - A system and method of storing in a computer device digital certificate data from a digital certificate are provided. When a digital certificate is received at the computer device, it is determined whether the digital certificate data in the digital certificate is stored in a first memory store in the computer device. The digital certificate data is stored in the first memory store upon determining that the digital certificate data is not stored in the first memory store. | 2011-11-03 |
| 20110271116 | SET OF METADATA FOR ASSOCIATION WITH A COMPOSITE MEDIA ITEM AND TOOL FOR CREATING SUCH SET OF METADATA - A set of metadata for association with the composite media item and a tool for creating a composite media item with an associated set metadata. In one embodiment, the tool comprises a component for extracting a portion of a first media item having first metadata and for extracting a portion of a second media item having second metadata, a component for combining the first portion and the second portion to form a composite media item, and a component for analyzing the first metadata and the second metadata to extract portions of the first and second metadata to form a new set of metadata for association with the composite media item. In one embodiment, the new metadata is a data container. | 2011-11-03 |
| 20110271117 | USER EQUIPMENT (UE), HOME AGENT NODE (HA), METHODS, AND TELECOMMUNICATIONS SYSTEM FOR HOME NETWORK PREFIX (HNP) ASSIGNMENT - A User Equipment (UE), Home Agent node (HA), methods, and a telecommunications system are provided for use during negotiation of IP security associations, such as during an Internet Key Exchange (IKE) procedure, between the UE and the HA. The UE sends to the HA an authentication request comprising an indicator relative to a Home Network Prefix (HNP) to be assigned to the UE. Based on the indicator, the HA assigns a new HNP or re-assigns the HNP already assigned, and sends back a response comprising the assigned HNP. If the UE performs a handover to another access network or establishes a simultaneous binding to the other access network, the UE sends its own HNP in the authentication request thus asking the HA to re-assign the same HNP for the new connection being established. If the UE makes an initial access with a network, the indicator may be left blank, asking for the assignment of a new HNP for the UE. | 2011-11-03 |
| 20110271118 | PASSWORD GENERATION METHODS AND SYSTEMS - Password generation and extraction is described. In one aspect, a user inputs multiple characters, including a user password, variable characters, and multiple terminator characters. Locations of the terminator characters are identified and used to extract the user password from the multiple characters input by the user. | 2011-11-03 |
| 20110271119 | Secure Data Storage and Transfer for Portable Data Storage Devices - Embodiments of system and method for protection of data in a portable data storage device are provided. In one aspect, a portable data storage device includes a first portable storage identification (PSID) parameter unique to the portable data storage device, one or more data storage media in which the first PSID parameter is stored, and control logic coupled to the one or more data storage media. The one or more data storage media include a data file section to store therein a data file, which includes data and a rights object. The rights object contains a second PSID parameter. The control logic controls access to the one or more data storage media by a user of the portable data storage device. The control logic determines whether or not the first PSID parameter and the second PSID parameter are equal and, if the first PSID parameter and the second PSID parameter are equal, causes the data in the data file to be provided to the user in response to a request for the data from the user. | 2011-11-03 |
| 20110271120 | Method and System for Verifying the Identity of an Individual by Employing Biometric Data Features Associated with the Individual - The invention relates to a method for verifying the identity of an individual by employing biometric data features associated with the individual, which method provides privacy of said biometric data features, comprising at least the steps of: a) for enrolment purposes deriving a first biometric template from at least a first set of first biometric data features associated with said individual, and b) for identity verifying purposes deriving a further biometric template from at least a further set of said first biometric data features associated with said individual, and c) comparing said further biometric template with said first biometric template. The invention also relates to a system for verifying the identity of an individual by employing biometric data features associated with the individual, which system at least comprises: an enrolment means and a verifying means, wherein said enrolment means are arranged in deriving a first biometric template data, said first biometric template data being secret and associated with a first set of first biometric data features of said individual, and in receiving a further set of first biometric data features of said individual, and in deriving a further biometric template data associated with said further set of first biometric data, and wherein said verifying means are arranged in comparing the first biometric template data with the further biometric template data to check for correspondence, wherein the identity of the individual is verified if correspondence exists. | 2011-11-03 |
| 20110271121 | DATA PROCESSING APPARATUS, DATA PROCESSING SYSTEM, AND METHOD FOR CONTROLLING THE SAME - A data processing apparatus acquires content, generates an encryption key by using an initial value written in an unwritten memory block in a write-once recording medium, encrypts the content by using the encryption key, and writes to the write-once recording medium the encrypted content and an address table for identifying the memory block storing the initial value used for generating the encryption key. | 2011-11-03 |
| 20110271122 | Configuring Cable Lines to Provide Data and Power - A method is provided for an upstream device to configure a plurality of lines in a cable. The method comprises the upstream device placing a first voltage on a first one of the lines traditionally specified to supply power; the upstream device grounding a second one of the lines traditionally specified to be a ground line; and the upstream device placing on a third one of the lines traditionally specified to convey data a second voltage for supplying power. | 2011-11-03 |
| 20110271123 | POWER CONTROL SYSTEM OF A BASEBOARD MANAGEMENT CONTROLLER AND METHOD THEREOF - A method controls power of a baseboard management controller (BMC). A power control signal of the BMC is generated for powering up or powering down the BMC. An enabling signal is generated according to the power control signal. A power supply device is directed to output one or more voltages to the BMC. | 2011-11-03 |
| 20110271124 | PROCESSOR PERFORMANCE STATE OPTIMIZATION - A processor performance state optimization includes a system to change a performance state of a processor. In an embodiment, the system to change a performance state of the processor includes a processor and a step logic sub-system operatively coupled with the processor and is operable to communicate a performance state change request to the processor. A core voltage regulator is operatively coupled with the step logic sub-system. An end performance state sub-system to determine a desired end performance state is coupled with the step logic sub-system. And, an enable sub-state transition sub-system to enable sub-state transitions is coupled with the step logic sub-system. | 2011-11-03 |
| 20110271125 | ETHERNET POWERED COMPUTING DEVICE AND SYSTEM - Apparatus and systems provide processing capabilities while utilizing power received via an Ethernet. A computing device has an Ethernet connector for receiving power and data, internal power supply circuitry for extracting power from the Ethernet connector, and a Central Processing Unit (CPU) for receiving the power. A housing may encompass the components of the computing device and be configured for installation in an electrical wall box. The housing may include a display or connectors for peripherals. A system includes at least two computing devices. Each device has an Ethernet connector for receiving power and communicating with other devices and are installed within a housing within an electrical wall box. One device has a display for receiving user input instructions for transmittal to another device, while another device has a peripheral connector for controlling a peripheral according to the instructions. | 2011-11-03 |
| 20110271126 | Data processing system - A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units. | 2011-11-03 |
| 20110271127 | METHOD FOR MANAGING ENERGY CONSUMPTION FOR MULTIPROCESSOR SYSTEMS - The invention relates to a method for the on-line management of energy consumption for multiprocessor systems, the method executing at least one application according to a chart of tasks, wherein the method includes, for each application: a first phase for the off-line characterization of the variation of the potential rate of parallelism of execution of the tasks as a function of time, this characterization being based on the worst-case task execution times; and a second phase for the on-line detection and exploitation of the inactivity intervals and of the potential time excesses. A DPM technique makes it possible to determine the duration of the inactivity interval during which a processor may remain inactive according to the potential rate of parallelism characterized in the worst case. | 2011-11-03 |
| 20110271128 | STATE TRANSITIONING CLOCK GATING - In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements, the use of STG may be used to reduce dynamic power consumption. | 2011-11-03 |
| 20110271129 | NETWORK-ATTACHED DISPLAY DEVICE AS AN ATTENDEE IN AN ONLINE COLLABORATIVE COMPUTING SESSION - In one embodiment, a network-attached display device (e.g., projector) may join an online collaborative computing session as an attendee. The display device may then receive data for the online collaborative computing session as an attendee over the computer network. As such, the display device may render images associated with being an attendee of the online collaborative computing session from the received data, and then visually display the images associated with the online collaborative computing session. | 2011-11-03 |
| 20110271130 | CIRCUIT CONFIGURATION HAVING A TRANSCEIVER CIRCUIT FOR A BUS SYSTEM AND NODES FOR A BUS SYSTEM - A circuit configuration for a node of a bus system includes a transceiver circuit and a control circuit connected to the transceiver circuit. The transceiver circuit has an idle mode, in which it has a reduced power consumption in comparison with at least one operating mode, and the transceiver circuit is supplied with power in the at least one operating mode via a power supply unit integrated into the transceiver circuit. The control circuit is connected to the power supply unit to supply the control circuit with power in the idle mode, and the circuit configuration has a controllable voltage regulator which is coupled to the transceiver circuit in such a way that the voltage regulator is deactivated in the idle mode to reduce the power consumption and activated in the operating mode to supply power to the transceiver circuit and the control circuit. | 2011-11-03 |
| 20110271131 | COMPUTER SYSTEM POWERED-OFF STATE AUXILIARY POWER RAIL CONTROL - Computer system powered-off state auxiliary power rail control. At least some of the illustrative embodiments are systems configured to have: a first powered-off state in which the main output power signal is deactivated within the power supply and the auxiliary power output signal is active and coupled to an auxiliary power rail of the printed circuit board; and a second powered-off state in which the main power output signal is deactivated and the auxiliary power output signal is active and decoupled from the auxiliary power rail of the printed circuit board. | 2011-11-03 |
| 20110271132 | METHOD AND DEVICE FOR CONTROLLING THE AWAKING OF FACILITIES BELONGING TO AT LEAST ONE MULTIPLEXED NETWORK, BY COUNTING UNTIMELY WAKE-UPS - A device (D) is dedicated to the control of the waking of facilities (OE | 2011-11-03 |
| 20110271133 | ADDRESS OUTPUT TIMING CONTROL CIRCUIT OF SEMICONDUCTOR APPARATUS - Various embodiments of a control circuit for controlling an address output timing of a semiconductor device are disclosed. In one exemplary embodiment, the circuit may include: a timing signal generation unit configured to decode operation specification information of a semiconductor device and generate a timing signal by delaying a read command or a write command based on a decoding result of the operation specification information; a storage control signal generation unit configured to generate a storage control signal in response to the read command or the write command; an output control signal generation unit configured to generate an output control signal in response to the timing signal; and a storage/output unit configured to store an address in response to the storage control signal, and output the stored address as a timing-adjusted address in response to the output control signal. | 2011-11-03 |
