44th week of 2011 patent applcation highlights part 14 |
Patent application number | Title | Published |
20110266535 | ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment of the present invention, an organic electroluminescent display device includes transistors formed on a substrate, an insulating layer on the transistors, a lower electrode formed on the insulating layer and coupled to a source or a drain of each of the transistors, a bank layer having openings to expose a part of the lower electrode, a bus electrode formed on the bank layer, an organic light-emitting layer formed to cover the lower electrode, the bank layer, and the bus electrode and patterned to expose at least a part of the bus electrode, and an upper electrode formed on the organic light-emitting layer and configured to come into contact with the exposed bus electrode. | 2011-11-03 |
20110266536 | Solution Composition for Manufacturing Metal Oxide Semiconductor - Provided is a solution composition for manufacturing a metal oxide semiconductor including aluminum salts, metal acetylacetonate and a solvent. In addition, provided is a method for manufacturing a metal oxide semiconductor, including: manufacturing of a metal oxide semiconductor by performing heat treatment after coating a solution composition for manufacturing the metal oxide semiconductor above a substrate. In addition, provided is a thin film transistor, including: a gate substrate; a metal oxide semiconductor manufactured to be overlapped with the gate substrate; a source electrode electrically connected to the metal oxide semiconductor; and a drain electrode that is electrically connected to the metal oxide semiconductor and faces the source electrode. | 2011-11-03 |
20110266537 | METHODS OF FABRICATING METAL OXIDE OR METAL OXYNITRIDE TFTS USING WET PROCESS FOR SOURCE-DRAIN METAL ETCH - The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel. | 2011-11-03 |
20110266538 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer. | 2011-11-03 |
20110266539 | High Performance Compliant Wafer Test Probe - An electrical connection includes a first electrical contact made of electrically conductive material. The first electrical contact is formed with a depression therein. Also included are a deformable pad, having a Young's modulus of less than 1,000,000 psi, which bears on the first contact; and a second electrical contact, made of electrically conductive material, which contacts the first electrical contact and is at least partially received into the depression. The deformable pad at least partially causes at least one lateral force on the first electrical contact, so as to induce the first electrical contact to make an electrical connection with the second electrical contact. An array of such contacts is also contemplated, as is an array of cantilevered contacts, which may or may not have depressions, and which are supported by at least one elastomeric pad, having a Young's modulus of less 72,500 psi. | 2011-11-03 |
20110266540 | SEMICONDUCTOR DEVICE - Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region. | 2011-11-03 |
20110266541 | Probe Pad On A Corner Stress Relief Region In A Semiconductor Chip - A semiconductor chip includes a circuit region and a corner stress relief (CSR) region. The CSR region is in a corner of the semiconductor chip. A device under test (DUT) structure or a functional circuit is disposed on the circuit region. A probe pad is disposed on the CSR region. A metal line extends from the circuit region to the CSR region to electrically connect the probe pad to the DUT structure or a functional circuit. | 2011-11-03 |
20110266542 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device including a dual gate transistor and a method of fabricating the same. The semiconductor device includes a lower gate electrode, an upper gate electrode on the lower gate electrode, a contact plug interposed between the lower gate electrode and the upper gate electrode, and connecting the lower gate electrode to the upper gate electrode, and a functional electrode spaced apart from the upper gate electrode and formed at the same height as the upper gate electrode. The dual gate transistor exhibiting high field effect mobility is applied to the semiconductor device, so that characteristics of the semiconductor device can be improved. In particular, since no additional mask or deposition process is necessary, a large-area high-definition semiconductor device can be mass-produced with neither an increase in process cost nor a decrease in yield. | 2011-11-03 |
20110266543 | CIRCUIT BOARD AND DISPLAY DEVICE - The present invention provides a circuit board that includes top gate TFTs and bottom gate TFTs formed on the same substrate and that can improve reliability of these TFTs. The present invention is a circuit board including a bottom gate thin film transistor and a top gate thin film transistor on a substrate,
| 2011-11-03 |
20110266544 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light emitting diode display, which can obtain a resonance effect by its metal mirror, and a manufacturing method thereof. The display includes a semiconductor layer, a dummy pattern layer, a gate insulating film, a pixel electrode, and a gate electrode. The semiconductor layer is formed of polysilicon on a base substrate. The dummy pattern layer is formed of polysilicon at a same layer level as the semiconductor layer and surrounds a light emitting region. The gate insulating film is on the base substrate while covering the semiconductor layer and the dummy pattern layer, and has recess portions corresponding to the light emitting region. The pixel electrode is filled in the recess portions, and is formed of a metal mirror multilayer including a transmissive conductive film and a reflective conductive film. The gate electrode is on the gate insulating film at a distance from the pixel electrode. | 2011-11-03 |
20110266545 | ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - An array substrate includes an active layer including a channel region, a gate electrode positioned corresponding to the channel region, and a gate insulating film between the active layer and the gate electrode. The gate electrode includes a transparent conductive film and an opaque conductive film, and the transparent conductive film is between the channel region and the opaque conductive film. | 2011-11-03 |
20110266546 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device and a manufacturing method thereof are disclosed. In one embodiment, the display device includes 1) a substrate having a pixel region, a transistor region, and a capacitor region and 2) a transistor formed in the transistor region, wherein the transistor comprises i) an active layer formed over the substrate, ii) a gate insulating layer formed on the active layer, iii) a gate electrode formed on the gate insulating layer, and iv) a first interlayer insulating layer covering the gate electrode and formed on the gate insulating layer, v) a second interlayer insulating layer formed on the first interlayer insulating layer and vi) a source electrode and a drain electrode electrically connected to the active layer. The display device further includes a capacitor formed in the capacitor region, wherein the capacitor comprises i) a lower electrode formed on the gate insulating layer and ii) an upper electrode formed on the first interlayer insulating layer, wherein the upper electrode is formed substantially directly above the lower electrode, and wherein the surface area of the lower electrode is less than the surface area of the upper electrode. | 2011-11-03 |
20110266547 | THIN FILM TRANSISTOR ARRAY PANEL AND DISPLAY DEVICE - A display device includes a first display panel including a common electrode disposed thereon, and a second display panel including; thin film transistors (“TFTs”) each including a gate electrode, a source electrode, and a drain electrode, a first passivation layer disposed on the source and drain electrodes, a second passivation layer disposed on the first passivation layer and including at least one sensing protrusion, pixel electrodes disposed on the second passivation layer and connected with the drain electrode, and at least one conductive member disposed on the sensing protrusion. | 2011-11-03 |
20110266548 | LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND MANUFACTURING APPARATUS THEREFOR - A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision. | 2011-11-03 |
20110266549 | LAMINATED STRUCTURE, PRODUCTION METHOD OF THE SAME, MULTILAYER CIRCUIT BOARD, ACTIVE MATRIX SUBSTRATE, AND ELECTRONIC DISPLAY - A disclosed laminated structure includes a wettability-variable layer containing a wettability-variable material whose surface energy changes when energy is applied thereto and including at least a high-surface-energy area having high surface energy and a low-surface-energy area having low surface energy; and a conductive layer formed on the high-surface-energy area. The high-surface-energy area includes a first area and a second area extending from the first area and having a width smaller than that of the first area. | 2011-11-03 |
20110266550 | METHOD OF FORMING OF A SEMICONDUCTOR FILM, METHOD OF MANUFACTURE OF A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - This invention provides a method of forming semiconductor films on dielectrics at temperatures below 400° C. Semiconductor films are required for thin film transistors (TFTs), on-chip sensors, on-chip micro-electromechanical systems (MEMS) and monolithic 3D-integrated circuits. For these applications, it is advantageous to form the semiconductor films below 400° C. because higher temperatures are likely to destroy any underlying devices and/or substrates. This invention successfully achieves low temperature growth of germanium films using diboran. First, diboran gas is supplied into a reaction chamber at a temperature below 400° C. The diboran decomposes itself at the given temperature and decomposed boron is attached to the surface of a dielectric, for e.g., SiO | 2011-11-03 |
20110266551 | HIGH BRIGHTNESS LIGHT EMITTING DIODE COVERED BY ZINC OXIDE LAYERS ON MULTIPLE SURFACES GROWN IN LOW TEMPERATURE AQUEOUS SOLUTION - A high brightness III-Nitride based Light Emitting Diode (LED), comprising multiple surfaces covered by Zinc Oxide (ZnO) layers, wherein the ZnO layers are grown in a low temperature aqueous solution and each have a (0001) c-orientation and a top surface that is a (0001) plane. | 2011-11-03 |
20110266552 | LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A light emitting element includes a substrate, a GaN layer formed on the substrate, a first low refractive index semiconductor layer formed on the GaN layer, and a lighting structure having a high refractive index formed on the first low refractive index semiconductor layer. A second low refractive index semiconductor layer is embedded in the first low refractive index semiconductor layer. The first low refractive index semiconductor layer and the GaN layer exhibit a lattice mismatch therebetween. | 2011-11-03 |
20110266553 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD OF MANUFACTURING THE SAME - An object of the present invention is to provide a nitride semiconductor light-emitting device in which contact resistance generated between an n-contact layer and an n-side electrode is effectively reduced while maintaining satisfactory external quantum efficiency, and a method of efficiently producing the nitride semiconductor light-emitting device. Specifically, the present invention characteristically provides a nitride semiconductor light-emitting device having a semiconductor laminated body including an n-type laminate, a light-emitting layer and a p-type laminate, and an n-side electrode and a p-side electrode, characterized in that: the n-type laminate includes an n-contact layer made of an Al | 2011-11-03 |
20110266554 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE DEVICE - In a manufacturing method of a semiconductor device, first, a first semiconductor layer, a second semiconductor layer, and a p-type third semiconductor layer are sequentially epitaxially grown on a substrate. After that, the third semiconductor layer is selectively removed. Then, a fourth semiconductor layer is epitaxially grown on the second semiconductor layer. Then, a gate electrode is formed on the third semiconductor layer. | 2011-11-03 |
20110266555 | METHOD OF GROWING SEMICONDUCTOR HETEROSTRUCTURES BASED ON GALLIUM NITRIDE - The method of growing non-polar epitaxial heterostructures for light-emitting diodes producing white emission and lasers, on the basis of compounds and alloys in AlGaInN system, comprising the step of vapor-phase deposition of one or multiple heterostructures layers described by the formula Al | 2011-11-03 |
20110266556 | METHOD FOR CONTROLLED GROWTH OF SILICON CARBIDE AND STRUCTURES PRODUCED BY SAME - A method for controlled growth of silicon carbide and structures produced by the method are disclosed. A crystal of silicon carbide (SiC) can be grown by placing a sacrificial substrate in a growth zone with a source material. The source material may include a low-solubility impurity. SiC is then grown on the sacrificial substrate to condition the source material. The sacrificial substrate is then replaced with the final substrate, and SiC is grown on the final substrate. A single crystal of silicon carbide is produced, wherein the crystal of silicon carbide has substantially few micropipe defects. Such a crystal may also include a substantially uniform concentration of the low-solubility impurity, and may be used to make wafers and/or SiC die. | 2011-11-03 |
20110266557 | Semiconductor Devices Having Improved Adhesion and Methods of Fabricating the Same - Wide bandgap semiconductor devices are fabricated by providing a wide bandgap semiconductor layer, providing a plurality of recesses in the wide bandgap semiconductor layer, and providing a metal gate contact in the plurality of recesses. A protective layer may be provided on the wide bandgap semiconductor layer, the protective layer having a first opening extending therethrough, a dielectric layer may be provided on the protective layer, the dielectric layer having a second opening extending therethrough that is narrower than the first opening, and a gate contact may be provided in the first and second openings. The metal gate contact may be provided to include a barrier metal layer in the plurality of recesses, and a current spreading layer on the barrier metal layer remote from the wide bandgap semiconductor layer. Related devices and fabrication methods are also discussed. | 2011-11-03 |
20110266558 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SILICON CARBIDE SEMICONDUCTOR DEVICE - There is provided a silicon carbide semiconductor device equipped with an ohmic electrode that exhibits both low contact resistance and favorable surface conditions,
| 2011-11-03 |
20110266559 | Semiconductor Component, Reflected-Light Barrier and Method for Producing a Housing Therefor - The application relates to a semiconductor component, a photo-reflective sensor, and also a method for producing a housing for a photo-reflective sensor, wherein the housing lower part is monolithic and has at least two cavities into which an emitter and a detector are introduced. | 2011-11-03 |
20110266560 | WHITE-EMITTING LED CHIPS AND METHOD FOR MAKING SAME - Methods and devices for light emitting diode (LED) chips are provided. In one embodiment of a method, a pre-formed capping wafer is provided, with the capping wafer comprising a conversion material. A wire-bond free LED wafer is fabricated comprising a plurality of LEDs. The capping wafer is bonded to the LED wafer using an adhesive. The LED chips are later singulated upon completion of all final fabrication steps. The capping wafer provides a robust mechanical support for the LED chips during fabrication, which improves the strength of the chips during fabrication. Additionally, the capping wafer may comprise an integrated conversion material, which simplifies the fabrication process. In one possible embodiment for an LED chip wafer, a submount wafer is provided, along with a plurality of LEDs flip-chip mounted on the submount wafer. Additionally, a capping wafer is bonded to the LEDs using an adhesive, and the capping wafer comprises a conversion material. At least some of the light emitted from the LEDs passes through the capping wafer where at least some of the light is converted by the conversion material. | 2011-11-03 |
20110266561 | Optical Systems Fabricated by Printing-Based Assembly - The present invention provides optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity. Optical systems of the present invention include, however, devices and device arrays provided on conventional rigid or semi-rigid substrates, in addition to devices and device arrays provided on flexible, shapeable and/or stretchable substrates. | 2011-11-03 |
20110266562 | GLASS SUBSTRATE WITH AN ELECTRODE, ESPECIALLY A SUBSTRATE INTENDED FOR AN ORGANIC LIGHT-EMITTING DIODE DEVICE - A glass substrate includes a first side and a second opposite side, and provided, on its second side, with an electrode which is formed by at least one electrically conductive film, the substrate having, over all of its second side, and through a thickness e extending toward the interior of the substrate in the direction of the first side, a refractive index variation, of the glass, obtained by an ion-exchange treatment, the refractive index at the surface being greater than that of the glass located beyond the thickness e. | 2011-11-03 |
20110266563 | METHOD FOR FORMING A MULTI-LEVEL SURFACE ON A SUBSTRATE WITH AREAS OF DIFFERENT WETTABILITY AND A SEMICONDUCTOR DEVICE HAVING THE SAME - The invention relates to a method | 2011-11-03 |
20110266564 | SEMICONDUCTOR DISPLAY DEVICE - A semiconductor display device using a light-emitting element, which can suppress luminance unevenness among pixels due to the potential drop of a wiring, is provided. Power supply lines to which a power supply potential is supplied are electrically connected to each other in a display region where a plurality of pixels are arranged. Further, an interlayer insulating film is formed over a wiring (an auxiliary power supply line) for electrically connecting the power supply lines to each other in the display region and a gate electrode of a transistor included in a pixel; and the power supply lines are formed over the interlayer insulating film which is formed over the auxiliary power supply line and the gate electrode. Furthermore, a wiring (an auxiliary wiring) formed over the interlayer insulating film is electrically or directly connected to the auxiliary power supply line. | 2011-11-03 |
20110266565 | DISPLAY PANEL - A display panel having a display area and a non-display area outside the display area is provided. The display panel includes a first substrate, a conductive light-shielding pattern, color filter patterns, first spacers, transparent pads, a second substrate, scan lines, data lines, pixel structures, third pads and fourth pads. The conductive light-shielding pattern defines a conductive matrix pattern, a plurality of first pads and second pads. Each first pad is electrically connected with one of the corresponding second pads through the conductive matrix pattern. The color filter patterns include a plurality of first filter patterns and second filter patterns. The second filter patterns are located within the non-display area and disposed on the second pads. The first spacers are disposed on the second filter patterns, and the transparent pads cover the first spacers and contact the second pads. | 2011-11-03 |
20110266566 | LED PACKAGE STRUCTURE WITH CONCAVE AREA FOR POSITIONING HEAT-CONDUCTING SUBSTANCE AND METHOD FOR MANUFACTURING THE SAME - An LED package structure with concave area for positioning heat-conducting substance includes a substrate unit, a heat-conducting adhesive unit, a light-emitting unit, a conductive unit and a package unit. The substrate unit has a substrate body, a concave space formed on the substrate body, and a plurality of positive and negative pads exposed on the substrate body. The heat-conducting adhesive unit has a heat-conducting adhesive layer positioned in the concave space. The light-emitting unit has a plurality of LED chips disposed on the heat-conducting adhesive layer and received in the concave space. The conductive unit has a plurality of wires. Each LED chip is electrically connected between each positive pad and each negative pad. The package unit has a translucent package resin body disposed on the substrate body in order to cover the LED chips and the wires. | 2011-11-03 |
20110266567 | Method for Producing a Radiation-Emitting Component and Radiation-Emitting Component - A method for manufacturing a radiation-emitting component ( | 2011-11-03 |
20110266568 | LIGHT EMITTING DEVICE WITH TRENCHES AND A TOP CONTACT - A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. A bottom contact disposed on a bottom surface of the semiconductor structure is electrically connected to one of the n-type region and the p-type region. A top contact disposed on a top surface of the semiconductor structure is electrically connected to the other of the n-type region and the p-type region. A mirror is aligned with the top contact. The mirror includes a trench formed in the semiconductor structure and a reflective material disposed in the trench, wherein the trench extends through the light emitting layer. | 2011-11-03 |
20110266569 | LED WAFER WITH LAMINATED PHOSPHOR LAYER - An LED wafer with a growth substrate is attached to a carrier substrate by, for example, a heat-releasable adhesive so that the LED layers are sandwiched between the two substrates. The growth substrate is then removed, such as by laser lift-off. The exposed surface of the LED layers is then etched to improve light extraction. A preformed phosphor sheet, matched to the LEDs, is then affixed to the exposed LED layer. The phosphor sheet, LED layers, and, optionally, the carrier substrate are then diced to separate the LEDs. The LED dice are released from the carrier substrate by heat or other means, and the individual LED dice are mounted on a submount wafer using a pick-and-place machine. The submount wafer is then diced to produce individual LEDs. The active layer may generate blue light, and the blue light and phosphor light may generate white light having a predefined white point. | 2011-11-03 |
20110266570 | LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - In a light emitting device package and manufacturing method thereof, a multi-layer structure is allocated upon a substrate, of which at least two films with different refractive indices are alternately stacked together. | 2011-11-03 |
20110266571 | Semiconductor Arrangement - According to at least one embodiment of the semiconductor arrangement, the latter comprises a mounting side, at least one optoelectronic semiconductor chip with mutually opposing chip top and bottom, and at least one at least partially radiation-transmissive body with a body bottom, on which the semiconductor chip is mounted such that the chip top faces the body bottom. Moreover, the semiconductor arrangement comprises at least two electrical connection points for electrical contacting of the optoelectronic semiconductor chip, wherein the connection points do not project laterally beyond the body and with their side remote from the semiconductor chip delimit the semiconductor arrangement on the mounting side thereof. | 2011-11-03 |
20110266572 | Organic Light Emitting Component and Illumination Means Comprising a Component of this Type - In at least one embodiment of the organic light-emitting component ( | 2011-11-03 |
20110266573 | SEMICONDUCTOR FOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The light emitting device includes a first conductive type semiconductor layer; an active layer on the first conductive type semiconductor layer; and a first electrode pad including a plurality of reflective layers on the first conductive type semiconductor layer. | 2011-11-03 |
20110266574 | LED PACKAGE - An LED package includes a substrate, an LED die, and an encapsulating layer. The LED die is arranged on the substrate. The encapsulating layer covers the LED die and at least a part of the substrate. The encapsulating layer includes a light dispersing element. A light scattering intensity of the light dispersing element is proportional to the light intensity of light generated by the LED die and illuminated at the encapsulating layer. A luminance at a center of the LED package is substantially identical to that at a circumference of the LED package. | 2011-11-03 |
20110266575 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor device includes: a nitride-based semiconductor multilayer structure including a p-type semiconductor region, a surface of the p-type semiconductor region being an m-plane; and an electrode that is arranged on the p-type semiconductor region, wherein the p-type semiconductor region is made of an Al | 2011-11-03 |
20110266576 | Optoelectronic Semiconductor Component - An optoelectronic semiconductor device at least one radiation-emitting semiconductor chip ( | 2011-11-03 |
20110266577 | ORGANIC ELECTROLUMINESCENCE DEVICE AND METHOD OF MANUFACTURING SAME - An organic light emitting device enables improvement on the loss of optical extraction efficiency due to total reflection and optical waveguide effects. The organic light emitting device has a structure wherein a first electrode, an organic substance layer, and a second electrode are sequentially laminated on a substrate, a random nano structure having a fine pattern of a peaks-and-valleys shape is formed between a substrate and a first electrode to extract any light that is wasted due to total reflection and an optical waveguide mode to the outside of the substrate so that an organic light emitting device with improved external quantum efficiency can be realized, and optical extraction patterns and color changes due to visual field angles can also be improved. | 2011-11-03 |
20110266578 | ANISOTROPIC CONDUCTIVE FILM AND LIGHT EMITTING DEVICE - An anisotropic conductive film is provided that does not have a light-reflecting layer on a light emitting diode element which causes costs to increase when a light emitting device that uses an LED element is flip-chip mounted, and that does not cause emission efficiency to deteriorate. Further, a light emitting device that uses such an anisotropic conductive film is provided. This anisotropic conductive film has a structure in which a light-reflecting insulating adhesive layer and an anisotropic conductive adhesive layer are laminated, wherein the light-reflecting insulating adhesive layer has a structure in which light-reflecting particles are dispersed in an insulating adhesive. The light emitting device has a structure in which a light emitting diode element is flip-chip-mounted on a substrate, with this anisotropic conductive film provided between a connection terminal on the substrate and a bump for connection of the light emitting diode element. | 2011-11-03 |
20110266579 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, LIGHT-EMITTING MODULE, AND ILLUMINATION DEVICE - A semiconductor light-emitting device having a substrate on which a semiconductor multilayer film is disposed, the semiconductor multilayer film having a layered structure in which a first conductive layer, a light-emitting layer and a second conductive layer are layered above the substrate from bottom to top in the stated order, and being divided into portions by grooves extending perpendicular to the substrate, each portion having a diode structure and serving as a light-emitting element | 2011-11-03 |
20110266580 | LIGHT SOURCE COMPRISING A LIGHT RECYCLING DEVICE AND CORRESPONDING LIGHT RECYCLING DEVICE - The invention relates to a light source ( | 2011-11-03 |
20110266581 | LIGHT-EMITTING DEVICE CONTAINING A COMPOSITE ELECTROPLATED SUBSTRATE - The application is related to a method of forming a substrate of a light-emitting diode by composite electroplating. The application illustrates a light-emitting diode comprising the following elements: a light-emitting epitaxy structure, a reflective layer disposed on the light-emitting epitaxy structure, a seed layer disposed on the reflective layer, a composite electroplating substrate disposed on the seed layer by composite electroplating, and a protection layer disposed on the composite electroplating substrate. | 2011-11-03 |
20110266582 | PACKAGE FOR LIGHT EMITTING DEVICE - A semiconductor light emitting package includes a base having a top surface with a flat portion, the base shaped into a substantially circle; a plurality of semiconductor light emitting devices on the base; an electrical circuit layer electrically connected to the plurality of semiconductor light emitting device; a plurality of screen members on the base; and a plurality of optical members formed of a light transmissive material such that light emitted from at least one of the semiconductor light emitting devices passes therethrough, wherein each of the screen members has an opening surrounding at least one of the semiconductor light emitting device, each opening of the screen members is shaped into a substantially circle, a diameter of the base is larger than a diameter of the opening of the screen members, and an edge portion of the optical members is in contact with one of the screen members. | 2011-11-03 |
20110266583 | PACKAGE FOR LIGHT EMITTING DEVICE - A semiconductor light emitting package is discussed, which includes a base having a top surface with a flat portion; a semiconductor light emitting device on the base; an electrical circuit layer electrically connected to the semiconductor light emitting device; a screen member having an opening and disposed on the base around the semiconductor light emitting device, the screen member shaped into a substantially circle; and an optical member formed of a light transmissive material such that light emitted from the semiconductor light emitting device passes therethrough, wherein a bottom surface of the screen member is positioned higher than the semiconductor light emitting device, an edge portion of the optical member is in contact with the screen member, a top surface of the optical member is substantially parallel to the flat portion of the base. | 2011-11-03 |
20110266584 | WHITE LIGHT EMITTING DIODE WITH YELLOW, GREEN AND RED LIGHT EMITTING PHOSPHORS - Provided is a white light emitting diode (LED) including a blue LED chip; and yellow, green, and red light emitting phosphors that are coated on the blue LED chip at a predetermined mixing ratio and converts light, emitted from the blue LED chip, into white light. | 2011-11-03 |
20110266585 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - A light emitting device is provided. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first dielectric layer over a part of an upper surface of the light emitting structure, and a pad electrode over the first dielectric layer. | 2011-11-03 |
20110266586 | LED PACKAGE AND MANUFACTURING METHOD THEREOF - An LED package includes a base, an LED chip, and an encapsulant. The LED chip is mounted on the base, and is enclosed by the encapsulant. The base includes a substrate and a blocking wall integrally formed with the substrate. The blocking wall divides a surface of the substrate into a first bonding area and a second bonding area. An electrically conductive layer and a solder are formed on the bonding area in sequence. The blocking wall can block the first and second solder to overflow outside the first and second bonding area at soldering respectively. A method for manufacturing the LED package is also provided. | 2011-11-03 |
20110266587 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - In some embodiments, a semiconductor device includes a semiconductor chip configured to receive or emit light, a chip mounting region for mounting the semiconductor chip, an electrode arranged surrounding the chip mounting region, an electric connecting element which electrically connects the semiconductor chip and the electrode, an optically-transparent element arranged on a top surface of the semiconductor chip and made of optically-transparent material, a protection film arranged on a top surface of the optically-transparent element so as to surround a light passing region through which the light passes, and a filler-contained insulating resin which seals the semiconductor chip, the electric connecting element, the electrode, the optically-transparent element, and the protection film in a state in which a top surface of the protection film and the light passing region surrounded by the protection film are exposed outside. | 2011-11-03 |
20110266588 | Method for Producing an Organic Radiation-Emitting Component and Organic Radiation-Emitting Component - A method for producing an organic radiation-emitting component is specified, which comprises, in particular, the following method steps: A) providing a first electrode layer ( | 2011-11-03 |
20110266589 | Light Emitting Diode Package Structure and Manufacturing Method Therefor - A light emitting diode (LED) package and a manufacturing method therefor are disclosed. In one aspect, a manufacturing method of a light emitting diode package may: heat a first light transmission insulation material to cause the first light transmission insulation material to become a sticky member; connect a lead frame to the sticky member; perform a chip-bonding step that bonds at least one light-emitting diode chip on the sticky member using a light transmission glue; encapsulate the at least one light-emitting diode chip with a second light transmission insulation material; and perform a drying step that forms the sticky member and the second light transmission insulation material into shape. | 2011-11-03 |
20110266590 | Encapsulated Optoelectronic Component and Method for the Production Thereof - A method for encapsulating an optoelectronic component by depositing a diffusion barrier for protection against environmental influences by means of an atmospheric pressure plasma on at least one subarea of the surface of the optoelectronic component. | 2011-11-03 |
20110266591 | BI-DIRECTIONAL DIODE STRUCTURE - In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic. | 2011-11-03 |
20110266592 | DEVICE AND METHOD FOR TRANSIENT VOLTAGE SUPPRESSOR - A transient voltage suppressor (TVS) device includes a semiconductor substrate of a first conductivity type, and a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate. A semiconductor layer of the second conductivity type overlies the first and the second semiconductor regions. The TVS device has a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate, and a fill material of the second conductivity type disposed in the first trench. A clamping diode in the TVS device has a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate. The TVS device also includes a first P-N diode formed in a first portion of the semiconductor layer, and a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate. | 2011-11-03 |
20110266593 | SEMICONDUCTOR DEVICES WITH GATE-SOURCE ESD DIODE AND GATE-DRAIN CLAMP DIODE - A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching. | 2011-11-03 |
20110266594 | METHOD FOR OBTAINING A LAYER OF ALN HAVING SUBSTANTIALLY VERTICAL SIDES - A method is disclosed, for producing a layer of AlN having substantially vertical sides relative to the surface of a substrate, comprising:
| 2011-11-03 |
20110266595 | SEMICONDUCTOR SUBSTRATE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. The semiconductor wafer further includes an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer. The inhibition layer inhibiting crystal growth of a compound semiconductor. Furthermore, a seed crystal is provided within the opening, and a compound semiconductor has a lattice match or a pseudo lattice match with the seed crystal. There is also provided an electronic device includes a substrate, an insulating layer that is provided on the substrate, a Si crystal layer that is provided on the insulating layer, an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer, where the inhibition layer inhibits crystal growth of a compound semiconductor, a seed crystal that is provided within the opening, a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal, and a semiconductor device that is formed using the compound semiconductor. | 2011-11-03 |
20110266596 | Semiconductor device and method of making the same - In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a Ni | 2011-11-03 |
20110266597 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an isolation layer formed on a semiconductor substrate; an active region defined by the isolation layer; at least one gate line formed to overlap with the active region; at least one first active tab formed on a first interface of the active region which overlaps with the gate line; and a first gate tab formed on a second interface facing away from the first interface in such a way as to project from the gate line. | 2011-11-03 |
20110266598 | Solid-state image pickup device - In a rear surface incidence type CMOS image sensor having a wiring layer | 2011-11-03 |
20110266599 | SOLID-STATE IMAGE PICKUP DEVICE - A solid-state image pickup device is provided which includes a substrate; a transistor formed on the substrate; a photoelectric conversion element including a first electrode connected to a drain or a source of the transistor, a semiconductor layer stacked on the first electrode, and a second electrode stacked on the semiconductor layer; an insulating layer disposed on the second electrode; and a bias line formed on the insulating layer to be connected to the second electrode, in which the insulating layer contains at least an inorganic insulating film, and the bias line is connected to the second electrode via a contact hole formed in the insulating layer, and a side surface of the semiconductor layer is in contact with the inorganic insulating film. | 2011-11-03 |
20110266600 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element. | 2011-11-03 |
20110266601 | Single Gate Semiconductor Device - A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor. | 2011-11-03 |
20110266602 | SEMICONDUCTOR DEVICES INCLUDING STORAGE NODE LANDING PADS SEPARATED FROM BIT LINE CONTACT PLUGS - A Dynamic Random Access Memory (DRAM) device can include a semiconductor substrate that includes an active region including a source region therein. A gate line can cross the active region and a first contact plug can be on the active region adjacent to the gate line and can be connected to the source region. A conductive layer can be on the first contact plug to expose a portion of the first contact plug and a capacitor storage node electrode can be on the conductive layer. | 2011-11-03 |
20110266603 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a memory capacitor; and a first compensation capacitor. The semiconductor substrate has at least first and second regions. The memory capacitor is positioned over the first region. The memory capacitor may include, but is not limited to: a first lower electrode; and a first dielectric film covering inner and outer surfaces of the first lower electrode. The first compensation capacitor is positioned over the second region. The first compensation capacitor includes, but is not limited to: a second lower electrode; a second dielectric film covering an inner surface of the second lower electrode; and a first insulating film covering an outer surface of the second lower electrode. | 2011-11-03 |
20110266604 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of strings each having vertically-stacked active layers over a plurality of word lines, at least one bit line connection unit vertically formed over one end of the word lines and having a stairway shape, and a plurality of bit lines each coupled to each of a plurality of active regions of the bit line connection unit. | 2011-11-03 |
20110266605 | Memristive Transistor Memory - A memory device ( | 2011-11-03 |
20110266606 | METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions. | 2011-11-03 |
20110266607 | Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same - Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors. | 2011-11-03 |
20110266608 | NONVOLATILE MEMORY DEVICES HAVING GATE STRUCTURES DOPED BY NITROGEN - Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein. | 2011-11-03 |
20110266609 | SiH4 SOAK FOR LOW HYDROGEN SIN DEPOSITION TO IMPROVE FLASH MEMORY DEVICE PERFORMANCE - Prior to deposition of a silicon nitride (SiN) layer on a structure, a non-plasma enhanced operation is undertaken wherein the structure is exposed to silane (SiH | 2011-11-03 |
20110266610 | MEMORY DEVICES HAVING REDUCED INTERFERENCE BETWEEN FLOATING GATES AND METHODS OF FABRICATING SUCH DEVICES - A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array. | 2011-11-03 |
20110266611 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer. | 2011-11-03 |
20110266612 | NAND-TYPE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide,
| 2011-11-03 |
20110266613 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shield electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shield electrodes. A gate electrode in at least one of the trenches is connected to at least one shield electrode in the trenches. | 2011-11-03 |
20110266614 | LDMOS WITH ENHANCED SAFE OPERATING AREA (SOA) AND METHOD THEREFOR - A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed. | 2011-11-03 |
20110266615 | SEMICONDUCTOR DEVICE - A semiconductor structure may include, but is not limited to: a semiconductor substrate; a first semiconductor structure extending upwardly over the semiconductor substrate; and a second semiconductor structure extending upwardly over the semiconductor substrate, the first and second semiconductor structures being aligned in a first < | 2011-11-03 |
20110266616 | TRENCHED POWER SEMICONDUCTOR STRUCTURE WITH REDUCED GATE IMPEDANCE AND FABRICATION METHOD THEREOF - A trenched power semiconductor structure with reduced gate impedance and a fabrication method thereof is provided. The trenched power semiconductor structure has a silicon base, a gate trench, a gate oxide layer, and a gate polysilicon structure. The gate trench is formed in the silicon base and extended to an upper surface of the silicon base. The gate oxide layer is formed at least on the inner surface of the gate trench. The gate polysilicon structure is formed in the gate trench with a protruding portion extended form the upper surface of the semiconductor substrate upward. A concave is formed on a sidewall of the protruding portion to expose the upper surface of the silicon base adjacent to the gate trench. | 2011-11-03 |
20110266617 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench. | 2011-11-03 |
20110266618 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates. | 2011-11-03 |
20110266619 | SEMICONDUCTOR TRANSISTOR COMPRISING TWO ELECTRICALLY CONDUCTIVE SHIELD ELEMENTS - It is disclosed a semiconductor transistor, comprising a semiconductor substrate ( | 2011-11-03 |
20110266620 | TRANSISTOR STRUCTURE WITH FEED-THROUGH SOURCE-TO-SUBSTRATE CONTACT - An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer. | 2011-11-03 |
20110266621 | FIELD EFFECT TRANSISTOR - A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode. | 2011-11-03 |
20110266622 | SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS - A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections. | 2011-11-03 |
20110266623 | Semiconductor Memory Device Having Three Dimensional Structure - A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers. | 2011-11-03 |
20110266624 | ELECTROSTATIC DISCHARGE PROTECTION HAVING MULTIPLY SEGMENTED DIODES IN PROXIMITY TO TRANSISTOR - An ESD protection device for an I/O pad ( | 2011-11-03 |
20110266625 | Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a Liner - Gate failures in sophisticated high-k metal gate electrode structures formed in an early manufacturing stage may be reduced by forming a protective liner material after the incorporation of a strain-inducing semiconductor alloy and prior to performing any critical wet chemical processes. In this manner, attacks in the sensitive gate materials after the incorporation of the strain-inducing semiconductor material may be avoided, without influencing the further processing of the device. In this manner, very sophisticated circuit designs may be applied in sophisticated gate first approaches. | 2011-11-03 |
20110266626 | GATE DEPLETION DRAIN EXTENDED MOS TRANSISTOR - A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors. | 2011-11-03 |
20110266627 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a plurality of active areas defined by a device isolation layer, a gate line structure crossing the plurality of active areas, a buffer insulation layer on the semiconductor substrate, the buffer insulation layer contacting a portion of a side of the gate line structure, a contact etching stopper layer on the buffer insulation layer, and a contact plug passing through the buffer insulation layer and the contact etching stopper layer to be connected to the plurality of active areas. | 2011-11-03 |
20110266628 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 2011-11-03 |
20110266629 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a first transistor of a first conductivity type provided on a first active region of a semiconductor region, and a second transistor of a second conductivity type provided on a second active region of the semiconductor region. The first transistor includes a first gate insulating film and a first gate electrode, the first gate insulating film contains a high-k material and a first metal, and the first gate electrode includes a lower conductive film, a first conductive film and a first silicon film. The second transistor includes a second gate insulating film and a second gate electrode, the second gate insulating film contains a high-k material and a second metal, and the second gate electrode includes a second conductive film made of the same material as the first conductive film, and a second silicon film. | 2011-11-03 |
20110266630 | Semiconductor Device and Method for Manufacturing the Same - A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT | 2011-11-03 |
20110266631 | SEMICONDUCTOR DEVICE - There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer. | 2011-11-03 |
20110266632 | Semiconductor Device - A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode. | 2011-11-03 |
20110266633 | Semiconductor Device Comprising Metal Gates and Semiconductor Resistors Formed on the Basis of a Replacement Gate Approach - In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches. | 2011-11-03 |
20110266634 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions. | 2011-11-03 |