44th week of 2012 patent applcation highlights part 29 |
Patent application number | Title | Published |
20120275227 | PHOTOSENSITIVE COMPOSITION AND COMPOUND FOR USE IN THE PHOTOSENESITIVE COMPOSITION - A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages. | 2012-11-01 |
20120275228 | INTERNAL WORDLINE CURRENT LEAKAGE SELF-DETECTION METHOD, DETECTION SYSTEM AND COMPUTER-READABLE STORAGE MEDIUM FOR NOR-TYPE FLASH MEMORY DEVICE - A wordline internal current leakage self-detection method, system and a computer-readable storage medium thereof employ the originally existed high voltage supply unit and the voltage detector connected to the wordline in the flash memory device, in which the high voltage supply unit applies the test signal to the selected wordline, and the voltage detector detects the voltage signal of the wordline. By comparing the test signal with the voltage signal, the wordline will be indicated as current leakage when the voltage signal is lower than the test signal. | 2012-11-01 |
20120275229 | APPARATUS AND METHOD FOR EXTERNAL CHARGE PUMP ON FLASH MEMORY MODULE - A memory module is provided. The memory module includes die packages and a charge pump that is external the die packages. Each die package includes a flash memory device, and each of the flash memory devices includes bit lines and memory cells coupled to the bit lines. The charge pump provides a charge pump voltage that is selectively provided to the bit lines in each flash memory device in each of the die packages. | 2012-11-01 |
20120275230 | METHOD OF STORING DATA ON A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure. | 2012-11-01 |
20120275231 | METHOD, APPARATUS, AND MANUFACTURE FOR FLASH MEMORY WRITE ALGORITHM FOR FAST BITS - A method, apparatus, and manufacture for a memory device is provided. The memory device includes memory cells that each store two bits, and a memory controller. During write operations, for each bit in each memory cell that is to be programmed, the memory controller determines whether both bits of the memory cell are being programmed. While controlling an application of programming pulses to the memory cell to program the bit, if both bits of the memory cell are being programmed, the memory controller causes the application of each programming pulse to the bit to occur for a standard duration. Otherwise, the memory controller causes the application of each programming pulse to the bit to occur for a reduced duration. The reduced duration is less than three-fourths of the standard duration. | 2012-11-01 |
20120275232 | SEMICONDUCTOR DEVICE AND ERASE METHODS THEREOF - An erase method of a semiconductor device includes performing an operation comprised of supplying an erase pulse to erase the memory cells of a memory block, performing an erase verify operation for detecting memory cells of the memory block having threshold voltages dropped to a target erase voltage, from among the memory cells, performing a pre-program operation on the memory cells having the threshold voltages dropped to the target erase voltage, if, as a result of the erase verify operation, the memory block comprises memory cells having the threshold voltages higher than the target erase voltage and the memory cells having the threshold voltages dropped to the target erase voltage, and repeating the operation of supplying an erase pulse, the erase verify operation, and the pre-program operation until the threshold voltages of all the memory cells drop to the target erase voltage. | 2012-11-01 |
20120275233 | SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE - Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage. | 2012-11-01 |
20120275234 | NONVOLATILE MEMORY DEVICES, MEMORY SYSTEMS AND COMPUTING SYSTEMS - A nonvolatile memory device configured to apply a wordline erase voltage to a plurality of wordlines connected to a plurality of memory cells, apply an erase voltage to a substrate where a memory cell string is formed while applying a specific voltage to at least one ground selection line connected to at least one ground selection transistor, and float the at least one ground selection line when a target voltage of the substrate reaches a target voltage. | 2012-11-01 |
20120275235 | METHOD AND APPARATUS FOR TEMPERATURE COMPENSATION FOR PROGRAMMING AND ERASE DISTRIBUTIONS IN A FLASH MEMORY - A method and apparatus for a memory device is provided. The memory device includes a memory cell, a memory controller, and a temperature-sensing device that detects a temperature. The memory controller enables adjusting, based on the detected temperature, a parameter associated with a bit-altering operation to the memory cell that changes a threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is compensated for variations in temperature. | 2012-11-01 |
20120275236 | Method and Apparatus for Power Domain Isolation during Power Down - An apparatus and method for isolating circuitry from one power domain from that of another power domain prior to performing a power down operation is disclosed. In one embodiment, circuitry in a first power domain is coupled to receive signals based on outputs from circuitry in a second power domain. The signals may be conveyed to the circuitry in the first power domain via passgate circuits. When powering down the circuitry of the first and second power domains, a control circuit may first deactivate the passgate circuits in order to isolate the circuitry of the first power domain from that of the second power domain. The circuitry in the second power domain may be powered off subsequent to deactivating the passgate circuits. The circuitry in the first power domain may be powered off subsequent to powering off the circuitry in the second power domain. | 2012-11-01 |
20120275237 | MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE - A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time. | 2012-11-01 |
20120275238 | MEMORY CIRCUIT AND CONTROL METHOD THEREOF - A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal. | 2012-11-01 |
20120275239 | MEMORY APPARATUS AND REFRESH METHOD THEROF - A memory apparatus includes a memory cell array comprising a plurality of memory cells connected with a plurality of bit lines and a plurality of word lines, a page buffer unit connected to the plurality of bit lines and latch data read from a memory cell selected from the plurality of memory cells, and a control unit configured to generate a refresh signal according to a prestored current status and provide the refresh signal to the page buffer unit in order to substantially prevent loss of the data latched by the page buffer unit. | 2012-11-01 |
20120275240 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a random address generation unit configured to receive a multi-bit source address and generate a multi-bit random address and a signal mixing unit configured to mix the multi-bit random address with a data, wherein the random address generation unit has a plurality of transmission lines configured to electrically connect the plurality of input terminals respectively corresponding to bits of the source address and the plurality of output terminals respectively corresponding to bits of the random address in one-to-one correspondence regardless of an order of the bits of the source address. | 2012-11-01 |
20120275241 | SEMICONDUCTOR MEMORY SYSTEM AND METHOD FOR DRIVING THE SAME - A method for driving a semiconductor memory device includes controlling a plurality of erase voltages for a plurality of memory blocks, respectively, comparing the plurality of controlled erase voltages, and determining whether or not to enable the plurality of memory blocks for a subsequent write operation in response to a result of the comparison. | 2012-11-01 |
20120275242 | VSS-SENSING AMPLIFIER - Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line. | 2012-11-01 |
20120275243 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first switch configured to couple a bit line to a first input/output line in response to an output selection signal including a pulse which is generated in response to a read command or write command; and a second switch configured to couple the first input/output line to a second input/output line in response to a switching control signal which is enabled after the output selection signal is enabled. | 2012-11-01 |
20120275244 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING FUSE CIRCUIT - A semiconductor integrated circuit includes: a fuse; a first driving unit configured to drive a sensing node in response to a first fuse sensing signal; a second driving unit configured to drive the sensing node in response to a second fuse sensing signal, wherein the second driving unit and the fuse form a driving path; a bypass resistor unit connected in parallel with the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node. | 2012-11-01 |
20120275245 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - A semiconductor device which is capable of high-speed writing with less power consumption and suitable for multi-leveled memory, and verifying operation. A memory cell included in the semiconductor device included a transistor formed using an oxide semiconductor and a transistor formed using a material other than an oxide semiconductor. A variation in threshold value of the memory cells is derived before data of a data buffer is written by using a writing circuit. Data in which the variation in threshold value is compensated with respect to the data of the data buffer is written to the memory cell. | 2012-11-01 |
20120275246 | MULTI-TEST APPARATUS AND METHOD FOR SEMICONDUCTOR CHIPS - An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods. | 2012-11-01 |
20120275247 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR REPAIRING THE SAME - A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses. | 2012-11-01 |
20120275248 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a memory block configured to have a normal cell array and a redundancy cell array; a column address buffer configured to compare a plurality of input column addresses with a fail column address signal-stored in a fuse array, and generate a column enable signal or a fail column enable signal; a column decoder configured to decode the column enable signal, and output a column selection signal to the normal cell array; and a column redundancy controller configured to generate a redundancy control signal in response to the fail column enable signal, generate a redundancy enable signal so as to reuse a redundancy bit line which has been substituted before according to the generated redundancy control signal, and output the generated redundancy enable signal to the redundancy cell array. | 2012-11-01 |
20120275249 | REDUNDANCY CIRCUITS AND OPERATING METHODS THEREOF - A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays. | 2012-11-01 |
20120275250 | SEMICONDUCTOR MEMORY DEVICE HAVING A DATA LINE SENSE AMPLIFIER - A memory device includes a data line sense amplifier configured to receive a sense amplifying power source voltage and a sense amplifying ground voltage through a sense amplifying power source line and a sense amplifying ground line, respectively, and sense-amplify data loaded on a pair of data lines, and a pre-charging unit configured to pre-charge and equalize the sense amplifying power source line and the sense amplifying ground line with a sense amplifying pre-charge voltage, generate the sense amplifying pre-charge voltage by voltage dividing the sense amplifying power source voltage and the sense amplifying ground voltage through a voltage dividing path including the sense amplifying power source line and the sense amplifying ground line, and apply the sense amplifying power source voltage to the sense amplifying power source line and the sense amplifying ground voltage to the sense amplifying ground line in response to a sense amplifying pre-charge control signal. | 2012-11-01 |
20120275251 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period. | 2012-11-01 |
20120275252 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT SWITCH TRANSISTORS - A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source. | 2012-11-01 |
20120275253 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PASS-GATE TRANSISTORS - A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-up transistors. | 2012-11-01 |
20120275254 | DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PRECHARGE TRANSISTORS - The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors. | 2012-11-01 |
20120275255 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE - A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof. | 2012-11-01 |
20120275256 | SEMICONDUCTOR DEVICE - A device may include, but is not limited to, a bit line; a power line supplied with a power voltage; a sense amplifier circuit amplifying a voltage of the bit line by using the power voltage of the power line; and a control circuit configured to respond to an active command and supply, as the power voltage, the power line with a first voltage during a first period and a second voltage lower than the first voltage during a second period. The control circuit is further configured to respond to a refresh command and supply, as the power voltage, the power line with the second voltage during both the first and second periods. | 2012-11-01 |
20120275257 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a first bit line section coupled to a first cell string, a second bit line section coupled to a second cell string, a page buffer coupled to the first bit line section and a switching circuit formed between the first bit line section and the second bit line section, wherein the switching circuit couples the first bit line section to second bit line section in response to a select signal. | 2012-11-01 |
20120275258 | MIXING TUMBLER - A mixing tumbler with two or more compartments, each designed to contain a different component used to prepare a desired mixture, which is structured so as to enable the user to initiate the collapse of the partitions between the compartments, enabling the components to mix and create the desired mixture. The mixing tumbler comprises a flask that is divided into two or more compartments, a cover, and separation discs between the said compartments. | 2012-11-01 |
20120275259 | MICROFLOW ANALYTICAL SYSTEM - A microflow analytical system includes a laminate pump assembly connectable with one or more sources of fluid, one or more pneumatic control pumps, a mixer, and a sensor. The laminate pump assembly is adapted to deliver predetermined volumes of the fluid(s) through a plurality of flow paths which are formed within layers of the assembly. Each flow path can include an inlet valve, a pump valve, and an outlet valve each of which are controllable by the pneumatic control pumps. A series of manifolds can be formed within the layers of the pump assembly to provide for simultaneous activation of selected flow paths. Delivered fluid volumes can be mixed in the mixer which, in some embodiments, may be integral with the laminate pump assembly. The sensor can measure one or more characteristics of the mixed fluids to determine one or more properties of the fluids. | 2012-11-01 |
20120275260 | MIXING APPARATUS - A mixing device has a frame, a cylindrical mixing container that is open toward the top, and a single-shaft agitator. A vertical agitator shaft extends into the mixing container from beneath. The agitator is an agitator without a stator and includes a rotor body arranged just above the container bottom in the mixing container. The rotor body is surrounded by a ring-shaped clearance between the rotor body and the container wall. Above the base plate fastened to the agitator shaft, the rotor body is provided with an inner clearance above the agitator shaft, mixing blades vertically arranged about the clearance, and flow channels arranged between the blades. The channels are delimited toward the top by a cover plate that is connected to the upper edges of the mixing blades. The cover plate is formed with a void arranged in the center and above the inner clearance. | 2012-11-01 |
20120275261 | BEAMFORMER, DIAGNOSTIC SYSTEM, MEDICAL IMAGE SYSTEM, AND METHOD FOR DISPLAYING DIAGNOSTIC IMAGE - A beamformer for forming a reception beam using a multichannel signal reflected from a subject is provided. The beamformer includes a signal generator that may generate a plurality of signals to which different apodization functions are applied, with respect to the multichannel signal, an estimator that may estimate a signal predominant component and a noise predominant component from the plurality of signals, a weight calculator that may calculate a weight to be applied to the signal predominant component according to each of channels, using the estimated signal predominant component and the estimated noise predominant component, and a weight applier that may apply the calculated weight to the estimated signal predominant component. | 2012-11-01 |
20120275262 | SECTION-ILLUMINATION PHOTOACOUSTIC MICROSCOPY WITH ULTRASONIC ARRAY DETECTION - Imaging systems, probes for imaging systems, and methods for noninvasive imaging are disclosed. In one example, a probe for use with an imaging system includes a slit configured to spatially filter a light beam from a light source. The probe includes a focusing device configured to cylindrically focus the spatially filtered light beam into an object, and an ultrasound transducer array configured to detect a photoacoustic signal emitted by the object in response to the cylindrically focused light beam. | 2012-11-01 |
20120275263 | METHOD FOR ADJUSTING THE SENSITIVITY OF ULTRASONIC SENSORS - A method for adjusting the sensitivity of ultrasonic sensors for detecting the distance of objects from a vehicle. A sensor sensitivity is set selected so that a sonic lobe is transmitted which has an intersection with the ground. A measurement is determined using the sensor, objects in the surroundings of the vehicle having a greater distance from the vehicle than the distance from the sensor to the intersection of the sonic lobe with the ground, so the distance from the sensor to the intersection of the lobe with the ground is detected as being the shortest distance from an object. The sensitivity of the sensor is set as a function of the distance between the sensor and the intersection of the lobe with the ground, so after sensitivity is set, the lobe, at its point closest to the ground, does not fall below a specified distance from the ground. | 2012-11-01 |
20120275264 | REMOVING FREE-SURFACE EFFECTS FROM SEISMIC DATA ACQUIRED IN A TOWED SURVEY - A technique includes towing a spread of at least one streamer to acquire seismic data in response to energy produced by a seismic source. The technique includes towing the seismic source at least 100 meters behind a front end of the spread to configure the spread to acquire a split spread gather record. | 2012-11-01 |
20120275265 | BUOY FOR MARINE SURVEYS - Buoy for marine surveys. At least some of the illustrated embodiments are a buoy including an elongated main body and a mast system coupled to the elongated main body. The mast system includes: a forward mast; an aft mast; a spanning portion coupled between a distal end of the forward mast and a distal end of the aft mast; and an aperture defined at least in part by the main body, forward mast, aft mast, and spanning portion. The buoy is configured to float in water such that the water level intersects the forward mast and aft mast, the elongated body is submerged, and the spanning portion resides above the water level. | 2012-11-01 |
20120275266 | SIMULTANEOUS CONVENTIONAL AND PHASE-ENCODED SEISMIC ACQUISITION - The invention relates to a process for two separate seismic crews to work in proximity to one another that would otherwise require expensive time sharing where one crew is a conventional seismic acquisition system and the other is a phase encoded seismic acquisition system. Typically, each recording system would receive seismic energy from the other that neither data set would be very useful. The invention primarily envisions some collaboration between the crews where each adjusts its sweeps to comprise a different time duration so that the energy the other crew's sources are distinguishable in the data set and easily eliminated therefrom. Distinctions may be further enhanced when the two crews use construct their sweeps so that each crew has a distinctly different start frequency and a distinctly different end frequency. | 2012-11-01 |
20120275267 | Seismic Data Processing - Provided is a method for processing seismic data. One exemplary embodiment includes the steps of obtaining a plurality of initial subsurface images; decomposing each of the initial subsurface images into components; identifying a set of components comprising one of (i) components having at least one substantially similar characteristic across the plurality of initial subsurface images, and (ii) components having substantially dissimilar characteristics across the plurality of initial subsurface images; and generating an enhanced subsurface image using the identified set of components. Each of the initial subsurface images is generated using a unique random set of encoding functions. | 2012-11-01 |
20120275268 | DEVICE AND METHOD FOR EXTRAPOLATING SPECULAR ENERGY OF REVERSE TIME MIGRATION THREE DIMENSIONAL ANGLE GATHERS - Computer instructions, computing device and method for processing seismic data under-sampled in an angle domain, the seismic data corresponding to a reverse time migration, three-dimensional, angle domain common image gather (ADCIG). The method includes receiving the seismic data; calculating, based on the seismic data, shot and receiver wave-fields with an RTM wave propagation engine; applying a wave-fields decomposition algorithm to obtain a propagation direction for the shot and receiver wave-fields; forming the ADCIG by applying an image condition to the shot and receiver wave-fields; determining that specular energies of the ADCIG are under-sampled around a reflection angle; during the step of forming the ADCIG, extrapolating the specular energies to a neighborhood of the reflection angle; and generating an image of a subsurface that is being surveyed based on the extrapolated specular energies. | 2012-11-01 |
20120275269 | METHOD AND SYSTEM FOR TRANSMISSION OF SEISMIC DATA - The transmission system combines a self-contained, wireless seismic acquistion unit and a wireless, line of site, communications unit to form a plurality of individual short-range transmission networks and also a mid-range, line of sight transmission network. | 2012-11-01 |
20120275270 | MEASUREMENT OF 3D COORDINATES OF TRANSMITTER - Implementations and techniques for measuring 3D coordinates of a transmitter using a receiver and a reflector are generally disclosed. The receiver may be attached asymmetrically to the reflector. | 2012-11-01 |
20120275271 | SYSTEMS AND METHODS FOR BLIND LOCALIZATION OF CORRELATED SOURCES - A system and a method for a blind direction of arrival estimation is provided for a nonlinear 1-dimensional array of M receivers of J2012-11-01 | |
20120275272 | WEARABLE SHOOTER LOCALIZATION SYSTEM - A wearable shooter localization system including a microphone array, processor, and output device for determining information about a gunshot. The microphone array may be worn by on the upper arm of the user. A second array, which may operate cooperatively or independently from the first array, may be worn on the other arm. The microphone array is sensitive to the acoustic effects of gunfire and provides a set of electrical signals to the processing unit, which identifies the origin of the fire. The system may include orientation and/or motion detection sensors, which the processor may use to either initially compute a direction to the origin of a projectile in a frame of reference meaningful to a wearer of the system or to subsequently update that direction as the wearer moves. | 2012-11-01 |
20120275273 | ACOUSTIC SURVEY METHODS IN WEAPONS LOCATION SYSTEMS - A survey method giving improvements in weapons fire location systems is disclosed. In an urban system with a distributed array in the midst of many buildings that block signal paths or create echoes, methods are provided to measure signal propagation. A survey or tour of the covered region uses a moving signal source to probe propagation inside the region. Survey results may indicate where more or fewer sensors are needed. Survey results plus current measured noise gives prediction of instantaneous system sensitivity. In addition, multipath propagation may be used to determine a location even when only one or two sensors detect the signal. In such exemplary cases, triangulation may be replaced or augmented by pattern recognition. Further, signals of the survey need not be acoustic impulses such as gunfire, but may be RF signals, or coded continuous signals so that gunfire-like sounds would not disturb citizens in the area. | 2012-11-01 |
20120275274 | ACOUSTIC TRANSPONDER FOR MONITORING SUBSEA MEASUREMENTS FROM AN OFFSHORE WELL - Sensor and communications systems for communicating measurements from subsea equipment, such as at an offshore well, to the surface. A sensor for a physical parameter, such as pressure or temperature at a blowout preventer, capping stack, or conduit in communication with the same, is electrically connected to a subsea acoustic transponder. An acoustic monitoring transponder deployed near the well periodically interrogates the acoustic transponder with an acoustic signal, in response to which the acoustic transponder transmits an acoustic signal encoded with the measurement. The measurement data are stored at the acoustic monitoring transponder. An acoustic communications device later interrogates the acoustic monitoring transponder to receive the stored measurement data for communication to a redundant network at the surface. | 2012-11-01 |
20120275275 | ANTI-ATTACHMENT DEVICE AND METHOD - Method and an anti-attachment device configured to be provided on a streamer. The anti-attachment device includes a body configured to be provided around the streamer and a first end is configured to be rotatably attached to the streamer. | 2012-11-01 |
20120275276 | ELECTRONIC TIMEPIECE - A power generation unit generates electric power depending on light to be irradiated to a light receiving surface. An electricity storage unit stores the electric power generated by the power generation unit and outputs the stored electric power. A voltage detection unit detects a voltage of the electric power that is output from the electricity storage unit. A processing unit performs time measurement. A chronograph indicator points a time counted by the processing unit and is fixed by a mechanism while the time measurement is stopped. A second driving circuit drives the chronograph indicator by the use of the electric power that is output from the electricity storage unit. The processing unit drives the second driving circuit when the voltage of the electric power which is output from the electricity storage unit is equal to or greater than a predetermined threshold value. | 2012-11-01 |
20120275277 | AUDIO MIXING METHOD AND AUDIO MIXING APPARATUS CAPABLE OF PROCESSING AND/OR MIXING AUDIO INPUTS INDIVIDUALLY - An audio mixing method includes: performing an audio processing operation upon a first audio input derived from at least one decoded audio input to generate a processed audio output, and generating a mixed audio signal by mixing at least a second audio input and the processed audio output. An audio mixing apparatus includes an audio processing circuit and an audio mixing circuit. The audio processing circuit is utilized for performing an audio processing operation upon a first audio input derived from at least one decoded audio input and accordingly generating a processed audio output. The audio mixing circuit is coupled to the audio processing circuit, and utilized for generating a mixed audio signal by mixing at least a second audio input and the processed audio output. | 2012-11-01 |
20120275278 | Systems and Methods for Data Write Loopback Based Timing Control - Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output. | 2012-11-01 |
20120275279 | Systems and Methods for Laser Write Control - Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted data write circuit is discussed that includes a heat write output, a magnetic write output, and a variable phase shift circuit operable to modify a relative phase of the heat write output to the magnetic write output. | 2012-11-01 |
20120275280 | THERMALLY-ASSISTED MAGNETIC RECORDING HEAD, HEAD GIMBAL ASSEMBLY AND MAGNETIC RECORDING DEVICE - A thermally-assisted magnetic recording head includes: a pole that generates a writing magnetic field from an end surface that forms a part of an air bearing surface that opposes a magnetic recording medium; a waveguide that propagates light to excite surface plasmon; and a plasmon generator that is provided between the pole and the waveguide and that generates near-field light from a near-field light generating end surface that forms a part of the air bearing surface by coupling with the light in a surface plasmon mode. The plasmon generator includes a flat plate part and a projection part that projects from the flat plate part to the waveguide side and is provided closer to a trailing side than the pole is. | 2012-11-01 |
20120275281 | DATA RECORDING AND REPRODUCING APPARATUS AND DATA LIBRARY DEVICE - A data recording and reproducing apparatus relative to a data library device includes a plurality of setup units for recording and reproducing data in a record and reproduction condition appropriate to a recording medium, and a storage unit for storing identification information and medium information of the recording medium, in this way, a setup processing is performed to reproduce the identification information from the recording medium when loading the recording medium, the medium information corresponding to the identification information is read out from the storage unit to perform the setup processing by a second setup unit when the medium information corresponding to the identification information is present in the storage unit, and the setup processing is performed by a third setup unit to reproduce the medium information from the recording medium and store in the storage unit together with the identification information, shortening a time period of the setup processing. | 2012-11-01 |
20120275282 | DEVICE AND METHOD FOR REPRODUCING DIGITAL SIGNAL AND DEVICE AND METHOD FOR RECORDING DIGITAL SIGNAL - A technique capable of realizing a power saving in a device for reproducing/recording digital signals by controlling a frequency of a clock. The device for reproducing/recording digital signals includes: a difference comparing circuit for comparing a first parameter updated each time a process for one correcting block is done in a demodulating circuit with a second parameter updated each time a process of one correcting block is done in an error correcting circuit; and a circuit for switching a frequency of a master clock depending on a comparison result of the difference comparing circuit. Thereby, the frequency of the clock can be switched both when the demodulation for one correcting block is ended and when the correcting process for one correcting block is ended by using the switched master clock. | 2012-11-01 |
20120275283 | RECORDABLE OPTICAL RECORDING CARRIER AND METHOD FOR MANUFACTURING RECORDABLE OPTICAL RECORDING CARRIER COMPATIBLE WITH CD-R - An optical recording carrier including, in a data recording area, a continuous-grooved main track for recording primary data to be stored, and a subtrack for recording control data including parameter data and address information. The control data includes a clock signal needless to be provided by the main track. The subtrack has a narrower full width at half maximum (FWHM) and a shallower depth than the main track. The distance between the main track and the subtrack is not more than half of that between two adjacent main tracks. The main track and the subtrack form a double-spiral pattern. When recording data, a recording spot tracks mostly along the centerline of the main track and reads the control data in the subtrack simultaneously to control the recording process. A method for manufacturing a recordable optical recording carrier compatible with a conventional CD-R is also provided. | 2012-11-01 |
20120275284 | OPTICALLY-READABLE ARTICLE WITH ELECTRO-OPTICAL ACCESS CONTROL DEVICE - An optically-readable disk includes a device that disrupts readability of the disk when the disk is spun at an angular velocity substantially greater than required to play the disk in its intended playing device, or when a defined integral of velocity and time is exceeded. The device may include a fluid container that disperses a data-disruptive fluid. The device may include a membrane or layer that is disrupted when the disk is rotated above a defined angular velocity, or when a defined integral of velocity and time is exceeded. The device may include an electro-optical material that is activated by an electrical signal from a controller in response to an input from a sensor responsive to motion of the disk. | 2012-11-01 |
20120275285 | Hard Disk Drives With Composite Housings and Related Methods - Improved hard disk drives of the invention comprise a composite housing, wherein the composite housing comprises a base and a cover, wherein at least a portion of the composite housing comprises a laminate of at least one rigid plastic layer and at least one metal coating. Methods for forming the same are also disclosed. | 2012-11-01 |
20120275286 | Hard Disk Drives Encapsulated With Polymeric Coatings and Related Methods - Improved hard disk drives of the invention comprise: a housing comprising an exterior surface; disk drive components enclosed within the housing for facilitating reading and recording of data at a desired location on at least one disk contained within the housing; and at least one continuous polymeric coating encapsulating the exterior surface of the housing. Methods of forming improved hard disk drives comprising a step of encapsulating the exterior surface of the hard disk drive housing with at least one polymeric coating are also disclosed. | 2012-11-01 |
20120275287 | Coupling of Hard Disk Drive Housing and Related Methods - A disk drive assembly of the invention comprises: a hard disk drive; a base; and a cover, wherein the base and the cover are mechanically coupled without using essentially any discrete mechanical fasteners to form an enclosed housing comprising internal hard disk drive components between the base and the cover and to irreversibly hermetically seal the hard disk drive. Methods for forming such disk drive assemblies are also disclosed. | 2012-11-01 |
20120275288 | OPTICAL DISC APPARATUS - An optical disc apparatus includes: a chassis; an optical pickup that is movably disposed on the chassis; a flexible member including wiring, which extends out from the optical pickup; and a wall portion that is provided in a standing manner at one end portion of the chassis. In the optical disc apparatus, an opening that allows the flexible member to be disposed in a bent state is formed through the chassis, and a first cutout is formed at the wall portion so as to be continuous with the opening. | 2012-11-01 |
20120275289 | LIGHT EMITTING DEVICE, OPTICAL PICKUP APPARATUS AND METHOD FOR MANUFACTURING THE SAME - In the present invention, to improve CD read/write characteristics having poor image height characteristics, a third light emitting source emitting a third laser beam for CD is disposed on an optical axis of an objective lens. Thereby, the third laser beam emitted from the third light emitting source travels along the optical axis of the objective lens, thus generating no coma aberration in the third laser beam. Furthermore, in the present invention, a second light emitting source emitting a second laser beam for DVD and a first light emitting source emitting a first laser beam for BD are disposed across the third light emitting source. Thereby the phase propagation directions of coma aberrations in the first and second laser beams coincide with each other. Adjustment of the coma aberration in one of the laser beams enables the coma aberration in the other laser beam to be adjusted. | 2012-11-01 |
20120275290 | LASER DIODE WRITE DRIVER - A laser diode write driver is described. This laser diode write driver comprises: a feedback loop coupled for receiving an input current signal, the feedback loop operative for reaching a steady state and comprising a Class AB driver in series with a Class A driver, wherein the feedback loop transmits a first current signal; a current mirror adapted to receive the first current signal, the current mirror operative for replicating the first current signal and transmitting a second current signal; a differential device adapted to receive the second current signal, the differential device operative for steering current in at least one direction and transmitting a first voltage signal; a second class AB driver adapted to receive the first voltage signal and transmit a first drive signal, a second Class A driver adapted to receive the first drive signal and transmit a second drive signal; and an output device coupled to the second drive signal and operative for transmitting a driver output signal that drives the light source in response to receiving the second drive signal. | 2012-11-01 |
20120275291 | WIRELESS COMMUNICATION APPARATUS AND WIRELESS COMMUNICATION METHOD - By using a discrete Fourier transform equation that is used to transform N data values (N is an integer equal to or greater than one) to N transformation values, a wireless communication apparatus calculates three continuous transformation values from the N data values. Then, the wireless communication apparatus obtains a fixed change in the phase difference from the three calculated transformation values; multiplies the calculated transformation value by a twiddle factor that is obtained from the change in the phase difference; and calculates not-yet calculated transformation values. | 2012-11-01 |
20120275292 | WIRELESS EEG DATA RECOVERY - A system and method can have an electroencephalographic (EEG) recording module and a host device. The EEG recording can have a memory module configured to record EEG signals from a patient and a wireless transceiver configured to wirelessly transmit the EEG signals as packets. The host device can have a wireless transceiver configured to wirelessly receive at least some of the packets transmitted by the recording module wireless transceiver and a processor configured to identify one or more missing packets. Upon a completion of transmission of the packets, the host device is configured to wirelessly transmit an identity of missing packets to the recording module wireless transceiver. Upon receiving the identity of the missing packets, the recording module wireless transceiver is configured to wirelessly transmit packets including the EEG signals corresponding to the missing packets to the host device. | 2012-11-01 |
20120275293 | METRO ETHERNET CONNECTIVITY FAULT MANAGEMENT ACCELERATION - In an Ethernet network element comprising at least one line interface element and a central processing unit (CPU) to control forwarding of data packets at the network element, a method comprising receiving continuity check messages (CCMs) at the at least one line interface element, and processing the CCMs in the at least one line interface element to provide continuity checks for connections to the network element without requiring processing of CCMs by the CPU. | 2012-11-01 |
20120275294 | RECOVERING FROM FAILURES WITHOUT IMPACT ON DATA TRAFFIC IN A SHARED BUS ARCHITECTURE - Methods of detecting and recovering from communication failures within an operating network switching device that is switching packets in a communication network, and associated structures. The communication failures addressed involve communications between the packet processors and a host CPU over a shared communications bus, e.g., PCI bus. The affected packet processor(s)—which may be all or a subset of the packet processors of the network switch—may be recovered without affecting hardware packet forwarding through the affected packet processors. This maximizes the up time of the network switching device. Other packet processor(s), if any, of the network switching device, which are not affected by the communication failure, may continue their normal packet forwarding, i.e., hardware forwarding that does not involve communications with the host CPU as well as forwarding or other operations that do involve communications with the host CPU. | 2012-11-01 |
20120275295 | BANDWIDTH GUARANTEED SYSTEM, RADIO NODE DEVICE AND BANDWIDTH GUARANTEEING METHOD - To establish an alternative path without giving an influence on signal continuity to a data transmission line to which a communication bandwidth cannot be secured any more when the transmission capacity decreased by adaptive modulation. | 2012-11-01 |
20120275296 | Protection Switching Method and System for Ethernet Dual-homed Link - The disclosure provides a protection switching method for an Ethernet dual-homed link, which comprises: a node on one path of a dual-homed link detects that a failure occurs in a link or node which is directly connected with the node per se; when the node which detects the failure is a non-master node, the non-master node continuously transmits N failure state protocol (SF) messages outwards through a non-failed port on the failure path; after receiving the SF messages, the master node switches traffic on the failure path to an available path. The disclosure further provides another protection switching method for an Ethernet dual-homed link and a protection switching system for an Ethernet dual-homed link. By means of the disclosure, when a failure occurs in a link or node, a fast protection switching for the Ethernet dual-homed link can be realized; moreover, when the link or node recovers from the failure, a fast backward switching for the Ethernet dual-homed link can be realized as required actually. | 2012-11-01 |
20120275297 | Multi-Chassis Link Aggregation on Network Devices - A data communication network includes a client device and multiple aggregation devices coupled to each other and the client via links within a link aggregation group (“LAG”) across the aggregation devices. The aggregation devices appear to the client as a single device coupled thereto, and operate in conjunction with each other by assigning at least one different identifier to each of the plurality of separate aggregation devices and storing information including the identifiers to association tables located on each of the aggregation devices. The multiple aggregation devices can be separate switches, and the LAG can include multiple ports across the switches, with a different identifier being assigned to each of the ports in the LAG. A virtual link trunk interface can couple aggregation devices, which can reconfigure communication paths thereacross with respect to the client device using the identifiers in the stored association tables when a LAG link fails. | 2012-11-01 |
20120275298 | Constructing A Transition Route In A Data Communications Network - A method is described of constructing a transition route in a data communication network having as components nodes and links. Upon receipt of a transition notification identifying a first component a non-neighboring node constructs a transition route around the first component. In an embodiment, a node performs detecting the first component transition; issuing a transition notification identifying the first component and recognizable by nodes configured to construct a transition route around the first component; and upon expiry of a notification transition period, issuing a transition advertisement recognizable by all nodes on the network. | 2012-11-01 |
20120275299 | METHODS AND SYSTEMS TO REROUTE DATA IN A DATA NETWORK - A disclosed example method involves determining a first quality of service parameter associated with a failed logical circuit, and a second quality of service parameter associated with a logical failover circuit. When the first quality of service parameter is equal to or less than the second quality of service parameter, data from the failed logical circuit is rerouted to the logical failover circuit without requiring authorization from a customer to communicate the data at the second quality of service parameter. When the second quality of service parameter is a lower level of quality than the first quality of service parameter, the customer is prompted for authorization to communicate the data via the logical failover circuit at the second quality of service parameter. When authorization is received, the data is rerouted to the logical failover circuit. When authorization is denied, the data is not rerouted to the logical failover circuit. | 2012-11-01 |
20120275300 | SERVICE EVENT TRIGGER - A Policy and Charging Enforcement Function (PCEF) node for a telecommunications network has a service traffic detector, for performing service traffic detection during a session. A processor detects a predetermined service condition from said service traffic detection. The PCEF notifies a Policy and Charging Rule Function (PCRF) of the detected service condition by means of a service event defined in an Event Trigger AVP over a Gx reference point. The PCRF receives the notification of the detected service condition, and controls the service provision in response to the detected service condition, for example by controlling the Quality of Service applied to the service. | 2012-11-01 |
20120275301 | Port and Priority Based Flow Control Mechanism for Lossless Ethernet - An apparatus comprising an aggregation/core switch configure to couple to an edge switch and receive information about a plurality of end system facing ports of the edge switch, wherein the information about the end system facing ports is used to associate the end system facing ports with a plurality of corresponding queues at the aggregation/core switch. Also disclosed is a network component comprising a receiver configured to receive information about a plurality of end system facing ports of an edge switch, a processor configured to establish and associate the end system facing ports with a plurality of corresponding queues, and a transmitter configured to return information about the associated end system facing ports. | 2012-11-01 |
20120275302 | FREE MARKET BASED PRICING FOR BANDWIDTH AND NETWORK USAGE - The disclosed embodiments include a system and method for establishing a price for communicating over a communications network. In one embodiment, the system includes a plurality of network nodes configured to communicate over the communications network and a primary network edge node configured to provide network access to a plurality of end user devices. The primary network edge node is configured to initiate a bandwidth occupancy query message to at least one of said network nodes along a traffic path to which an end user device is communicating, determine a highest bandwidth occupancy of said network nodes along the traffic path, and compute a current price for the end user device communicating over the traffic path based on the highest bandwidth occupancy. | 2012-11-01 |
20120275303 | METHOD, DEVICE, AND NETWORK SYSTEM OF ESTABLISHING A TUNNEL - A method, a device, and a network system of establishing a tunnel are provided in embodiments of the present disclosure. The method of establishing the tunnel includes: obtaining, by a WTP, an address of an AC and an address of a BRAS from a DHCP server; using, by the WTP, the address of the AC to establish a CAPWAP control tunnel with the AC; and using, by the WTP, the address of the BRAS to establish a CAPWAP data tunnel with the BRAS. By using the technical scheme provided in the embodiments of the present disclosure, the CAPWAP data tunnel may be established between the WTP and the BRAS. | 2012-11-01 |
20120275304 | HIERARCHICAL PROFILED SCHEDULING AND SHAPING - Various exemplary embodiments relate to a method and related network node including one or more of the following: determining, by the network node, that a port of the network node is ready to receive a packet; identifying a packet having a highest packet priority among a plurality of packets received via a plurality of interfaces, wherein the step of identifying includes, for each of a plurality of components at a first hierarchy level: identifying a first level highest priority packet among a plurality of packets available to the component, based on a packet priority associated with each of the plurality of packets available to the component, sharing the packet priority of the first level highest priority packet with at least one component at a second hierarchy level; and transmitting the packet having the highest priority to the port. | 2012-11-01 |
20120275305 | PRIORITIZED RANDOM ACCESS METHOD, RESOURCE ALLOCATION METHOD AND COLLISION RESOLUTION METHOD - A prioritized random access method, a resource allocation method, and a collision resolution method are proposed for wireless communication devices with different priority levels pre-assigned according to their respective service requirements. In the prioritized random access method, different priorities are assigned to connection requirements of wireless communication devices according to their respective service characteristics. Collision resolution mechanisms of the prioritized random access method enable establishing connections of different service requirements such as time strict, delay tolerant, and normal user service. The resource allocation method allows different types of contention accesses have different collision opportunities and connection setup delays, and also enables dynamical adjustment in resource allocation according to practical application requirements, the number of MTC devices and system loading. Thus, resource utilization rate of the overall wireless communication network is enhanced. | 2012-11-01 |
20120275306 | NETWORK ASSESSMENT AND SHORT - TERM PLANNING PROCEDURE - A method for relieving network node congestion includes determining a moving average of an aggregated load on a network node that routes network traffic using historical data for a period of time for a portion of a communication network that includes the network node. Demand on the network node is projected based on the moving average. A current level of congestion on the network node is determined. A level of congestion on the network node is projected based on the projected demand and the current level of congestion. Available capacity of other network nodes in the portion of the communication network is estimated. A determination is made whether the projected level of congestion can be relieved using the estimated available capacity of the other network nodes. The communication network is reconfigured to relieve the projected level of congestion when the projected level of congestion can be relieved. | 2012-11-01 |
20120275307 | METHODS AND APPARATUS FOR FLOW-CONTROLLABLE MULTI-STAGED QUEUES - In one embodiment, a method includes sending a first flow control signal to a first stage of transmit queues when a receive queue is in a congestion state. The method also includes sending a second flow control signal to a second stage of transmit queues different from the first stage of transmit queues when the receive queue is in the congestion state. | 2012-11-01 |
20120275308 | Data Link Layer Tunneling Technique for High-Speed Data in a Noisy Wireless Environment - A data link layer tunneling technique improves the throughput of high speed data in noisy wireless environments. Recovering lost frames transmitted between a packet sending unit and a packet receiving unit in a data communications system generally comprises (a) identifying a failure to successfully receive a missed frame at the packet receiving unit; (b) establishing a logical tunnel channel at the packet receiving unit to acknowledge the next successfully received frame; (c) starting a first timer at the packet receiving unit; (c) upon receiving a tunnel establishment request from the packet receiving unit, the packet sending unit resending the missed frame on the logical tunnel channel and starting a second timer; and (d) the packet sending unit resending the missed frame a specified number of times until receiving an acknowledgement from the packet receiving unit. | 2012-11-01 |
20120275309 | ROUTING COST NORMALIZING - A computing device ranks multiple routing pairs based on a current routing configuration for weighted links in a network, and ranks the multiple routing pairs based on a proposed routing configuration, different than the current routing configuration, for the weighted links in the network. The computing device compares a current rank order of a first routing pair and a second routing pair in the multiple routing pairs with a proposed rank order of the first routing pair and the second routing pair. The computing device identifies a change between the current rank order and the proposed rank order and generates a data structure that indicates the identified change between the current rank order and the proposed rank order for the first routing pair and the second routing pair. | 2012-11-01 |
20120275310 | METHOD AND APPARATUS FOR CONTROLLING THE APPLICATION OF SELECTED IP TRAFFIC OFFLOAD AND LOCAL IP ACCESS - A method and apparatus are described for controlling the application of Selected Internet Protocol (IP) traffic offload (SIPTO) or Local IP Access (LIPA) services for a wireless transmit/receive unit (WTRU). The SIPTO and LIPA services may be performed over packet data network (PDN) connections. A user of the WTRU may be prompted to accept or reject the usage of the SIPTO or LIPA services. The user of the WTRU may request switching from SIPTO or LIPA services to non-SIPTO or non-LIPA services. | 2012-11-01 |
20120275311 | Automatic Network Topology Detection and Modeling - A method and system for identifying the topology of a network is disclosed. One or more monitoring probes capture data packets from network interfaces. Network elements, such as physical ports, physical links, network nodes, logical links, and SCTP associations, are identified from the captured data packets. A data model is created for storing the network elements, including the physical ports, physical links, network nodes, logical links, and SCTP associations. The data model also stores associations between the network elements. The monitoring probes pass network element data to a monitoring server. A topology agent in each monitoring probe identifies duplicates of previously detected network elements within the probe. A topology agent in the monitoring system server identifies duplicates of previously detected network elements within the monitoring system server. | 2012-11-01 |
20120275312 | Transmission of the PDP Context Activation Rejection Cause Codes to the UICC - A method and system for introducing support for SM rejections in a USAT network rejection event including an APN. The method and system provide the UICC with all PDP Context activation rejection cause codes received by the ME and their respective APNs. Such a method and system allows the UICC to monitor all the rejections to intelligently select an appropriate APN to activate using its Open channel command. | 2012-11-01 |
20120275313 | Enhancement of Download Multi-User Multiple-Input Multiple-Output Wireless Communications - A method implemented in a user equipment configured to be used in a multi-user (MU) multiple-input multiple-output (MIMO) wireless communications system is disclosed. In an aspect, the user equipment transmits to a base station a first channel state information (CSI) report determined according to a single-user (SU) MIMO rule and a second CSI report based on a residual error. | 2012-11-01 |
20120275314 | Enhancement of Download Multi-User Multiple-Input Multiple-Output Wireless Communications - A method implemented in a user equipment configured to be used in a multi-user (MU) multiple-input multiple-output (MIMO) wireless communications system is disclosed. In an aspect, the user equipment transmits to a base station a first channel state information (CSI) report determined according to a single-user (SU) MIMO rule and a second CSI report determined according to an MU-MIMO rule. | 2012-11-01 |
20120275315 | PHYSICAL-LAYER CELL IDENTITY (PCI) CONFLICT DETECTION - Physical layer cell identity (PCI) misconfiguration in a self-organizing network (SON) ( | 2012-11-01 |
20120275316 | Failure Detection Method and Device for FCoE Virtual Link - A failure detection method and device for a FCoE virtual link. A first FCoE devices receives a Keep Alive Request packet from a Transmit switch, the Keep Alive Request packet having a response period; in response to receiving the Keep Alive Request packet, the first FCoE device creates a virtual link aging timer, configures expiration time of the timer according to the response period, and transmits a packet for maintaining the FCoE virtual link to a second FCoE device. If the first FCoE device does not receive a packet for maintaining the FCoE virtual link returned by the second FCoE device by the time the timer expires, the first FCoE device detects that the FCoE virtual link between the first FCoE device and the second FCoE device is in failure. | 2012-11-01 |
20120275317 | TIMING OVER PACKET DEMARCATION ENTITY - Apparatus for monitoring a packet switched network, the apparatus comprising: at least one port for receiving and transmitting packets; a local clock; and a packet inspector that uses time from the local clock to timestamp packets received at a port of the at least one port, and additionally copies timing information from received timing distribution packets, which are transmitted from a master clock to a slave clock in order to discipline the slave clock, and forwards the received packets for transmission from a port of the at least one port; wherein the apparatus uses the timestamp of a received timing distribution packet and the copied timing information to monitor timing distribution performance of the network . | 2012-11-01 |
20120275318 | METHOD FOR SELECTIVELY SHARING A COMMUNICATION CHANNEL BETWEEN COORDINATION AND INTERFERENCE - A method for sharing a communication channel between a first network and a second network. The method includes transmitting a signal from the second network to the first network in response to the second network detecting presence of the first network. The signal includes a predetermined sequence measuring the strength of the signal arriving at the first network and transmitting a unification request from the first network to the second network when a metric based on the measured strength is less than a unification threshold. The unification request invites the second network to coordinate operation with the first network to reduce interference between the first network and the second network. | 2012-11-01 |
20120275319 | CONCURRENT TRANSMISSION OF WI-FI AND BLUETOOTH SIGNALS - A method and device for concurrently transmitting a Wi-Fi signal and a Bluetooth signal via a common power amplifier and antenna. A first set of values indicative of transmission power levels of a Wi-Fi signal and a corresponding set of values indicative of transmission power levels of a BT signal are stored in a table. Information about activities pertaining to the BT signal including a value of a transmission power level of the BT signal is received. Based on the received value of the transmission power level of the BT signal, a corresponding value of a transmission power level of the Wi-Fi signal may be looked up from the table. Transmission of one or more of the Wi-Fi or BT signals may be controlled, based on at least one of the received information or the looked-up value of the transmission power level of the Wi-Fi signal. | 2012-11-01 |
20120275320 | SIGNAL STRENGTH AWARE BAND STEERING - A system or method that receives a current request from a client, and responds to the current request based on signal strength associated with a previous request. If the current request is received on a non-preferred communication band, and a previous request was received on a preferred communication band within a pre-determined time, the system determines whether the signal strength associated with the previous request is weaker than a pre-determined threshold signal strength level for the preferred communication band. If so, the system responds to the current request. Otherwise, the system ignores the current request. If no recent request on the preferred communication band is received, and the signal strength associated with the current request is weaker than a pre-determined threshold signal strength level for the non-preferred communication band, the system responds to the current request on the non-preferred communication band. Otherwise, the system ignores the current request. | 2012-11-01 |
20120275321 | APPARATUS AND METHOD FOR ARBITRATION OF UPDATES PROVIDED TO A UNIVERSAL INTEGRATED CIRCUIT CARD - Systems and methodologies are described that determine whether to communicate an update message to a UICC. A UE may be equipped a status update message from at least one of a first radio access technology (RAT) module supporting a first RAT and a second RAT module supporting a second RAT. The first RAT and the second RAT are different. Further, the UE may be equipped to determine whether to generate a universal integrated circuit card (UICC) update message to update a UICC by applying one or more RAT arbitration factors to the received status update message. The UICC includes current UICC status information associated with a current RAT. A status update message may include, a service status, RAT information, and location information, and the UE may apply the RAT arbitration factors to at least a portion of the status update message. | 2012-11-01 |
20120275322 | METHOD AND APPARATUS FOR RESTRICTED MEASURING IN A WIRELESS NETWORK - Methods and apparatuses are provided that include determining resources over which to measure signals from a base station. One or more parameters related to a resource restriction pattern can be provided to the device for measuring signals over indicated resources. The resource restricted pattern can correspond to a bitmap where each bit relates to a time period over which signals can be transmitted by the base station, and the bit can specify whether a signal received over the resource should be measured. The resource restriction pattern can correspond to a set or protected resources negotiated using a resource partitioning scheme. | 2012-11-01 |
20120275323 | SCALABLE POLICY-CONTROLLED PACKET INSPECTION SYSTEMS AND METHODS FOR ADVANCED APPLICATION INTERFACE - Systems, methods, and instrumentalities are disclosed to determine quality of service information. A device, such as a user equipment (UE), may receive a policy. The policy may indicate a level of inspection relating to application identification for a session. The device may receive information associated with the session. For example, the information may include application provided information, packet data, operating system provided information, etc. The device may perform an inspection of the received information at the level indicated by the policy. The device may perform the inspection in order to identify an application associated with the session. | 2012-11-01 |
20120275324 | PACKET TRANSMISSION SYSTEM AND PACKET RECEPTION SYSTEM - This invention provides a simultaneous packet transmission system and a simultaneous packet reception system which enable a reception side to receive simultaneous packets without transmitting a retransmission request to retransmit discarded simultaneous packets even if part of simultaneous packets are discarded. A wireless LAN base station multicasts a simultaneous packet which is obtained by allocating a sequence number to a LAN packet a plurality of times. If a wireless LAN terminal receives the same simultaneous packets a plurality of times, the wireless LAN terminal discards duplicated simultaneous packets and leaves only one simultaneous packet. Since the simultaneous packet is multicast a plurality of times, the wireless LAN terminal can receive the simultaneous packet as long as all the same simultaneous packets are not lost. | 2012-11-01 |
20120275325 | COMMUNICATION APPARATUS AND METHOD - In a communication apparatus, based on the relationship among a first port for outputting frames including tag information, a frame destination address, and bandwidth specified to the first port, a controller generates threshold value information to be associated with a second port to which the frames including tag information are input. With respect to the frames input from the second port, a reception processor measures a reception rate according to the tag information and the frame destination address, and selects, based on the reception rate and the threshold value information, frames to be preferentially discarded at the first port. | 2012-11-01 |
20120275326 | Non-Beacon Network Communications Using Frequency Subbands - Systems and methods for designing, using, and/or implementing non-beacon network communications using frequency subbands are described. In various implementations, these systems and methods may be applicable to Power Line Communications (PLC). For example, a method may include transmitting a beacon request message over a given one of a plurality of frequency subbands, receiving a plurality of beacons in response to having transmitted the beacon request message, each of the plurality of beacons received over a respective one of the plurality of frequency subbands, and calculating a downlink quality report based, at least in part, upon the received beacons. The method may also include transmitting the downlink quality report over each of the plurality of frequency subbands and receiving a subband allocation command in response to having transmitted the downlink quality report, the subband allocation command indicating a downlink subband assignment and an uplink subband assignment. | 2012-11-01 |