44th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120273827 | LIGHT EMITTING DIODE - A light emitting diode includes a first semiconductor layer, an active layer, a second semiconductor layer, an upper electrode, and a lower electrode. The active layer is sandwiched between the first semiconductor layer and the second semiconductor layer. The lower electrode is electrical connected with the first semiconductor layer, and the upper electrode is electrical connected with the second semiconductor layer. A surface of the second semiconductor layer away from the active layer is used as the light extraction surface. A surface of the first semiconductor layer connected with the lower electrode is a patterned surface comprising a plurality of grooves. | 2012-11-01 |
20120273828 | LIGHT EMITTING DIODE - A light emitting diode includes a substrate, a first semiconductor layer, an active layer and a second semiconductor layer. The first semiconductor layer, the active layer and the second semiconductor layer are stacked on one side of the substrate in that order. The first semiconductor layer is oriented to the substrate. A number of channels are defined between the first semiconductor layer and the substrate. | 2012-11-01 |
20120273829 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODES AND LIGHT EMITTING DIODES OBTAINED THEREBY - A method for manufacturing LEDs includes following steps: forming circuit structures on a substrate, each circuit structure having a first metal layer and a second metal layer formed on opposite surfaces of the substrate and a connecting section interconnecting the first and second metal layers; cutting through each circuit structure along a middle of the connecting section to form first and second electrical connecting portions insulated from each other via a gap therebetween; arranging LED chips on the substrate and electrically connecting the LED chips to the first and second electrical connecting portions; forming an encapsulation on the substrate to cover the LED chips; and cutting through the substrate and the encapsulation between the first and second electrical connecting portions of neighboring circuit structures to obtain the LEDs. | 2012-11-01 |
20120273830 | LIGHT EMITTING DIODE CHIP AND METHOD OF MANUFACTURING THE SAME - An LED chip includes a substrate, a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first electrode and a second electrode formed on the substrate in sequence. A surface of the first type semiconductor layer away from the substrate comprises an exposed first area and a second area covered by the light-emitting layer. The first electrode is formed on the exposed first area of the substrate. A number of recesses are defined in the second area of the surface of the first type semiconductor layer. The recesses are spaced apart from each other and arranged in sequence in a direction away from the first electrode; depths of the recesses gradually decrease following an increase of a distance between the recesses and the first electrode. The second electrode is formed on the second type semiconductor layer. | 2012-11-01 |
20120273831 | SEMICONDUCTOR DEVICE, PROCESS FOR PRODUCING SAME, AND DISPLAY DEVICE | 2012-11-01 |
20120273832 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package and a method for manufacturing the same are provided. The light emitting device package comprises a package body comprising a cavity at an upper portion; a first and second metal layers on the cavity of the package body; an open area recessed in the cavity; a first metal plate disposed in the open area and spaced apart from the first and second metal layers; a semiconductor device disposed on the first metal plate and electrically connected to at least one of the first and the second metal layers; and a resin material in the cavity. | 2012-11-01 |
20120273833 | Light Emitting Diode Package - A light emitting diode (LED) package including a carrier, a housing, at least one LED chip and at least one electrostatic discharge protector (ESD protector) is provided. The housing encapsulating a portion of the carrier has at least one first opening, at least one second opening and a barricade. The barricade separates the first opening from the second opening. The first opening and the second opening expose a first surface of the carrier. The LED chip is disposed on the first surface of the carrier, located in the first opening, and electrically connected to the carrier. The ESD protector is disposed on the first surface of the carrier, located in the second opening, and electrically connected to the carrier. | 2012-11-01 |
20120273834 | LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE - An object is to provide a light-emitting device having a structure in which an external connection portion can easily be connected and a method for manufacturing the light-emitting device. A light-emitting device includes a lower support | 2012-11-01 |
20120273835 | LED PACKAGE WITH TOP-BOTTOM ELECTRODE - An LED package with an extended top electrode and an extended bottom electrode is made from a single metal sheet, one manufacturing process embodiment includes: preparing a piece of single metal sheet, forming a first metal and a coplanar second metal, mounting an LED on an inner end of the first metal, wire-bonding top electrode to an inner end of the second metal, encapsulating at least the LED and the bonding wire with a protection glue, bending an outer end of the first metal upward twice 90 degrees to form a top flat as an extended top electrode of the package, and bending an outer end of the second metal downward twice 90 degrees to form a bottom flat as an extended bottom electrode of the package. | 2012-11-01 |
20120273836 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a transistor region including an IGBT having a gate electrode and an emitter electrode; a termination region placed around the transistor region; and an extraction region placed between the transistor and the termination region and extracting redundant carriers. A P-type layer is placed on an N-type drift layer in the extraction region. The P-type layer is connected to the emitter electrode. A dummy gate electrode is placed via an insulation film on the P-type layer. The dummy gate electrode is connected to the gate electrode. Life time of carriers in the termination region is shorter than life time of carriers in the transistor region and the extraction region. | 2012-11-01 |
20120273837 | SOLID STATE IMAGING DEVICE - According to one embodiment, a solid state imaging device includes a photoelectric converting portion including a semiconductor region and a semiconductor film. The semiconductor region has a first region and a second region. The first region is of a second conductivity type. The first region is provided in a semiconductor substrate. The second region is of a first conductivity type. The first conductivity type is a different conductivity type from the second conductivity type. The second region is provided on the first region. The semiconductor film is of the second conductivity type. The semiconductor film is provided on the semiconductor region. An absorption coefficient of a material of the semiconductor film to a visible light is higher than an absorption coefficient of a material of the semiconductor substrate to the visible light. A thickness of the semiconductor film is smaller than a thickness of the semiconductor region. | 2012-11-01 |
20120273838 | MINORITY CARRIER BASED HgCdTe INFRARED DETECTORS AND ARRAYS - Disclosed are minority carrier based mercury-cadmium telluride (HgCdTe) infrared detectors and arrays, and methods of making, are disclosed. The constructions provided by the invention enable the detectors to be used at higher temperatures, and/or be implemented on less expensive semiconductor substrates to lower manufacturing costs. An exemplary embodiment a substrate, a bottom contact layer disposed on the substrate, a first mercury-cadmium telluride layer having a first bandgap energy value disposed on the bottom contact layer, a second mercury-cadmium telluride layer having a second bandgap energy value that is greater than the first bandgap energy value disposed on the first mercury-cadmium telluride layer, and a collector layer disposed on the second mercury-cadmium telluride layer, wherein the first and second mercury-cadmium telluride layers are each doped with an n-type dopant. | 2012-11-01 |
20120273839 | SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING PHOTO-ELECTRIC CONVERSION DEVICE - A semiconductor wafer includes a base wafer, a sacrificial layer that is lattice-matched or pseudo lattice-matched to the base wafer, a first crystal layer that is formed on the sacrificial layer and made of an epitaxial crystal of Si | 2012-11-01 |
20120273840 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are disclosed. The method comprises: disposing a first dielectric material layer on a first semiconductor layer and defining openings in the first dielectric material layer; epitaxially growing a second semiconductor layer on the first semiconductor layer via the openings defined in the first dielectric material layer, wherein the second semiconductor layer and the first semiconductor layer comprise different materials from each other; and forming plugs of a second dielectric material in the second semiconductor layer at positions where the openings are defined in the first dielectric material layer and also at middle positions between adjacent openings. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed. | 2012-11-01 |
20120273841 | Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same - A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell. | 2012-11-01 |
20120273842 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line. | 2012-11-01 |
20120273843 | SEMICONDUCTOR MEMORY DEVICE AND REPAIR METHOD THEREOF - A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip. | 2012-11-01 |
20120273844 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic random access memory includes a first gate electrode and a second gate electrode arranged at a predetermined pitch in a first direction, and extending in a second direction perpendicular to the first direction, a first magnetoresistive element formed above a portion between the first gate electrode and the second gate electrode, an electrode layer formed in a position higher than the first magnetoresistive element, and formed to have a distance which is a half of the pitch from the first magnetoresistive element in the first direction, an interconnection formed in a position higher than the electrode layer, and extending in the first direction, and a first via which connects the first magnetoresistive element and the interconnection, and the electrode layer and the interconnection, by using one conductive layer. | 2012-11-01 |
20120273845 | ELECTRONIC PH SENSOR DIE PACKAGING - A pH sensor is provided. The pH sensor comprises a substrate and an ion sensitive field effect transistor (ISFET) die comprising an ion sensing part that responds to pH, wherein the ISFET die is located over the substrate. The pH sensor also comprises a protective layer formed over at least a portion of an outer surface of the ISFET die and at least a portion of the substrate. Further, the pH sensor comprises a cover member mechanically coupled to the protective layer, wherein the cover member houses the ISFET die and the substrate, and wherein the cover member defines an opening proximate to the ion sensing part. | 2012-11-01 |
20120273846 | Sensor for Detecting a Component of a Gas Mixture - A sensor for detecting a first component in a gas mixture is disclosed having a gas-sensitive electrode and a catalyst which is arranged on and/or spaced apart from the electrode in a porous carrier ceramic. The catalyst has the effect that a second component in the gas mixture is chemically altered such that the component contributes to no substantial change in the potential of the electrode. | 2012-11-01 |
20120273847 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device achieved by the method has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a { 100} crystallographic plane of the substrate. | 2012-11-01 |
20120273848 | BORDERLESS CONTACT STRUCTURE EMPLOYING DUAL ETCH STOP LAYERS - Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed. | 2012-11-01 |
20120273849 | Electronic Module Metalization System, Apparatus, and Methods of Forming Same - Embodiments of electronic module metallization systems and apparatus and methods for forming same are described generally herein. Other embodiments may be described and claimed. | 2012-11-01 |
20120273850 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are disclosed. A fin of the semiconductor device including a fin-shaped channel region is configured in the form of a non-uniform structure, and a leakage current caused by the electric field effect generated in the semiconductor device is prevented from being generated, resulting in an increased operation stability of the semiconductor device. | 2012-11-01 |
20120273851 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device includes forming a structure comprising an interlayer dielectric layer on a substrate, an ultra-low-k material layer on the interlayer dielectric layer and a plug. The plug passes through the interlayer dielectric layer and the ultra-low-k material layer, and is formed of a first metal material. The method further includes removing an upper portion of the plug by etching to form a recessed portion, and filling the recessed portion with a second metal material. According to the method, contact-hole photolithography is performed only once, and thus avoids alignment issues that may occur when contact-hole photolithography needs to be performed twice. | 2012-11-01 |
20120273852 | TRANSISTORS HAVING TEMPERATURE STABLE SCHOTTKY CONTACT METALS - A semiconductor structure having: a semiconductor comprising a indium gallium phosphide and molybdenum metal in Schottky contact with the semiconductor. | 2012-11-01 |
20120273853 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area. | 2012-11-01 |
20120273854 | GLOBAL SHUTTER PIXEL WITH IMPROVED EFFICIENCY - A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer. | 2012-11-01 |
20120273855 | UNIT PIXEL, AND CMOS IMAGE SENSOR HAVING THE SAME - A unit pixel of a CMOS image sensor include a photodiode that transforms light to an electric charge, and accumulates the electric charge, and a plurality of transistors that generate an electric signal based on the accumulated electric charge. The photodiode has a slope shape based on incident angle of the light in a semiconductor substrate. | 2012-11-01 |
20120273856 | TUNNELING MAGNETORESISTIVE EFFECT ELEMENT AND SPIN MOS FIELD-EFFECT - A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer. | 2012-11-01 |
20120273857 | SEMICONDUCTOR DEVICE STRUCTURE AS A CAPACITOR - A capacitor structure includes a conductive region; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; and a third conductive layer within the second dielectric layer and on the conductive material. | 2012-11-01 |
20120273858 | SEMICONDUCTOR MEMORY DEVICE - An object is to provide a semiconductor memory device that enables low power consumption of a memory cell of a CAM including a nonvolatile memory device. Another object is to provide a semiconductor memory device without degradation due to repeated data writing. Still another object is to provide a nonvolatile memory device that enables high density of memory cells. A semiconductor memory device is provided which includes a memory circuit including a first transistor including an oxide semiconductor in a semiconductor layer, and a capacitor in which a potential corresponding to written data can be retained by turning off the first transistor; and a reference circuit for referring the written potential. The semiconductor memory device enables a high-speed search function by obtaining the address of data generated by detecting the conducting state of a second transistor in the reference circuit. | 2012-11-01 |
20120273859 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate groove; a first diffusion region in the semiconductor substrate, the first diffusion region covering an upper portion of a first side of the first gate groove; and a second diffusion region in the semiconductor substrate. The second diffusion region covers a second side of the first gate groove. The second diffusion region has a bottom which is deeper than a top of the first fin structure. | 2012-11-01 |
20120273860 | NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY - An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. | 2012-11-01 |
20120273861 | METHOD OF DEPOSITING GATE DIELECTRIC, METHOD OF PREPARING MIS CAPACITOR, AND MIS CAPACITOR - The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO | 2012-11-01 |
20120273862 | SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS - Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments. | 2012-11-01 |
20120273863 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode. | 2012-11-01 |
20120273864 | HIGH ENDURANCE NON-VOLATILE MEMORY CELL AND ARRAY - Systems of electrically programmable and erasable memory cell are disclosed. In one exemplary implementation, a cell may have two storage transistors in a substrate of semiconductor material of a first conductivity type. The first storage transistor is of the type having a first region and a second region each of a second conductivity type in the substrate. The second storage transistor is of the type having a third region and a fourth region each of a second conductivity type in the substrate. Arrays formed of such memory cells and non-volatile memory cells are also disclosed. | 2012-11-01 |
20120273865 | 3-D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers. | 2012-11-01 |
20120273866 | Semiconductor Memory Device with a Buried Drain and Its Memory Array - A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate ( | 2012-11-01 |
20120273867 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a substrate; a first conductive layer over the substrate, a second conductive layer over the first conductive layer, a stacked structure disposed over the second conductive layer, wherein the stacked structure includes a plurality of first inter-layer dielectric layers and a plurality of third conductive layers alternately stacked, a pair of first channels that penetrate the stacked structure and the second conductive layer, a second channel which is buried in the first conductive layer, covered by the second conductive layer, and coupled to lower ends of the pair of the first channels; and a memory layer formed along internal walls of the first and second channels. | 2012-11-01 |
20120273868 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOF - A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer. | 2012-11-01 |
20120273869 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). | 2012-11-01 |
20120273870 | MEMORY ARRAYS HAVING SUBSTANTIALLY VERTICAL, ADJACENT SEMICONDUCTOR STRUCTURES AND THE FORMATION THEREOF - Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line. | 2012-11-01 |
20120273871 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 2012-11-01 |
20120273872 | Three Dimensional Semiconductor Memory Devices and Methods of Fabricating the Same - A three dimensional semiconductor memory device includes an electrode structure having a plurality of conductive electrode patterns and insulating patterns alternatingly stacked on a substrate. Opposite sidewalls of the electrode structure include respective grooves therein extending in a direction substantially perpendicular to the substrate. First and second active patterns protrude from the substrate and extend within the grooves in the opposite sidewalls of the electrode structure, respectively. Respective data storing layers extend in the grooves between the conductive electrode patterns of the electrode structure and sidewalls of the first and second active patterns adjacent thereto. Related fabrication methods are also discussed. | 2012-11-01 |
20120273873 | PACKAGE WITH MULTIPLE DIES - A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package. | 2012-11-01 |
20120273874 | MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF - A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line. | 2012-11-01 |
20120273875 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 2012-11-01 |
20120273876 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate that includes a cell region and a peripheral circuit area. The method for forming the semiconductor includes forming a guard pattern of an insulation material. The guard pattern is located at an edge part between the cell region and the peripheral circuit region and is buried in the semiconductor substrate. As a result, the semiconductor device prevents oxidation of the guard pattern, such that a cell gate oxidation integrity (GOI) failure is improved and an IDD failure is prevented from being generated. | 2012-11-01 |
20120273877 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A trench is formed so as to reach a p | 2012-11-01 |
20120273878 | THROUGH SILICON VIA PROCESSING TECHNIQUES FOR LATERAL DOUBLE-DIFFUSED MOSFETS - The present invention features a field effect transistor forming on a semiconductor substrate having formed thereon gate, source and drain regions, with said gate region having a lateral gate channel. A plurality of spaced-apart trenches each having an electrically conductive plug formed therein in electrical communication with said gate, source and drain regions, with said trenches extend from a back surface of said semiconductor substrate to a controlled depth. A trench contact shorts the source region and a body region. A source contact is in electrical communication with said source region and a drain contact in electrical communication with said drain region, with said source and drain contacts being disposed on opposite sides of said gate channel. | 2012-11-01 |
20120273879 | TOP DRAIN LDMOS - In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate. | 2012-11-01 |
20120273880 | Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction Capacitance | 2012-11-01 |
20120273881 | DMOS Transistor with a Cavity that Lies Below the Drift Region - A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor. | 2012-11-01 |
20120273882 | SHALLOW-TRENCH CMOS-COMPATIBLE SUPER JUNCTION DEVICE STRUCTURE FOR LOW AND MEDIUM VOLTAGE POWER MANAGEMENT APPLICATIONS - A novel lateral super junction device compatible with standard CMOS processing techniques using shallow trench isolation is provided for low- and medium-voltage power management applications. The concept is similar to other lateral super junction devices having N- and P-type implants to deplete laterally to sustain the voltage. However, the use of shallow trench structures provides the additional advantage of reducing the Rdson without the loss of the super junction concept and, in addition, increasing the effective channel width of the device to form a “FINFET” type structure, in which the conducting channel is wrapped around a thin silicon “fin” that forms the body of the device. The device is manufactured using standard CMOS processing techniques with the addition of super junction implantation steps, and the addition of polysilicon within the shallow trench structures to form fin structures. | 2012-11-01 |
20120273883 | HIGH VOLTAGE DEVICES AND METHODS FOR FORMING THE SAME - A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is disposed over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is disposed over a second well region of a second dopant type. The first thickness is larger than the second thickness. An isolation structure is disposed between the gate dielectric structure and a drain region disposed within the first well region. A gate electrode is disposed over the gate dielectric structure. | 2012-11-01 |
20120273884 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 2012-11-01 |
20120273885 | High-Voltage Transistor Structure with Reduced Gate Capacitance - In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer. | 2012-11-01 |
20120273886 | EMBEDDED SOURCE/DRAIN MOS TRANSISTOR AND METHOD FOR FORMING THE SAME - An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate. | 2012-11-01 |
20120273887 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device including a transistor formed on a first surface of a silicon layer; a first insulating film formed on the first surface of said silicon layer and covering said transistor; a wiring section formed in the first insulating film and electrically connected to the transistor; a supporting substrate formed on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; and an adjusting insulating film for adjusting a threshold voltage of said transistor, the adjusting insulating film being formed on a second surface of said silicon layer opposing the first surface of said silicon layer. Some embodiments may include a probing electrode electrically connected to the transistor and an opening in the silicon layer for exposing the probing electrode. | 2012-11-01 |
20120273888 | SEMICONDUCTOR DEVICE WITH ELECTRICALLY FLOATING BODY - A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion. | 2012-11-01 |
20120273889 | SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER - A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer ( | 2012-11-01 |
20120273890 | Method of Fabricating a Gate Stack Integration of Complementary MOS Device - A method includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer. | 2012-11-01 |
20120273891 | SEMICONDUCTOR DEVICE WITH REDUCED SURFACE FIELD EFFECT AND METHODS OF FABRICATION THE SAME - Embodiments of the present invention describe a semiconductor device implementing the reduced-surface-field (RESURF) effect. The semiconductor device comprises a source/drain region having a plurality of isolation regions interleaved with source/drain extension regions. A gate electrode is formed on the semiconductor device, where the gate electrode includes gate finger elements formed over the isolation regions to induce capacitive coupling. The gate finger elements enhance the depletion of the source/drain extension regions, thus inducing a higher breakdown voltage. | 2012-11-01 |
20120273892 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring. | 2012-11-01 |
20120273893 | SEMICONDUCTOR DEVICE AND POWER SUPPLY DEVICE USING THE SAME - A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced. | 2012-11-01 |
20120273894 | HIGH PRESSURE DEUTERIUM TREATMENT FOR SEMICONDUCTOR/HIGH-K INSULATOR INTERFACE - An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator. | 2012-11-01 |
20120273895 | DAMASCENE METHOD OF FORMING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE WITH MULTIPLE FIN-SHAPED CHANNEL REGIONS HAVING DIFFERENT WIDTHS - Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET. | 2012-11-01 |
20120273896 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area. | 2012-11-01 |
20120273897 | Semiconductor Device and Electric Power Conversion Device Using Same - The trench IGBT is provided with a plurality of trench gates disposed in a manner so as to form wide and narrow of gaps; has a MOS structure that has a channel of a first conductivity type and that is between the trench gate pair that is disposed with a narrow gap therebetween; and is provided with a floating semiconductor layer of the first conductivity type and that is separated from the trench gates by interposing a portion of a third semiconductor layer of a second conductivity type between the trench gate pair that is disposed with a wide gap therebetween. Also, this floating semiconductor layer is disposed parallel to and at a position corresponding to an emitter electrode and a first semiconductor layer having the same electric potential, with a insulating film therebetween. | 2012-11-01 |
20120273898 | SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F | 2012-11-01 |
20120273899 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted. | 2012-11-01 |
20120273900 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer. | 2012-11-01 |
20120273901 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, when a gate is formed via a replacement gate process, a portion of a work function metal layer and a portion of a first metal layer are removed after the work function metal layer and the first metal layer are formed, and then the removed portions are replaced with a second metal layer. A device having such a gate structure greatly reduces the resistivity of the whole gate, due to a portion of the work function metal layer with a high resistivity being removed and the removed portion being filled with the second metal layer with a low resistivity, thereby AC performances of the device are improved. | 2012-11-01 |
20120273902 | GATE STACK STRUCTURE WITH ETCH STOP LAYER AND MANUFACTURING PROCESS THEREOF - A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer. | 2012-11-01 |
20120273903 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode. | 2012-11-01 |
20120273904 | MINERAL ELECTRET-BASED ELECTROMECHANICAL DEVICE AND METHOD FOR MANUFACTURING SAME - This device includes a dielectric stack including at least one electret layer ( | 2012-11-01 |
20120273905 | CFA RESIST SILYLATION FOR LIMITING COLOR INTERACTIONS AND IMPROVING CROSSTALK - An electronic imager includes a pixel sensor array, a plurality elements of a color filter array containing pigments forming multiple color filter patterns on the pixel sensor array and a silylating agent formed between at least first and second elements of the multiple color filter patterns. A method for forming a color filter array on a pixel sensor array of an electronic imager includes forming a pixel sensor array on a substrate, forming a first color filter pattern on the pixel sensor array, depositing a silylating agent on the first color filter pattern, disposing elements of a second color filter pattern on the silylating agent between respective elements of the first color filter pattern and disposing elements of a third color filter pattern on the silylating agent between respective elements of the first color filter pattern. | 2012-11-01 |
20120273906 | DIELECTRIC BARRIERS FOR PIXEL ARRAYS - Pixel arrays are provided for image sensors that have barriers between color filters in an array of color filters. Color filter barriers may be formed from a transparent or semi-transparent material. Color filter barriers may be formed from a low refractive index material. Color filters may be etched and color filter barrier material may be formed in the etched regions of the color filters. If desired, a layer of color filter barrier material may be etched to form open regions and color filter material may be formed in the open regions of the color filter barrier material. An image sensor may be a front-side illuminated image sensor or a back-side illuminated image sensor. | 2012-11-01 |
20120273907 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes: a substrate having a plurality of unit pixel region; a light receiving element formed in the substrate at the unit pixel region; an interlayer dielectric layer formed over the substrate; a lightguide formed in the interlayer dielectric layer for the light receiving element; a light focusing pattern formed over the interlayer dielectric layer at the pixel region; a planarization layer formed over the substrate and covering the light focusing pattern; and a lens formed over the planarization layer at the pixel region. | 2012-11-01 |
20120273908 | STACKED SENSOR PACKAGING STRUCTURE AND METHOD - Disclosed herein is a stacked chip package including an image sensor including a recess formed on a surface thereof, and a digital signal processor chip that is positioned within the recess. Also disclosed herein is a method of fabricating a stacked chip package including the steps of forming a recess on a surface of an image sensor and positioning a digital signal processor in the recess of the image sensor. | 2012-11-01 |
20120273909 | SEMICONDUCTOR LIGHT-RECEIVING DEVICE - A semiconductor light-receiving includes: a substrate; a semiconductor light-receiving element that is provided on the substrate and has a first conductivity region and a second conductivity region; a first electrode electrically coupled to the first conductivity region; a second electrode electrically coupled to the second conductivity region; an insulating layer located on the second conductivity region; and a wiring that is located on the insulating layer and is electrically coupled to the first electrode, the wiring being elongated from the first electrode to a peripheral region of the semiconductor light-receiving element, the wiring having a region of first width and a region of second width narrower than the first width, the region of second width of the wiring being located on the second conductivity region. | 2012-11-01 |
20120273910 | PHOTODETECTOR, IMAGE SENSOR AND METHOD FOR MANUFACTURING - The finding that with a reasonable effort a layer thickness and/or refractive index variation may be acquired which realizes different internal optical path lengths for impinging radiation whereby fluctuation of spectral sensitivity of the photodetector is reduced is used to provide image sensors with a less fluctuating spectral sensitivity with respect to different wavelengths, or photodetectors with a small fluctuation of the spectral sensitivity from photodetector to photodetector with respect to defined wavelengths, with a reasonable effort. | 2012-11-01 |
20120273911 | PHOTOELECTRIC TRANSDUCER - A photoelectric transducer ( | 2012-11-01 |
20120273912 | X-Y ADDRESS TYPE SOLID STATE IMAGE PICKUP DEVICE AND METHOD OF PRODUCING THE SAME - In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced. | 2012-11-01 |
20120273913 | FLEXIBLE LATERAL PIN DIODES AND THREE-DIMENSIONAL ARRAYS AND IMAGING DEVICES MADE THEREFROM - Flexible lateral p-i-n (“PIN”) diodes, arrays of flexible PIN diodes and imaging devices incorporating arrays of PIN diodes are provided. The flexible lateral PIN diodes are fabricated from thin, flexible layers of single-crystalline semiconductor. A plurality of the PIN diodes can be patterned into a single semiconductor layer to provide a flexible photodetector array that can be formed into a three-dimensional imaging device. | 2012-11-01 |
20120273914 | Image Sensor and Method of Fabricating Same - Provided is a method of fabricating an image sensor device. The method includes providing a device substrate having a front side and a back side. The method includes forming first and second radiation-sensing regions in the device substrate, the first and second radiation-sensing regions being separated by an isolation structure. The method also includes forming a transparent layer over the back side of the device substrate. The method further includes forming an opening in the transparent layer, the opening being aligned with the isolation structure. The method also includes filling the opening with an opaque material. | 2012-11-01 |
20120273915 | ELECTRODE AND FABRICATING METHOD THEREOF - An electrode includes a substantially planar metallic thin film layer with a patterned structure including a plurality of parallel lines or a plurality of crossed lines, the metallic thin film layer configured to transmit an incident light through the metallic thin film layer. | 2012-11-01 |
20120273916 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type. | 2012-11-01 |
20120273917 | High Voltage Resistance Coupling Structure - The disclosed invention provides a structure and method for providing a high lateral voltage resistance between the electrical networks, sharing a lateral plane, of conductive elements (e.g., having different high voltage potentials) comprising a coupler. In one embodiment, an integrated coupler providing a high lateral voltage resistance comprises a primary conductive element and a secondary conductive element. An isolating material is laterally configured between the electrical network of the primary conductive element and an electrical network of the secondary conductive element. The isolating material may comprise a low-k dielectric layer and prevents any lateral barrier layers (e.g., etch stop layers, diffusion barrier layers, etc.) from extending between the first conductive element and the electrical network of the second conductive element. The structure therefore provides a galvanically isolated integrated coupler which avoids electrical shorting between circuits (e.g., at barrier layers) resulting in an improved high voltage resistance. | 2012-11-01 |
20120273918 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. In a method for forming the semiconductor substrate including a cell region and a peripheral region, a guard pattern defined by an epitaxial growth layer located at the edge part between the cell region and the peripheral region is formed. As the guard pattern is not damaged by an oxidation process, a bias leakage path between an N-well bias and a P-well bias of the peripheral region is prevented from occurring Reliability of a gate oxide film may be increased, resulting in an increased production yield of the semiconductor device and implementation of stable voltage and current characteristics. | 2012-11-01 |
20120273919 | SEMICONDUCTOR CELL AND METHOD FOR FORMING THE SAME - A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices. | 2012-11-01 |
20120273920 | Devices including composite thermal capacitors - Embodiments of the present disclosure include devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like. | 2012-11-01 |
20120273921 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a dielectric layer, where the dielectric layer includes a metal oxide layer, a metal nitride carbide layer including hydrogen therein, and a reduction prevention layer inserted between the metal nitride carbide layer and the dielectric layer. | 2012-11-01 |
20120273922 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An amorphous carbon film and an interlayer insulation film are formed in a memory cell region and a peripheral circuit region, respectively. An insulating film is formed on the amorphous carbon film and the interlayer insulation film. A portion of the insulating film that corresponds to capacitors on the amorphous carbon film is removed so that lower electrodes of the capacitors are supported from opposite sides of the lower electrodes. An insulating film pattern continuously extends from the memory cell region to the peripheral circuit region wholly covered with the insulating film pattern. Subsequently, the amorphous carbon film is removed to leave the capacitors supported by the insulating film pattern on both sides of the lower electrodes. | 2012-11-01 |
20120273923 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND WAFER - A method of manufacturing semiconductor device and a wafer are provided in accordance with embodiments of the present invention, which relates to semiconductor technology. The method includes: providing a substrate, and forming a gate oxide layer and a polysilicon layer on a first surface of the substrate; etching the polysilicon layer by use of a patterned mask so as to form a polysilicon gate with reentrants; depositing a tensile stress film on a second surface of the substrate before etching the polysilicon layer. The tensile stress film can be deposited on the second surface of the substrate for generating the tensile stress for the wafer. Thus, a polysilicon gate with reentrants can be formed in etching process. In this way, semiconductor devices can have smaller gate-source/drain overlap capacitance and better TDDB parameters, and the performance of the devices can be improved. | 2012-11-01 |
20120273924 | ACTINIC-RAY- OR RADIATION-SENSITIVE RESIN COMPOSITION, ACTINIC-RAY- OR RADIATION-SENSITIVE FILM THEREFROM AND METHOD OF FORMING PATTERN USING THE COMPOSITION - Provided are an actinic-ray- or radiation-sensitive resin composition that excels in the sensitivity, roughness characteristics and exposure latitude, and a method of forming a pattern using the same. The composition includes (A) a resin that when acted on by an acid, is decomposed to thereby increase its solubility in an alkali developer, and (B) a compound that when exposed to actinic rays or radiation, is decomposed to thereby generate an acid, the compound being any of compounds of general formula (1-1) below. | 2012-11-01 |
20120273925 | PATTERNED DOPING OF SEMICONDUCTOR SUBSTRATES USING PHOTOSENSITIVE MONOLAYERS - A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate. | 2012-11-01 |
20120273926 | Semiconductor Device and Method of Forming Shielding Layer Over Active Surface of Semiconductor Die - A semiconductor wafer contains a plurality of semiconductor die separated by a non-active area of the semiconductor wafer. A plurality of contact pads is formed on an active surface of the semiconductor die. A first insulating layer is formed over the semiconductor wafer. A portion of the first insulating layer is removed to expose the contact pads on the semiconductor die. An opening is formed partially through the semiconductor wafer in the active surface of the semiconductor die or in the non-active area of the semiconductor wafer. A second insulating layer is formed in the opening in the semiconductor wafer. A shielding layer is formed over the active surface. The shielding layer extends into the opening of the semiconductor wafer to form a conductive via. A portion of a back surface of the semiconductor wafer is removed to singulate the semiconductor die. | 2012-11-01 |