44th week of 2008 patent applcation highlights part 16 |
Patent application number | Title | Published |
20080265240 | Memory device with improved performance - The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less. | 2008-10-30 |
20080265241 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a channel formation region formed on a side wall, having a mixture of a first semiconductor material with a first lattice constant, a second semiconductor material and carbon, the second semiconductor material having a second lattice constant differing from the first lattice constant. | 2008-10-30 |
20080265242 | CMOS IMAGE SENSOR WITH ENHANCED PHOTOSENSITIVITY - A photosensitive device is disclosed which comprises a semiconductor substrate, at least one reverse biased device, such as a P-N junction diode formed in the semiconductor substrate, and at least one photosensitive layer disposed above the semiconductor substrate and substantially covering the reverse biased device, the photosensitive layer releasing electrons and holes when struck by photons, wherein the photon generated electrons and holes in the photosensitive layer reach the reverse biased device and create a combination current therein when a light shines thereon. | 2008-10-30 |
20080265243 | Magnetic floating gate flash memory structures - Methods of forming ferromagnetic floating gate structures are described. The methods include atomic layer deposition of multiple precursor films, followed by alloying the metals in the precursor films, to form a ferromagnetic floating gate. Devices that include ferromagnetic floating gates formed with these methods are also described. | 2008-10-30 |
20080265244 | Alignment Tolerant Patterning on Flexible Substrates - A method is provided for fabricating a multilayer electronic device on a flexible substrate including at least a first and a second patterned layer, wherein the first patterned layer is defined with a linewidth that is smaller than the linewidth of the second patterned layer, and the second patterned layer is defined by a patterning technique which is capable of correcting for local distortions of the pattern of said first layer on top of the flexible substrate and wherein the first patterned layer is laid-out in such a way that the geometric overlap between a portion of the second layer and a portion of the first layer is insensitive against small variations of the position of the second patterned layer. | 2008-10-30 |
20080265245 | SUBSTRATE OF EMITTING DEVICE AND EMITTING DEVICE USING THE SAME - Provided is a substrate for a light-emitting device having good light emitting efficiency and light-emitting device using the substrate. A light transparent substrate | 2008-10-30 |
20080265246 | POLYMER FILM AND POLYMER FILM DEVICE USING THE SAME - The present invention relates to a polymer film comprising a polymer having liquid crystallinity, having a number-average molecular weight in terms of polystyrene of 10 | 2008-10-30 |
20080265247 | UNIFIED TEST STRUCTURE FOR STRESS MIGRATION TESTS - A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an insulating layer between the lower metallization segments and the upper metallization segments, and connection segments. Each of the connection segments is electrically connected to a contact region of one of the lower metallization segments and to a contact region of one of the upper metallization segments to thereby electrically connect the respective lower metallization segment and the respective upper metallization segment, and the first half chain and the second half chain are of different configuration. | 2008-10-30 |
20080265248 | Leadframe Configuration to Enable Strip Testing of SOT-23 Packages and the Like - A sacrificial lead and a common lead hold a die paddle of each integrated circuit SOT-23 package to a leadframe within a strip of leadframes after isolating signal leads from the leadframe. Strip testing of most devices in the SOT-23 three and five lead packages may then be performed. The common lead may be at the center of an edge of the SOT-23 package. Also the common lead may be any one of the leads of the SOT-23 package. In addition the sacrificial lead may be at the center of an opposite edge of the SOT-23 package. | 2008-10-30 |
20080265249 | STACKED SEMICONDUCTOR DEVICE ASSEMBLY AND PACKAGE - In a stacked semiconductor device assembly, solder balls | 2008-10-30 |
20080265250 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, an active device array, an detecting circuit, a plurality of driver chip pads, a plurality of flexible printed circuit (FPC) pads, a plurality of connection lines and an inner shorting ring is provided. The active device array and the detecting circuit are disposed on the substrate, and the detecting circuit is electrically connected to the active device array. The driver chip pads and the FPC pads are disposed on the substrate, wherein the driver chip pads are electrically connected to the active device array. The connection lines are disposed on the substrate, and each of the connection lines is respectively connected to the detecting circuit and the corresponding FPC pad. The inner shorting ring is disposed on the substrate, and the inner shorter ring is respectively electrically connected to the corresponding FPC pad and the active device array. | 2008-10-30 |
20080265251 | STRUCTURE AND METHOD FOR DETERMINING A DEFECT IN INTEGRATED CIRCUIT MANUFACTURING PROCESS - The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas. | 2008-10-30 |
20080265252 | Semiconductor device - Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex. | 2008-10-30 |
20080265253 | THIN FILM TRANSISTOR DISPLAY PANEL, MANUFACTURING METHOD AND DETECTION METHOD THEREOF - A thin film transistor (TFT) display panel as well as a manufacturing method and a detection method thereof are provided. The TFT display panel comprises at least two display regions and a detection region, wherein a gate detection line is correspondingly connected at least with all the gate lines from one of the display regions in the detection region. The embodiments of the present invention improve the safety of the circuits in the detection region, and simplify the mask process of the TFT display panel and the detection process for the display region, which in turn increases the production efficiency of the TFT and reduces the production cost. | 2008-10-30 |
20080265254 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, METHOD OF MANUFACTURING SAME, AND DISPLAY DEVICE - A thin film transistor array substrate in accordance with the present invention comprising a semiconductor layer formed over the substrate and having source/drain regions, a gate insulating film, a gate electrode, an interlayer insulating film, wiring electrodes connected to the source/drain regions, a protective film, a pixel electrode connected to the wiring electrode, a lower capacitor electrode formed with and extending from the semiconductor layer, a common line electrode formed from the same layer as the gate electrode and arranged in the opposed position to the lower capacitor electrode with the gate insulating film interposed therebetween, and an upper capacitor electrode arranged in the opposed position to the common line electrode with a dielectric film (protective film) having film thickness thinner than the interlayer insulating film interposed therebetween. | 2008-10-30 |
20080265255 | Semiconductor-based, large-area, flexible, electronic devices on <100> oriented substrates - Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices. | 2008-10-30 |
20080265256 | MOS devices with improved source/drain regions with SiGe - A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage. | 2008-10-30 |
20080265257 | THIN FILM TRANSISTOR - Embodiments of a thin film transistor (TFT) are disclosed. | 2008-10-30 |
20080265258 | Group III Nitride Semiconductor Device and Epitaxial Substrate - Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be decreased. In a high electron mobility transistor | 2008-10-30 |
20080265259 | GaN-BASED PERMEABLE BASE TRANSISTOR AND METHOD OF FABRICATION - An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same. | 2008-10-30 |
20080265260 | Power Device - A power device having a transistor structure is formed by using a wide band gap semiconductor. A current path | 2008-10-30 |
20080265261 | PROCESS FOR TRANSFERRING A LAYER OF STRAINED SEMICONDUCTOR MATERIAL - Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer. | 2008-10-30 |
20080265262 | Methods and systems for testing a functional status of a light unit - A method for testing a status of a light unit is provided, wherein the method includes electrically coupling the light unit to a controller and transmitting a negative voltage from the controller to the light unit. The method also includes detecting at least one of current and voltage passing through the light unit and determining a status of the light unit based on at least one of the detected current and detected voltage. | 2008-10-30 |
20080265263 | Polarized Semiconductor Light Emitting Device - A light emitting device includes a light emitting diode (LED), a concentrator element, such as a compound parabolic concentrator, and a wavelength converting material, such as a phosphor. The concentrator element receives light from the LED and emits the light from an exit surface, which is smaller than the entrance surface. The wavelength converting material is, e.g., disposed over the exit surface. The radiance of the light emitting diode is preserved or increased despite the isotropic re-emitted light by the wavelength converting material. In one embodiment, the polarized light from a polarized LED is provided to a polarized optical system, such as a microdisplay. In another embodiment, the orthogonally polarized light from two polarized LEDs is combined, e.g., via a polarizing beamsplitter, and is provided to non-polarized optical system, such as a microdisplay. If desired, a concentrator element may be disposed between the beamsplitter and the microdisplay. | 2008-10-30 |
20080265264 | Beta-Ga2O3 single crystal growing method, thin-film single crystal growing method, Ga2O3 light-emitting device, and its manufacturing method - A method for growing a β-Ga | 2008-10-30 |
20080265265 | InGaAlN LIGHT-EMITTING DEVICE CONTAINING CARBON-BASED SUBSTRATE AND METHOD FOR MAKING THE SAME - One embodiment of the present invention provides an InGaAlN-based semiconductor light-emitting device which comprises an InGaAlN-based semiconductor multilayer structure and a carbon-based substrate which supports InGaAlN-based semiconductor multilayer structure, wherein the carbon-based substrate comprises at least one carbon-based layer. This carbon-based substrate has both high thermal conductivity and low electrical resistivity. | 2008-10-30 |
20080265266 | Housing for an Optoelectronic Component, Optoelectronic Component and Method for the Production of an Optoelectronic Component - A housing for an optoelectronic component which includes a carrier with a chip mounting surface is disclosed. An optical element which is produced separately from the carrier is applied to the carrier. The chip mounting surface and the optical element define a parting plane, the parting plane between carrier and optical element being arranged in the plane of the chip mounting surface. Also disclosed is an optoelectronic component having a housing of this type and a method for producing an optoelectronic component of this type. | 2008-10-30 |
20080265267 | Light emitting diode - At un upper part of an AlGaInP based compound semiconductor layer including an active layer | 2008-10-30 |
20080265268 | Optoelectronic Component - An optoelectronic component is described, comprising a semiconductor body that emits electromagnetic radiation of a first wavelength when the optoelectronic component is in operation, and a separate optical element disposed spacedly downstream of the semiconductor body in its radiation direction. The optical element comprises at least one first wavelength conversion material that converts radiation of the first wavelength to radiation of a second wavelength different from the first. | 2008-10-30 |
20080265269 | White light emitting device and white light source module using the same - A white light emitting device including: a blue light emitting diode chip having a dominant wavelength of 443 to 455 nm; a red phosphor disposed around the blue light emitting diode chip, the red phosphor excited by the blue light emitting diode chip to emit red light; and a green phosphor disposed around the blue light emitting diode chip, the green phosphor excited by the blue light emitting diode chip to emit green light, wherein the red light emitted from the red phosphor has a color coordinate falling within a space defined by four coordinate points (0.5448, 0.4544), (0.7079, 0.2920), (0.6427, 0.2905) and (0.4794, 0.4633) based on the CIE 1931 chromaticity diagram, and the green light emitted from the green phosphor has a color coordinate falling within a space defined by four coordinate points (0.1270, 0.8037), (0.4117, 0.5861), (0.4197, 0.5316) and (0.2555, 0.5030) based on the CIE 1931 color chromaticity diagram. | 2008-10-30 |
20080265270 | LED ELEMENT FOR AN LED STREAM - An LED element of an LED stream has an LED and a hollow seat for holding the LED. The LED has a body and two pins extended from a bottom face of the body. The hollow seat has two opposite through side holes defined in an outside of the hollow seat. To assembly the LED element, the LED with the two pins upwardly plugs to inside of the hollow seat. Then the two pins respectively and outwardly pass through the corresponding through side hole of the seat until the body is held by an upper portion of the hollow seat. | 2008-10-30 |
20080265271 | LIGHT-EMITTING ELEMENT PACKAGE AND LIGHT SOURCE APPARATUS USING THE SAME - A light-emitting element package including a heat conductive layer having a first surface and a second surface, a dielectric layer disposed on the first surface of the heat conductive layer and having an opening exposing the heat conductive layer, two electrodes disposed on the dielectric layer at a side far away from the heat conductive layer, a light-emitting element, and a transparent sealing layer. The light-emitting element is disposed in the opening, carried on the first surface of the heat conductive layer, and electrically coupled to the two electrodes. The transparent sealing layer encapsulates the light-emitting element, the heat conductive layer, and the two electrodes, and exposes part of the two electrodes and the second surface of the heat conductive layer. | 2008-10-30 |
20080265272 | Light Emitting Device Having Zener Diode Therein And Method Of Fabricating The Same - Disclosed are a light emitting device having a zener diode therein and a method of fabricating the light emitting device. The light emitting device comprises a P-type silicon substrate having a zener diode region and a light emitting diode region. A first N-type compound semiconductor layer is contacted to the zener diode region of the P-type silicon substrate to exhibit characteristics of a zener diode together with the P-type silicon substrate. Further, a second N-type compound semiconductor layer is positioned on the light emitting diode region of the P-type silicon substrate. The second N-type compound semiconductor layer is spaced apart from the first N-type compound semiconductor layer. Meanwhile, a P-type compound semiconductor layer is positioned on the second N-type compound semiconductor layer, and an active layer is interposed between the second N-type compound semiconductor layer and the P-type compound semiconductor layer. | 2008-10-30 |
20080265273 | Light set with heat dissipation means - Disclosed is a light source, which includes a light-permeable casing, a thermoconductor, which is mounted inside the casing and has a flat end portion, a plurality of radiation fins fastened to the periphery of the thermoconductor inside the casing, a light source formed of an array of LEDs and installed in the flat end portion of the thermoconductor inside the casing, and a power unit mounted inside the casing to provide the light source with the necessary working voltage. | 2008-10-30 |
20080265274 | Light emitting diode element having a voltage regulating capability - An LED element having a voltage regulating capability has a body, two pins, a resistor and a conductive sleeve. The resistor is connected to a shorter pin through the conductive sleeve, so an operator can easily use the conductive sleeve to cover the shorter pin and one of two terminals of the resistor. Further, to increase connecting strength among the conductive sleeve, the shorter pin and the terminal of the resistor, an operator further uses a tongs to deform the conductive sleeve to tight the pin and the terminal. | 2008-10-30 |
20080265275 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A laser diode includes a first n-cladding layer disposed on and lattice-matched to an n-semiconductor substrate, wherein the first n-cladding layer is n-AlGaInP or n-GaInP; a second n-cladding layer of n-AlGaAs supported by the first n-cladding layer; and an inserted layer disposed between the first n-cladding layer and the second n-cladding layer, wherein the inserted layer includes the same elements as the first n-cladding layer, the inserted layer has the same composition ratios of Al and Ga (and P) as the first n-cladding layer, and the inserted layer contains a lower composition ratio of In than the first n-cladding layer. | 2008-10-30 |
20080265276 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention has a body layer of a P-type impurity region formed on an N | 2008-10-30 |
20080265277 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING IT - A semiconductor device with a field ring in an edge pattern of a semiconductor body with a central cell area and with field plate discharge pattern. The edge pattern exhibits at least one horizontal field plate which is arranged with one end over the field ring and with its other end on insulating layers towards the edge of the semiconductor body. A first ring-shaped area of a type of conduction doped complementary to a drift section material exhibits a field ring effect. A second highly doped ring-shaped area which contacts the one end of the horizontal field plate and forms a pn junction with the first ring-shaped area and which is arranged within the first area exhibits a locally limited punch-through effect or a resistive contact to the drift section material. | 2008-10-30 |
20080265278 | Semiconductor Device and Semiconductor Integrated Circuit Device for Driving Plasma Display Using the Semiconductor Device - A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density. | 2008-10-30 |
20080265279 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a channel formation region formed on a side wall and includes a mixture of a first semiconductor material, having a first lattice constant and a second semiconductor material with a second lattice constant differing from the first lattice constant, wherein a proportion of the second semiconductor material increases with increasing distance from the side wall. | 2008-10-30 |
20080265280 | HYBRID FIN FIELD-EFFECT TRANSISTOR STRUCTURES AND RELATED METHODS - Abstract Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide. | 2008-10-30 |
20080265281 | EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER - Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET. | 2008-10-30 |
20080265282 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 2008-10-30 |
20080265283 | Hetero-junction bipolar transistor - A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In the first collector layer, a delta-doped layer is provided. | 2008-10-30 |
20080265284 | SEMICONDUCTOR DEVICE - A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region. | 2008-10-30 |
20080265285 | MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME - A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure. | 2008-10-30 |
20080265286 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×10 | 2008-10-30 |
20080265287 | INTERLINE CCD IMPLEMENTATION OF HYBRID TWO COLOR PER PIXEL ARCHITECTURE - An image sensor includes at least first and second photo-sensitive regions; a color filter array having at least two different colors that selectively absorb specific bands of wavelengths, and the two colors respectively span portions of predetermined photo-sensitive regions; and wherein the two photo sensitive regions are doped so that electrons that are released at two different depths in the substrate are collected in two separate regions of the photo sensitive regions so that, when wavelengths of light pass through the color filter array, light is absorbed by the photo sensitive regions which photo sensitive regions consequently releases electrons at two different depths of the photo sensitive regions and are stored in first and second separate regions; at least two charge-coupled devices adjacent the first photo sensitive regions; and a first transfer gate associated with the first photo sensitive region that selectively passes charge at first and second levels which, when at the first level, causes the charge stored in the first region to be passed to one of its associated charge-coupled devices, and when the transfer gate is at the second level, charge stored in the second region is passed to one of the associated charge-coupled devices. | 2008-10-30 |
20080265288 | INTERLINE CCD IMPLEMENTATION OF HYBRID TWO COLOR PER PIXEL ARCHITECTURE - An image sensor includes at least first and second photo-sensitive regions; a color filter array having at least two different colors that selectively absorb specific bands of wavelengths, and the two colors respectively span portions of predetermined photo-sensitive regions; and wherein the two photo sensitive regions are doped so that electrons that are released at two different depths in the substrate are collected in two separate regions of the photo sensitive regions so that, when wavelengths of light pass through the color filter array, light is absorbed by the photo sensitive regions which photo sensitive regions consequently releases electrons at two different depths of the photo sensitive regions and are stored in first and second separate regions; at least two charge-coupled devices adjacent the first photo sensitive regions; and a first transfer gate associated with the first photo sensitive region that selectively passes charge at first and second levels which, when at the first level, causes the charge stored in the first region to be passed to one of its associated charge-coupled devices, and when the transfer gate is at the second level, charge stored in the second region is passed to one of the associated charge-coupled devices. | 2008-10-30 |
20080265289 | Device structure and manufacturing method using HDP deposited source-body implant block - This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced. | 2008-10-30 |
20080265290 | DOUBLE MESH FINFET - A multiple gate field-effect transistor is built from an overlapping mesh assembly. The assembly comprises a first layer comprising a semiconductor material formed into at least one fin, a least one source, and at least one drain. The first layer comprises a portion of a first mesh, electrically separated from the rest of the mesh. Similarly, a second layer is formed over the first layer and electrically isolated from the first layer, the second layer being electrically conductive and comprising a gate for the at least one fin of the transistor. The second layer comprises a portion of a second mesh offset from the first mesh and overlapping the first mesh, the second layer of the MuGFET device electrically separated from the rest of the second mesh. | 2008-10-30 |
20080265291 | MOSFET DEVICE INCLUDING A SOURCE WITH ALTERNATING P-TYPE AND N-TYPE REGIONS - Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body ( | 2008-10-30 |
20080265292 | Novel HVNMOS structure for reducing on-resistance and preventing BJT triggering - A high-voltage metal-oxide-semiconductor (HVMOS) device and methods for forming the same are provided. The HVMOS device includes a substrate; a first high-voltage n-well (HVNW) region buried in the substrate; a p-type buried layer (PBL) horizontally adjoining the first HVNW region; a second HVNW region on the first HVNW region; a high-voltage p-well (HVPW) region over the PBL; an insulating region at a top surface of the second HVNW region; a gate dielectric extending from over the HVPW region to over the second HVNW region, wherein the gate dielectric has a portion over the insulating region; and a gate electrode on the gate dielectric. | 2008-10-30 |
20080265293 | Thin film transistor and method for fabricating the same, and liquid crystal display device and method for manufacturing the same - A thin film transistor (TFT) including a nanowire semiconductor layer having nanowires aligned in one direction in a channel region is disclosed. The nanowire semiconductor layer is selectively formed in the channel region. A method for fabricating the TFT, a liquid crystal display (LCD) device using the TFT, and a method for manufacturing the LCD device are also disclosed. The TFT fabricating method includes forming alignment electrodes on the insulating film such that the alignment electrodes face each other, to define a channel region, forming an organic film, to expose the channel region, coating a nanowire-dispersed solution on an entire surface of a substrate including the organic film, forming a nanowire semiconductor layer in the channel region by generating an electric field between the alignment electrodes such that nanowires of the nanowire semiconductor layer are aligned in a direction, and removing the organic film. | 2008-10-30 |
20080265294 | Semiconductor device manufacturing method including forming a metal silicide layer on an indium-containing layer - The present invention provides a semiconductor device manufacturing method of a semiconductor device having a contact plug, in which a contact hole formed by a surface portion of a high-concentration N-type diffusion layer formed on a semiconductor silicon substrate surface and an interlayer insulating film is implanted with indium ions at an energy ranging from 30 to 120 keV and an implantation amount ranging from 1.0×10 | 2008-10-30 |
20080265295 | METHODS, STRUCTURES AND SYTEMS FOR AN IMAGE SENSOR DEVICE FOR IMPROVING QUANTUM EFFICIENCY OF RED PIXELS - A method and structure for providing a high energy implant in only the red pixel location of a CMOS image sensor. The implant increases the photon collection depth for the red pixels, which in turn increases the quantum efficiency for the red pixels. In one embodiment, a CMOS image sensor is formed on an p-type substrate and the high energy implant is a p-type implant that creates a p-type ground contact under the red pixel, thus reducing dark non-uniformity effects. In another embodiment, a CMOS image sensor is formed on an n-type substrate and a high energy p-type implant creates a p-type region under only the red pixel to increase photon collection depth, which in turn increases the quantum efficiency for the red pixels. | 2008-10-30 |
20080265296 | IMAGING ELEMENT AND IMAGING DEVICE - An imaging element comprises: an optical element substrate part in which the imaging element generates a signal charge by photo-electrically converting an incident light applied from one surface side of the optical element substrate part to read the signal charge from the other surface side of the optical element substrate part and picks up an image; and a CMOS circuit substrate part connected to the other surface side of the optical element substrate part so as to transfer the signal charge generated in the photoelectric conversion layer, wherein the optical element substrate part comprises: a photoelectric conversion layer to generate the signal charge by photo-electrically converting the incident light; a charge storage part that stores the signal charge; and a reading transistor that reads the signal charge stored in the charge storage part. | 2008-10-30 |
20080265297 | CMOS image sensor and method for manufacturing the same - A CMOS image sensor and a method for manufacturing the same are disclosed, in which a blue photodiode is imparted with a greater thickness to improve sensitivity of blue light. The blue photodiode of a CMOS image sensor includes a first lightly doped P-type epitaxial layer formed on a heavily doped P-type semiconductor substrate; a gate electrode of a transfer transistor formed on the first epitaxial layer; a first N-type blue photodiode region formed on the first epitaxial layer; and a second N-type blue photodiode region formed on the first epitaxial layer corresponding to the first blue photodiode region. | 2008-10-30 |
20080265298 | SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film. | 2008-10-30 |
20080265299 | Strained channel dynamic random access memory devices - DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined. | 2008-10-30 |
20080265300 | Semiconductor device having plural dram memory cells and a logic circuit and method for manufacturing the same - A memory cell capacitor (C | 2008-10-30 |
20080265301 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer. | 2008-10-30 |
20080265302 | MEMORY STRUCTURE AND FABRICATING METHOD THEREOF - A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench. | 2008-10-30 |
20080265303 | METHODS OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES WITH BURIED BIT LINES IN NON-VOLATILE MEMORIES AND DEVICES, CARDS, AND SYSTEMS SO FORMED - Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines. | 2008-10-30 |
20080265304 | Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems - A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes. | 2008-10-30 |
20080265305 | INTEGRATED CIRCUITS WITH SUBSTRATE PROTRUSIONS, INCLUDING (BUT NOT LIMITED TO) FLOATING GATE MEMORIES - A floating gate memory cell's channel region ( | 2008-10-30 |
20080265306 | Non-Volatile Memory Device Having a Gap in the Tunnuel Insulating Layer and Method of Manufacturing the Same - A non-volatile memory device ( | 2008-10-30 |
20080265307 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES - A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer. | 2008-10-30 |
20080265308 | METHODS OF FORMING FINFETS AND NONVOLATILE MEMORY DEVICES INCLUDING FINFETS - A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected to the device isolation layer and has a different thickness than the device isolation layer. A gate electrode crosses over the fin. A gate insulating layer is between the gate electrode and the fin. Source and drain regions are on the fins and on opposite sides of the gate electrode. Related nonvolatile memory devices that include FinFETs and methods of making FinFETs and nonvolatile memory devices are also disclosed. | 2008-10-30 |
20080265309 | Semiconductor memory device and manufacturing method thereof - After an ONO film in which a silicon nitride film ( | 2008-10-30 |
20080265310 | NANO REGION EMBEDDED DIELECTRIC LAYERS, MEMORY DEVICES INCLUDING THE LAYERS, AND METHODS OF MAKING THE SAME - In one aspect, a memory cell includes a plurality of dielectric layers located within a charge storage gate structure. At least one of the dielectric layers includes an dielectric material including oxygen, and nano regions including oxygen embedded in the dielectric material, where an oxygen concentration of the dielectric material is the greater than an oxygen concentration of the nano regions. In another aspect, at least one of the dielectric layers includes a dielectric material and nano regions embedded in the dielectric material, where an atomic composition of the dielectric material is the same as the atomic composition of the nano regions, and a density of the dielectric material is the greater than a density of the nano regions. | 2008-10-30 |
20080265311 | VERTICAL TRANSISTOR AND METHOD FOR PREPARING THE SAME - A vertical transistor comprises a substrate having a step structure, two doped regions positioned in the substrate at the two sides of the step structure, and a carrier channel positioned in the substrate between the two doped regions, wherein the step structure includes an inclined edge and the width of the carrier channel at the inclined edge is larger than the width of the doped regions. The step structure comprises two non-rectangular surfaces, such as the trapezoid or triangular surfaces, and a rectangular surface. The non-rectangular surfaces connect to the doped regions, and the rectangular surface is perpendicular to the non-rectangular surface. | 2008-10-30 |
20080265312 | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout - This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region. | 2008-10-30 |
20080265313 | SEMICONDUCTOR DEVICE HAVING ENHANCED PERFORMANCE AND METHOD - In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation. | 2008-10-30 |
20080265314 | Semiconductor device having vertical MOSFET and method of manufacturing the same - An ON-resistance of a semiconductor device including a vertical MOSFET whose source electrode, gate electrode, and drain electrode are formed on a single surface is reduced. A drift region which is lower in impurity concentration than a drain region is formed over the drain region. A gate trench and a drain contact trench are simultaneously formed in the drift region. A gate insulating film and a gate electrode are formed in the gate trench. A drain electrode is formed in the drain contact trench. A drain contact region which is higher in impurity concentration than the drift region is formed immediately under the drain contact trench. | 2008-10-30 |
20080265315 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY AND METHOD FOR PRODUCING IT - A semiconductor device with a semiconductor body and to a method for producing it. In one embodiment, the semiconductor body has first electrodes which contact first highly doped semiconductor zones and complementary-conduction body zones surrounding the first semiconductor zones. The semiconductor body has a second electrode which contacts a second highly doped semiconductor zone. Between the second semiconductor zone and the body zones, a drift zone is arranged. Control electrodes which are insulated from the semiconductor body by a gate oxide and act on the body zones for controlling the semiconductor device are arranged on the semiconductor body. The body zones have minority charge carrier injector zones with complementary conduction to the body zones, arranged between the first semiconductor zones and the drift zone. | 2008-10-30 |
20080265316 | SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate | 2008-10-30 |
20080265317 | TECHNIQUE FOR FORMING THE DEEP DOPED COLUMNS IN SUPERJUNCTION - A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled. | 2008-10-30 |
20080265318 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING IT - A semiconductor component includes a surface region. A modified doping region is provided in the edge region of the cell array. In the surface region or modified doping region the doping concentration is lowered and/or in the surface region or modified doping region the conductivity type is formed such that it is opposite to the conductivity type of the actual semiconductor material region, or in which a field plate region is provided. | 2008-10-30 |
20080265319 | METHOD OF PROVIDING ENHANCED BREAKDOWN BY DILUTED DOPING PROFILES IN HIGH-VOLTAGE TRANSISTORS - A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described. | 2008-10-30 |
20080265320 | COMPONENT ARRANGEMENT INCLUDING A POWER SEMICONDUCTOR COMPONENT HAVING A DRIFT CONTROL ZONE - A component arrangement including a MOS transistor having a field electrode is disclosed. One embodiment includes a gate electrode, a drift zone and a field electrode, arranged adjacent to the drift zone and dielectrically insulated from the drift zone by a dielectric layer a charging circuit, having a rectifier element connected between the gate electrode and the field electrode. | 2008-10-30 |
20080265321 | Fin Field-Effect Transistors - A fin field-effect transistor (finFET) with improved source/drain regions is provided. In an embodiment, the source/drain regions of the fin are removed while spacers adjacent to the fin remain. An angled implant is used to implant the source/drain regions near a gate electrode, thereby allowing for a more uniform lightly doped drain. The fin may be re-formed by either epitaxial growth or a metallization process. In another embodiment, the spacers adjacent the fin in the source/drain regions are removed and the fin is silicided along the sides and the top of the fin. In yet another embodiment, the fin and the spacers are removed in the source/drain regions. The fins are then re-formed via an epitaxial growth process or a metallization process. Combinations of these embodiments may also be used. | 2008-10-30 |
20080265322 | METAL OXIDE SEMICONDUCTOR TRANSISTOR WITH Y SHAPE METAL GATE AND FABRICATING METHOD THEREOF - A method of manufacturing a metal oxide semiconductor transistor having a metal gate is provided. The method firstly includes a step of providing a substrate. A dummy gate is formed on the substrate, a spacer is formed around the dummy gate, and doped regions are formed in the substrate outside of the dummy gate. A bevel edge is formed on the spacer, and a trench is formed in the inner sidewall of the spacer. A barrier layer, and a metal gate are formed in the trench and on the bevel edge, and the barrier layer will not form poor step coverage. | 2008-10-30 |
20080265323 | Semiconductor Device and Manufacturing Method Thereof - An object is to provide a semiconductor device in which, through a simpler process, junction capacitance and power consumption can be reduced more than a conventional semiconductor device, and a manufacturing method thereof. An insulating film including an opening is formed over a base substrate and a part of a bond substrate is transferred to the base substrate, with the insulating film interposed therebetween, whereby a semiconductor film including a cavity between the semiconductor film and the base substrate is formed over the base substrate. Then, a semiconductor device including a semiconductor element such as a transistor is manufactured using the semiconductor film. The transistor includes a cavity between the base substrate and the semiconductor film used as an active layer. One cavity may be provided or a plurality of cavities may be provided. | 2008-10-30 |
20080265324 | Semiconductor device and method of manufacturing the same - A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO | 2008-10-30 |
20080265325 | BUILDING FULLY-DEPLETED AND PARTIALLY-DEPLETED TRANSISTORS ON SAME CHIP - An integrated circuit having fully-depleted silicon-on-insulator (FD-SOI) transistors and partially-depleted silicon-on-insulator (PD-SOI) transistors on a semiconductor substrate is disclosed. | 2008-10-30 |
20080265326 | Structure and method for self protection of power device with expanded voltage ranges - A vertical semiconductor power device includes a top surface and a bottom surface of a semiconductor substrate constituting a vertical current path for conducting a current there through. The semiconductor power device further includes an over current protection layer composed of a material having a resistance with a positive temperature coefficient (PTC) and the over current protection layer constituting as a part of the vertical current path connected to a source electrode and providing a feedback voltage a gate electrode of the vertical semiconductor power device for limiting a current passing there through for protecting the semiconductor power device at any voltage. | 2008-10-30 |
20080265327 | Substrate Isolated Intergrated High Voltage Diode Integrated Within A Unit Cell - An asymmetric semiconductor device ( | 2008-10-30 |
20080265328 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device comprising the steps of: forming a first silicon oxide film which covers a first region on the top surface of a silicon substrate, but which does not cover a second region and a third region thereon; oxidizing the silicon substrate to thicken the first silicon oxide film formed on the first region, and to form a second silicon oxide film on the second region and the third region; forming a first silicon film which covers the first region and the second region, but which does not cover the third region; etching and removing the second silicon oxide film formed on the third region by using the first silicon film as a mask; and forming a third silicon oxide film on the third region, the third silicon oxide film being thinner than the second silicon oxide film. | 2008-10-30 |
20080265329 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING IT - A semiconductor device which has a semiconductor body and a method for producing it. At the semiconductor body, a first electrode which is electrically connected to a first near-surface zone of the semiconductor body and a second electrode which is electrically connected to a second zone of the semiconductor body are arranged. A drift section is arranged between the first and the second electrode. In the drift section, a coupling structure is provided for at least one field plate arranged in the drift section. The coupling structure has a floating first area doped complementarily to the drift section and a second area arranged in the first area. The second area forms a locally limited punch-through effect or an ohmic contact to the drift section, and the field plate is electrically connected at least to the second area. | 2008-10-30 |
20080265330 | TECHNIQUE FOR ENHANCING TRANSISTOR PERFORMANCE BY TRANSISTOR SPECIFIC CONTACT DESIGN - By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained. | 2008-10-30 |
20080265331 | Manufacturing method of semiconductor apparatus and semiconductor apparatus, power converter using the same - In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm | 2008-10-30 |
20080265332 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant. | 2008-10-30 |
20080265333 | STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS - Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p-substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well. | 2008-10-30 |
20080265334 | SEMICONDUCTOR DEVICE CAPABLE OF AVOIDING LATCHUP BREAKDOWN RESULTING FROM NEGATIVE VARIATION OF FLOATING OFFSET VOLTAGE - A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p | 2008-10-30 |
20080265335 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING GATE AND METAL LINE THEREOF - A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction. | 2008-10-30 |
20080265336 | METHOD OF FORMING A HIGH-K GATE DIELECTRIC LAYER - A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer. | 2008-10-30 |
20080265337 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device fabrication method for forming a gate insulating film of a low leakage transistor and a gate insulating film of a high performance transistor. A first SiON film is formed over a Si substrate through first film formation. The first SiON film is left where the low leakage transistor is to be formed, and is removed where the high performance transistor is to be formed. Through second film formation, a second SiON film is formed where the first SiON film is removed, and a third SiON film including the first SiON film is formed where the first SiON film is left. The formed first SiON film has thickness and nitrogen concentration so that the third SiON film has thickness and nitrogen concentration to be the gate insulting film of the low leakage transistor. | 2008-10-30 |
20080265338 | Semiconductor Device Having Multiple Fin Heights - A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal. | 2008-10-30 |
20080265339 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit includes: a first electrode; a transistor, having a second electrode, formed on a semiconductor substrate; and third and fourth electrodes formed in a same metal layer. The first electrode is connected with a diffusion region constituting the transistor. The second electrode constitutes the gate of the transistor. The third and fourth electrodes are respectively in a comb shape and formed to at least partly overlie the transistor. None of the first to fourth electrodes is connected with any of the other electrodes. | 2008-10-30 |