| 44th week of 2009 patent applcation highlights (10-29-09/10-29-09_41) part 41 |
| Patent application number | Title | Published |
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| 20090269826 | VACCINE AGAINST STREPTOCOCCUS AGALACTIAE INFECTION USING NATIVE OR RECOMBINANT S. AGALACTIAE GLYCERALDHEYDE-3-PHOSPHATE DEHYDROGENASE (GAPDH) AS A TARGET ANTIGEN - The present invention regards a vaccine against | 10-29-2009 |
| 20090269827 | Thermophilic and thermoacidophilic metabolism genes and enzymes from alicyclobacillus acidocaldadarius and related organisms, methods - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 10-29-2009 |
| 20090269828 | ACYLTRANSFERASES FOR ALTERATION OF POLYUNSATURATED FATTY ACIDS AND OIL CONTENT IN OLEAGINOUS YEASTS - Two acyltransferases are provided, suitable for use in the manufacture of microbial oils enriched in omega fatty acids in oleaginous yeast (e.g., | 10-29-2009 |
| 20090269829 | NOVEL COMPOSITIONS WITH POLYMERASE ACTIVITY - The invention provides novel compositions with polymerase activity and methods of using the compositions. | 10-29-2009 |
| 20090269830 | Culture System and Method for Propagation of Human Blastocyst-Derived Stem Cells - The present invention relates to a culture system for and a method for propagation of human blastocyst-derived stem cells (hBS cells) upon enzymatic dissociation into a single cell suspension. The culture system for propagation of human blastocyst-derived stem (hBS) cells comprises
| 10-29-2009 |
| 20090269831 | Modified cytosine deaminases - The document provides modified cytosine deaminases with increased solubility and high levels of DNA cytosine deaminase activity. | 10-29-2009 |
| 20090269832 | Growth of Microorganisms in Media Containing Crude Glycerol - The present invention provides novel methods of growing of microorganisms in cell culture media comprising crude glycerol as a carbon source. The present invention further provides novel cell culture media comprising crude glycerol as a carbon source. In certain embodiments, inventive cell culture media substantially lack refined glycerol. In certain embodiments, inventive cell culture media comprise crude glycerol as the sole carbon source. | 10-29-2009 |
| 20090269833 | DEGRADATION OF HYDROPHOBIC ESTER PESTICIDES AND TOXINS - The present invention relates to methods for degrading hydrophobic ester pesticides and toxins. In particular, the present invention relates to the use of insect esterases, and mutants thereof, in the bioremediation of hydrophobic ester pesticides and toxins residues, such as pyrethroid residues, contaminating the environment and horticultural commodities. | 10-29-2009 |
| 20090269834 | MICRO REFINERY SYSTEM FOR ETHANOL PRODUCTION - The micro refinery first detects the weight of the sugar added to the fermentation tank and then calculates the water needed for fermentation. The feed stock is then inserted into the fermentation tank and the system adds the corresponding volume of water. The control system monitors the weight of the batch and maintains the temperature within a fermentation temperature range so the batch is converted into ethanol. In another mode of operation, discarded alcoholic beverages can be placed in the fermentation tank and processed by the micro refinery to extract the ethanol. The fermented liquid is heated and the ethanol vapors travel through a distillation tube to a membrane separation unit that separates water from the ethanol. The distillation tube has an alignment system that orients the distillation tube vertically automatically. The ethanol from the membrane separation unit is then stored in a storage container prior to use in a vehicle. The micro refinery can blend the ethanol with gasoline to produce any desire ratio of fuel. | 10-29-2009 |
| 20090269835 | Thermal Cycler with Self-Adjusting Lid - A thermal cycling instrument for PCR and other reactions performed on multiple samples with temperature changes between sequential stages in the reaction procedure is supplied with a thermal block to provide rapid changes and close control over the temperature in each sample vessel and a pressure plate incorporated into a motorized lid that detects anomalies in the reaction vessels or in their positioning over the thermal block, and automatically adjusts the plate position to achieve an even force distribution over the sample vessels. | 10-29-2009 |
| 20090269836 | Apparatus and Method for Analysing a Biological Sample in Response to Microwave Radiation - Apparatus and method of exposing a chemical, biological or biochemical sample to radiation. A sample in liquid or vapour phase is segmented and conveyed along a sample path. At least one generator or source for generating electromagnetic radiation is directed at the sample and at least one of reflected, emitted and transmitted radiation is measured at least one point along the sample path. In one embodiment, the sample is a luminescent culture produced by a continuous culture system. | 10-29-2009 |
| 20090269837 | System for assessing the efficacy of stored red blood cells using microvascular networks - A system for assessing the microvascular fitness of a sample of stored red blood cells. The system has a network device having at least one network unit. The network unit has a single inlet and a single outlet for the sample and a plurality of microchannels. The plurality of microchannels receive the sample from the single inlet and drain the sample into the single outlet. The network unit includes an aspiration pressure means for providing movement of liquid sample through the at least one network unit. The system further includes an analysis unit that receives the network device therein. The analysis unit includes a sensor for capturing measurements related to the sample and a processor capable of comparing the captured measurements to measurements stored in a database of healthy red blood cells to determine the microvascular fitness of the stored red blood cells. | 10-29-2009 |
| 20090269838 | Dry analysis element - There is provided a dry analysis element including, on a transparent support, a reagent layer including a gelatin thin film containing at least a water absorbing polymer. The dry analysis element is capable of analyzing, for example, a biological material in a liquid sample rapidly and simply, and a development layer is not required to be provided therein. | 10-29-2009 |
| 20090269839 | Process of Producing Oil from Algae Using biological Rupturing - A process for production of biofuels from algae can include cultivating an oil-producing algae, extracting the algal oil, and converting the algal oil to form biodiesel. Extracting the algal oil from the oil-producing algae can include biologically rupturing cell wall and oil vesicles of the oil-producing algae using at least one enzyme such as a cellulose or glycoproteinase, a structured enzyme system such as a cellulosome, a virus, or combination of these materials. | 10-29-2009 |
| 20090269840 | Biological Products - There are disclosed antibody molecules containing at least on CDR derived from a mouse monoclonal antibody having specificity for human KDR. There is also disclosed a CDR grafted antibody wherein at least one of the CDRs is a hybrid CDR. Further disclosed are DNA sequences encoding the chains of the antibody molecules, vectors, transformed host cells and uses of the antibody molecules in the treatment of diseases in which VEGF and/or KDR are implicated. | 10-29-2009 |
| 20090269841 | METHOD AND SYSTEM FOR THE PRODUCTION OF CELLS AND CELL PRODUCTS AND APPLICATIONS THEREOF - A cell culture system for the production of cells and cell derived products includes a reusable instrumentation base device incorporating hardware to support cell culture growth. A disposable cultureware module including a cell growth chamber is removably attachable to the instrumentation base device. The base device includes microprocessor control and a pump for circulating cell culture medium through the cell growth chamber. The cultureware module is removably attached to the instrumentation base device. Cells are introduced into the cell growth chamber and a source of medium is fluidly attached to the cultureware module. Operating parameters are programmed into the microprocessor control. The pump is operated to circulate the medium through the cell growth chamber to grow cells or cell products therein. The grown cells or cell products are harvested from the cell growth chamber and the cultureware module is then disposed. | 10-29-2009 |
| 20090269842 | TRANSMEMBRANE DELIVERY PEPTIDE AND BIO-MATERIAL COMPRISING THE SAME - The present invention relates to a transmembrane delivery peptide derived from human in which a target protein may be easily delivered into cells, and a recombinant vector comprising a nucleic acid coding the peptide. More specifically, the present invention relates to the transmembrane delivery peptide having an amino acid sequence described in SEQ ID No. 1 including 11 amino acids of specific sites in amino acid sequences of human G protein alpha 12, and a recombinant vector comprising a nucleic acid coding the same, a transformant prepared by introducing said recombinant vector, and the like. Since transmembrane delivery peptides of the present invention can be efficiently delivered into cells, they may be usefully used for the purposes of delivering various target materials, including proteins, nucleic acid, drugs and the like. | 10-29-2009 |
| 20090269843 | Hemopexin fusion proteins - Fusion proteins comprising a first protein fused to hemopexin are provided, said fusion proteins exhibit an increased circulation time. | 10-29-2009 |
| 20090269844 | NUCLEIC ACIDS ENCODING A RECEPTOR FOR IL-17 HOMOLOGOUS POLYPEPTIDES - The present invention is directed to novel polypeptides having sequence identity with IL-17, IL-17 receptors and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided herein are methods for treating degenerative cartilaginous disorders and other inflammatory diseases. | 10-29-2009 |
| 20090269845 | PLURIPOTENT CELLS - The present invention is directed to pluripotent cells that can be readily expanded in culture on tissue culture substrate that is not pre-treated with protein or an extracellular matrix, and do not require a feeder cell line. The present invention also provides methods to derive the pluripotent cell line from human embryonic stem cells. | 10-29-2009 |
| 20090269846 | Inhibitors of tyrosine kinase receptor dimerization - The teachings relate to methods of identifying inhibitors of dimerization of tyrosine receptor kinases such as EGFR. The methods comprise providing, on a digital computer, a molecular model comprising a complex of extracellular dimerization domains of an RTK, docking a chemical databases to the molecular model, scoring the compounds comprised by the database, and identifying one or more high-scoring compounds. The methods further comprise testing a compound for RTK inhibitory activity in vitro, and testing a compound for specificity as an RTK inhibitor. Also disclosed are compounds selected by the described methods, and methods of treatment using the compounds. Two compounds (NSC11241 and NSC56452) are disclosed that inhibit EGF receptor kinase activation in a dose-dependent manner. | 10-29-2009 |
| 20090269847 | SELF-ASSEMBLING PEPTIDE AMPHIPHILES AND RELATED METHODS FOR GROWTH FACTOR DELIVERY - Amphiphilic peptide compounds comprising one or more epitope sequences for binding interaction with one or more corresponding growth factors, micellar assemblies of such compounds and related methods of use. | 10-29-2009 |
| 20090269848 | TECHNIQUE FOR CULTURE OF MESENCHYMAL STEM CELL UTILIZING LAMININ-5 - Disclosed is an agent for improving at least one activity selected from the group consisting of the growth activity, adhesion activity and extension activity of mesenchymal stem cells, which comprises laminin-5 as an active ingredient. A method of culturing mesenchymal stem cells; a method of isolating mesenchymal stem cells; and a medium, vessel or sheet for use in culturing mesenchymal stem cells are also provided. | 10-29-2009 |
| 20090269849 | Bioreactor Apparatus - A bioreactor includes a fluid containment vessel and a rotating mixing element including radial inflow elements configured to direction fluid radially inwardly of the mixing element and axial out flow elements configured to redirect the radial inward flow in an axial direction. Both the vessel and the mixing element are made from plastic and the vessel comprises a flexible bag supported by a rigid housing. In one embodiment, the mixing element is pneumatically driven by the buoyancy of gas introduced into the vessel and trapped within gas entrapment cups formed on the periphery of the mixing element. As the volumetric capacity of the bioreactor increases, the ratio of the diameter of the mixing element to the width of the vessel decreases, and a gap defined between the bottom of the mixing element and the bottom of the vessel increase. | 10-29-2009 |
| 20090269850 | Mutant Paramyxovirus and Method for Production Thereof - The present invention provides a modified paramyxovirus containing a reduced amount of receptor-binding protein compared with the wild type; a method of preparing a modified paramyxovirus, comprising the following steps: (1) a step for introducing a nucleic acid that suppresses the expression of a receptor-binding protein of a paramyxovirus into an animal cell, (2) a step for infecting the paramyxovirus to the cell, and (3) a step for isolating paramyxovirus particles replicated in the cell; and a modified paramyxovirus prepared by the method of preparation mentioned above. | 10-29-2009 |
| 20090269851 | USE OF DISK SURFACE FOR ELECTROPORATION OF ADHERENT CELLS - Adherent cells on the surface of a disk are transfected by electroporation between coaxial circular cylinders with electrodes on the opposing surfaces on either side of the annular space between the cylinders by placing a buffer solution containing the transfecting species in the annular space over the cell and applying an electric potential between the electrodes. | 10-29-2009 |
| 20090269852 | Novel gene gms 01 - The present invention relates to microorganisms genetically engineered to increase yield and/or efficiency of biomass production from a carbon source, such as e.g. glucose. Processes for generating such microorganisms are also provided by the present invention. The invention also relates to polynucleotide sequences comprising genes that encode proteins that are involved in the bioconversion of a carbon source such as e.g. glucose into biomass. The invention also features polynucleotides comprising the full-length polynucleotide sequences of the novel genes and fragments thereof, the novel polypeptides encoded by the polynucleotides and fragments thereof, as well as their functional equivalents. Also included are processes of using the polynucleotides and modified polynucleotide sequences to transform host microorganisms leading to a microorganism with reduced carbon source diversion, i.e. higher yield and/or efficiency of biomass production from a carbon source such as e.g. glucose. | 10-29-2009 |
| 20090269853 | TRIOXYETHYLENE GOLD NANOCLUSTERS FUNCTIONALIZED WITH A SINGLE DNA - A method of making a nanoclusters functionalized with a single DNA strand comprising the steps of providing nanoclusters, combining said nanoclusters with thiolated DNA, incubating said nanoclusters and thiolated DNA mixture, combining said mixture with a solution comprising ethanol and dichloromethane; separating said mixture into an aqueous phase and an organic phase, mixing said aqueous phase with a solution comprising dicholormethane and NaCl, and separating the mixture into an aqueous phase and an organic phase; wherein said organic phase comprises said nanoclusters functionalized with a single DNA strand. Further, provided is a nanocluster functionalized with a single DNA strand comprising a nanocluster, said nanocluster being functionalized with a single DNA strand, said DNA strand having a length of about 10 to about 50 bases. | 10-29-2009 |
| 20090269854 | MICROCHIP - The capture rate of a target such as antigen and antibody in a sample is improved and the concentration of reaction product of a recognition substance is uniformized regardless of the position of a reaction field. By contacting microparticles and the sample using centrifugal force, the contact time of the target and the recognition substance is equalized regardless of the position in mixing chamber The microparticles and the sample are mixed evenly in the mixing chamber by changing the rotation direction and the concentration of reactant in a liquid mixture is uniform regardless of the position of the mixing chamber. When the liquid mixture having a uniform concentration is obtained, it is enough to extract a part of the liquid mixture and use the same for a process subsequent to a mixing process without the need of using all the liquid mixture. | 10-29-2009 |
| 20090269855 | Methods and compositions for mass spectrometry analysis - Methods and compounds are provided to improve the desorption and ionization of analyte for mass spectrometry analysis. More specifically, it is for laser desorption/ionization mass spectrometry. The method uses photon energy absorbing molecules that can bind with analyte either temporarily or permanently to improve the desorption and ionization of analyte. The photon energy absorbing molecules can be positively charged or negatively charged. | 10-29-2009 |
| 20090269856 | METHODS AND COMPOSITIONS FOR EVALUATING BREAST CANCER PROGNOSIS - Methods and compositions for evaluating the prognosis of a breast cancer patient, particularly an early-stage breast cancer patient, are provided. The methods of the invention comprise detecting expression of at least one, more particularly at least two, biomarker(s) in a body sample, wherein overexpression of the biomarker or a combination of biomarkers is indicative of breast cancer prognosis. In some embodiments, the body sample is a breast tissue sample, particularly a primary breast tumor sample. The biomarkers of the invention are proteins and/or genes whose overexpression is indicative of either a good or bad cancer prognosis. Biomarkers of interest include proteins and genes involved in cell cycle regulation, DNA replication, transcription, signal transduction, cell proliferation, invasion, proteolysis, or metastasis. In some aspects of the invention, overexpression of a biomarker of interest is detected at the protein level using biomarker-specific antibodies or at the nucleic acid level using nucleic acid hybridization techniques. | 10-29-2009 |
| 20090269857 | Instruments for detecting low-molecular weight substance - To provide the following instruments 1 and 2 as a low-molecular-weight substance detection instrument employing immunochromatography capable of detecting conveniently and sensitively detecting a low-molecular weight substance such as an environmental pollutant (e.g., a dioxin), as a target substance contained in a test sample:
| 10-29-2009 |
| 20090269858 | METHOD OF DETERMINING THE CONCENTRATION OF AN ANALYTE USING ANALYTE SENSOR MOLECULES COUPLED TO A POROUS MEMBRANE - The present invention relates to a method of determining the concentration of an analyte in a sample and/or the binding kinetics of an analyte to an analyte sensor molecule. For this purpose the invention relies on detecting the interaction between the analyte and the analyte sensor molecule with the latter being physically adsorbed to a solid, porous support which is in the form of a micro array. In a preferred embodiment, the method may be operated in repeated cycles. | 10-29-2009 |
| 20090269859 | Mobile Bead Configuration Immunoaffinity Column and Methods of Use - It has been discovered that a column configuration which allows for suspension of the beads, such as a mobile bead, during washing results in significantly lower levels of background and hence more sensitive levels of quantitation. The present invention provides columns, kits, and methods for more sensitive detection of a toxin or other analyte. | 10-29-2009 |
| 20090269860 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH | 10-29-2009 |
| 20090269861 | Device and method for manufacturing a semiconductor wafer - In order to manufacture an epitaxial wafer having satisfactory flatness over its entire surface, epitaxial layers are experimentally grown upon actual wafer samples under various different layer formation conditions, the thickness profiles are measured over the entire surfaces of these wafers before and after growth of the layers, and, from the differences thereof, layer thickness profiles over the entire areas of the epitaxial layers under the various different layer formation conditions are ascertained and stored. Thereafter, the thickness profile of a substrate wafer is measured over its entire area, this is added to each of the layer thickness profiles under the various different layer formation conditions which have been stored, and the planarities of the manufactured wafers which would be manufactured under these various different layer formation conditions are predicted. And one set of processing conditions is selected which is predicted to satisfy a required flatness specification, and an epitaxial layer is actually grown upon the substrate wafer under these processing conditions. | 10-29-2009 |
| 20090269862 | ALIGNMENT METHOD OF CHIPS - An alignment method of chips that are formed on a surface of a semiconductor wafer with alignment marks corresponding to the chips includes the steps of irradiating an alignment mark corresponding to a predetermined alignment chip in a predetermined area including the chips with a laser light; detecting reflected waves from the alignment mark of the predetermined alignment chip to obtain a position of the alignment mark of the predetermined alignment chip; irradiating an alignment mark of an alternative chip different from the predetermined alignment chip with the laser light in case of not being able to obtain the position of the alignment mark of the predetermined alignment chip; obtaining a position of the alignment mark of the alternative chip by detecting the reflected waves from the alignment mark of the alternative chip; and aligning the chips in the predetermined area based on positions of alignment marks including the position of the alignment mark of the alternative chip. | 10-29-2009 |
| 20090269863 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a semiconductor manufacturing method, a metal film is formed on a substrate and heat treated. The relationship between substrate warping and the heat treatment temperature during suicide formation is acquired (S | 10-29-2009 |
| 20090269864 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE BY CONSIDERING THE EXTINCTION COEFFICIENT DURING ETCHING OF AN INTERLAYER INSULATING FILM - The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation absorbing film of a silicon-rich film under an etching condition using an oxygen gas flow rate corresponding to the extinction coefficient. | 10-29-2009 |
| 20090269865 | Method for PMOS Device Processing Using a Polysilicon Footing Characteristic to Achieve Low Leakage - A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate. | 10-29-2009 |
| 20090269866 | Method of manufacturing organic light emitting display - A method of manufacturing an organic light emitting display is disclosed. The method includes forming a first electrode and a bank layer including an opening area exposing the first electrode on a target substrate, forming a medium substrate including an organic layer and an absorbing layer on the target substrate, forming a mask including an opening corresponding to the opening area of the bank layer on the medium substrate, emitting light on the medium substrate through the mask and transferring the organic layer on a portion of the first electrode exposed by the bank layer to form an organic light emitting layer on the target substrate, and forming a second electrode on the organic light emitting layer. | 10-29-2009 |
| 20090269867 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR AND NITRIDE SEMICONDUCTOR ELEMENT - The present invention provides a method of manufacturing a nitride semiconductor capable of improving the crystallinity and the surface state of the nitride semiconductor crystal formed on top of a high-temperature AlN buffer layer. An AlN buffer layer is formed on top of a growth substrate, and then nitride semiconductor crystals are grown on top of the AlN buffer layer. In a stage of manufacturing the nitride semiconductor, the crystal of the AlN buffer layer is grown at a high temperature of 900° C. or higher. In addition, an Al-source material of the AlN buffer layer is started to be supplied first to a reaction chamber and continues to be supplied without interruption, and then a N-source material is supplied intermittently. | 10-29-2009 |
| 20090269868 | Methods of Manufacture for Quantum Dot optoelectronic devices with nanoscale epitaxial lateral overgrowth - Optoelectronic devices are provided that incorporate quantum dots as the electroluminescent layer in an inorganic wide-bandgap heterostructure. The quantum dots serve as the optically active component of the device and, in multilayer quantum dot embodiments, facilitate nanoscale epitaxial lateral overgrowth (NELOG) in heterostructures having non-lattice matched substrates. The quantum dots in such devices will be electrically pumped and exhibit electroluminescence, as opposed to being optically pumped and exhibiting photoluminescence. There is no inherent “Stokes loss” in electroluminescence thus the devices of the present invention have potentially higher efficiency than optically pumped quantum dot devices. Devices resulting from the present invention are capable of providing deep green visible light, as well as, any other color in the visible spectrum, including white light by blending different sizes and compositions of the dots and controlling manufacturing processes. | 10-29-2009 |
| 20090269869 | Multiple reflection layer electrode, compound semiconductor light emitting device having the same and methods of fabricating the same - Provided are a multiple reflection layer electrode, a compound semiconductor light emitting device having the same and methods of fabricating the same. The multiple reflection layer electrode may include a reflection layer on a p-type semiconductor layer, an APL (agglomeration protecting layer) on the reflection layer so as to prevent or retard agglomeration of the reflection layer, and a diffusion barrier between the reflection layer and the APL so as to retard diffusion of the APL. | 10-29-2009 |
| 20090269870 | LIGHT EMITTING ELEMENT, LIGHT EMITTING DEVICE AND SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a semiconductor device, in particular, a light emitting element which can be easily manufactured with a wet method. One feature of the invention is a light emitting device including a transistor and a light emitting element. In the light emitting element, an organic layer, a light emitting layer, and a second electrode are sequentially formed over a first electrode, and the transistor is electrically connected to the light emitting element through a wiring. Here, the wiring contains aluminum, carbon, and titanium. The organic layer is formed by a wet method. The first electrode which is in contact with the organic layer is formed from indium tin oxide containing titanium oxide. | 10-29-2009 |
| 20090269871 | EL Display Device and Method of Manufacturing the Same - To provide a high throughput film deposition means for film depositing an organic EL material made of polymer accurately and without any positional shift. A pixel portion is divided into a plurality of pixel rows by a bank, and a head portion of a thin film deposition apparatus is scanned along a pixel row to thereby simultaneously apply a red light emitting layer application liquid, a green light emitting layer application liquid, and a blue light emitting layer application liquid in stripe shapes. Heat treatment is then performed to thereby form light emitting layers luminescing each of the colors red, green, and blue. | 10-29-2009 |
| 20090269872 | Array substrate for liquid crystal display device and method of fabricating the same - An array substrate for a liquid crystal display (LCD) device includes a substrate including a display region and a non-display region, a driving circuit in the non-display region, at least a first thin film transistor (TFT) in the display region, a storage capacitor in the display region including a first storage electrode, a second storage electrode, and a third storage electrode, wherein the first storage electrode includes a first semiconductor layer and a counter electrode, and the third storage electrode includes a first transparent electrode pattern and a first metal pattern, a gate line and a data line crossing each other to define a pixel region in the display region, and a pixel electrode connected to the first TFT in the pixel region. | 10-29-2009 |
| 20090269873 | LIQUID-CRYSTAL ELECTRO-OPTICAL APPARATUS AND METHOD OF MANUFACTURING THE SAME - A liquid crystal device comprising:
| 10-29-2009 |
| 20090269874 | METHOD FOR FABRICATING FLEXIBLE PIXEL ARRAY SUBSTRATE - In a method for fabricating a flexible pixel array substrate, first, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and the release layer being higher than that between the release layer and the polymer film. The polymer film is formed by spin coating a polymer monomer and performing a curing process to form a polymer layer. Afterwards, a pixel array is formed on the polymer film. The polymer film with the pixel array formed thereon is separated from the rigid substrate. | 10-29-2009 |
| 20090269875 | METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - An embrittlement layer is formed in the single crystal semiconductor substrate and a first impurity semiconductor layer, a first electrode, and an insulating layer are formed on one surface of the single crystal semiconductor substrate. After attaching the insulating layer and a supporting substrate to each other to bond the single crystal semiconductor substrate and the supporting substrate, the single crystal semiconductor substrate is separated along the embrittlement layer to form a stack including a first single crystal semiconductor layer. A first semiconductor layer and a second semiconductor layer are formed over the first single crystal semiconductor layer. A second single crystal semiconductor layer is formed by solid phase growth. A second impurity semiconductor layer having a conductivity type opposite to that of the first impurity semiconductor layer is formed on the second single crystal semiconductor layer. A second electrode is formed on the second impurity semiconductor layer. | 10-29-2009 |
| 20090269876 | SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD AND DRIVE METHOD THEREOF, AND CAMERA - A solid-state imaging device capable of reducing an eclipse (blocking) of an incident light at a circumferential portion of a light receiving portion and realizing a larger angle of view and high-speed driving. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon layer is adopted. Two shunt wirings extending in a horizontal direction are formed on the first transfer electrodes connected in a horizontal direction and, for example, four-phase transfer pulses are supplied to first transfer electrodes and second transfer electrodes on transfer channels through low-resistance shunt wirings extending in the horizontal direction. | 10-29-2009 |
| 20090269877 | METHOD AND APPARATUS FOR ACHIEVING LOW RESISTANCE CONTACT TO A METAL BASED THIN FILM SOLAR CELL - A system and method of forming a thin film solar cell with a metallic foil substrate are provided. After forming a semiconductor absorber film over the front surface of the metallic foil substrate a back surface of the metallic foil substrate is treated using a material removal process to form a treated back surface in a process chamber. In one embodiment, the material removal process is performed while depositing a transparent conductive layer over the semiconductor absorber film in the process chamber. | 10-29-2009 |
| 20090269878 | EMBEDDED WAVEGUIDE DETECTORS - A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer. | 10-29-2009 |
| 20090269879 | Metalorganic Chemical Vapor Deposition of Zinc Oxide - A method of metalorganic chemical vapor deposition includes converting a condensed matter source to provide a first gas, the source including at least one element selected from the group consisting of gold, silver and potassium. The method further includes providing a second gas comprising zinc and a third gas comprising oxygen, transporting the first gas, the second gas, and the third gas to a substrate, and forming a p-type zinc-oxide based semiconductor layer on the substrate. | 10-29-2009 |
| 20090269880 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A method for manufacturing a thin film transistor containing an channel layer | 10-29-2009 |
| 20090269881 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR INCLUDING LOW RESISTANCE CONDUCTIVE THIN FILMS - A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer. | 10-29-2009 |
| 20090269882 | ROTARY CHIP ATTACH - A rotary chip attach process and manufacturing approach takes chips (e.g., integrated circuits (ICs)) from a wafer in a rotary process. A chip wafer with a positioning unit is placed over the top of a sprocketed wheel that picks the ICs directly from the wafer and moves them in a semi-continuous in-step motion to a web that will accept the ICs. The sprocketed wheel includes chips that are preferably the same type as used in a typical pick-and-place robotic system, with vacuum heads adapted to pierce the wafer flat membrane (if needed), grab and IC and place and IC as desired. This positioning system keeps the IC's placement in an accurate position on the web, which can be made to move continuously with a plurality of sprocketed wheel placement units in place. | 10-29-2009 |
| 20090269883 | Controlling Flip-Chip Techniques for Concurrent Ball Bonds in Semiconductor Devices - A device has a first semiconductor chip ( | 10-29-2009 |
| 20090269884 | ACTIVE SOCKET FOR FACILITATING PROXIMITY COMMUNICATION - One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads. | 10-29-2009 |
| 20090269885 | PACKAGED SEMICONDUCTOR DEVICE WITH DUAL EXPOSED SURFACES AND METHOD OF MANUFACTURING - The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces. | 10-29-2009 |
| 20090269886 | Manufacturing Method of Semiconductor Device - A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with an second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer. | 10-29-2009 |
| 20090269887 | Apparatus for Manufacturing Semiconductor Package for Wide Lead Frame and Method of Constructing Semiconductor Package Using the Same - An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a die attach portion attaching a semiconductor chip on the lead frame supplied to the index rail. | 10-29-2009 |
| 20090269888 | CHIP-BASED THERMO-STACK - A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through-chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid. | 10-29-2009 |
| 20090269889 | Apparatus for Manufacturing Semiconductor Package for Wide Lead Frame and Method of Constructing Semiconductor Package Using the Same - An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a wire bonding portion electrically connecting the lead frame and a semiconductor chip attached to the lead frame supplied to the index rail using a wire bond. | 10-29-2009 |
| 20090269890 | SEMICONDUCTOR DEVICE - The method of manufacture includes preparing a wiring board which has a front surface and an opposing rear surface, a plurality of conductive portions which are formed on the front and rear surfaces of the core material thereof, respectively, forming a first resist film and a second resist film on the front surface and rear surface of the core material, respectively, such that the conductive portions are exposed therefrom; mounting the semiconductor chip to the main surface side of the wiring board via adhesive material; electrically connecting the pads provided on the semiconductor chip, with the first conductive portions of the wiring board via bonding wires, respectively; and sealing the semiconductor chip and the bonding wires. | 10-29-2009 |
| 20090269891 | THERMAL ENHANCED PACKAGE - A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector. | 10-29-2009 |
| 20090269892 | THIN FILM SEMICONDUCTOR DEVICE, POLYCRYSTALLINE SEMICONDUCTOR THIN FILM PRODUCTION PROCESS AND PRODUCTION APPARATUS - A process for producing an image display device using a thin film semiconductor device is provided which includes forming a polycrystalline semiconductor thin film on a substrate. A substantially belt-shaped crystal is formed which is crystallized so as to grow crystal grains in a direction substantially parallel to a scanning direction of a CW laser beam by scanning the CW laser beam along the substrate, thereby irradiating the CW laser beam on portions of the polycrystalline semiconductor thin film formed onto the substrate. | 10-29-2009 |
| 20090269893 | Semiconductor integrated circuit device and method of producing the same - A semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate electrode structure including a tunnel insulating film and a floating gate electrode formed thereon. The floating gate electrode has sidewall surfaces covered with a protection insulating film. The semiconductor device has a gate insulating film and a gate electrode formed thereon. A bird's beak structure is formed of a thermal oxide film at an interface of the tunnel insulating film and the floating gate electrode, the bird's beak structure penetrating into the floating gate electrode along the interface from the sidewall faces of the floating gate electrode, and the gate insulating film is interposed between the substrate and the gate electrode to have a substantially uniform thickness. | 10-29-2009 |
| 20090269894 | Semiconductor device and method of fabricating the same cross-reference to related applications - A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain diffusion layer formed in the semiconductor substrate at both sides of the gate electrode, and a channel region formed in the semiconductor substrate between a source and a drain of the source/drain diffusion layer and arranged below the gate insulating film, wherein an upper surface of the source/drain diffusion layer is positioned below a bottom surface of the gate electrode, and an upper surface of the channel region is positioned below the upper surface of the source/drain diffusion layer. | 10-29-2009 |
| 20090269895 | Method of Manufacturing Non-Volatile Memory Device - Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer. | 10-29-2009 |
| 20090269896 | Technique for Controlling Trench Profile in Semiconductor Structures - A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope. | 10-29-2009 |
| 20090269897 | METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL - Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions. | 10-29-2009 |
| 20090269898 | METAL OXIDE SEMICONDUCTOR (MOS) FIELD EFFECT TRANSISTOR HAVING TRENCH ISOLATION REGION AND METHOD OF FABRICATING THE SAME - A leakage current occurring on a boundary of a trench isolation region and an active region can be prevented in a Metal Oxide Semiconductor (MOS) Field Effect transistor, and a fabricating method thereof is provided. The transistor includes the trench isolation region disposed in a predetermined portion of a semiconductor substrate to define the active region. A source region and a drain region are spaced apart from each other within the active region with a channel region disposed between the source region and the drain region. A gate electrode crosses over the channel region between the source region and the drain region, and a gate insulating layer is disposed between the gate electrode and the channel region. An edge insulating layer thicker than the gate insulating layer is disposed on a lower surface of the gate electrode around the boundary of the trench isolation region and the active region. | 10-29-2009 |
| 20090269899 | Semiconductor integrated circuit device with reduced leakage current - The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data. | 10-29-2009 |
| 20090269900 | SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD THEREOF - An object is to provide an element structure of a semiconductor device for increasing an etching margin for various etching steps and a method for manufacturing the semiconductor device having the element structure. An island-shaped semiconductor layer is provided over an insulator having openings. The island-shaped semiconductor layer includes embedded semiconductor layers and a thin film semiconductor layer. The embedded semiconductor layers have a larger thickness than that of the thin film semiconductor layer. | 10-29-2009 |
| 20090269901 | CAPACITOR ELEMENT MANUFACTURING JIG AND CAPACITOR ELEMENT MANUFACTURING METHOD - The invention relates to a jig for producing capacitor elements, which is formed of resin material and is used for accommodate a plurality of capacitor element substrates therein to thereby batch-process the substrates. The jig is characterized in that portions of the jig at which the jig is supported during the process are protected with metal material. According to the invention, a group of capacitors each having a semiconductor layer serving as one electrode can be simultaneously produced with narrow variety in capacitance and with good precision, repeatedly, by using the jig having a high durability. | 10-29-2009 |
| 20090269902 | CAPACITOR HAVING TAPERED CYLINDRICAL STORAGE NODE AND METHOD FOR MANUFACTURING THE SAME - A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node. | 10-29-2009 |
| 20090269903 | METHODS FOR FABRICATING ACTIVE DEVICES ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE UTILIZING MULTIPLE DEPTH SHALLOW TRENCH ISOLATIONS - Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer. | 10-29-2009 |
| 20090269904 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a first diffusion region formed in the semiconductor substrate, a semiconductor element formed in the first diffusion region, and a channel formed in the first diffusion region to receive a cooling fluid. | 10-29-2009 |
| 20090269905 | Tapered Through-Silicon Via Structure - An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV. | 10-29-2009 |
| 20090269906 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate is provided by a method suitable for mass production. Further, a semiconductor substrate having an excellent characteristic with effective use of resources is provided. A single crystal semiconductor substrate is irradiated with ions to form a damaged region in the single crystal semiconductor substrate; an insulating layer is formed over the single crystal semiconductor substrate; the insulating layer and a supporting substrate are bonded to each other; a first single crystal semiconductor layer is formed over the supporting substrate by partially separating the single crystal semiconductor substrate at the damaged region; a first semiconductor layer is formed over the first single crystal semiconductor layer; a second semiconductor layer is formed over the first semiconductor layer with a different condition from that used for forming the first semiconductor layer; a second single crystal semiconductor layer is formed by improving crystallinity of the first and the second semiconductor layers. | 10-29-2009 |
| 20090269907 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substrate. Subsequently, the SOI substrate is cleaved at the hydrogen ion implantation section by carrying out heat treatment, so that an unnecessary part of the SOI substrate is removed, Furthermore, the BOX layer remaining on the single-crystal silicon thin-film transistor is removed by etching. With this, it is possible to from a single-crystal silicon thin-film device on an insulating substrate, without using an adhesive. Moreover, it is possible to provide a semiconductor device which has no surface damage and includes a single-crystal silicon thin film which is thin and uniform in thickness. | 10-29-2009 |
| 20090269908 | Manufacturing method of a semiconductor device - A manufacturing method of a semiconductor device comprises a process of doping conductive impurities in a silicon carbide substrate, a process of forming a cap layer on a surface of the silicon carbide substrate, a process of activating the conductive impurities doped in the silicon carbide substrate, a process of oxidizing the cap layer after a first annealing process, and a process of removing the oxidized cap layer. It is preferred that the cap layer is formed from material that includes metal carbide. Since the oxidation onset temperature of metal carbide is comparatively low, the oxidization of the cap layer becomes easy if metal carbide is included in the cap layer. Specifically, it is preferred that the cap layer is formed from metal carbide that has an oxidation onset temperature of 1000 degrees Celsius or below, such as tantalum carbide. | 10-29-2009 |
| 20090269909 | NITRIDE BASED SEMICONDUCTOR DEVICE USING NANORODS AND PROCESS FOR PREPARING THE SAME - Disclosed are a nitride based semiconductor device, including a high-quality GaN layer formed on a silicone substrate, and a process for preparing the same. A nitride based semiconductor device in accordance with the present invention comprises a plurality of nanorods aligned and formed on the silicone substrate in the vertical direction; an amorphous matrix layer filling spaces between nanorods so as to protrude some upper portion of the nanorods; and a GaN layer formed on the matrix layer. | 10-29-2009 |
| 20090269910 | METHOD OF FABRICATING PHASE CHANGE MEMORY DEVICE - In a method of fabricating a phase change memory (PCM) device, a substrate having bottom electrodes formed therein is provided. A first dielectric layer having cup-shaped thermal electrodes is formed over the substrate. Second dielectric layers are formed on the substrate. Stacked structures are formed on the substrate. A PC material film is formed over the substrate and covers the stacked structures and the second dielectric layers. The PC material film is anisotropically etched to form PC material spacers on sidewalls of the stacked structures, and each of the PC material spacers physically and electrically contacts each of the cup-shaped thermal electrodes and top electrodes. The PC material spacers include phase change material. The PC material spacers are over-etched to remove the PC material film on the sidewalls of the second dielectric layers. | 10-29-2009 |
| 20090269911 | NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate ( | 10-29-2009 |
| 20090269912 | EDGE SEAL FOR A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 10-29-2009 |
| 20090269913 | JUNCTION FORMATION ON WAFER SUBSTRATES USING GROUP IV NANOPARTICLES - A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for a first time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region. | 10-29-2009 |
| 20090269914 | PROCESS FOR FORMING A DIELECTRIC ON A COPPER-CONTAINING METALLIZATION AND CAPACITOR ARRANGEMENT - Process for forming a dielectric. The process may include forming the dielectric on a metallization and capacitor arrangement. The process allows the direct application of a dielectric layer to a copper-containing metallization. Accordingly, two process gases may be excited with different plasma powers per unit substrate area, or one process gas may be excited with a plasma and another process gas may not be excited. | 10-29-2009 |
| 20090269915 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE PREVENTING LOSS OF JUNCTION REGION - A method for manufacturing a semiconductor device includes forming an insulation layer having a contact hole on a semiconductor substrate. A metal silicide layer is deposited on a surface of the contact hole and the insulation layer to have a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, with the lower portion of the metal silicide layer having the silicon-rich composition and the upper portion of the metal silicide layer having the metal-rich composition. The metal silicide layer is then annealed so that the compositions of metal and silicon in the metal silicide layer become uniform. | 10-29-2009 |
| 20090269916 | METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SEMICIRCULAR TOP SURFACES AND ROUNDED TOP CORNERS AND EDGES - Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded. | 10-29-2009 |
| 20090269917 | Method for manufacturing recess gate in a semiconductor device - A method for manufacturing a recess gate in a semiconductor device includes forming a field oxide layer on a substrate to define an active region, forming a hard mask pattern over the substrate to selectively expose at least a portion of the active region, forming a recess pattern in the active region through an etching process using the hard mask pattern as an etch barrier, removing the hard mask pattern, forming a gate insulating layer over the substrate, and forming a gate electrode over the gate insulating layer to cover at least the recess pattern. | 10-29-2009 |
| 20090269918 | METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SMOOT SIDEWALLS AND ROUNDED TOP CORNERS AND EDGES - Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures. | 10-29-2009 |
| 20090269919 | SPLIT GATE TYPE NON-VOLATILE MEMORY DEVICE - Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers. | 10-29-2009 |
| 20090269920 | METHOD OF FORMING INTERCONNECTION LINE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE - A method of forming an interconnection line and a method of manufacturing a thin film transistor substrate are provided in accordance with one or more embodiments of the present invention. The method of forming an interconnection line in accordance with one or more embodiments of the present invention includes preparing a substrate, forming a lower organic layer and an upper organic layer on the substrate in lamination, forming trenches in parts of the upper organic layer and the lower organic layer, forming a lower interconnection layer in the trenches formed in parts of the lower organic layer, removing the upper organic layer, and filling the trenches formed in parts of the lower organic layer with an upper interconnection layer. | 10-29-2009 |
| 20090269921 | Method for growing carbon nanotubes, and electronic device having structure of ohmic connection to carbon element cylindrical structure body and production method thereof - An electronic device having a structure of an ohmic connection to a carbon element cylindrical structure body, wherein a metal material is positioned inside the junction part of a carbon element cylindrical structure body joined to a connection objective and the carbon element cylindrical structure body and the connection objective are connected by an ohmic contact. Methods for producing such an electronic device are also disclosed. Further, a method for growing a carbon nanotube is disclosed. | 10-29-2009 |
| 20090269922 | Method of depositing a metal seed layer over recessed feature surfaces in a semiconductor substrate - We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of the metal seed layer on the wafer via plasma deposition at a sufficient ratio of wafer substrate bias to DC source power that bottom coverage is achieved while resputtering of surfaces of the recessed device features is inhibited. The method also comprises depositing a second portion of the metal seed layer at a ration of substrate RF bias to DC source power such that resputtering is not inhibited. | 10-29-2009 |
| 20090269923 | ADHESION AND ELECTROMIGRATION IMPROVEMENT BETWEEN DIELECTRIC AND CONDUCTIVE LAYERS - A method and apparatus for processing a substrate is provided. The method of processing a substrate includes providing a substrate comprising a conductive material, performing a pre-treatment process on the conductive material, flowing a silicon based compound on the conductive material to form a silicide layer, performing a post treatment process on the silicide layer, and depositing a barrier dielectric layer on the substrate. | 10-29-2009 |
| 20090269924 | Method for Forming Fine Pattern by Spacer Patterning Technology - In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer is attached to a sidewall of the partition. Thereafter, the spacer is divided into bar patterns by selectively removing the partition. A polysilicon layer pattern is formed by selectively etching a portion of the poly silicon layer exposed by the divided bar patterns and then a target layer pattern is formed by selectively etching a portion of the target layer exposed by the polysilicon layer pattern. | 10-29-2009 |
| 20090269925 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plating technique, wherein the copper wiring layer is formed by passing a current of application pattern determined from the relationship between application pattern of current passed at electrolytic plating and impurity content characteristic in the formed copper wiring layer so that the impurity content in the formed copper wiring layer becomes desired one; and the wiring forming step of polishing the formed copper wiring layer into a wiring. | 10-29-2009 |
