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Last week patent highlights (10-29-09):
1. RECESS CHANNEL TRANSISTOR - includes a semiconductor substrate
2. Single Poly NVM Devices and Arrays - single-poly non-volatile memory includes a PMOS select transistor formed with a select gate , and P+ source and
3. THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY
4. DIELECTRIC MULTILAYER STRUCTURES OF MICROELECTRONIC DEVICES AND METHODS FOR FABRICATING THE SAME
5. STRUCTURE AND PROCESS INTEGRATION FOR FLASH STORAGE ELEMENT AND DUAL CONDUCTOR COMPLEMENTARY MOSFETS
6. NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
7. GATE STRUCTURES IN SEMICONDUCTOR DEVICES
8. Flash memory device and method for fabricating the same
9. NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS
10. NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
11. SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
12. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING NOTCHED GATE MOSFET
13. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
14. THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY
15. MOSFET STRUCTURE WITH GUARD RING - trench Metal-Oxide-Semiconductor Field Effect Transistor structure with guard ling includes: a substrate including an
16. METHOD FOR FABRICATING SILICON CARBIDE VERTICAL MOSFET DEVICES
17. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
18. TRENCHED MOSFET WITH GUARD RING AND CHANNEL STOP
19. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
20. MOSFET DEVICE HAVING DUAL INTERLEVEL DIELECTRIC THICKNESS AND METHOD OF MAKING SAME
21. STRUCTURE AND METHOD FOR SEMICONDUCTOR POWER DEVICES
22. ESD PROTECTED RF TRANSISTOR - The electronic device comprising a RF transistor that is designed for a fundamental RF frequency and that is integrated
23. Semiconductor integrated circuit devices
24. SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS
25. Semiconductor Device and Method for Fabricating the Same
26. SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD THEREOF
27. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
28. Localized Spacer For A Multi-Gate Transistor
29. MOS COMPRISING SUBSTRATE POTENTIAL ELEVATING CIRCUITRY FOR ESD PROTECTION
30. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
31. DEVICE STRUCTURES INCLUDING DUAL-DEPTH TRENCH ISOLATION REGIONS AND DESIGN STRUCTURES FOR A STATIC RANDOM ACCESS MEMORY
32. METHOD OR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY USING SUCH A METHOD
33. SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS THEREFOR
34. SEMICONDUCTOR DEVICE - includes a semiconductor substrate a p-channel MIS transistor formed on the substrate
35. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
36. INCREASING BODY DOPANT UNIFORMITY IN MULTI-GATE TRANSISTOR DEVICES
37. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
38. Semiconductor Device - According to the present invention, a semiconductor device having a field effect transistor is provided
39. METHOD OF MANUFACTURING A SEMICONDUCTOR SENSOR DEVICE AND SEMICONDUCTOR SENSOR DEVICE
40. WAFER LEVEL PACKAGE STRUCTURE, AND SENSOR DEVICE OBTAINED FROM THE SAME PACKAGE STRUCTURE
41. METHOD OF MANUFACTURING A DEVICE WITH A CAVITY
42. DUAL-FACE FLUID COMPONENTS - fluid component includes at least one substrate of a material that can be etched and an etch stop layer for said material
43. ELECTRET CAPACITOR TYPE COMPOSITE SENSOR
44. SEMICONDUCTOR PHOTODETECTOR - includes a semiconductor substrate of a first conductivity type a light absorption layer of the first conductivity type on
45. Apparatus and Method For Using Spacer Paste to Package an Image Sensor
46. PRE-ENCAPSULATED CAVITY INTERPOSER - , a pre-encapsulated frame, for a semiconductor device
47. METHOD OF MANUFACTURING AN IMAGE SENSING MICROMODULE
48. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
49. SEMICONDUCTOR DEVICE WITH A CHARGE CARRIER COMPENSATION STRUCTURE IN A SEMICONDUCTOR BODY AND METHOD FOR ITS PRODUCTION
50. DOUBLE PATTERNING TECHNIQUES AND STRUCTURES
51. A METHOD FOR FORMING A MULTI-LAYER SHALLOW TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE
52. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
53. DEVICE STRUCTURES FOR ACTIVE DEVICES FABRICATED USING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
54. SYSTEM FOR POWER PERFORMANCE OPTIMIZATION OF MULTICORE PROCESSOR CHIP
55. SEMICONDUCTOR DEVICE HAVING A REDUCED FUSE THICKNESS AND METHOD FOR MANUFACTURING THE SAME
56. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
57. METHOD OF INCREASING THE QUALITY FACTOR OF AN INDUCTOR IN A SEIMICONDUCTOR DEVICE
58. Through-substrate power-conducting via with embedded capacitance
59. METAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE AND METHODS OF FABRICATING SAME
60. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
61. SEMICONDUCTOR STRUCTURE INCLUDING TRENCH CAPACITOR AND TRENCH RESISTOR
62. METHOD FOR MANUFACTURING AN ENERGY STORAGE DEVICE AND STRUCTURE THEREFOR
63. GALLIUM NITRIDE MATERIAL PROCESSING AND RELATED DEVICE STRUCTURES
64. PHOTO-PATTERNED CARBON ELECTRONICS - system is provided for the manufacture of carbon based electrical components including an ultraviolet light source
65. Freestanding III-Nitride Single-Crystal Substrate and Method of Manufacturing Semiconductor Device Utilizing the Substrate
66. SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME
67. CMP METHODS AVOIDING EDGE EROSION AND RELATED WAFER
68. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
69. SEMICONDUCTOR CHIP HAVING TSV (THROUGH SILICON VIA) AND STACKED ASSEMBLY INCLUDING THE CHIPS
70. SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT
71. HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING
72. SEMICONDUCTOR DEVICE FOR PREVENTING THE LEANING OF STORAGE NODES AND METHOD FOR MANUFACTURING THE SAME
73. SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR
74. ISOLATION LAYER HAVING A BILAYER STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
75. METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE INCLUDING LASER ANNEALING
76. Vertical Transmission Structure - for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the
77. SEMICONDUCTOR PACKAGE - includes a semiconductor chip, a number of pads, a number of lead bars and an encapsulation material
78. MULTI-CHIP PACKAGE FOR REDUCING TEST TIME
79. EDGE SEAL FOR A SEMICONDUCTOR DEVICE AND METHOD THEREFOR
80. Zero-reflow TSOP stacking - The present invention mechanically integrates a flexible printed circuit pre-disposed with solder and flux and two or more
81. STACKED SEMICONDUCTOR PACKAGE - includes a circuit board with a number of pads disposed thereon
82. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
83. SEMICONDUCTOR PACKAGE HAVING CHIP SELECTION THROUGH ELECTRODES AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME
84. Semiconductor device - At a semiconductor device, an integrated circuit including an optoelectronic conversion device is formed on a front face of a
85. INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF
86. WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME
87. Semiconductor Device - The invention offers technology for suppressing damage to semiconductor devices due to temperature changes
88. Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
89. ELECTRONIC CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SAME
90. POWER MODULE SUBSTRATE, METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE, AND POWER MODULE
91. INKJET PRINTED LEADFRAMES - Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit
92. Semiconductor device - in which a semiconductor element is mounted on one of a front side and a back side of a wiring board
93. Heat Extraction from Packaged Semiconductor Chips, Scalable with Chip Area
94. ULTRA-THIN CHIP PACKAGING - packaging method involves attaching a first chip to a stable base forming contact pads at locations on the stable base
95. 3-D STACKING OF ACTIVE DEVICES OVER PASSIVE DEVICES
96. SEMICONDUCTOR DEVICE - antenna formed on one surface side of a silicon substrate and a semiconductor element provided on the other surface side of the
97. Low Voltage Drop and High Thermal Performance Ball Grid Array Package
98. MEMS Package Having Formed Metal Lid - hermetic MEMS device comprising a carrier having a surface including a device and an attachment stripe
99. CIRCUIT DEVICE INCLUDING ROTATED STACKED DIE
100. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
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