43rd week of 2010 patent applcation highlights part 19 |
Patent application number | Title | Published |
20100271036 | BATTERY MODULE, BATTERY SYSTEM AND ELECTRIC VEHICLE - A battery module includes a plurality of battery cells, and includes a voltage bus bar and a voltage/current bus bar that connect electrodes of the plurality of battery cells to one another. Solder traces are formed in regions that are spaced apart from each other in the voltage/current bus bar. Furthermore, the battery module includes an amplifying circuit and a detecting circuit. The amplifying circuit amplifies a voltage between the solder traces formed in the voltage/current bus bar. The detecting circuit detects the voltage between the solder traces amplified by the amplifying circuit. | 2010-10-28 |
20100271037 | DIFFERENTIAL-MODE CURRENT SENSOR - Systems, methods, and devices are disclosed, including a ground-fault sensor that has a plurality of conductors each disposed one inside of another except for an outer conductor and a field sensor configured to sense an electric field, a magnetic field, or both. In some embodiments, the field sensor is disposed adjacent the outer conductor. | 2010-10-28 |
20100271038 | DIFFERENTIAL-MODE CURRENT SENSOR METHOD - Systems, methods, and devices are disclosed, including a ground-fault sensor that has a plurality of conductors each disposed one inside of another except for an outer conductor and a field sensor configured to sense an electric field, a magnetic field, or both. In some embodiments, the field sensor is disposed adjacent the outer conductor. | 2010-10-28 |
20100271039 | APPARATUS FOR DETECTING IMBALANCES IN A PAIRED LINE - A device for measuring and isolating noise-creating imbalances in a paired telecommunications line has an internal circuit. The internal circuit includes a pulse generator. Pulses provided by the pulse generator are applied to an interface which includes balanced pathways to the conductors. The pulses are applied simplex (longitudinally) to the pair of conductors. Upon encountering a fault in the pair, a reflected metallic voltage signal is received by the interface. The reflected metallic voltage signal is sampled by an analog-to-digital converter. Data relating to the sampled signal is displayed for detection and location of faults on the pair. | 2010-10-28 |
20100271040 | ARRANGEMENTS FOR DETECTING DISCONTINUITY OF FLEXIBLE CONNECTIONS FOR CURRENT FLOW AND METHODS THEREOF - A detection circuit arrangement in a plasma processing chamber having movable lower electrode is provided. The arrangement includes flexible connector having a first flexible connector end, a second flexible connector end and at least a slit. At least portion of the slit is disposed in a direction parallel to a line drawn between two flexible connector ends. One end is coupled to the movable lower electrode and another end is coupled to a component of the plasma processing chamber. Flexible connector provides low impedance current path between the movable lower electrode and the component of the plasma processing chamber. The arrangement also includes means for detecting current flow through conductor material disposed on one side of the slit. The means for detecting includes at least a coil wound around the conductor material and a detector circuit coupled to the coil for detecting the current flow interruption due to a tear. | 2010-10-28 |
20100271041 | TESTING APPARATUS WITH HIGH EFFICIENCY AND HIGH ACCURACY - A testing apparatus includes a public test board, a single DUT (device under test) test board and a holder. The public test board includes a plurality of public test channel sets each having a plurality of public signal terminals for receiving test signals. On the single DUT test board, a plurality first signal terminals are arranged according to the pin layout of a DUT, a plurality second signal terminals are arranged according to the terminal layout of a public channel set, and a plurality traces are arranged for electrically connecting corresponding first and second signal terminals. The holder can connect the pins of the DUT to corresponding first signal terminals. | 2010-10-28 |
20100271042 | SENSOR APPARATUS - A sensor apparatus of the present invention includes a failure diagnosis circuit for setting as a failure diagnosis object section at least any one of a drive circuit section, a detection device, a detection circuit section and a processing circuit section, and determining whether the failure diagnosis object section is normal or abnormal. The sensor apparatus also includes a time point measuring unit for measuring time point information, and adding the time point information to an output concerning generation of the failure detection signal outputted from the failure diagnosis object section and an output concerning generation of the sense signal such that the output concerning generation of the failure detection signal is made to correspond to the output concerning generation of the sense signal using time point information in terms of time points. In the case of the failure diagnosis circuit determining abnormality of the failure diagnosis object section, the first output terminal outputs the sense signal added with the time point information at the time of occurrence of the abnormality and the sense signal added with the time point information after the time of occurrence of the abnormality, as a signal outside a range of a normal output voltage. Alternatively, the sensor apparatus of the present invention includes an output circuit section for outputting a sense signal from the processing circuit section and a failure detection signal from a failure diagnosis circuit by the time division system. In the case of the failure diagnosis circuit determining abnormality of the failure diagnosis object section, the output circuit section outputs the sense signal added with the time point information at the time of occurrence of the abnormality and the sense signal added with the time point information after the time of occurrence of the abnormality, as a signal outside a range of a normal output voltage. | 2010-10-28 |
20100271043 | INSPECTION PIN PROTECTION STRUCTURE OF CONDUCTION CHECK APPARATUS - In order to smoothly advance and retreat a protection board without inclining the protection board, and to surely perform conduction check without an unfavorable bending force or the like to act upon the protection board at the conduction check of a connector, the present invention provides a conduction check apparatus as follow. | 2010-10-28 |
20100271044 | REMOTE DETECTION OF DISCHARGE ON A POWER LINE NETWORK - Apparatus for remote detection of discharge on a power line, including a line sampler for obtaining samples of a signal on a power line; a high pass filter for identifying high frequency components of the signal, where the high frequency components are indicative of discharge within the signal; and a reporting unit for reporting identified components as a remote discharge. | 2010-10-28 |
20100271045 | Open Fuse Detection by Neutral Point Shift - Systems and methods are shown for detecting a blown fuse in a three-phase line by comparing neutral points in the line before and after the fuses. Diode rectifier circuits may be used to compare the neutral points and generate a DC output voltage when neutral points are off from one another, and photocoupler circuits may provide electrical isolation when signaling a neutral point shift. The neutral points compared need not be on immediate sides of the fuses, so intermediate components may exist, and in some embodiments one of the compared points may be within a load connected to the three-phase line. | 2010-10-28 |
20100271046 | IMPLEMENTING AT-SPEED WAFER FINAL TEST (WFT) WITH COMPLETE CHIP COVERAGE - A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits. | 2010-10-28 |
20100271047 | METHODS AND SYSTEMS FOR DETECTING THE PRESENCE, OR DETERMINING THE LOCATION OR THE SIZE, OR DETECTING CHANGES OF MATERIAL PROPERTIES, OF AN OBJECT WITHIN A PREDEFINED SPACE - A method for detecting the presence, and/or determining the location, and/or detecting changes in the material properties, of a first object ( | 2010-10-28 |
20100271048 | POSITION DETECTOR - There is provided a multilayer made up of: a support member | 2010-10-28 |
20100271049 | SENSOR ELECTRONICS IN A VEHICLE DOOR HANDLE - A solution for sensor electronics provided in a door handle of a vehicle with a sensor control circuit ( | 2010-10-28 |
20100271050 | CAPACITIVE ROTATION SENSOR - A capacitive rotation sensor for detecting the position of an object moving relative to a stationary object, comprising a shaft rotatably supported in a housing flange, said shaft being connected integral in rotation therewith to a rotor to which, separated by an air gap, a stator situated opposite thereto is assigned, wherein at least the rotor, the stator and an evaluation circuit are enclosed by an electrically conductive cap, wherein a stator surface is arranged on the underside of a circuit board and the stator surface has assigned thereto, situated opposite thereto and separated by the air gap, a non-rotation-symmetrical rotor disc which, in turn, is fixed on a rotor support, said rotor support being fastened highly precisely on the outer periphery of the shaft so as to be integral in rotation therewith. | 2010-10-28 |
20100271051 | CENTROID POSITION DETECTOR DEVICE AND WEARING TYPE ACTION ASSISTANCE DEVICE INCLUDING CENTROID POSITION DETECTOR DEVICE - Load measuring parts | 2010-10-28 |
20100271052 | Disconnection detecting device - A control circuit turns on a switching element to discharge a capacitor, and after a voltage between both ends of the capacitor becomes zero, the control circuit turns off the switching element. The control circuit measures the voltage V | 2010-10-28 |
20100271053 | Method of Characterizing Particles - Mixtures containing homogeneously-sized particles with a minimum concentration of agglomerates or larger particles are desired in various manufacturing processes such as, for example, in the manufacture and use of chemical mechanical polishing slurries, food emulsions, pharmaceutical products, paints, and print toner. The method disclosed herein provides these industries with an accurate and efficient method of screening such mixtures for such agglomerates and large particles. The method generally includes preparing a suspension of the mixture in an electrolyte, wherein the suspension includes a specified concentration of small particles per unit of electrolyte. The method further includes passing the prepared suspension, and a plurality of the particles therein, through an aperture of a device capable of characterizing particles according to the Coulter principle to obtain data on the particles. Still further, the method includes deriving a particle size distribution of the large particles from the obtained data. The suspension includes at least one small particle per aperture volume. The large particles have an average diameter that is at least five times greater than the average diameter of the small particles. The aperture has a diameter that is (i) at least 50 times greater than the average diameter of the small particles, and (ii) about 1.2 times greater than the average diameter of the large particles to less than about 50 times greater than the average diameter of the large particles. | 2010-10-28 |
20100271054 | INTEGRATED CIRCUIT DEVICE HAVING GROUND OPEN DETECTION CIRCUIT - An integrated circuit device includes a chip having a power supply terminal, a ground terminal, an input terminal, and an internal circuit formed therein. The chip comprises: a unidirectional device disposed between the input terminal and the ground terminal and directed from the ground terminal to the input terminal; and a ground open detection circuit including a first transistor having the gate connected to the input terminal and the source and the drain connected between the power supply terminal and the ground terminal, a second transistor having the gate connected to the ground terminal and the source and the drain connected between the power supply terminal and the ground terminal, and a comparator for comparing potentials of nodes respectively between drains of the first and second transistors and the power supply terminal, and for outputting a ground open detection signal. | 2010-10-28 |
20100271055 | Assembly for Electrical Conductivity Measurements in the Piston Cylinder Device - An assembly apparatus for measurement of electrical conductivity or other properties of a sample in a piston cylinder device wherein pressure and heat are applied to the sample by the piston cylinder device. The assembly apparatus includes a body, a first electrode in the body, the first electrode operatively connected to the sample, a first electrical conductor connected to the first electrode, a washer constructed of a hard conducting material, the washer surrounding the first electrical conductor in the body, a second electrode in the body, the second electrode operatively connected to the sample, and a second electrical conductor connected to the second electrode. | 2010-10-28 |
20100271056 | CONTAINER, A METHOD FOR DISPOSING THE SAME, AND A MEASUREMENT METHOD - The present invention restrains adverse effects caused by refraction of a terahertz wave by a device under test when the terahertz wave is fed to the device under test for measurement. A container | 2010-10-28 |
20100271057 | Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit - A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node. | 2010-10-28 |
20100271058 | SYSTEM AND METHOD FOR PROBING WORK PIECES - A system and method of probing work pieces is described. A first and second arm each having a pivot point and a guide end are pivotally coupled together at the respective pivot points. A probe tip holder is coupled to at least one of the first arm or the second arm. A guide means guides movement of the guide ends of the pivotally coupled arms, such that movement of the guide end of the first arm and the second arm move the probe tip holder in a plane parallel to the work piece surface. | 2010-10-28 |
20100271059 | METHOD OF DETERMINING AN ELECTRICAL PROPERTY OF A TEST SAMPLE - A method of obtaining an electrical property of a test sample, comprising a non-conductive area and a conductive or semi-conductive test area, by performing multiple measurements using a multi-point probe. The method comprising the steps of providing a magnetic field having field lines passing perpendicularly through the test area, bringing the probe into a first position on the test area, the conductive tips of the probe being in contact with the test area, determining a position for each tip relative to the boundary between the non-conductive area and the test area, determining distances between each tip, selecting one tip to be a current source positioned between conductive tips being used for determining a voltage in the test sample, performing a first measurement, moving the probe and performing a second measurement, calculating on the basis of the first and second measurement the electrical property of the test area. | 2010-10-28 |
20100271060 | MEMBRANE PROBING METHOD USING IMPROVED CONTACT - A substrate, preferably constructed of a ductile material and a tool having the desired shape of the resulting device for contacting contact pads on a test device is brought into contact with the substrate. The tool is preferably constructed of a material that is harder than the substrate so that a depression can be readily made therein. A dielectric (insulative) layer, that is preferably patterned, is supported by the substrate. A conductive material is located within the depressions and then preferably lapped to remove excess from the top surface of the dielectric layer and to provide a flat overall surface. A trace is patterned on the dielectric layer and the conductive material. A polyimide layer is then preferably patterned over the entire surface. The substrate is then removed by any suitable process. | 2010-10-28 |
20100271061 | CONTACT PROBE AND SOCKET - A contact probe include: a first plunger to be connected to an object to be inspected; a second plunger to be connected to a board for inspection; and a spring operable to urge the first and second plungers in directions of moving the first and second plungers apart from each other. A pillar part of one of the first and second plungers is slidably engaged with an inner periphery of a tubular part of the other of the first and second plungers. The pillar part includes an elastically deformable part which is in contact with a part of the inner periphery of the tubular part. | 2010-10-28 |
20100271062 | METHOD AND APPARATUS FOR PROBE CARD ALIGNMENT IN A TEST SYSTEM - Embodiments of methods and apparatus for aligning a probe card assembly in a test system are provided herein. In some embodiments, an apparatus for testing devices may include a probe card assembly having a plurality of probes, each probe having a tip for contacting a device to be tested, and having an identified set of one or more features that are preselected in accordance with selected criteria for aligning the probe card assembly within a prober after installation therein. In some embodiments, the identity of the identified set of one or more features may be communicated to the prober to facilitate a global alignment of the probe card assembly that minimizes an aggregate misalignment of all of the tips in the probe card assembly | 2010-10-28 |
20100271063 | TEST APPARATUS - Multiple test pins receive, as input data, multiple data output from a DUT. Multiple multiplexers receive the multiple data input to the multiple test pins and selects one of the data thus input, and outputs the data thus selected. Multiple logical comparators are respectively provided for the multiple multiplexers and judge whether or not the data selected by the corresponding multiplexers match the expected values. | 2010-10-28 |
20100271064 | Integrated Circuit Self-Monitored Burn-In - An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal. | 2010-10-28 |
20100271065 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MEASURING SYSTEM - A semiconductor device includes: a well of a second conductive type formed on or above a semiconductor substrate of a first conductive type; a first diffusion layer of the second conductive type formed in a surface portion of the well; a second diffusion layer of the first conductive type formed separately from the first diffusion layer in the surface portion of the well; first to third first-layer conductive layers formed above the well; and first to third second-layer conductive layers formed above the first to third first-layer conductive layers. The first second-layer conductive layer, the first first-layer conductive layer, the first diffusion layer and the well are conductively connected as a first conductive path. The second second-layer conductive layer, the second first-layer conductive layer, and the second diffusion layer are conductively connected as a second conductive path. The third second-layer conductive layer, and the third first-layer conductive layer are conductively connected as a third conductive path. | 2010-10-28 |
20100271066 | CIRCUIT PROTECTING APPARATUS AND ASSOCIATED METHOD, AND CIRCUIT PROTECTING LAYER - A circuit protecting apparatus is provided. The circuit protecting apparatus comprises a selecting module, a routing module, a processing module, and a controlling module. The selecting module selects for each of a plurality of a minimum-sized routing region a routing pattern from a plurality of predetermined routing patterns, and generates an input signal. The routing module then generates the routing comprising the selected routing patterns on a to-be-protected region to form a circuit protecting layer. The routing receives the input signal and outputs an output signal. The processing module decodes the output signal into a restored signal a compares the restored signal with the input signal to generate a comparison result, according to which the controlling module selectively fails a chip. | 2010-10-28 |
20100271067 | DIGITAL NOISE PROTECTION CIRCUIT AND METHOD - A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state. | 2010-10-28 |
20100271068 | LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA - A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer. | 2010-10-28 |
20100271069 | INPUT/OUTPUT CIRCUIT AND INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME - An input/output circuit includes an I/O node connected to a pull up and pull down circuit having a pull up and pull down transistors. Data is sent and received at through the I/O node. A level shifter provides voltages including a supply voltage and a high voltage higher than the supply voltage. A signal control circuit controls the voltage level applied to the pull up and pull down circuit. During a data input mode, data is received at the I/O node and the pull up transistor is biased at the high voltage to cut off the pull up transistor. During a data output mode, data is output at the I/O node and the pull down transistor pulls down the I/O node to ground when the output data is low, and the pull up transistor is activated when the output data is high. | 2010-10-28 |
20100271070 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 2010-10-28 |
20100271071 | Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks - A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack. | 2010-10-28 |
20100271072 | DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME - There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result. | 2010-10-28 |
20100271073 | QUARTER CYCLE WAVEFORM DETECTOR - A method for extracting peak information from an amplitude varying sinusoidal waveform output from a sensor is provided. The method includes gating a counter with a keying signal having a keying-signal period generated by a sinusoidal waveform associated with the amplitude varying sinusoidal waveform, receiving high frequency clock signals at the gated counter during keying-signal periods, wherein a clock-signal period is much less than the keying-signal periods, disabling the counter at the end of each keying-signal period, generating a quarter-count value based on the disabling, and outputting a sample pulse associated with each keying-signal period. If a current-keying-signal period is the same as a last-keying-signal period, the sample pulse is generated at a quarter-wave of the sinusoidal waveform. If the current-keying-signal period differs from the last-keying-signal period, the associated output sample pulses are adjusted to the quarter-wave of the sinusoidal waveform in the next-keying-signal period. | 2010-10-28 |
20100271074 | COMPARISON CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS - A comparison circuit includes a comparator into a first input terminal of which an input signal is input, and into a second input terminal of which a reference voltage for comparison is input, a controller which monitors an output signal of the comparator, and a voltage generation circuit into which a threshold voltage control signal from the controller is input, wherein the voltage generation circuit, when the voltage level of the output signal of the comparator is a first level, outputs as the reference voltage a first threshold voltage which is one of a high potential side threshold voltage and a low potential side threshold voltage which define a hysteresis width, and when the voltage level of the output signal of the comparator is a second level, outputs as the reference voltage a second threshold voltage which is the other one of the high potential side threshold voltage and low potential side threshold voltage. | 2010-10-28 |
20100271075 | TEST AND MEASUREMENT INSTRUMENT WITH AN AUTOMATIC THRESHOLD CONTROL - A test and measurement instrument including a plurality of channels, each channel configured to receive a corresponding input signal. Each channel includes a comparator configured to compare the input signal to a threshold for the channel; an edge detector configured to detect an edge of an output signal of the comparator; and a threshold controller configured to adjust the threshold for the channel in response to the edge detector. | 2010-10-28 |
20100271076 | PRECISION SAMPLING CIRCUIT - A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input. | 2010-10-28 |
20100271077 | LIGHT RECEIVING CIRCUIT - A light receiving circuit in accordance with an exemplary aspect of the present invention includes a photodiode | 2010-10-28 |
20100271078 | CIRCUITRY IN A DRIVER CIRCUIT - A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail. | 2010-10-28 |
20100271079 | POWER SEMICONDUCTOR DEVICE - Disclosed is a power semiconductor device including a bootstrap circuit. The power semiconductor device includes a high voltage unit that provides a high voltage control signal so that a high voltage is output; a low voltage unit that provides a low voltage control signal so that a ground voltage is output, and is spaced apart from the high voltage unit; a charge enable unit that is electrically connected to the low voltage unit and charges a bootstrap capacitor for supplying power to the high voltage unit when the high voltage is output, when the ground voltage is output; and a high voltage cut-off unit that cuts off the high voltage when the high voltage is output so that the high voltage is not applied to the charge enable unit, and includes a first terminal electrically connected to the charge enable unit and a second terminal electrically connected to the high voltage unit. | 2010-10-28 |
20100271080 | DRIVER COMPARATOR CIRCUIT - A first resistor is arranged such that a first voltage is applied to a first terminal thereof, and a second terminal thereof is connected to an input/output terminal. The first voltage is applied to a first terminal of a second resistor. A tail current source generates a predetermined tail current. A current switch receives data to be transmitted to a second device, selects one from among the second terminals of the first and second resistors, and connects the terminal thus selected to the tail current source. A voltage dividing circuit includes a third resistor and a fourth resistor provided in series between the second terminals of the first resistor and the second resistor. A load balancer includes a fifth resistor arranged such that a second voltage is applied to a first terminal thereof, and a second terminal thereof is connected to the second terminal of the second resistor. | 2010-10-28 |
20100271081 | GATE DRIVE CIRCUITRY FOR NON-ISOLATED GATE SEMICONDUCTOR DEVICES - One embodiment is a gate drive circuitry for switching a semiconductor device having a non-isolated input, the gate drive circuitry having a first circuitry configured to turn-on the semiconductor device by imposing a current on a gate of the semiconductor device so as to forward bias an inherent parasitic diode of the semiconductor device. There is a second circuitry configured to turn-off the semiconductor device by imposing a current on the gate of the semiconductor device so as to reverse bias the parasitic diode of the semiconductor device wherein the first circuitry and the second circuitry are coupled to the semiconductor device respectively through a first switch and a second switch. | 2010-10-28 |
20100271082 | MULTIMODE MILLIMETER-WAVE FREQUENCY DIVIDER CIRCUIT WITH MULTIPLE PRESETTABLE FREQUENCY DIVIDING MODES - A multimode millimeter-wave frequency divider circuit with multiple selectable frequency dividing modes is proposed, which is designed for integration with a millimeter wave (MMW) circuit system, such as a phase-locked loop (PLL) circuit, for providing multimode frequency dividing functions. In actual application, the millimeter wave frequency divider circuit of multi frequency dividing mode provides at least three frequency dividing operational modes, including modes of dividing two, dividing 3 and dividing four. In practice, the millimeter wave frequency divider circuit of multi frequency divider mode may be integrated with a millimeter wave phase-locked circuit to provide a frequency synthetic function having multi frequency sections, such as including 38 GHZ, 60 GHZ and 77 GHZ, and may use reduced circuit layout surfaces and operational power. | 2010-10-28 |
20100271083 | FLIP-FLOP CIRCUIT AND PRESCALER CIRCUIT INCLUDING THE SAME - A prescaler circuit according to an exemplary aspect of the present invention includes a first flip-flop circuit that detects second output data and outputs the detected data as first output data, and a second flip-flop circuit that detects the first output data and outputs the data as the second output data. The first flip-flop circuit includes a master-side latch circuit that generates intermediate data, a slave-side latch circuit that detects the intermediate data and outputs the data as the first output data, and a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4. The master-side latch circuit generates the intermediate data based on the second output data and the control signal. | 2010-10-28 |
20100271084 | SOUCE-SYNCHRONOUS DATA LINK FOR SYSTEM-ON-CHIP DESIGN - A method of producing an integrated circuit ( | 2010-10-28 |
20100271085 | DELAY CHAIN INITIALIZATION - A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous. | 2010-10-28 |
20100271086 | DUAL-BAND COUPLED VCO - In a dual band capable voltage controlled oscillator VCO circuit comprising two voltage controlled oscillator units VCO | 2010-10-28 |
20100271087 | DELAY LOCKED LOOP AND OPERATING METHOD THEREOF - A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit. | 2010-10-28 |
20100271088 | SYNTHESIZER, SYNTHESIZER MODULE, AND RECEPTION DEVICE AND ELECTRONIC DEVICE USING SAME - A synthesizer including an oscillator for outputting an oscillation signal based on an output signal from a comparator, a frequency divider for dividing a frequency of an output signal from the oscillator based on control from a controller, and a temperature sensor for detecting an error between a preset frequency and a frequency based on a reference oscillation signal. The comparator compares an output signal from the frequency divider with an output signal from a MEMS oscillator and outputs a signal indicating the comparison result to the oscillator. The controller changes the frequency division ratio of the frequency divider based on an output signal from the temperature sensor and changes the frequency division ratio in a state in which the frequency division ratio is kept at the past value. Thus, phase noise deterioration in the synthesizer can be suppressed. | 2010-10-28 |
20100271089 | Enhanced polar modulator for transmitter - Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±π/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +π (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics. | 2010-10-28 |
20100271090 | Adaptive Temporal Filtering of Single Event Effects - Technologies are described herein for mitigating the effects of single event effects or upsets on digital semiconductor device data paths and clocks utilizing an adaptive temporal filter. The adaptive temporal filter includes a master delay line and a slave delay line to generate two output clock signals that remain unaffected by variations in process, voltage and temperature (PVT) conditions. The adaptive temporal filter supplies the three independent clock signals having a programmable phase relationship, to a triple voting register structure for storing and outputting an uncorrupted data value using a majority voter. | 2010-10-28 |
20100271091 | METHOD OF FAST TRACKING AND JITTER IMPROVEMENT IN ASYNCHRONOUS SAMPLE RATE CONVERSION - A method for fast tracking and jitter improvement in an asynchronous sample rate conversion includes a digital phase locked loop (DPLL) for an asynchronous sample rate conversion (ASRC) device. A control apparatus in the DPLL includes a gain controller that sets and maintains gains (K | 2010-10-28 |
20100271092 | LOW-POWER SOURCE-SYNCHRONOUS SIGNALING - Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal. | 2010-10-28 |
20100271093 | ADJUSTMENT APPARATUS, ADJUSTMENT METHOD AND TEST APPARATUS - Provided is an adjustment apparatus that adjusts signal output timings, comprising a control section that causes a first signal output section to output a signal having a rising edge and causes a second signal output section to output a signal having a falling edge; a signal acquiring section that acquires a composite signal obtained by combining the signal output by the first signal output section and the signal output by the second signal output section; and an adjusting section that adjusts a timing difference between a signal output timing of the first signal output section and a signal output timing of the second signal output section, such that the signal acquiring section acquires the composite signal having a composite waveform in which the rising edge and the falling edge overlap. | 2010-10-28 |
20100271094 | Signal Alignment System - Through the use of a multi-step sweep, the present invention is capable of increasing the speed and improving the error resistance of a signal alignment. In a specific embodiment of the invention, a method for the signal alignment of a target signal and an adjustable signal is disclosed. The target signal is sampled using three or more phase shifted versions of the adjustable signal to obtain a group of target signal state values. Next, through reference to the group of target signal state values it is determined that an edge of the target signal lies between a first phase shifted version and a second consecutive phase shifted version. In response, the first phase shifted version is selected as the starting point for a second sweep. During the second sweep, the phase of the first phase shifted version is sequentially adjusted in relatively small incremental steps to minimize the phase difference relative to the target signal. | 2010-10-28 |
20100271095 | OUTPUT SIGNAL ERROR DETECTION, CIRCUMVENTION, SIGNAL RECONSTRUCTION AND RECOVERY - A method of dealing with anomalies in an output signal is provided. The method includes monitoring transitions in the output signal. When transitions do not occur at expected times, detecting an anomalous signal. Determining the type of anomalous signal based at least in part on the time period of the anomalous signal and conditioning the output signal based on the type of anomalous signal detected. | 2010-10-28 |
20100271096 | WAVEFORM PROCESSING CIRCUIT - A rising edge or a falling edge is finely adjusted, or a dead time and a period are adjusted with high accuracy. A waveform processing circuit includes: an integration circuit | 2010-10-28 |
20100271097 | Pulse Width Modulation Sequence Maintaining Maximally Flat Voltage During Current Transients - A digital circuit implementing pulse width modulation controls power delivered in what one can model as a second order or higher order system. An exemplary control plant could embody a step-down switch mode power supply providing a precise sequence of voltages or currents to any of a variety of loads such as the core voltage of a semiconductor unique compared to its input/output ring voltage. One of several algorithms produce a specific predetermined sequence of pulses of varying width such that the voltage maintains maximally flat characteristics while the current delivered to the load from the system plant varies within a range bounded only by inductive element continuous conduction at the low power extreme and non-saturation of the inductor core at the high power extreme. The specific pulse width modulation sequence controls a plant such that the voltage maintains maximally flat characteristics in one embodiment without a feed-forward or feedback loop physically embodied in the control system thereby reducing the parts cost or control semiconductor production yield cost while enhancing noise immunity and long term reliability of the control system. Several specific algorithms maintain maximally flat voltage despite extreme load variations therewith control plant element parameters otherwise exacerbating excessive voltage fluctuation during the given current transients. | 2010-10-28 |
20100271098 | LOW-OFFSET CHARGE PUMP, DUTY CYCLE STABILIZER, AND DELAY LOCKED LOOP - A charge pump circuit can include a first pair of transistors having connected sources and gates configured to receive a first pump signal and an inverse first pump signal and a second pair of transistors having connected drains and gates configured to receive a second pump signal and an inverse second pump signal, sources of the second pair of transistors being connected to drains of the first pair of transistors at first and second connection nodes, wherein the first and second pair of transistors are all of the same transistor type and provide an output current in response to the first and second pump signals. The charge pump circuit can also include a voltage stabilizer circuit connected to the second connection node and configured to regulate the second connection node to have a voltage within a predetermined range about a selectable voltage. Duty cycle stabilizers and control loops such as delay locked loops can include the charge pump circuit. | 2010-10-28 |
20100271099 | FINE GRAIN TIMING - A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain. | 2010-10-28 |
20100271100 | MINIMAL BUBBLE VOLTAGE REGULATOR - A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator. | 2010-10-28 |
20100271101 | Master Clock Generation Unit for Satellite Navigation Systems - A master clock generation unit for satellite navigation systems, comprises a plurality of frequency inputs for receiving a respective atomic clock signal, each having a first or a second reference frequency, and a number of frequency converters each having an input connected to one of the frequency inputs and an output. Each of the frequency converters receives an offset frequency (selected according to the first and second reference frequency at the assigned frequency input) from at least one frequency synthesizer, for providing the same intermediate frequency at each of the converter outputs. A switching matrix is connected to each of the converter outputs for selecting one of the intermediate frequencies as a primary clock provided at a first matrix output, and another of the intermediate frequencies as a secondary clock provided at a second matrix output. A frequency generator having an input connected to the first matrix output and connected to a number of frequency outputs of the master clock generation unit, derives an output reference frequency from the primary clock, and provides it at the frequency outputs. A phase meter having a first meter input connected to the first matrix output and a second meter input connected to the second matrix output, determines a phase difference between the primary and the secondary clock for detecting abnormal behavior. | 2010-10-28 |
20100271102 | Semiconductor integrated circuit - Provided is a semiconductor integrated circuit including: a differential driver that is, disposed between a first power supply and a second power supply and drives differential input signals to generate differential output signals; and a control signal generation circuit that generates a first control signal for controlling a voltage level of each of the differential output signals. When each of a pair of output signals forming the differential output signals is changed from a voltage level corresponding to the first power supply to a voltage level corresponding to the second power supply, an amount of change in the voltage level of the corresponding output signal is controlled based on the first power supply. | 2010-10-28 |
20100271103 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When a high-voltage output is Hi, a first N-type transistor and a second P-type transistor are in an OFF state, and a second N-type transistor and a first P-type transistor are in an ON state, where a high voltage is applied to drain-source of the first N-type transistor. In a process to shift the high voltage output to Lo, a gate potential of the first N-type transistor is once put to an intermediate state between VDD and GND to lower a drain-source voltage of the first N-type transistor, then the gate potential is raised to VDD. In this manner, a state where the drain-source voltage of the first N-type transistor is large and also a drain current of the same is large is avoided, so that an On withstand voltage of the level shift circuit is increased, thereby preventing a breakdown. | 2010-10-28 |
20100271104 | IMAGE SIGNAL INPUT CIRCUIT - An image signal input circuit includes an input terminal configured to receive an image signal, a clamp circuit configured to hold a sink chip voltage contained in the image signal to be a constant value, a level shift circuit that includes a first emitter follower having a first transistor and a first current source, and a second emitter follower having a second transistor and a second current source, a base of the second transistor being connected to an emitter of the first transistor, and that is configured to shift a level of the sink chip voltage which is held constant, and an electric current source configured to attract a base current of the first transistor. | 2010-10-28 |
20100271105 | High Boosting-Ratio/Low-Switching-Delay Level Shifter - A circuit receives an input signal characterized by a first pair of rail voltages and generates in response thereto an output signal characterized by a second pair of rail voltages. The circuit comprises first and second transistors coupled in series between a high reference voltage and a low reference voltage. The input signal drives a control lead of the second transistor. The logical inverse of the input signal drives a control lead of a third transistor, which couples a charge source to the control lead of the first transistor in response thereto in order to turn off the first transistor. The charge source can be either a voltage source or a charged capacitive node. Of importance, the third transistor does not have to overcome contention with other transistors to turn off said first transistor. | 2010-10-28 |
20100271106 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a 1/2-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal. | 2010-10-28 |
20100271107 | ANALOG FINITE IMPULSE RESPONSE FILTER - According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both a first and second differential output terminals of the FIR filter. The FIR includes a summing circuit that provides operational advantages to the FIR filter. | 2010-10-28 |
20100271108 | GEIGER-MODE PHOTODIODE WITH INTEGRATED AND JFET-EFFECT-ADJUSTABLE QUENCHING RESISTOR, PHOTODIODE ARRAY, AND CORRESPONDING MANUFACTURING METHOD - An embodiment of a Geiger-mode avalanche photodiode, having: a body made of semiconductor material of a first type of conductivity, provided with a first surface and a second surface and forming a cathode region; and an anode region of a second type of conductivity, extending inside the body on top of the cathode region and facing the first surface. The photodiode moreover has: a buried region of the second type of conductivity, extending inside the body and surrounding an internal region of the body, which extends underneath the anode region and includes the internal region and defines a vertical quenching resistor; a sinker region extending through the body starting from the first surface and in direct contact with the buried region; and a contact region made of conductive material, overlying the first surface and in direct contact with the sinker region. | 2010-10-28 |
20100271109 | DUAL REFERENCE CAPACITIVE SENSING USER INTERFACE - A module for controlling power supply to a load in a product which includes a microchip, and an electromechanical switch and a proximity/touch sensor connected to the microchip, preferably to the same input. The switch is primarily used to activate or deactivate the load and the proximity/touch sensor to vary the effect of operating the switch, or to control additional functions such as the activation of a signal, typically a light signal, which helps to locate the product, particularly in the dark, and to vary the duration of an automatic time-out period at the end of which the load is deactivated. | 2010-10-28 |
20100271110 | DEVICE FOR THE OPERATION OF ELECTRONIC CIRCUITS ON A HIGH-VOLTAGE POTENTIAL - A device for operating an electronic circuit at a high-voltage potential includes a diode array installed in a high-voltage line, wherein a current is configured to flow over the high-voltage line through the diode array. A voltage drop over the diode array is applied to the electronic circuit, which is configured to provide information ascertained on the high-voltage line. An evaluation unit connected to the electronic circuit via a galvanically separated transmission device receives the information from the electronic circuit. | 2010-10-28 |
20100271111 | Bootstrap circuit - Disclosed herein is a bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein: a node section connecting a gate electrode of the first transistor and a specific one of the source and drain areas of a third transistor to each other is put in a floating state when the third transistor is put in a turned-off state; a gate electrode of the second transistor is connected to a clock supply line which conveys the other one of the two clock signals; and a voltage-variation repression capacitor is provided between the node section and a first voltage supply line. | 2010-10-28 |
20100271112 | SPIN TRANSISTOR AND METHOD OF OPERATING THE SAME - Disclosed are a spin transistor and a method of operating the spin transistor. The disclosed spin transistor includes a channel formed of a magnetic material selectively passing a spin-polarized electron having a specific direction, a source formed of a magnetic material, a drain, and a gate electrode. When a predetermined voltage is applied to the gate electrode, the channel selectively passes a spin-polarized electron having a specific direction and thus, the spin transistor is selectively turned on. | 2010-10-28 |
20100271113 | INTEGRATED CIRCUIT WITH MULTIPLE INDEPENDENT POWER SUPPLY ZONES - An integrated circuit comprising multiple independent power supply zones at substantially the same voltage level and a method for utilizing such power supply zones. An integrated circuit may comprise a first module and may, for example, comprise a second module. A first power supply bus may communicate first electrical power to the first module, where the first electrical power is characterized by a first set of power characteristics comprising a first voltage level. A second power supply bus may communicate second power to the second module, where the second power is characterized by a second set of power characteristics comprising a second voltage level that is substantially similar to the first voltage level. The second set of power characteristics may, for example, be substantially different than the first set of power characteristics. The second power supply bus may also, for example, communicate the second electrical power to the first module. | 2010-10-28 |
20100271114 | SYSTEM CORRECTED PROGRAMMABLE INTEGRATED CIRCUIT - A system corrected programmable integrated circuit is applied to a power supply and includes a comparator unit, a digital output unit and a programming unit. The comparator unit includes an external feedback voltage input end and a reference voltage input end for inputting a feedback voltage and a reference voltage respectively, such that when the feedback voltage equals the reference voltage, the comparator unit transmits a control signal to the digital output unit. When receiving the control signal, the digital output unit stops outputting the reference voltage and the current reference voltage is recorded as a programming voltage for outputting to the programming unit. When receiving the programming voltage, the programming unit programs the programming voltage and transmits the voltage to the reference voltage input end. Accordingly, the present invention automatically detects and compensates a system error to reduce external element, yet still achieving a qualified range of product specification. | 2010-10-28 |
20100271115 | INTERNAL VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR DEVICE - An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock. | 2010-10-28 |
20100271116 | VOLTAGE REGULATOR CIRCUIT - Embodiments of circuits, systems, and methods relating to a voltage regulator circuit are disclosed. In particular, in accordance with some embodiments, a voltage regulator having a field effect transistor (FET) portion and a heterojunction bipolar transistor (HBT) portion integrated into a common substrate is provided. Other embodiments may be described and claimed. | 2010-10-28 |
20100271117 | VOLTAGE CONVERTER - A voltage converter including a first transistor, a second transistor, an inductor and a control module is provided. The first transistor has a source terminal receiving an input signal, and a body terminal receiving a first bias voltage. The second transistor has a drain terminal coupled to a drain terminal of the first transistor, a source terminal coupled to ground, and a body terminal receiving a second bias voltage. The inductor has a first terminal coupled to the drain terminal of the first terminal and a second terminal generating an output voltage. The control module is coupled to a gate terminal of the first transistor and a gate terminal of the second transistor for controlling conducting states of the first transistor and the second transistor. | 2010-10-28 |
20100271118 | I/O Buffer with Low Voltage Semiconductor Devices - Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively. | 2010-10-28 |
20100271119 | ENVELOPE DETECTOR, LINEARIZATION CIRCUIT, AMPLIFIER CIRCUIT, METHOD FOR DETECTING A MODULATION ENVELOPE AND WIRELESS COMMUNICATION UNIT - An envelope ( | 2010-10-28 |
20100271120 | DISTRIBUTED THRESHOLD ADJUSTMENT FOR HIGH SPEED RECEIVERS - According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal. | 2010-10-28 |
20100271121 | MULTIPORT AMPLIFIERS IN COMMUNICATIONS SATELLITES - In order to maintain isolation of signals within a multiport amplifier of a communications satellite and to reduce cross-talk components, by monitoring communications signals passing through the multiport amplifier, output signals of the multiport amplifier are sensed and downconverted to baseband, and applied to an emulator mechanism of the multiport amplifier. The emulator mechanism comprises a reverse matrix of the multiport amplifier, which recovers the input signals of the multiport amplifier together with cross-talk components, and a digital signal processor which carries out a frequency analysis of the cross-talk components by means of an EFT, and employs a digital model of the multiport amplifier to determine the state of the multiport amplifier which gives rise to such cross-talk components. The digital signal processor may be located at a ground station to which communication is made via a telemetry link. | 2010-10-28 |
20100271122 | VARIABLE-GAIN AMPLIFIER CIRCUIT AND WIRELESS COMMUNICATION DEVICE INTEGRATED CIRCUIT EQUIPPED THEREWITH - There is disclosed a variable-gain amplifier circuit that operates on a low voltage, exhibits low distortion, provides a wide range of variation, and is suitable for use in a low-power-consumption wireless communication system. The variable-gain amplifier circuit is configured so that a variable-load circuit, which includes three reactance function elements and provides a wide range of impedance variation, is connected to a conductor circuit whose output terminal generates a positive-phase output current proportional to conductance with respect to an input voltage. | 2010-10-28 |
20100271123 | ADAPTIVE DIGITAL PREDISTORTION OF COMPLEX MODULATED WAVEFORM USING LOCALIZED PEAK FEEDBACK FROM THE OUTPUT OF A POWER AMPLIFIER - Exemplary embodiments of the invention includes an amplifier and a processor that adapts a baseline or previous model of the input-output signal characteristic of the amplifier using metrics of the system, including peak power, peak voltage, average power, root mean square (RMS) voltage, samples of the output signal of the amplifier, etc. In particular, the system comprises an amplifier; a device to measure a metric of the system; a processor to generate a present model of the input-output signal characteristic of the amplifier based on the system metric as determined through a localized sampling window of the output signal; and a predistortion device to predistort the input signal for the amplifier based on the present amplifier model. | 2010-10-28 |
20100271124 | Distortion Compensation Device - A distortion in an amplified signal obtained by amplifying a first input signal, is compensated for by applying a correction factor to the first input signal. The correction factor is updated based on the first input signal and the amplified signal. Updating the correction factor is prohibited when a value of the first input signal is same as a value of a second input signal among a plurality of input signals input previous to the first input signal. | 2010-10-28 |
20100271125 | DISTORTION COMPENSATION APPARATUS AND METHOD FOR DETECTING FAILURE IN THE SAME - There is provided a distortion compensation apparatus for compensating distortion of an output of a power amplifier included in a radio transmitter. The distortion compensation apparatus includes a difference value calculator to calculate a difference value between a reference signal and a feedback signal, where the reference signal is branched from an input signal to the power amplifier and the feedback signal is branched from an output from the power amplifier; an integrator to accumulate the difference value; and a failure determiner to determine based on the accumulated difference value whether or not a failure has occurred or not. | 2010-10-28 |
20100271126 | MATCHED INTEGRATED ELECTRONIC COMPONENTS - A switchable integrated electronic device includes at least three elements r | 2010-10-28 |
20100271127 | ELECTRONIC AMPLIFIER - An electronic amplifier is characterized by a first stage ( | 2010-10-28 |
20100271128 | COMPOSITE DIFFERENTIAL RF POWER AMPLIFIER LAYOUT - A composite differential Radio Frequency (RF) power amplifier includes a plurality of differential RF cascode power amplifiers coupled in parallel. Each differential RF cascode power amplifier includes a positive transconductance stage and a positive cascode stage coupled in series with the positive transconductance stage between a voltage node and ground. Each also includes a negative transconductance stage and a negative cascode stage coupled in series with the negative transconductance stage between the voltage node and ground. The plurality of parallel differential RF cascode power amplifiers resides adjacent one another in a single semiconductor substrate such that the positive transconductance stage of a first differential RF cascode power amplifier resides adjacent a negative transconductance stage of a second differential RF cascode power amplifier and the positive cascode stage of the first differential RF cascode power amplifier resides adjacent a negative cascode stage of a second differential RF cascode power amplifier. | 2010-10-28 |
20100271129 | Output circuit using analog amplifier - An output circuit includes an analog amplifier circuit including a differential amplifier stage configured to receive an input voltage, and first to n | 2010-10-28 |
20100271130 | AMPLIFIER CIRCUIT, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT - An amplifier circuit includes an amplifier section that includes a P-type differential section, an N-type differential section, and an output section, an offset adjustment section that adjusts an offset of the amplifier section, a first offset adjustment register that stores a first offset adjustment value for the P-type differential section, a second offset adjustment register that stores a second offset adjustment value for the N-type differential section, and a control section that sets the first offset adjustment value in the offset adjustment section in a first operation mode in which the P-type differential section operates, and sets the second offset adjustment value in the offset adjustment section in a second operation mode in which the N-type differential section operates. | 2010-10-28 |
20100271131 | INTEGRATED POWER AMPLIFIER - Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies. | 2010-10-28 |
20100271132 | Amplifier circuit with resistive current limitter - An amplifier circuit includes first transistor of first conductivity type having source connected to first power supply, while having gate connected to input terminal and drain connected to output terminal; transistor of second conductivity type having source connected to second power supply and drain connected to the output terminal; second transistor of the first conductivity type whose source and gate are connected to the source and gate of the first transistor of the first conductivity type, respectively; resistor whose one end connected to drain of the second transistor of the first conductivity type, and an output control circuit; current input terminal connected to the opposite end of the resistor; and voltage output terminal connected to the gate of the transistor of the second conductivity type. The output control circuit controls the gate voltage of the transistor of the second conductivity type based on the input current of the current input terminal. | 2010-10-28 |
20100271133 | Electronic Circuits including a MOSFET and a Dual-Gate JFET - Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths. | 2010-10-28 |
20100271134 | High Gain Stacked Cascade Amplifier with Current Compensation to reduce Gain Compression - A high gain stacked cascade amplifier includes a first amplifying element, a second amplifying element, a current mirror bias element, and a dynamic bias adjustment element. The first and second amplifying elements are coupled in series to form the high gain stacked cascade amplifier configuration. The current mirror bias element provides a bias to the first and second amplifying elements. The dynamic bias adjustment element is coupled to the second amplifying element. The dynamic bias adjustment element is configured to increase a gain compression point of a composite filter, formed by the first and second amplifying elements, in response to a determination that an input signal causes gain compression in the first amplifying element. | 2010-10-28 |
20100271135 | CMOS RF POWER AMPLIFIER WITH LDMOS BIAS CIRCUIT FOR LARGE SUPPLY VOLTAGES - Bias circuitry that may be used within a communications or other device includes a first current mirror having first and second transistors with sources coupled to ground and operable to receive a reference current at a drain of first transistor. A second current mirror has first and second transistors with drains coupled to a battery voltage supply. A third current mirror has first and second transistors with drains coupled to sources of the first and second transistors of the second current mirror, respectively. A biasing transistor couples between the second transistor of the first current mirror and the first transistor of the third current mirror and operable to receive a tuning input voltage at its gate. A resistive element coupled between the second transistor of the third current mirror and ground produces a bias voltage produced at a connection of the resistive element and the second transistor of the third current mirror. | 2010-10-28 |