| 43rd week of 2010 patent applcation highlights part 14 |
| Patent application number | Title | Published |
|---|
| 20100270535 | ELECTRONIC DEVICE INCLUDING AN ELECTRICALLY POLLED SUPERLATTICE AND RELATED METHODS - A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the selectively polable superlattice for selective poling thereof. | 2010-10-28 |
| 20100270536 | Concentric Gate Nanotube Transistor Devices - Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications. | 2010-10-28 |
| 20100270537 | OPTOELECTRONIC DEVICES AND ORGANIC COMPOUNDS USED THEREIN - An optoelectronic device comprises a cathode; an electron-transporting layer comprising a compound of formula I; | 2010-10-28 |
| 20100270538 | Organic light emitting display device and method of manufacturing the same - Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a substrate; at least one thin film transistor including a gate electrode including a metal oxide layer and a metal layer, a semiconductor layer including source/drain regions and a channel layer; at least one capacitor including a first electrode formed on a layer on which the gate electrode is formed by using a material forming the gate electrode, and a second electrode formed on a layer on which the source/drain electrodes are formed by using a material used to form the source/drain electrodes; and at least one organic light emitting device including a pixel electrode formed on a layer on which the gate electrode is formed by using a material used to form the gate electrode and connected to the source/drain electrodes via a contact hole. | 2010-10-28 |
| 20100270539 | ORGANIC EL ELEMENT AND ORGANIC EL MATERIAL-CONTAINING SOLUTION - An organic EL device ( | 2010-10-28 |
| 20100270540 | Iridium Complex Containing Carbazole-Substituted Pyridine and Phenyl Derivatives as Main Ligand and Organic Light-Emitting Diodes Containing the Same - The present invention relates to a novel iridium complex into which carbazole-substituted pyridine derivatives and various substituents-substituted phenyl derivatives are introduced as main ligand and a electrophosphorescence diode containing the same as a dopant of a light-emitting layer. When the iridium complex according to the present invention is applied to an organic light-emitting diode, the heat-resistance property and the light-emitting property can be significantly improved as well as the light-emitting efficiency and the like can be significantly improved by doping the iridium complex compound into the light-emitting layer as compared to the conventional organic light-emitting diode. | 2010-10-28 |
| 20100270541 | SYSTEM FOR DISPLAY IMAGES AND FABRICATION METHOD THEREOF - A system for displaying images including a display panel and a fabrication method thereof are provided. The display panel includes a substrate having a first, second and third areas, a first patterned semiconductor layer disposed over the first area of the substrate, a first insulating layer covering the first patterned semiconductor layer and the first, the second and the third areas of the substrate, a second patterned semiconductor layer disposed on the first insulating layer of the first and the third areas respectively, a second insulating layer covering the second patterned semiconductor layer and the first insulating layer, and a patterned conductive layer disposed on the second insulating layer to form a first thin-film transistor at the first area and a second thin-film transistor at the third area. | 2010-10-28 |
| 20100270542 | Solution Processable Organic Semiconductors - Semiconductor devices, methods of making semiconductor devices, and coating compositions that can be used to provide a semiconductor layer within a semiconductor device are described. The coating compositions include a small molecule semiconductor, an insulating polymer, and an organic solvent that can dissolve both the small molecule semiconductor material and the insulating polymer. The small molecule semiconductor is an anthracene-based compound (i.e., anthracene derivative) substituted with two thiophene groups as well as with two silylethynyl groups. | 2010-10-28 |
| 20100270543 | Biomolecule-Based Electronic Device - The present invention relates to a biomolecule-based electronic device in which the biomolecule with redox potential is directly immobilized on the substrate. The present invention enables to excellently exhibit the capability of a protein-based bio-memory device in which it is preferable to use the substrate on which cysteine-introduced recombinant proteins are effectively immobilized and a self-assembled layer (SAM) is fabricated. It becomes realized that a redox potential is regulated using intrinsic redox potential of the protein dependent on applied voltage. The present invention provides a novel operating method in which three potentials are applied throughout four steps. The present invention has some advantages of fabricating a protein layer in a convenient manner and inducing electron transfer by fundamental electrochemical or electronic operation. The method of this invention is considered as a new concept in the senses that intrinsic electron transfer mechanisms induced by natural-occurring biomolecules are used to develop an information storage device. | 2010-10-28 |
| 20100270544 | POLYMER LIGHT EMITTING ELEMENT, METHOD FOR MANUFACTURING THE SAME AND POLYMER LIGHT EMITTING DISPLAY DEVICE - A polymer light emitting element having a large light releasing surface, a high light emitting efficiency and a long life, a polymer light emitting display device and planar light source, as well as a method for manufacturing the polymer light emitting element are provided. The polymer light emitting element is characterized by comprising a first electrode, a second electrode and a light emitting layer provided between the first electrode and the second electrode and containing a polymer compound, wherein the second electrode is composed of three layers, a first layer, a second layer and a third layer arranged in this order viewed from the light emitting layer, and at least one of materials contained in the second layer has a reducing action on at least one of materials contained in the first layer, and the visible light transmittance of the third layer is 40% or more. | 2010-10-28 |
| 20100270545 | LIGHT-EMITTING DEVICE USING VOLTAGE SWITCHABLE DIELECTRIC MATERIAL - A voltage switchable dielectric material (VSD) material as part of a light-emitting component, including LEDs and OLEDs. | 2010-10-28 |
| 20100270546 | LIGHT-EMITTING DEVICE USING VOLTAGE SWITCHABLE DIELECTRIC MATERIAL - A voltage switchable dielectric material (VSD) material as part of a light-emitting component, including LEDs and OLEDs. | 2010-10-28 |
| 20100270547 | SEMICONDUCTOR DEVICE - Semiconductor devices having at least one barrier layer with a wide energy band gap are disclosed. In some embodiments, a semiconductor device includes at least one active layer composed of a first compound, and at least one barrier layer composed of a second compound and disposed on at least one surface of the at least one active layer. The at least one barrier layer may have a wider energy band gap than an energy band gap of the at least one active layer. The compositions of the first and second compounds may be controlled to adjust the difference between Fermi functions for conduction band and valence band in the at least one active layer. | 2010-10-28 |
| 20100270548 | Semiconductor element and method of making same - A semiconductor element includes a substrate including gallium oxide and having a predetermined plane direction, and a semiconductor layer formed on the substrate, in which, the semiconductor element is in chip form and further includes a first end face formed along a cleaved surface of the substrate and a second end face formed perpendicular to the first end face, wherein the first end face has a stronger cleavage property than the second end face. | 2010-10-28 |
| 20100270549 | Semiconductor Device and Method of Providing Electrostatic Discharge Protection for Integrated Passive Devices - A semiconductor device has an integrated passive device (IPD) formed over a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed over the first side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed over the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed over the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed over the substrate and electrically connects the conductive layer to a ground point. | 2010-10-28 |
| 20100270550 | Pixel Structure and the Method of Forming the Same - A pixel structure includes a drain shielding extension portion disposed on a floating semiconductor layer, wherein the floating semiconductor layer is formed together with a thin-film transistor channel layer. Therefore, the total thickness of the floating semiconductor layer and the drain shielding extension portion is increased, such that the distance between the gate line and the drain shielding extension portion is enlarged, and the coupling capacitance between the gate line and the drain shielding extension portion can be lowered. Therefore, the display panel with the pixel structure of the present invention can have low coupling capacitance so as to improve the flicker phenomena obviously. | 2010-10-28 |
| 20100270551 | BOTTOM GATE THIN FILM TRANSISTOR AND ACTIVE ARRAY SUBSTRATE - A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other. | 2010-10-28 |
| 20100270552 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A protrusion of dry-etched pattern of a thin film transistor substrate generated due to a difference between isotropy of wet etching and anisotropy of dry etching is removed by forming a plating part on a surface of the wet etched pattern through an electroless plating method. If the plating part is formed on a data pattern layer of the substrate, the width or the thickness of the data pattern layer may be increased without loss of aperture ratio, the channel length of the semiconductor layer may be reduced under the limit according to the stepper resolution and the protrusion part of the semiconductor layer may be removed. As a result, the aperture ratio may be increased, the resistance may be reduced, and the driving margin may be increased due to rising of the ion current. Furthermore, the so-called water-fall noise phenomenon may be eliminated. | 2010-10-28 |
| 20100270553 | LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a thin film transistor having high performance in a liquid crystal display, and a manufacturing method of a liquid crystal display according to an exemplary embodiment of the present invention that includes: forming a gate line including a gate electrode on a substrate; forming a gate insulating layer on the gate line; forming a data line including a source electrode and a drain electrode facing the source electrode on the gate insulating layer; forming a partition defining a pixel area and having an opening region exposing the gate insulating layer on the gate electrode, the source electrode and the drain electrode on the gate line, and the data line and the drain electrode; forming a semiconductor in the opening region; forming a color filter in the pixel area defined by the partition; and forming a pixel electrode connected to the drain electrode on the color filter. | 2010-10-28 |
| 20100270554 | METHOD OF REFORMING A METAL PATTERN, ARRAY SUBSTRATE, AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE - A method of reforming a metal pattern for improving the productivity and reliability of a manufacturing process, an array substrate and a method of manufacturing the array substrate are disclosed. In the method, a first wiring pattern is formed on an insulation substrate. The first wiring pattern is removed. A second wiring pattern is formed on an embossed pattern by using the embossed pattern as an alignment mask. The embossed pattern is defined by a recess formed on a surface of the insulation substrate. Accordingly, the insulation substrate having the recess formed thereon may not be discarded, and may be reused in forming the first wiring pattern. In addition, the embossed pattern defined by the recess is used as an alignment mask, so that the alignment reliability of a metal pattern may be improved. | 2010-10-28 |
| 20100270555 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other. | 2010-10-28 |
| 20100270556 | TFT LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A TFT LCD array substrate and a manufacturing method thereof. The TFT LCD array substrate comprises a substrate. A gate line and a gate electrode that is formed integrally with the gate line are formed on the substrate. A first insulating layer and a semiconductor layer are formed sequentially on the gate line and the gate electrode. A second insulting layer covers sidewalls of the gate line and the gate electrode, the first insulating layer, and the semiconductor layer. An etching stop layer is formed on the semiconductor layer and exposes a part of the semiconductor layer on both sides of the etching stop layer. The TFT LCD of the present invention can be manufactured with a four-mask process. | 2010-10-28 |
| 20100270557 | METHODS OF PRODUCING HIGH UNIFORMITY IN THIN FILM TRANSISTOR DEVICES FABRICATED ON LATERALLY CRYSTALLIZED THIN FILMS - Methods of producing high uniformity in thin film transistor devices fabricated on laterally crystallized thin films are described. A thin film transistor (TFT) includes a channel area disposed in a crystalline substrate, which has grain boundaries that are approximately parallel with each other and are spaced apart with approximately equal spacings. The shape of the channel area includes a non-equiangular polygon that has two opposing side edges that are oriented substantially perpendicular to the grain boundaries. The polygon further has an upper edge and a lower edge. At least a portion of each of the upper and lower edges is oriented at a tilt angle with respect to the grain boundaries. The tilt angles are selected such that the number of grain boundaries covered by the polygon is independent of the location of the channel area within the crystalline substrate. | 2010-10-28 |
| 20100270558 | FABRICATING METHOD OF POLYCRYSTALLINE SILICON THIN FILM, POLYCRYSTALLINE SILICON THIN FILM FABRICATED USING THE SAME - Provided are a method of fabricating a polycrystalline silicon thin film using high temperature heat generated by Joule heating induced by application of an electrical field to a conductive layer, which can ensure process stability at high temperature and thus processing time can be reduced and a polycrystalline silicon thin film having excellent crystallinity can be obtained, a polycrystalline thin film using the method and a thin film transistor including the polycrystalline thin film. The method includes providing a substrate, forming a metal or metal alloy layer having a melting point of 13000 C or more on the substrate, forming an insulating layer on the metal or metal alloy layer, forming an amorphous silicon (a-Si) thin film, an amorphous/polycrystalline composite silicon thin film, or a poly-Si thin film on the insulating layer, and applying an electrical filed to the metal or metal alloy layer to induce Joule heating and generate high temperature heat, and crystallizing and annealing the amorphous silicon (a-Si) thin film, the amorphous/polycrystalline composite silicon thin film, or the poly-Si thin film using the high temperature heat. | 2010-10-28 |
| 20100270559 | FIELD EFFECT TRANSISTOR AND PROCESS FOR MANUFACTURING SAME - A field effect transistor includes: a channel layer | 2010-10-28 |
| 20100270560 | SYSTEM AND METHOD FOR EMITTER LAYER SHAPING - Embodiments of an LED disclosed has an emitter layer shaped to a controlled depth or height relative to a substrate of the LED to maximize the light output of the LED and to achieve a desired intensity distribution. In some embodiments, the exit face of the LED may be selected to conserve radiance. In some embodiments, shaping the entire LED, including the substrate and sidewalls, or shaping the substrate alone can extract 100% or approximately 100% of the light generated at the emitter layers from the emitter layers. In some embodiments, the total efficiency is at least 90% or above. In some embodiments, the emitter layer can be shaped by etching, mechanical shaping, or a combination of various shaping methods. In some embodiments, only a portion of the emitter layer is shaped to form the tiny emitters. The unshaped portion forms a continuous electrical connection for the LED. | 2010-10-28 |
| 20100270561 | Method for manufacturing a cubic silicon carbide single crystal thin film and semiconductor device based on the cubic silicon carbide single crystal thin film - A cubic silicon carbide single crystal thin film is manufactured by a method. A sacrificial layer is formed on a surface of a substrate. A cubic semiconductor layer is formed on the sacrificial layer, the cubic semiconductor layer having at least a surface of cubic crystal structure. A cubic silicon carbide single crystal layer is formed on the cubic semiconductor layer. The sacrificial layer is etched away to release a multilayer structure of the cubic semiconductor layer and the 3C—SiC layer from the substrate. A cubic silicon carbide single crystal thin film of a multilayer structure includes an Al | 2010-10-28 |
| 20100270562 | Semiconductor wafer, semiconductor thin film, and method for manufacturing semiconductor thin film devices - A method for manufacturing a semiconductor thin film device includes: forming a buffer layer on an Si (111) substrate and a single crystal semiconductor layer on the buffer layer; forming an island including the semiconductor layer, buffer layer, and a portion of the substrate; forming a coating layer on the island; etching the substrate along its Si (111) plane to release the island from the substrate, the coating layer serving as a mask; and bonding the released island to another substrate, a released surface of the released island contacting the another substrate. A semiconductor device includes a single crystal semiconductor layer other than Si, which has a semiconductor device formed on a front surface of an Si (111) layer lying in a (111) plane. The layer is bonded to another substrate with a back surface contacting the another substrate or a bonding layer formed on the another substrate. | 2010-10-28 |
| 20100270563 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, ACTIVE MATRIX DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - A method of manufacturing a semiconductor device includes: forming, on one surface of a substrate, source electrodes and drain electrodes, a semiconductor layer provided between the source electrodes and the drain electrodes, and a gate insulator layer provided to cover a surface of the semiconductor layer; forming an insulator layer on a surface of the gate insulator layer, the insulator layer having through portions; and forming electrodes on the gate insulator layer around the bottom of the through portions and on the insulator layer in the vicinity of the through portions by a vapor film formation method simultaneously so as not to come into contact with each other, forming gate electrodes by using the electrodes formed on the gate insulator layer, and forming pixel electrodes electrically connected to the source electrodes or the drain electrodes by using the electrodes formed on the insulator layer. | 2010-10-28 |
| 20100270564 | LED PACKAGE AND BACKLIGHT UNIT USING THE SAME - The invention relates to an LED package having a large beam angle of light emitted from an LED, simplifying a shape of a lens and an assembly process, and to a backlight unit using the same. The LED package includes a housing with a seating recess formed therein and at least one LED seated in the seating recess. The LED package also includes a lens having a predetermined sag on an upper side thereof, covering an upper part of the LED. The LED package and the backlight unit using the same can emit light uniformly without bright spots formed in an output screen, uses a simpler shaped lens with an increased beam angle, and minimizes a color mixing region to achieve miniaturization. | 2010-10-28 |
| 20100270565 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - The invention provides a semiconductor light-emitting device package structure. The semiconductor light-emitting device package structure includes a substrate, N sub-mounts, and N semiconductor light-emitting die modules, wherein N is a positive integer lager than or equal to 1. Each of the sub-mounts is embedded on the substrate and exposed partially. Each of the semiconductor light-emitting die modules is mounted on the exposed surface of one of the sub-mounts. | 2010-10-28 |
| 20100270566 | LIGHT EMITTING DEVICE WITH SELECTIVE REFLECTION FUNCTION - A light emitting device with selective reflection function being applied to general light emitting device and AC-type light emitting device is revealed. The light emitting device includes at least one vertical light emitting unit, at least one selective reflection layer and a phosphor layer. The selective reflection layer is disposed over the vertical light emitting unit and the phosphor layer is arranged over the selective reflection layer. Thus first colored light from the vertical light emitting unit passes the selective reflection layer and then to be converted into second colored light by the phosphor layer. The selective reflection layer reflects the second colored light while the first colored light is mixed with the second colored light to form mixing colored light. By the selective reflection layer that prevents the second colored light emitting into the light emitting unit, the lighting efficiency of the light emitting device is enhanced. | 2010-10-28 |
| 20100270567 | LIGHTING DEVICE - A light emission package includes multiple colored solid state emitters each having a different non-white dominant wavelength in the visible range, and at least one lumiphor arranged to receive emissions from at least one other solid state emitter, with each emitter arranged on or adjacent to a common submount. The at least one other emitter and lumiphor may be arranged in combination to emit white light. Each emitter is independently controllable, permitting color and/or color temperature of a lighting device to be varied during operation of the device. At least one white emitter may be combined with red, green, and blue LEDs. | 2010-10-28 |
| 20100270568 | Light Emitting Device and Method of Fabricating the Same - A light emitting device comprises a light emitting layer section having a double heterostructure of an n-type cladding layer, an active layer and a p-type cladding layer, each composed of AlGaInP stacked in this order. Supposing a bonding object layer having a first main surface side as p type and a second main surface side as n type, a light extraction side electrode is formed to cover the first main surface partially. An n-type transparent device substrate composed of Group III-V compound semiconductor having greater band gap energy than the active layer is bonded to the second main surface of the bonding object layer. On one sides of the transparent device substrate and the bonding object layer, a bonding surface to the other is formed, and an InGaP intermediate layer is formed to have a high concentration Si doping layer formed on the bonding surface side. | 2010-10-28 |
| 20100270569 | OPTOELECTRONIC COMPONENT - The invention relates to an optoelectronic component having at least one semi-conductor body ( | 2010-10-28 |
| 20100270570 | LIGHT EMITTING ELEMENT - The present invention provides a light emitting element comprising a first substrate, a light emitting unit disposed on the first substrate, at least a selective reflection layer disposed on an emitting side of the light emitting unit so that a light of a first color emitted from the light emitting unit passes through the selective reflection layer, and a fluorescent layer disposed on the emitting side of the light emitting unit and converting the light of the first color passing therethrough into a light of a second color, wherein a light of a mixed color is formed by the lights of the first and second color and only the light of the second color is reflected by the selective reflection layer. | 2010-10-28 |
| 20100270571 | SLIM LED PACKAGE - Disclosed herein is a slim LED package. The slim LED package includes first and second lead frames separated from each other, a chip mounting recess formed on one upper surface region of the first lead frame by reducing a thickness of the one upper surface region below other upper surface regions of the first lead frame, an LED chip mounted on a bottom surface of the chip mounting recess and connected with the second lead frame via a bonding wire, and a transparent encapsulation material protecting the LED chip while supporting the first and second lead frames. | 2010-10-28 |
| 20100270572 | PHOTONIC CRYSTAL LED - A semiconductor light emitting diode ( | 2010-10-28 |
| 20100270573 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device, a light emitting device package, and a lighting system including the light emitting device and the light emitting device package. The light emitting device includes a light emitting structure, a dielectric, a second electrode layer, a semiconductor region, and a first electrode. The light emitting device includes a plurality of semiconductor layers that form a heterojunction that produces light and a homojunction that protects the device from a reverse current. | 2010-10-28 |
| 20100270574 | Silicone coated light-emitting diode - A silicone coated light-emitting diode and the method for making the silicone coated light-emitting diode. | 2010-10-28 |
| 20100270575 | AC LED package structure - An AC LED package structure includes a heat-sink slug, an AC LED module, a positive-electrode frame, a negative-electrode frame, and an insulation submount. The AC LED module is electrically connected with the positive-electrode frame and the negative-electrode frame, respectively. The insulation submount is interposed between the AC LED module and the heat-sink slug. The insulation submount is characterized by having a voltage-resistance value greater than 1000 volts. Therefore, it is possible to prevent the AC LED chip of an AC LED device from being broken through by high voltage, causing an electric shock if a human body touches the AC LED device. And moreover, the AC LED device can satisfy the requirements of a certified safety specification. | 2010-10-28 |
| 20100270576 | LIGHT EMITTING DIODE PACKAGE - There is provided a light emitting diode package, including a package body including a recess portion having a housing space and a lead frame mounted on the recess portion to be exposed; a light emitting diode chip mounted to be electrically connected to the lead frame; and a position indicator formed on the lead frame and guiding the mounting position of the light emitting diode chip. | 2010-10-28 |
| 20100270577 | PLASTIC COMPONENT FOR A LIGHTING SYSTEMS - The invention relates to a plastic component for use in a lighting system, the plastic component comprising a semi-aromatic polyamide (X) comprising repeat units derived from aliphatic diamines and dicarboxylic acids wherein: (a) the aliphatic diamines consist a mixture of 10-70 mole % of a short chain aliphatic diamine with 2-5 C atoms and 30-90 mole % of a long chain aliphatic diamine with at least 6 C atoms; (b) the dicarboxylic acids consist of a mixture of 5-65 mole % aliphatic dicarboxylic acid and optionally aromatic dicarboxylic acid other than terephthalic acid, and 35-95 mole % terephthalic acid; and (c) the combined molar amount of terephthalic acid and the long chain aliphatic diamine is at least 60 mole %, relative to the total molar amount of the dicarboxylic acids and diamines. The invention also relates to a polymer composition that can be used for making the said plastic component comprising 100 pbw of a semi-aromatic polyamide (X) and 1-250 pbw of an inorganic material. | 2010-10-28 |
| 20100270578 | Light Emitting Diode Chip with Overvoltage Protection - A light emitting diode chip includes a device for protection against overvoltages, e.g., an ESD protection device. The ESD protection device is integrated into a carrier, on which the semiconductor layer sequence of the light emitting diode chip is situated, and is based on a specific doping of specific regions of said carrier. By way of example, the ESD protection device is embodied as a Zener diode that is connected to the semiconductor layer sequence by means of an electrical conductor structure. | 2010-10-28 |
| 20100270579 | LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device (LED) package and a lighting system including the same. The LED package comprises a package body comprising a recess in an upper portion thereof, and an LED chip provided in the recess of the package body. | 2010-10-28 |
| 20100270580 | SUBSTRATE BASED LIGHT SOURCE PACKAGE WITH ELECTRICAL LEADS - A light source and method for making the same are disclosed. The light source includes a base member and a lead structure. The lead structure is attached to the base member such that the lead structure extends beyond the base member and has an opening for accessing a surface of the base member. A die containing a light emitting semiconductor device is bonded to the surface of the base member. The die is electrically connected to the lead structure and overlaid with a transparent material. An electrically insulating layer is bonded between the lead structure and the base member, the electrically insulating layer having an opening for accessing the surface of the base member. The electrically insulating layer can be an adhesive for bonding the lead structure to the base member. | 2010-10-28 |
| 20100270581 | OPTICAL SEMICONDUCTOR PACKAGE SEALING RESIN MATERIAL - An optical semiconductor package sealing resin material used to seal an optical semiconductor chip in a semiconductor package includes a thermosetting epoxy composition and a hydrophobic smectite clay mineral. The hydrophobic smectite clay mineral is hydrophobized by subjecting a hydrophilic smectite clay mineral to an intercalation reaction with an alkylammonium halide. The smectite clay mineral is bentonite, saponite, hectorite, vermiculite, stevensite, tainiolite, montmorillonite, or nontronite. | 2010-10-28 |
| 20100270582 | Coated light-emitting diode - The present invention relates to a coated light-emitting diode and the method for making the coated light-emitting diode. | 2010-10-28 |
| 20100270583 | MANUFACTURING METHOD OF NITRIDE SEMI-CONDUCTOR LAYER, AND A NITRIDE SEMI-CONDUCTOR LIGHT EMITTING DEVICE WITH ITS MANUFACTURING METHOD - In a process of fabricating a nitride nitride semi-conductor layer of Al | 2010-10-28 |
| 20100270584 | Semiconductor Switching Device with Gate Connection - The present disclosure provides a semiconductor switching device including a substrate having deposited thereon a cathode, an anode and a gate of the semiconductor switching device, and a connection means for electrically connecting the cathode in the gate of the semiconductor switching device to an external circuit unit. The connection includes a cathode-gate connection unit having a coaxial structure including a gate conductor and a cathode conductor for electrically connecting the cathode and the gate of the semiconductor switching device to the external circuit unit. | 2010-10-28 |
| 20100270585 | METHOD FOR MANUFACTURING A REVERSE-CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR - A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask. | 2010-10-28 |
| 20100270586 | WIDE BAND GAP SEMICONDUCTOR DEVICE - A semiconductor device having high reliability and high load short circuit withstand capability while maintaining a low ON resistance is provided, by using a WBG semiconductor as a switching element of an inverter circuit. In the semiconductor device for application to a switching element of an inverter circuit, a band gap of a semiconductor material is wider than that of silicon, a circuit that limits a current when a main transistor is short circuited is provided, and the main transistor that mainly serves to pass a current, a sensing transistor that is connected in parallel to the main transistor and detects a microcurrent proportional to a current flowing in the main transistor, and a lateral MOSFET that controls a gate of the main transistor on the basis of an output of the sensing transistor are formed on the same semiconductor. | 2010-10-28 |
| 20100270587 | REVERSE-CONDUCTING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A REVERSE-CONDUCTING SEMICONDUCTOR DEVICE - A reverse-conducting semiconductor device (RC-IGBT) including a freewheeling diode and an insulated gate bipolar transistor (IGBT), and a method for making the RC-IGBT are provided. A wafer has first and second sides emitter and collector sides of the IGBT, respectively. At least one layer of a first or second conductivity type is created on the second side before at least one layer of a different conductivity type is created on the second side. The at least one layer of the first or second conductivity type and the at least one layer of the different conductivity type are arranged alternately in the finalized RC-IGBT. A second electrical contact, which is in direct electrical contact with the layers of the first or second and different conductivity types, is created on the second side. A shadow mask is applied on the second side, and the layer of the first or second conductivity type is created through the shadow mask. Another layer of the first or second conductivity type can be created on the second side, and a shadow mask is applied on the other layer of the first or second conductivity type, and at least one electrically conductive island, which is part of a second electrical contact in the finalized RC-IGBT, is created through the shadow mask. The electrically conductive island is used as a mask for the creation of the layer of the different conductivity type, and those parts of the other layer of the first conductivity type which are covered by an electrically conductive island form the layer of the first or second conductivity type. | 2010-10-28 |
| 20100270588 | Formulations for voltage switchable dielectric material having a stepped voltage response and methods for making the same - Formulations for voltage switchable dielectric materials include two or more different types of semiconductive materials uniformly dispersed within a dielectric matrix material. The semiconductive materials are selected to have different bandgap energies in order to provide the voltage switchable dielectric material with a stepped voltage response. The semiconductive materials can comprise inorganic particles, organic particles, or an organic material that is soluble in, or miscible with, the dielectric matrix material. Formulations optionally can also include electrically conductive materials. At least one of the conductive or semiconductive materials in a formulation can comprise particles characterized by an aspect ratio of at least 3 or greater. | 2010-10-28 |
| 20100270589 | PHOTODETECTORS CONVERTING OPTICAL SIGNAL INTO ELECTRICAL SIGNAL - Provided is a photodetector converting an optical signal into an electrical signal. The photodetector includes: a plurality of semiconductor layers sequentially stacked on a substrate; a plurality of photoelectric conversion units formed in the semiconductor layers, respectively, and having different spectral sensitivities from each other; and buffer layers interposed between the adjacent semiconductor layers, respectively. Each of the buffer layers alleviates stress between the adjacent semiconductor layers. | 2010-10-28 |
| 20100270590 | ALD OF SILICON FILMS ON GERMANIUM - The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An example embodiment includes a tantalum nitride gate electrode on a hafnium dioxide gate dielectric on the silicon film (TaN/HfO | 2010-10-28 |
| 20100270591 | HIGH-ELECTRON MOBILITY TRANSISTOR - Disclosed are high electron mobility transistors (HEMTs). In some embodiments, a HEMT includes a channel layer composed of a first compound semiconductor material and one or more barrier layers disposed on either one side or both sides of the channel layer and composed of a second compound semiconductor material. | 2010-10-28 |
| 20100270592 | SEMICONDUCTOR DEVICE - Semiconductor devices having at least one barrier layer with a wide energy band gap are disclosed. In some embodiments, a semiconductor device includes at least one active layer, and at least one barrier layer disposed on at least one surface of the at least one active layer. The at least one barrier layer has a wider energy band gap than the energy band gap of the at least one active layer. The compounds of the active layer and the barrier layer may be selected to reduce relaxation time of an electron or hole in the active layer. | 2010-10-28 |
| 20100270593 | INTEGRATED CIRCUIT 3D MEMORY ARRAY AND MANUFACTURING METHOD - A 3D memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable element and a rectifier. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension. | 2010-10-28 |
| 20100270594 | IMAGE SENSOR - An image sensor according to the present invention includes a second conductivity type first impurity region provided on a surface of a first conductivity type semiconductor substrate for constituting a transfer channel for signal charges, a charge increasing portion provided on the first impurity region for increasing the amount of signal charges by impact ionization, an increasing electrode provided on the side of the surface of the semiconductor substrate for applying a voltage to the charge increasing portion, and a second conductivity type second impurity region opposed to the first impurity region through a prescribed region of the semiconductor substrate and suppliable with charges. | 2010-10-28 |
| 20100270595 | Device for Detection of a Gas or Gas Mixture and Method for Manufacturing Such a Device - A device for detecting a gas or gas mixture has a first and a second gas sensor. The first gas sensor is a MOSFET, which comprises a first source, a first drain, a first channel zone disposed between the latter elements, and a first gas sensitive layer capacitively coupled to the first channel zone that contains palladium and reacts to a change in the concentration of the gas to be detected with a change in its work function. The second gas sensor has, in a semiconductor substrate, a second source, a second drain, and a second channel zone between the latter elements, which is capacitively coupled via an air gap to a suspended gate. The latter comprises a second gas sensitive layer that reacts to a change in the concentration of the gas to be detected with a change in its work function. The second gas sensitive layer is arranged on a support layer and faces the air gap. The support layer is formed by another semiconductor substrate, and the first gas sensor is integrated in the front side of the second semiconductor substrate facing away from the air gap. | 2010-10-28 |
| 20100270596 | MEMS SENSOR, METHOD OF MANUFACTURING MEMS SENSOR, AND ELECTRONIC APPARATUS - A MEMS sensor includes: a substrate; a fixed electrode portion formed in the substrate; a movable weight portion formed above the fixed electrode portion via a gap; a movable electrode portion formed in the movable weight portion and disposed so as to face the fixed electrode portion; a supporting portion; and a connecting portion that couples the supporting portion with the movable weight portion and is elastically deformable, wherein the movable weight portion is a stacked structure having conductive layers and an insulating layer, and plugs having a larger specific gravity than the insulating layer are embedded in the insulating layer. | 2010-10-28 |
| 20100270597 | METHOD AND APPARATUS FOR PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS - Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone. | 2010-10-28 |
| 20100270598 | METHOD FOR FORMING HIGHLY STRAINED SOURCE/DRAIN TRENCHES - A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable I | 2010-10-28 |
| 20100270599 | TRANSISTOR STRUCTURE WITH HIGH RELIABILITY AND METHOD FOR MANUFACTURING THE SAME - A transistor structure with high reliability includes a substrate unit, a solid ozone boundary layer, a gate oxide layer and a gate electrode. In addition, the substrate unit has a substrate body, a source electrode exposed on a top surface of the substrate body, and a drain electrode exposed on the top surface of the substrate body and separated from the source electrode by a predetermined distance. The solid ozone boundary layer is gradually grown on the top surface of the substrate body by continually mixing gaseous ozone into deionized water under 40˜95□, and the solid ozone boundary layer is formed between the source electrode and the drain electrode and formed on the substrate body. The gate oxide layer is formed on a top surface of the solid ozone boundary layer. The gate electrode is formed on a top surface of the gate oxide layer. | 2010-10-28 |
| 20100270600 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF DESIGNING THE SAME - A method of designing a semiconductor integrated circuit device includes: arranging standard cells constituting a MISFET; analyzing an operation timing and/or power consumption of the arranged standard cells; identifying one of the standard cells that is desired to have improved properties as a cell of interest based on the obtained analysis result; optimizing an arrangement and a shape of blank areas around the cell of interest taking into account an influence of a well proximity effect; and replacing the blank area and/or the cell of interest with a WPE-reduced or WPE-enhancing cell. | 2010-10-28 |
| 20100270601 | Semiconductor Device Having Reduced Single Bit Fails and a Method of Manufacture Thereof - One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein. | 2010-10-28 |
| 20100270602 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device and a method for manufacturing the same are disclosed, which reduce parasitic capacitance generated between a storage node contact and a bit line of a high-integration semiconductor device. A method for manufacturing a semiconductor memory device includes forming a buried word line in an active region of a cell region, forming an insulation layer in the cell region and a lower electrode layer of a gate in a peripheral region so that a height of the insulation layer is substantially equal to that of the lower electrode layer, and providing a first conductive layer over the cell region and the peripheral region to form a bit line layer and an upper electrode layer. | 2010-10-28 |
| 20100270603 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises gates comprising a first conductive layer, landing plug contacts formed adjacent to the gate and formed of a second conductive layer, a bit line formed over the landing plug contacts and formed of a third conductive layer, and storage electrode contacts formed over the landing plug contacts and the bit line and formed of a fourth conductive layer. The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are made of the same material. | 2010-10-28 |
| 20100270604 | Non-Volatile Memories and Methods of Fabrication Thereof - Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region is disposed adjacent an interface between the oxide layer and the semiconductor substrate. After the first nitridation step, the oxide layer is exposed to a second nitridation step to form a second nitrogen rich region. A first gate electrode is formed on the oxide layer, wherein the second nitrogen rich region is disposed adjacent an interface between the oxide layer and the first gate electrode. | 2010-10-28 |
| 20100270605 | NONVOLATILE MEMORY CELL AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate. | 2010-10-28 |
| 20100270606 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm. | 2010-10-28 |
| 20100270607 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell. | 2010-10-28 |
| 20100270608 | Integrated Circuits And Fabrication Using Sidewall Nitridation Processes - Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches. | 2010-10-28 |
| 20100270609 | Modification of charge trap silicon nitride with oxygen plasma - A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer. | 2010-10-28 |
| 20100270610 | NROM FLASH MEMORY DEVICES ON ULTRATHIN SILICON - An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top. | 2010-10-28 |
| 20100270611 | SEMICONDUCTOR DEVICE INCLUDING A MOS TRANSISTOR AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar. | 2010-10-28 |
| 20100270612 | Method for producing a vertical transistor component - A method for producing a vertical transistor component includes providing a semiconductor substrate, applying an auxiliary layer to the semiconductor substrate, and patterning the auxiliary layer for the purpose of producing at least one trench which extends as far as the semiconductor substrate and which has opposite sidewalls. The method further includes producing a monocrystalline semiconductor layer on at least one of the sidewalls of the trench, producing an electrode insulated from the monocrystalline semiconductor layer on the at least one sidewall of the trench and the semiconductor substrate. | 2010-10-28 |
| 20100270613 | Method for manufacturing semiconductor device, and semiconductor device - In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upper end of a trench. This source interconnect layer is connected to a source electrode formed in the transistor region immediately above the trench. A gate extending region is provided outside the source extending region, and the gate electrode and a gate interconnect layer are connected. The gate electrode is formed by performing etchback without forming a resist pattern, after a polysilicon film is formed. Here, the polysilicon film remains like a side-wall on the sidewall of the portion of the source interconnect layer protruding from the upper end of the trench. | 2010-10-28 |
| 20100270614 | PROCESS FOR MANUFACTURING DEVICES FOR POWER APPLICATIONS IN INTEGRATED CIRCUITS - An embodiment method for forming a MOS transistor for power applications in a substrate of semiconductor material, said method being integrated in a process for manufacturing integrated circuits which uses an STI technique for forming the insulating regions. The method includes the phases of forming an insulating element on a top surface of the substrate and forming a control electrode on a free surface of the insulating element. The insulating element insulates the control electrode from the substrate. Said insulating element comprises a first portion and a second portion. The extension of the first portion along a first direction perpendicular to the top surface is lower than the extension of the second portion along such first direction. The phase of forming the insulating element comprises generating said second portion by locally oxidizing the top surface. | 2010-10-28 |
| 20100270615 | METHOD FOR INCREASING BREAKING DOWN VOLTAGE OF LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR - A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed on a portion of the p-type bulk and one of the plurality of field oxide layers. At least one deep trench isolation structure is disposed in the p-type bulk and adjacent to the n-type well region. | 2010-10-28 |
| 20100270616 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device in which the degradation of electric characteristics can be inhibited. A semiconductor substrate has a main surface, and a trench in the main surface. A buried insulating film is buried in the trench. The trench has one wall surface and the other wall surface which oppose each other. A gate electrode layer is located over at least the buried insulating film. The trench has angular portions which are located between the main surface of at least either one of the one wall surface and the other wall and a bottom portion of the trench. | 2010-10-28 |
| 20100270617 | Nanowire electronic devices and method for producing the same - The present invention is directed to an electrical device that comprises a first and a second fiber having a core of thermoelectric material embedded in an electrically insulating material, and a conductor. The first fiber is doped with a first type of impurity, while the second fiber is doped with a second type of impurity. A conductor is coupled to the first fiber to induce current flow between the first and second fibers. | 2010-10-28 |
| 20100270618 | PRODUCTION METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The present invention provides a production method of a semiconductor device, capable of improving surface flatness of a semiconductor chip formed on a semiconductor substrate and thereby suppressing a variation in electrical characteristics of the semiconductor chip transferred onto a substrate with an insulating surface, and further capable of improving production yield. The present invention provides a production method of a semiconductor device including a semiconductor chip on a substrate with an insulating surface, the semiconductor chip having a conductive pattern film,
| 2010-10-28 |
| 20100270619 | FIN FIELD EFFECT TRANSISTOR HAVING LOW LEAKAGE CURRENT AND METHOD OF MANUFACTURING THE FINFET - Provided is a fin field effect transistor (FinFET) having low leakage current and a method of manufacturing the same. The FinFET includes: a bulk silicon substrate; a fence-shaped body formed by patterning the substrate; an insulating layer formed on a surface of the substrate to a first height of the fence-shaped body; a gate insulating layer formed at side walls and an upper surface of the fence-shaped body at which the insulating layer is not formed; a gate electrode formed on the gate insulating layer; source/drain formed at regions of the fence-shaped body where the gate electrode is not formed. The gate electrode includes first and second gate electrodes which are in contact with each other and have different work functions. Particularly, the second gate electrode having a low work function is disposed to be close to the drain. As a result, the FinFET according to the present invention increases a threshold voltage by using a material having the high work function for the gate electrode and lowers the work function of the gate electrode overlapping with the drain, so that gate induced drain leakage (GIDL) can be reduced. | 2010-10-28 |
| 20100270620 | System and Method for Constructing Shielded Seebeck Temperature Difference Sensor - An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor. | 2010-10-28 |
| 20100270621 | Semiconductor device and method of manufacturing the semiconductor device - A semiconductor device includes: a FinFET (Fin Field Effect Transistor); and a PlanarFET (Planar Field Effect Transistor). The FinFET is provided on a chip. The PlanarFET is provided on the chip. A second gate insulating layer of the PlanarFET is thicker than a first gate insulating layer of the FinFET. | 2010-10-28 |
| 20100270622 | Semiconductor Device Having a Strain Inducing Sidewall Spacer and a Method of Manufacture Therefor - The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure over a substrate, and forming a strain inducing sidewall spacer proximate a sidewall of the gate structure, the strain inducing sidewall configured to introduce strain in a channel region below the gate structure. | 2010-10-28 |
| 20100270623 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device fabrication method including: forming a gate conductor including a gate for a transistor in the first region, and a gate for a transistor in the second region, and a first film over a first stress film for covering the transistors; etching the first film from the second region by using a mask layer and etching the first film under the mask layer in the direction parallel to the surface of the semiconductor substrate by a first width from an edge of the first mask layer, and the first stress film from the second region; forming a second stress film covering the first stress film and the first film; etching the second stress film so that a portion of the second stress film overlaps a portion of the first stress film and a portion of the first film; and forming a contact hole connected with the gate conductor. | 2010-10-28 |
| 20100270624 | REDUCED-STEP CMOS PROCESSES FOR LOW COST RADIO FREQUENCY IDENTIFICATION DEVICES - Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular needs for low-cost integrated circuits such as RFID devices (for example, reduced needs for performance, power and longevity) and by identifying a reduced set of CMOS process steps, an advantageous solution is achieved for producing low-cost integrated circuits and low-cost RFID devices. | 2010-10-28 |
| 20100270625 | METHOD OF FABRICATING HIGH-VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR DEVICES - A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing the topography associated with the transistor. The process includes forming the gate oxide region and a field oxide region on a substrate. A polysilicon layer is formed on the gate oxide region and the field oxide region. A sacrificial nitride layer is formed on the polysilicon layer, wherein the sacrificial nitride layer has a thickness approximately equal to or greater than a thickness of the gate oxide region. A polysilicon gate is formed by selectively removing portions of the polysilicon layer and the sacrificial layer to expose a portion of the gate oxide region adjacent to the polysilicon gate. Source/drain regions are formed adjacent to the polysilicon gate using lightly-doped drain (LDD) implantation. A spacer layer is formed over the polysilicon gate and source/drain regions. Portions of the spacer layer are selectively removed, along with the sacrificial nitride layer and the gate oxide region to form sidewall spacers at each end of the polysilicon gate. A pre-metal dielectric layer is formed on the high-voltage MOS transistor, and the pre-metal dielectric layer is planarized. | 2010-10-28 |
| 20100270626 | ATOMIC LAYER DEPOSITION OF HAFNIUM LANTHANUM OXIDES - There is provided an improved method for depositing thin films using precursors to deposit binary oxides by atomic layer deposition (ALD) techniques. Also disclosed is an ALD method for depositing a high-k dielectric such as hafnium lanthanum oxide (HfLaO) on a substrate. Embodiments of the present invention utilize a combination of ALD precursor elements and cycles to deposit a film with desired physical and electrical characteristics. Electronic components and systems that integrate devices fabricated with methods consistent with the present invention are also disclosed. | 2010-10-28 |
| 20100270627 | METHOD FOR PROTECTING A GATE STRUCTURE DURING CONTACT FORMATION - A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions. | 2010-10-28 |
| 20100270628 | MULTIFUNCTION MENS ELEMENT AND INTEGRATED METHOD FOR MAKING MOS AND MULTIFUNCTION MENS - A multifunction MENS element includes a first cantilever, a second cantilever and a MENS component. The first cantilever, the second cantilever and the MENS component together form a MENS structure. The MENS component includes an inductor device. | 2010-10-28 |
| 20100270629 | PRESSURE SENSOR AND MANUFACTURING METHOD THEREOF - The pressure sensor according to the present invention has a sensor chip having a first semiconductor layer that has an opening portion, and a second semiconductor layer, formed on the first semiconductor layer, having a recessed portion that forms a diaphragm and a base, having a pressure guiding hole that is connected to the opening portion, bonded to the sensor chip. The recessed portion in the second semiconductor layer is larger than the opening portion of the first semiconductor layer. The opening portion of the first semiconductor layer has an opening diameter on the second semiconductor layer side that is larger than the opening diameter on the base side. | 2010-10-28 |
| 20100270630 | Semiconductor device and method for manufacturing the same - A semiconductor device includes: a first substrate made of semiconductor and having first regions, which are insulated from each other and disposed in the first substrate; and a second substrate having electric conductivity and having second regions and insulation trenches. Each insulation trench penetrates the second substrate so that the second regions are insulated from each other. The first substrate provides a base substrate, and the second substrate provides a cap substrate. The second substrate is bonded to the first substrate so that a sealed space is provided between a predetermined surface region of the first substrate and the second substrate. The second regions include an extraction conductive region, which is coupled with a corresponding first region. | 2010-10-28 |
| 20100270631 | MEMS MICROPHONE - A MEMS microphone ( | 2010-10-28 |
| 20100270632 | Resonator and Methods of Making Resonators - A resonator and method of making a resonator are provided. A particular method includes etching a silicon substrate to form a resonator structure. The resonator structure includes at least one resonator beam. The method also includes converting at least a portion of the at least one resonator beam to dry oxide. | 2010-10-28 |
| 20100270633 | NONVOLATILE MEMORY DEVICE - Ferromagnetic layers have magnetizations oriented to such directions as to cancel each other, so that the net magnetization of the ferromagnetic layers is substantially zero. That is, the ferromagnetic layers are exchange-coupled with a nonmagnetic layer interposed therebetween, thereby forming an SAF structure. Since the net magnetization of the ferromagnetic layers forming the SAF structure is substantially zero, the magnetization of a recording layer is determined by the magnetization of a ferromagnetic layer. Therefore, the ferromagnetic layer is made of a CoFeB alloy having high uniaxial magnetic anisotropy, and the ferromagnetic layers are made of a CoFe alloy having a high exchange-coupling force. | 2010-10-28 |
| 20100270634 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH | 2010-10-28 |
