43rd week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120267744 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - There are provided semiconductor substrate, ground layer formed on semiconductor substrate and having an upper surface corresponding to pixel region, the upper surface being lower than an upper surface corresponding to peripheral circuit region, a plurality of color filters disposed two-dimensionally on the upper surface corresponding to pixel region in ground layer, and partition wall provided between color filters. In a section which is orthogonal to the upper surface corresponding to pixel region in ground layer, an occupied area of partition wall provided in outer portion disposed in contact with peripheral circuit region is smaller than that of partition wall provided in central portion of pixel region. | 2012-10-25 |
20120267745 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid-state imaging device includes a semiconductor substrate having a photodiode formed therein, and a lamination structure of an insulating film and a wiring. The solid-state imaging device includes a partition wall formed on a wiring layer, constituted by an inorganic material and formed in a portion corresponding to a portion provided between the adjacent photodiodes, and a color filter constituted by an organic material and formed between the adjacent partition walls. The solid-state imaging device includes an adhesion layer constituted by an organic material and formed between a side surface of the partition wall and the color filter. An adhesive property of the adhesion layer to the color filter is higher than that of the partition wall to the color filter, and an adhesive property of the adhesion layer to the partition wall is higher than an adhesive property of the color filter to the partition wall. | 2012-10-25 |
20120267746 | PHOTO DETECTOR ARRAY OF GEIGER MODE AVALANCHE PHOTODIODES FOR COMPUTED TOMOGRAPHY SYSTEMS - The photo detector array is configured to generate pulses with short rise and fall times because each Geiger mode avalanche photodiode includes an anode contact, a cathode contact, an output contact electrically insulated from the anode and cathode contacts, a semiconductor layer, and at least one shield or metal structure in the semiconductor layer capacitively coupled to the semiconductor layer and coupled to the output contact. The output contacts of all Geiger mode avalanche photodiodes are connected in common and are configured to provide for detection of spikes correlated to avalanche events on any avalanche photodiode of the array. | 2012-10-25 |
20120267747 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid-state image pickup device according to the present invention is a backside-illuminated solid-state image pickup device that includes a plurality of pixels each having a photoelectric conversion portion. A p-type semiconductor region | 2012-10-25 |
20120267748 | SEMICONDUCTOR DEVICE INCLUDING SCHOTTKY BARRIER JUNCTION AND PN JUNCTION - A semiconductor device includes a first conductivity-type semiconductor stack including the recesses which extend from a first principal surface toward a second principal surface and have bottoms not reaching the second principal surface, the second conductivity-type anode regions which are embedded at a distance from one another in the first principal surface, each of which has a part of an outer edge region exposed to a side surface of the corresponding recess, an anode electrode which is provided on the first principal surface of the semiconductor stack to form a Schottky barrier junction with the semiconductor stack in a region where the plurality of anode regions are not formed and form ohmic junctions with the anode regions; and a cathode electrode provided on the second principal surface of the semiconductor stack. | 2012-10-25 |
20120267749 | SEMICONDUCTOR DEVICE HAVING FUSE ELEMENTS AND GUARD RING SURROUNDING THE FUSE ELEMENTS - The semiconductor memory device has a fuse area in which fuse elements for registering addresses of defective memory cells are arranged. A guard ring is formed around the fuse area and is covered by a passivation film. The passivation film above the fuse area has an opening. The guard ring has a first ring in a first layer, a second ring in a second layer and a third ring in a third layer. These rings are connected by a first connecting ring and a second connecting ring. The first ring is positioned at an inward part of the second ring to provide an area unoccupied by the first ring beneath the second ring. | 2012-10-25 |
20120267750 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having a bootstrap-type driver circuit includes a cavity for a SON structure formed below a bootstrap diode Db, and a p-type floating region formed in a n | 2012-10-25 |
20120267751 | INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC - A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel. | 2012-10-25 |
20120267752 | INDEPENDENTLY VOLTAGE CONTROLLED VOLUME OF SILICON ON A SILICON ON INSULATOR CHIP - A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide. | 2012-10-25 |
20120267753 | INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a integrated circuit device and a method for fabricating the same. The integrated circuit device includes a semiconductor substrate having a dielectric layer disposed over the semiconductor substrate and a passive element disposed over the dielectric layer. The integrated circuit further includes an isolation matrix structure, underlying the passive element, wherein the isolation matrix structure includes a plurality of trench regions each being formed through the dielectric layer and extending into the semiconductor substrate, the plurality of trench regions further including an insulating material and a void area. | 2012-10-25 |
20120267754 | Method of Fabricating Isolated Capacitors and Structure Thereof - A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors. | 2012-10-25 |
20120267755 | SEMICONDUCTOR DEVICE WITH ELECTRIC FUSE HAVING A FLOWING-OUT REGION - A method for cutting an electric fuse formed on a semiconductor substrate by applying a predetermined electric voltage between a first interconnect and a second interconnect to flow an electric current in the electric fuse such that the electric conductor is flowed toward outside from the second interconnect to form a void region between the via and the first interconnects or in the via. | 2012-10-25 |
20120267756 | Semiconductor Package with Embedded Spiral Inductor - In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector. | 2012-10-25 |
20120267757 | CAPACITOR STRUCTURE WITH METAL BILAYER AND METHOD FOR USING THE SAME - A method for using a metal bilayer is disclosed. First, a bottom electrode is provided. Second, a dielectric layer which is disposed on and is in direct contact with the lower electrode is provided. Then, a metal bilayer which serves as a top electrode in a capacitor is provided. The metal bilayer is disposed on and is in direct contact with the dielectric layer. The metal bilayer consists of a noble metal in direct contact with the dielectric layer and a metal nitride in direct contact with the noble metal. | 2012-10-25 |
20120267758 | Isolated Capacitors Within Shallow Trench Isolation - A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer ( | 2012-10-25 |
20120267759 | DECOUPLING CAPACITORS RECESSED IN SHALLOW TRENCH ISOLATION - A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer. | 2012-10-25 |
20120267760 | CAPACITOR AND MANUFACTURING METHOD THEREOF - A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer. | 2012-10-25 |
20120267761 | CAPACITOR - A capacitor is provided. The capacitor includes first and second electrode layers facing each other, a first conductive pattern disposed between the first and second electrode layers, the first conductive pattern forming a closed loop in plan view, a second conductive pattern disposed within an inner space surrounded by the closed loop of the first conductive pattern, the second conductive pattern being spaced from the first conductive pattern, and a first contact plug passing through the second conductive pattern to contact the first and second electrode layers. | 2012-10-25 |
20120267762 | Capacitor Structure - One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates. | 2012-10-25 |
20120267763 | INTEGRATED CIRCUITS HAVING PLACE-EFFICIENT CAPACITORS AND METHODS FOR FABRICATING THE SAME - An integrated circuit having a place-efficient capacitor includes a lower capacitor electrode having a surface area comprised of an inner surface area of a partial opening and a via opening formed in a patterned dielectric layer on a semiconductor substrate, a capacitor insulating layer overlying the lower capacitor electrode, and an upper capacitor electrode including a metal fill material filling the partial opening and the via opening and having a surface area that includes the inner surface area of the partial opening and via opening. | 2012-10-25 |
20120267764 | BIPOLAR JUNCTION TRANSISTOR WITH LAYOUT CONTROLLED BASE AND ASSOCIATED METHODS OF MANUFACTURING - The present technology discloses a bipolar junction transistor (BJT) device integrated into a semiconductor substrate. The BJT device comprises a collector, a base and an emitter. The collector is of a first doping type on the substrate; the base is of a second doping type in the collector from the top surface of the semiconductor device and the base has a base depth; and the emitter is of a first doping type in the base from the top surface of the semiconductor device. The base depth is controlled by adjusting a layout width in forming the base. | 2012-10-25 |
20120267765 | WAFER-LEVELED CHIP PACKAGING STRUCTURE AND METHOD THEREOF - A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias. | 2012-10-25 |
20120267766 | RESIST UNDERLAYER COMPOSITION AND PROCESS OF PRODUCING INTEGRATED CIRCUIT DEVICES USING THE SAME - A resist underlayer composition includes a solvent and an organosilane condensation polymerization product, the organosilane condensation polymerization product including about 40 to about 80 mol % of a structural unit represented by the following Chemical Formula 1, | 2012-10-25 |
20120267767 | SEMICONDUCTOR OVERLAPPED PN STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities. | 2012-10-25 |
20120267768 | FORMATION OF ALPHA PARTICLE SHIELDS IN CHIP PACKAGING - A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads. | 2012-10-25 |
20120267769 | INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS - A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively. | 2012-10-25 |
20120267770 | DEVICE AND METHOD INCLUDING A SOLDERING PROCESS - A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate. | 2012-10-25 |
20120267771 | STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR - A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. | 2012-10-25 |
20120267772 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device having suspension leads with less distortion. In QFN having a plurality of external terminal portions at the periphery of the bottom surface of a sealing body, a plurality of leads is linked to a plurality of long suspension leads of the QFN at an intermediate portion thereof or at between the intermediate portion and a position near the die pad. These long suspension leads are each supported by these leads, making it possible to suppress distortion of each of the suspension leads in a wire bonding step or molding step in the fabrication of the QFN. | 2012-10-25 |
20120267773 | Functional Capping - A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices. | 2012-10-25 |
20120267774 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices. | 2012-10-25 |
20120267775 | System and Method to Manufacture an Implantable Electrode - The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason. | 2012-10-25 |
20120267776 | CHIP STACK PACKAGE - A chip stack package is provided. The chip stack package includes an n number of chips stacked on each other and an n number of interconnection strands connecting the chips. The interconnection strands are spirally rotated and insulated from each other. In one embodiment, the chips are substantially structurally identical. In another embodiment, each of the interconnection strands is electrically coupled to a chip selection signal. | 2012-10-25 |
20120267777 | MULTI-CHIP MODULE WITH STACKED FACE-DOWN CONNECTED DIES - A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate. | 2012-10-25 |
20120267778 | CIRCUIT BOARD, SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING CIRCUIT BOARD, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A circuit board includes: an electrode portion which has a copper layer, a copper oxide layer formed thereon, and a removal portion formed by partially removing the copper oxide layer so as to partially expose the copper layer from the copper oxide layer; and a solder bump for flip chip mounting formed on the copper layer exposed by the removal portion. | 2012-10-25 |
20120267779 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3. | 2012-10-25 |
20120267780 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other. | 2012-10-25 |
20120267781 | MECHANISMS FOR FORMING COPPER PILLAR BUMPS USING PATTERNED ANODES - This disclosure relates to a bump structure on a substrate including a copper layer, wherein the copper layer fills an opening created in a dielectric layer and a polymer layer. The bump structure further includes an under-bump-metallurgy (UBM) layer lines the opening and the copper layer is deposited over the UBM layer. The bump structure further includes a surface of the copper layer facing away from the substrate is curved. This disclosure also relates to two bump structures with different heights on a substrate where a thickness of the first bump structure is different than a thickness of the second bump structure. This disclosure also relates to a semiconductor device including a bump structure. | 2012-10-25 |
20120267782 | PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE - Disclosed is a package-on-package semiconductor device comprising a bottom package, a top package thereon and a ACA (Anisotropic Conductive Adhesive) layer. A plurality of ball pads are disposed on the peripheries of an upper surface of the substrate of the bottom package. A plurality of solder balls are disposed at the peripheries of the lower surface of the substrate of the top package. The ACA layer having a central opening is interposed between the bottom package and the top package where the ACA layer contains a plurality of conductive particles. Therein, the size of the central opening and the thickness of the ACA layer are selected such that the anisotropic conductive adhesive layer adheres the peripheries of the upper surface of the bottom package to the peripheries of the lower surface of the top package and the solder balls are encapsulated inside the anisotropic conductive adhesive layer. The solder balls encapsulate some of the conductive particles to mechanically joint and electrically connect to the ball pads. Thereby, the bonding strength of the solder balls can be improved and the warpage of the substrate of the bottom package is effectively reduced to avoid failure of electrical connections between both packages caused by the breaking of soldering joints. | 2012-10-25 |
20120267783 | STACKED-SUBSTRATE STRUCTURE - The stacked-substrate structure includes a first substrate having a first die embedded therein, a second substrate having a second die embedded therein, a plurality of soldering elements, and a third die. The soldering elements are disposed between the first and the second substrates and connected to the first and the second substrates. The first and the second substrates are electrically connected via the soldering elements. The first substrate, the second substrate, and the soldering elements define an accommodating space. The third die is arranged in the accommodating space and is connected to one surface of the first substrate. The third die is electrically connected to the first and the second dies via the first substrate. Thus, the thickness of the stacked-substrate structure can be reduced, and the first and the second dies of the stacked-substrate structure can be test separately in different platforms. | 2012-10-25 |
20120267784 | Semiconductor Device and Bonding Wire - A semiconductor device includes a semiconductor chip, a contact pad of the semiconductor chip and a first layer arranged over the contact pad. The first layer includes niobium, tantalum or an alloy including niobium and tantalum. | 2012-10-25 |
20120267785 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING DAMASCENE INTERCONNECTS THEREIN WITH METAL DIFFUSION BARRIER LAYERS AND DEVICES FORMED THEREBY - Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique. | 2012-10-25 |
20120267786 | MICROELECTRONIC DEVICES WITH THROUGH-SILICON VIAS AND ASSOCIATED METHODS OF MANUFACTURING - Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material. | 2012-10-25 |
20120267787 | Wafer Level Chip Scale Package Method Using Clip Array - A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface. | 2012-10-25 |
20120267788 | Hybrid TSV and Method for Forming the Same - Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion. | 2012-10-25 |
20120267789 | VIAS IN POROUS SUBSTRATES - A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction. | 2012-10-25 |
20120267790 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction. | 2012-10-25 |
20120267791 | MULTI CHIP PACKAGE, MANUFACTURING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE MULTI CHIP PACKAGE - A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes. | 2012-10-25 |
20120267792 | SEMICONDUCTOR DEVICE - A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal. | 2012-10-25 |
20120267793 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region. | 2012-10-25 |
20120267794 | STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME - Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical. | 2012-10-25 |
20120267795 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer, an active region defined in the semiconductor layer, first fingers provided on the active region and arranged in parallel with respect to a first direction, second fingers provided on the active region and interleaved with the first fingers, a bus line that is provided on an outside of the active region and interconnects the first fingers, first air bridges that are provided on the outside of the active region and are extended over the bus line, and that are connected to the second fingers, and second air bridges that are provided on the outside of the active region and are arranged in a second direction which crosses to the first direction, and that interconnect the first air bridges. | 2012-10-25 |
20120267796 | FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES - A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture. | 2012-10-25 |
20120267797 | FLIP-CHIP, FACE-UP AND FACE-DOWN WIREBOND COMBINATION PACKAGE - A microelectronic assembly can include a substrate having an aperture extending between first and second surfaces thereof, the substrate having substrate contacts at the first surface and terminals at the second surface. The microelectronic assembly can include a first microelectronic element having a front surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, and leads electrically connecting the contacts of the second microelectronic element with the terminals. The second microelectronic element can have contacts exposed at the front surface thereof beyond an edge of the first microelectronic element. The first microelectronic element can be configured to regenerate at least some signals received by the microelectronic assembly at the terminals and to transmit said signals to the second microelectronic element. The second microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. | 2012-10-25 |
20120267798 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly is disclosed that comprises a substrate having first and second openings, a first microelectronic element and a second microelectronic element in a face-down position. The first element has an active surface facing the front surface of the substrate and bond pads aligned with the first opening, a rear surface remote therefrom, and an edge extending between the front and rear surfaces. The second microelectronic element has a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, and bond pads at the front surface of the second microelectronic element aligned with the second opening. | 2012-10-25 |
20120267799 | PACKAGE STRUCTURES - A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die. | 2012-10-25 |
20120267800 | Semiconductor Device and Method of Forming IPD in Fan-Out Wafer Level Chip Scale Package - A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer. | 2012-10-25 |
20120267801 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING MOLD FLASH PREVENTION TECHNOLOGY - An integrated circuit package system that includes: a support structure including an electrical contact; a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface; an integrated circuit over the support structure; and encapsulant over the integrated circuit and in contact with the solder mask flange. A mold system that includes a first mold having a projection along a first mold bottom surface, the projection between a first cavity and a recess. | 2012-10-25 |
20120267802 | POSITION DETERMINATION IN A LITHOGRAPHY SYSTEM USING A SUBSTRATE HAVING A PARTIALLY REFLECTIVE POSITION MARK - The invention relates to a substrate for use in a lithography system, said substrate being provided with an at least partially reflective position mark comprising an array of structures, the array extending along a longitudinal direction of the mark, characterized in that said structures are arranged for varying a reflection coefficient of the mark along the longitudinal direction, wherein said reflection coefficient is determined for a predetermined wavelength. In an embodiment a specular reflection coefficient varies along the substrate, wherein high order diffractions are substantially absorbed by the substrate. A position of a beam on a substrate can thus be determined based on the intensity of its reflection in the substrate. The invention further relates to a positioning device and lithography system for cooperation with the substrate, and a method of manufacture of the substrate. | 2012-10-25 |
20120267803 | ADHESIVE FOR SEMICONDUCTOR BONDING, ADHESIVE FILM FOR SEMICONDUCTOR BONDING, METHOD FOR MOUNTING SEMICONDUCTOR CHIP, AND SEMICONDUCTOR DEVICE - The present invention is aimed to provide an adhesive for bonding a semiconductor which has high transparency and facilitates recognition of a pattern or position indication on the occasion of semiconductor chip bonding. | 2012-10-25 |
20120267804 | ROOM VENT HUMIDIFIER - A room humidifying apparatus is provided which operates with minimum cost and without any electrical power. The humidifier is located so as to make use of a stream of air coming from a register. The humidifier has a casing carrying a main water tank, a water pan and an evaporative filter element which are located in the casing. The tank drips water onto the filter element, which has a lower portion located in the water pan to collect any excess water dripping down the filter element and also to moisten it with capillary effect. Heated air from the register becomes humidified on passing through the filter element. The water tank can be filled manually from the top or be detachable and filled through a bottom refill opening. Alternatively, the water tank can be connected to a water source with a valve to regulate the flow of water into the water tank. The water tank may be balanced so as to displace, for example tilt, from a first position when it contains water to a second position when it is empty. | 2012-10-25 |
20120267805 | SHAPED PACKING ELEMENT - The present invention provides a packing element comprising at least one sheet having a plurality of deformations, the sheet being operable to form a folded or helical configuration wherein adjacent portions of the at least one sheet are spaced to allow for flow of at least one of fluid, air and gas therebetween. | 2012-10-25 |
20120267806 | EXHAUST GAS TREATMENT APPARATUS - The exhaust gas treatment apparatus has a sealed vessel which is vertically partitioned into two spaces by a partition. A portion of the sealed vessel lower than the partition is an absorbing liquid storage portion, and a portion of the sealed vessel upper than the partition is an exhaust gas introducing portion. The partition is provided with a large number of sparger pipes so that the sparger pipes reach inside an absorbing liquid stored in the absorbing liquid storage portion. The partition is provided with a single gas riser in communication with a space upper than the absorbing liquid in the absorbing liquid storage portion. An upper end of the gas riser passes through a top plate portion of the sealed vessel and protrudes upward. | 2012-10-25 |
20120267807 | MESH STRUCTURE FOR SURFACE PLASMON RESONANCE SPECTROSCOPY - The invention relates to producing a profiled mesh structure on a substrate for use in surface plasmon resonance spectroscopy, wherein a flat board is coated with a positive photoresist, the photoresist is illuminated in parallel tracks corresponding to the mesh constant, subsequently developed, and the development interrupted before the development process reaches the surface of the board. After metallizing and galvanically molding the developed and rinsed surface profile, a matrix is available allowing low-cost molding of the substrate from a thermoplastic material. | 2012-10-25 |
20120267808 | Contact Lens Packages - A package having a roughened surface that does not adhere to a medical device enclosed therein. | 2012-10-25 |
20120267809 | APPARATUS AND METHOD FOR PRODUCTION OF LIPOSOMES - Disclosed are: an apparatus which enables the easy production of liposomes having uniform particle diameters; and others. Specifically disclosed is a liposome production apparatus comprising: a microtube having a flow path through which a lipid-dissolved solution comprising at least one lipid, water and a water-miscible organic solvent can pass; a housing section in which the microtube is accommodated; and a cooling means for cooling the dissolved solution contained in the microtube in the housing section to a temperature at which liposomes can be produced. The apparatus enables the production of liposomes having uniform particle diameters. | 2012-10-25 |
20120267810 | DEVICES AND METHODS FOR FORMING NON-SPHERICAL PARTICLES - Embodiments of the present disclosure provide for devices, methods for forming non-spherical particles, and the like. | 2012-10-25 |
20120267811 | METHODS AND APPARATUS FOR THE RAPID MANUFACTURE OF DIRECT CUSTOM MOUTHPIECES - A method for rapidly creating a custom mouthpiece is disclosed. The method may include providing a form defining a void sized and configured to accommodate teeth of a user. The method may also include applying a curing polymer within the void. The method may also include placing the form and the curing polymer within a mouth of the user so as to move the teeth of the user into the curing polymer to make a mold of the teeth of the user. The method may also include allowing the curing polymer to cure while in the mouth of the user, and removing the form and curing polymer from the mouth of the user. | 2012-10-25 |
20120267812 | COMPOSITION USEFUL AS MORTAR OR COATINGS REFRACTORIES - This invention relates to a composition comprising: ceramic refractory particulates made from alumina, one or more rare earth oxides, one or more oxides of a transition metal, the transition metal being Sc, Zn, Ga, Y, Cd, In, Sn, Tl, or a mixture of two or more thereof; an alumina and phosphate containing composition; and water. The composition is free of SiO | 2012-10-25 |
20120267813 | Device For A Layerwise Manufacturing Of A Three-Dimensional Object And Method For Supplying A Building Material | 2012-10-25 |
20120267814 | Roll fed flotation/impingement air ovens and related thermoforming Systems For Corrugation-Free Heating And Expanding Of Gas Impregnated Thermoplastic Webs - Disclosed herein are roll fed air heated flotation ovens and related thermoforming systems, assemblies, and machines that enable the corrugation-free expansion of a gas impregnated thermoplastic web passing through an oven chamber (without use of a pin-chain assembly), as well as to related methods. In an embodiment, a gas impregnated thermoplastic web is conveyed and expanded through an elongated air heated oven chamber, wherein the elongated oven chamber includes a plurality of downwardly directed heated air nozzles positioned at regular intervals along and within the upper portion of the oven chamber, and a plurality of upwardly directed heated air nozzles positioned at regular intervals along and within the lower portion of the oven chamber, but staggered apart from the downwardly directed heated air nozzles such that the gas impregnated thermoplastic material web undulates in an up and down wavelike fashion, thereby minimizing sagging, bagging, puckering, and/or buckling of the web. | 2012-10-25 |
20120267815 | INJECTION MOLDING MACHINE AND INJECTION MOLDING METHOD - An injection molding machine includes a gas feeding mechanism configured to feed gas to a cavity formed between a first mold plate and a second mold plate in a clamped state; an injection apparatus configured to inject a foamable resin into the cavity having an inside pressure thereof increased to be higher than an atmospheric pressure by the gas feeding mechanism; and a gas releasing mechanism configured to release the gas inside the cavity to an atmosphere through a gap formed between an inner wall surface of a through hole formed through one of the first mold plate and the second mold plate and an outer circumferential surface of a mold member inserted into the through hole, during or after the injection of the foamable resin by the injection apparatus. | 2012-10-25 |
20120267816 | PROCESS AND APPARATUS FOR MOLDING A FILTER - The invention provides a method for forming a fibrous layer within a tubular support, which comprises the steps of: (a) providing the tubular support; (b) providing forming mesh over the curved surface of the support and closing its ends against escape of fluid; and (c) introducing fibrous slurry (e.g. an aqueous slurry of borosilicate glass microfibers and water dispersible heat curable acrylic resin at a pH of about 3) from a pressurized source into an annular molding space between a rotary molding torpedo and an inner surface of the support, the torpedo having at least one channel for slurry opening along a curved surface thereof, fibers in the slurry collecting within the forming mesh to form the layer. The invention also provides apparatus for forming a fibrous layer within a tubular support, which comprises:(a) a mould having a molding space for the tubular support; (b) forming mesh in the molding space for covering an exterior curved surface of the support, the forming mesh being configured to collect fibers and permit liquid to pass through it; (c) headstock and tailstock end closures for closing headstock and tailstock ends of the support against escape of fluid; (d) a rotary molding torpedo extendible into and retractable from the molding space for defining with an internal curved surface of the support an annular space for formation of the fibrous layer, the torpedo having at least one channel for slurry opening along a curved surface thereof; (e) a drive coupled to the torpedo for rotation thereof during molding; and (f) a supply line for supplying fibrous slurry from a pressurized source to the torpedo for flow into and through the molding space; and (g) suction means for withdrawing fluid from the molding space. | 2012-10-25 |
20120267817 | Process for Preparing Pramipexole Dihydrochloride Tablets - The present invention relates to a process for preparing tablets of pramipexole dihydrochloride. In particular, the present invention relates to a process for preparing tablets of pramipexole dihydrochloride wherein the tablets exhibit enhanced storage stability properties. | 2012-10-25 |
20120267818 | METHOD AND DEVICE FOR GRANULATING PLASTICS AND/OR POLYMERS - A method and apparatus for the pelletization of plastics and/or polymers, in which a melt coming from a melt generator is supplied via a diverter valve having different operating positions to a plurality of pelletizing heads through which the melt is pelletized. The plurality of pelletizing heads have different throughput capacities and are used sequentially for the start-up of the pelletizing process, with the melt first being supplied to a first pelletizing head having a smaller throughput capacity and then the melt volume flow being increased and the diverter valve being switched over such that the melt is diverted by the diverter valve to a second pelletizing head having a larger throughput capacity. | 2012-10-25 |
20120267819 | ANTIOXIDANT DOPING OF CROSSLINKED POLYMERS AT HIGH PRESSURES - Methods for an antioxidant doped polymer in the form of an implant bearing component. The process includes: (a) contacting a crosslinked polymer with a liquid composition comprising an antioxidant, to provide an intermediate polymer with the antioxidant on its surface; and (b) homogenizing the intermediate polymer by raising the pressure to increase the onset melting temperature of the polymer, and then heating above the ambient onset temperature but below the raised onset melting point of the polymer. | 2012-10-25 |
20120267820 | FIBER DRAW SYNTHESIS - Fiber draw synthesis process. The process includes arranging reactants in the solid state in proximate domains within a fiber preform. The preform is fluidized at a temperature below the melting temperature of the reactants. The fluidized preform is drawn into a fiber thereby bringing the reagents in the proximate domains into intimate contact with one another resulting in a chemical reaction between the reactants thereby synthesizing a compound within the fiber. The reactants may be dissolved or mixed in a host material within the preform. In a preferred embodiment, the reactants are selenium and zinc. | 2012-10-25 |
20120267821 | Extrusion Kit and Extruder - This invention provides methods and devices for manufacturing moldable materials including various types of natural and synthetic clays, edible materials such as cookie dough, and modeling compound by forming a moldable billet through various techniques, and reducing the cross section of said moldable billet such that features in the moldable billet appear in a similar arrangement in the resulting extruded product. | 2012-10-25 |
20120267822 | POLY(TRIMETHYLENE ARYLATE) FIBERS, PROCESS FOR PREPARING, AND FABRIC PREPARED THEREFROM - A fine denier poly(trimethylene arylate) spun drawn fiber is characterized by high denier uniformity. A process for preparing uniform fine denier yarns at spinning speeds of 4000 to 6000 m/min is further disclosed. The poly(trimethylene arylate) fiber hereof comprises 0.1 to 3% by weight of polystyrene dispersed therewithin. Fabrics prepared therefrom are also disclosed. | 2012-10-25 |
20120267823 | SYSTEM AND METHOD FOR A PNEUMATIC TIRE MOLD - A system for securing a mold blade to a mold segment includes a plurality of pins placed across the length of the mold blade and a plurality of corresponding recesses on an inner surface of the mold segment. Each pin is placed within a recess securing the mold blade to the mold segment. | 2012-10-25 |
20120267824 | MANUFACTURING A COMPOSITE COMPONENT - Manufacturing of a composite component, such as a composite component of an aircraft, is provided with a molding tool that includes, but is not limited to a first mold, a second mold and a pressure generator. Between the first mold and the second mold, a membrane is arranged so that between the first mold and the membrane a first region is formed, and between the second mold and the membrane a second region is formed. In the first region, a fibrous mat is arranged. In the second region with the use of the pressure generator | 2012-10-25 |
20120267825 | METHOD OF MANUFACTURING INERTIAL SENSOR - The method of manufacturing an inertial sensor includes: (A) disposing a first mold | 2012-10-25 |
20120267826 | MOLD FOR PRODUCING MICROPRODUCT AND METHOD OF PRODUCING MICROPRODUCT - A mold for producing a microproduct includes a first mold on which a stamper member is disposed, and a second mold that relatively moves with respect to the first mold. The first mold includes a frame and a base mold. The base mold includes a back side section that supports the back side of the stamper member. The frame includes a front side restriction section that is positioned opposite to the front side edge area of the stamper member, and a sidewall that is positioned opposite to the side of the stamper member. A given clearance is provided between the front side edge area of the stamper member and the front side restriction section of the frame and/or between the side of the stamper member and the sidewall of the frame. | 2012-10-25 |
20120267827 | RAPID PRODUCTION APPARATUS WITH PRODUCTION ORIENTATION DETERMINATION - A method of producing an object by sequentially printing layers of construction material one on top of the other, the method comprising: providing the construction material at a first lower temperature; flowing the construction material through a heated flow path in a flow structure to heat the construction material and delivering the heated construction material to a heated reservoir in a printing head; and dispensing the heated construction material from the reservoir to build the object layer by layer. | 2012-10-25 |
20120267828 | ZONE CONTROL OF TOOL TEMPERATURE - A tool system for moulding an article is provided which comprising a tool ( | 2012-10-25 |
20120267829 | DEVICE AND METHOD FOR PRODUCING A GREEN COMPACT FROM A POWDERED OR GRANULAR MATERIAL - A device and method for producing a green compact from a powdered or granular material by successive application and compression of the material, is disclosed. The device includes a fill shoe, which is filled with the material and is adjustable by an adjusting device, where a first park position is provided for the fill shoe. A matrix having at least one construction chamber is filled with the material layer-by-layer by the fill shoe between a first and second end position. A press having a lower punch and an upper punch, which are adjustable by a height adjustment device, compresses the material applied layer-by-layer in the at least one construction chamber. After filling the construction chamber with the material, the fill shoe is moved out of the second end position into a second park position, where the second park position is different from the first park position. | 2012-10-25 |
20120267830 | Method of rapid sintering of ceramics - Rapid sintering techniques for densifying zirconium dioxide based ceramic materials employing electromagnetic induction heating or inductive coupled plasma, reducing processing time from hours to minutes. In one embodiment a water-cooled coil is connected to a radio frequency power supply. The coil surrounds a susceptor body which in turn surrounds the ceramic to be sintered. The susceptor heats up in response to a magnetic field emanating from the coil as the coil receives electric power. The heat in turn is radiated from the susceptor and heats the ceramic. In another embodiment, the coil is connected to a radio frequency power supply of sufficiently high frequency and power to establish a plasma in the gas which surrounds the ceramic. The plasma then heats the ceramic. The method is especially useful for sintering ceramic dental appliances, in minutes which can lead to in situ fabrication of such appliances while a dental patient waits. | 2012-10-25 |
20120267831 | SEMICONDUCTOR CRYSTAL BODY PROCESSING METHOD AND SEMICONDUCTOR CRYSTAL BODY PROCESSING DEVICE - A semiconductor crystal body processing method includes providing a semiconductor crystal body, sandwiching the semiconductor crystal body between a pair of conductive pressurizing tools, applying a pulse-like current between the pair of pressurizing tools to heat the semiconductor crystal body to a target temperature equal to or higher than a temperature at which the semiconductor crystal body is plastically deformed by pressurization and lower than its melting point, and applying pressure and a pulse-like current between the pair of pressurizing tools to thereby maintain the temperature of the semiconductor crystal body at the target temperature and mold the semiconductor crystal body into a target shape by plastic deformation. | 2012-10-25 |
20120267832 | METHOD AND DEVICE FOR BLOW-MOLDING CONTAINERS - The invention relates to a method and a device for blow-molding containers. A preform produced of a thermoplastic material is subjected to a thermal conditioning process along a transport path in the region of a heating section. The preform is then shaped in a blow mold by the effect of a blowing pressure to give the container. The preform is subjected to a temperature profile at least along part of its transport path in the region of the heating section, said temperature profile being generated by at least one tubular radiation heater. The temperature profile extends in a longitudinal direction of the preform. The radiation emitted by the radiation heater is emitted in different spatial directions with different intensities by a heating device positioning the radiation heater. | 2012-10-25 |
20120267833 | METHOD OF FORMING A WOVEN FIBER STRUCTURE USING A TACKIFIER COMPOSITION - A method of forming a woven fiber structure for a molding process to produce a ceramic matrix composite, includes depositing a tackifier composition having a carrier solvent, a resin material, and an inorganic filler onto at least a portion of a woven fiber structure; drying the tackifier composition on woven fiber structure to remove at least a portion of the carrier solvent from the tackifier composition; and forming the dried woven fiber structure into a preform. | 2012-10-25 |
20120267834 | POURING EQUIPMENT HAVING MELTING FURNACE - To transfer the molten metal that is melted in the melting furnace into the pouring ladle, which is a vessel for transporting the molten metal to the place for pouring, and to further lift the pouring ladle by another crane to pour the molten metal, requires time, such that the molten metal that had a high temperature when melted by the melting furnace is likely to cool down and to cause a defective cast product. To solve the problem the pouring equipment of the present invention pours the molten metal into the mold, comprising the melting furnace that produces molten metal by melting metal material and a driving apparatus that can move the melting furnace backward and forward or in a traverse direction, wherein the pouring equipment moves the melting furnace to the predetermined position by the driving apparatus, and then pours the molten metal into a mold by tilting the melting furnace relative to the mold. | 2012-10-25 |
20120267835 | LEAF SPRING ARRANGEMENT - In a leaf spring arrangement for a chassis of a motor vehicle, a leaf spring includes multiple layers made of a glass fiber composite plastic, a reinforcement made of a carbon composite plastic and being disposed between an upper and a lower one of the layers, and a core made of a different material than the reinforcement and being disposed between the upper and lower layers, wherein the reinforcement is arranged along a longitudinal a side of the core. The leaf spring is coupled at its center region to an axle of the motor vehicle by a center connection and to the vehicle body by bodywork connections, wherein the leaf spring is tilted by an angle relative to the vertical axis of the motor vehicle. | 2012-10-25 |
20120267836 | GAS SPRING END MEMBER AS WELL AS GAS SPRING ASSEMBLY AND SUSPENSION SYSTEM INCLUDING SAME - A gas spring end member is dimensioned for securement along an associated suspension member having an associated planar surface and at least an associated first side surface. The gas spring end member can include a base wall disposed transverse to a longitudinal axis and a bracket wall that extends longitudinally-outwardly from the base wall. The bracket wall can be adapted for operative connection to the associated suspension member such that the gas spring end member can be supported thereon with the base wall disposed in longitudinally spaced-apart relation to the associated planar surface of the associated suspension member. A gas spring assembly including such an end member can be included. A suspension system and a method of installation including such a gas spring assembly can also be included. | 2012-10-25 |
20120267837 | One-Piece Multipole Plate for a Magnetic Holding Apparatus, Process for Making Such Plate and Magnetic Apparatus Using Such Plate - A one-piece multipole plate for a magnetic clamping apparatus, a process for making such plate and a magnetic apparatus having such plate. The magnetic apparatus has a plurality of pole pieces and the plurality of pole pieces extend from the plate and are formed of one piece with the plate. | 2012-10-25 |
20120267838 | Spring Actuated Link Clamp - A clamp has a housing with a piston assembly positioned in the housing. A detent mechanism is coupled with the piston rod and is positioned in the housing. A clamping arm is coupled with the piston rod. The clamping arm is moved by a biasing mechanism from a position parallel to the piston rod, when in a retracted position, to a position substantially perpendicular to the piston rod, when in a clamping position. | 2012-10-25 |
20120267839 | Universal Clamping Block - An interface component is provided for use in combination with a clamp or compressive tool imparting a compressive force against respective planar contact surfaces of two components being joined at a miter joint. The interface features an elongated member having a projection projecting away from a top surface in a substantially circular path. The curved surface provides a means to redirect the compressive force communicated against said curved surface to the miter joint at a substantially normal angle. | 2012-10-25 |
20120267840 | DEVICE FOR CLEANING BAKING TRAYS - A device for cleaning trays comprises a tub that has a bottom and a wall. The tub is dimensioned such that a baking tray can be placed therein. The device further comprises a dish drain that can be placed in the tub. Said device for cleaning a baking tray uses only a small amount of space in a kitchen and is easy to handle. In fact, in a typical kitchen that already has a dish drain, the device requires no additional space. | 2012-10-25 |
20120267841 | PRINTING DEVICE WITH DETACHABLE STAPLING DEVICE - The present invention discloses a printing device with a detachable stapling device including a printing device housing, a connecting frame and a stapling device. The connecting frame has a locating post and a fixing hook and is connected with the stapling device. The position of the connecting frame can be adjusted by the locating post of the connecting frame, and the connecting frame can be assembled on the printing device housing or detached from the printing device housing by the fixing hook. | 2012-10-25 |
20120267842 | CONTROL APPARATUS FOR CONTROLLING STAPLING AND IMAGE FORMING APPARATUS FOR CONTROLLING STAPLING - A control apparatus that controls a stapling unit configured to staple sheets includes a control unit configured to determine a turning-over direction of sheets to be stapled by the stapling unit and to determine a maximum number of staplable sheets according to the determined turning-over direction. | 2012-10-25 |
20120267843 | RECORDING MEDIUM OVERTURNING DEVICE AND RECORDING MEDIUM PROCESSING APPARATUS USING THE SAME - The present invention provides a recording medium turnover device and a recording medium processing apparatus using the same. The recording medium turnover device comprises: a passage assembly, configured to form a first passage ( | 2012-10-25 |