43rd week of 2013 patent applcation highlights part 31 |
Patent application number | Title | Published |
20130279202 | Efficient Side-Light Distribution System - Improved side-light distribution systems are disclosed. One exemplary system includes a light source and a side-light distribution member. The light source supplies light to the side-light distribution member having (1) an net port on the first end of the member for receiving the light and (2) a second end having a reflective means. The inlet port consists of part of the surface area of the first end of the member. The reflective means associated with the second end of the member receives light from the first end and directs light towards the first end. At least part of a surface area of the first end of outside of the inlet port includes a reflective means for receiving the light from the second end and directing the light towards the second end of the rod. | 2013-10-24 |
20130279203 | SWITCHING POWER SUPPLY DEVICE - A switching power supply device that can reduce power supply noise includes a switching power supply device main body that switches a semiconductor switching element at a power supply frequency fs, and supplies power to an electronic instrument such as an AM radio receiver. The switching power supply device detects an AM radio reception frequency fc and a power supply harmonic component that interferes with the AM radio reception frequency fc. Further, the switching power supply device determines, in a sideband of the AM radio reception frequency fc on a side that does not include the power supply harmonic component, a jitter width Δf for the power supply frequency fs, avoiding a bandwidth BW of the AM radio reception frequency fc, controlling the jitter of the power supply frequency fs in the jitter width Δf, and switching the semiconductor switching element at a frequency of [fs±Δf/2]. | 2013-10-24 |
20130279204 | POWER SUPPLY SYSTEM, POWER CONVERTER AND VOLTAGE REGULATING METHOD - A power converter includes a power module, a feedback module, and a control module. The power module is used for converting an input voltage into an output voltage. The feedback module is electrically connected with the power module for generating a feedback voltage according to the output voltage. The control module is electrically connected with the feedback module and the power module for comparing a reference duty cycle value with a duty cycle, generating a variable reference voltage according to the comparison between the reference duty cycle value and the duty cycle, comparing the variable reference voltage with the feedback voltage, and adjusting the duty cycle according to the comparison between the variable reference voltage and the feedback voltage. | 2013-10-24 |
20130279205 | HOLD-UP TIME ENHANCEMENT CIRCUIT FOR LLC RESONANT CONVERTER - An open loop half-bridge LLC power converter includes circuitry to reliably increase hold-up time without sacrificing efficiency. An LLC resonant circuit includes resonant inductance, a primary transformer winding, and resonant capacitance. An auxiliary circuit includes an auxiliary transformer winding, an inductor, and a third switching element coupled in series. A controller is coupled across a voltage sensor and effective thereby to determine a holdup time condition. In a “normal” operating condition the controller generates switch driver signals to turn OFF the third switching element and disable the auxiliary circuit, and in a hold-up time condition the controller turns ON the third switching element and enables the auxiliary circuit wherein the output voltage is increased via current supplied from the auxiliary winding. In various embodiments the auxiliary winding may be an auxiliary primary or secondary, or a secondary to an auxiliary primary winding of a second transformer. | 2013-10-24 |
20130279206 | CONTROL CIRCUIT FOR AN INVERTER WITH SMALL INPUT CAPACITOR - A control circuit for an inverter according to the present invention comprises a PWM circuit and a controller. The PWM circuit generates switching signals in accordance with a PWM control signal. The switching signals are coupled to switch a transformer through transistors for generating an output of the inverter. The controller is coupled to receive a command signal and an input signal for generating the PWM control signal. The input signal is correlated to an input voltage waveform of the inverter. The command signal is utilized to determine a power level of the output of the inverter. The advantages of the control circuit are lower cost, small size, good power factor and higher reliability. | 2013-10-24 |
20130279207 | POWER SUPPLY DEVICE AND A SYNCHRONOUS RECTIFIER PCB - A power supply device includes a main unit and a power switching module. The main unit includes a primary circuit board, a transformer including a primary and a secondary coil, a primary-side circuit and a secondary-side circuit. The power switching module includes a separate PCB formed with at least two connection pads and two conductive tracks, and at least one power switching element disposed on the PCB and having two terminals respectively connected to the two connection pads through the two conductive tracks. The power switching module is in the form of a separate PCB that is electrically connected to the primary- or secondary-side circuits through the two connection pads. | 2013-10-24 |
20130279208 | POWER CONVERTER AND CONTROLLING METHOD - A power converter and a method of controlling the same are disclosed. The power converter includes a transformer, a first switch unit, a second switch unit, and a control unit. The control unit turns on/off the first switch unit and the second switch unit according to magnitude of an input voltage. When the input voltage is at a high voltage range, the control unit turns on the first switch unit and turns off the second switch unit; when the input voltage is at a low voltage range, the control unit turns on the second switch unit and turns off the first switch unit. Accordingly, a turn ratio of the transformer is adaptively adjusted with variations of the input voltage, thus maintaining the power converter to be | 2013-10-24 |
20130279209 | DYNAMIC DRIVE OF SWITCHING TRANSISTOR OF SWITCHING POWER CONVERTER - The drive current of the switch in a switching power converter is adjusted dynamically according to line or load conditions within a switching cycle and/or over a plurality of switching cycles. The magnitude of the switch drive current can be dynamically adjusted within a switching cycle and/or over a plurality of switching cycles, in addition to the pulse widths or pulse frequencies of the switch drive current. | 2013-10-24 |
20130279210 | Power Conditioning Units - We describe a power conditioning unit with maximum power point tracking (MPPT) for a dc power source, in particular a photovoltaic panel. A power injection control block has a sense input coupled to an energy storage capacitor on a dc link and controls a dc-to-ac converter to control the injected mains power. The power injection control block tracks the maximum power point by measuring a signal on the dc link which depends on the power drawn from the dc power source, and thus there is no need to measure the dc voltage and current from the dc source. In embodiments the signal is a ripple voltage level and the power injection control block controls an amplitude of an ac current output such that an amount of power transferred to the grid mains is dependent on an amplitude of a sinusoidal voltage component on the energy storage capacitor. | 2013-10-24 |
20130279211 | Modular Multilevel Converter - A power electronic converter for use in high voltage direct current power transmission and reactive power compensation includes at least one converter limb, which includes first and second DC terminals and an AC terminal. Each converter limb defines first and second limb portions connected in series between the AC terminal and a respective one of the first and second DC terminals. Each limb portion includes a chain-link converter connected in series with at least one primary switching element. Each chain-link converter includes a plurality of modules connected in series, and each module includes at least one secondary switching element connected to at least one energy storage device. Each primary switching element in each limb portion of a respective converter limb selectively defines a circulation path which carries a DC circulation current to regulate the energy level of at least one energy storage device in a respective chain-link converter. | 2013-10-24 |
20130279212 | DUAL FUNCTION SOLID STATE CONVERTER - A dual function solid state power converter operable from a three phase AC input current simultaneously provides; an AC or DC output current on an aircraft power cable to provide ground power to a parked aircraft, and a low voltage DC current on a battery charging power cable to charge batteries in nearby service vehicles. The power converter includes an AC to DC converter which converts the current on an internal DC bus, a DC to AC converter which converts the DC bus current to an AC current at a higher voltage and frequency, or a DC to DC converter which converts the DC bus current to a lower voltage DC, for supplying ground power to a parked aircraft, and a DC to DC converter for converting the DC bus current to a lower voltage battery charging current on the battery charging cable. | 2013-10-24 |
20130279213 | POWER REGENERATION APPARATUS AND POWER CONVERSION APPARATUS - A power regeneration apparatus includes a power conversion unit, an AC reactor, a voltage detecting unit, a phase detecting unit, a drive control unit for controlling the power conversion unit based on a phase detection value, and a reactive current component detecting unit. The phase detecting unit detects the phase of the AC power supply. The reactive current component detecting unit detects a reactive current component of a current. The drive control unit includes a phase correction section. The phase correction section corrects the phase detection value based on the reactive current component. | 2013-10-24 |
20130279214 | POWER REGENERATIVE CONVERTER AND POWER CONVERSION APPARATUS - A power regenerative converter includes: a power conversion unit configured to convert AC power supplied from an AC power supply into DC power and convert DC power into AC power to be supplied as regenerative electric power to the AC power supply supply; an LCL filter including a reactor unit having a plurality of reactors connected in series between the power conversion unit and the AC power supply, and capacitors each having one end connected to a series connection point of the reactors in the reactor unit; a drive control unit for controlling the power conversion unit based on an AC voltage command; and a voltage command compensation unit for calculating a compensation value in accordance with a capacitor voltage being a voltage at the series connection point of the reactors and adding the compensation value to the AC voltage command input to the drive control unit. | 2013-10-24 |
20130279215 | Assembly For Converting An Input AC Voltage To An Output AC Voltage - An assembly for converting an assembly input AC voltage to an assembly output AC voltage may include: plural converters, each including a rectifier stage for rectifying an input AC voltage to a DC voltage, the rectifier including: first and second input terminals between which the input AC voltage is applied; first and second thyristors connected in series, wherein the first input terminal is connected between the first and second thyristors; first and second diodes connected in series, wherein the second input terminal is connected between the first and second diodes; and first and second output terminals between which the DC voltage is achieved, wherein the first thyristor and the first diode are connected to the first output terminal, and the second thyristor and the second diode are at least indirectly connected to the second output terminal. | 2013-10-24 |
20130279216 | COMPENSATING RIPPLE ON PULSE WITH MODULATOR OUTPUTS - A ripple compensation apparatus comprises a ripple detection unit to detect a ripple on a dual DC bus, a waveform generation unit to generate a modulated waveform based on a base waveform and the detected ripple, and a multi-phase control signal generation unit to receive the modulated waveform and to generate at least one pulse width modulated control signal based on the modulated waveform. | 2013-10-24 |
20130279217 | ELECTRICAL SUPPLY APPARATUS - The present invention is directed to an electrical supply apparatus having an input for connecting the electrical supply apparatus to a mains supply which provides an alternating voltage as input voltage, having an output for connecting the electrical supply apparatus to a load, wherein the output provides a DC voltage as output voltage, having a rectifier which rectifies the input voltage to form a rectified input voltage, having a PFC module which comprises a smoothing device for smoothing the rectified input voltage and an active power factor correction device, wherein the power factor correction device is designed to form a time-dependent supply current for the smoothing device depending on a time-dependent current form signal in such a way that a time-dependent input current in the PFC module is matched to the current form signal, wherein the current form signal is produced by an analogue circuit. | 2013-10-24 |
20130279218 | SWITCH CIRCUIT AND ELECTRONIC DEVICE - An electronic device includes a power supply, a load, and a switch circuit controlling the power supply. The switch circuit includes a control unit and a key switch capable of establishing an electrical connection between the power supply and the control unit in response to an operation by a user. When the key switch establishes the electrical connection, the control unit receives a supply voltage from the power supply and is charged-up by the supply voltage to generate a first control signal, the first control signal enables the power supply to power the load. | 2013-10-24 |
20130279219 | POWER CIRCUIT - A power circuit includes a first and a second switches between a input terminal and a reference power source; an inductor between a output terminal and a node between the first and the second switches, a main capacitor coupled to the output terminal, a main switch between the inductor and the output terminal, a sub capacitor coupled to a node between the inductor and the main switch through a sub switch, and a control circuit. And the control circuit performs: switching operation of the first and the second switches, and suspension operation that maintains an off-state of the first and the second switches after switching operation; the switching operation on the main capacitor by switching on the main switch; the switching operation on the sub capacitor by switching on the sub switch; and the switching operation by switching on the main switch and the sub switch. | 2013-10-24 |
20130279220 | SWITCHING CONTROL CIRCUIT WITH SIGNAL PROCESS TO ACCOMMODATE THE SYNCHRONOUS RECTIFIER OF POWER CONVERTERS - A switching control circuit of a power converter according to the present invention comprises an input circuit and a clock generator. The input circuit is coupled to receive a feedback signal for generating a switching signal. The clock generator generates a clock signal to determine a switching frequency of the switching signal. The feedback signal is correlated to an output of the power converter. The switching signal is coupled to switch a transformer of the power converter for regulating the output of the power converter. The pulse width of the switching signal is reduced before the switching frequency of the switching signal is changed from a low frequency to a high frequency. | 2013-10-24 |
20130279221 | POWER SUPPLY - A power supply to convert AC power to DC power with a relatively constant voltage and linear current delivery. The DC power may be positive and/or negative voltage. A fluctuating voltage from an AC voltage source (e.g., a transformer) is utilized to charge and substantially discharge a storage device on a cycle by cycle basis. Both the output of the storage device and the output of the transformer is combined to provide relatively constant voltage to a load. Unlike a typical power supply, (a) the discharge of the storage device forces power into a load, (b) total capacitance may be substantially less than the capacitance of a typical power supply, (c) a shunt capacitor is not required, and (d) the transformer may be continuously utilized throughout the entire cycle (rather than for only a brief portion of each cycle), reducing noise. | 2013-10-24 |
20130279222 | CONVERTER SYSTEM AND CONTROL METHOD THEREOF - A control method of a converter system includes: sampling a current of each three-phase winding to obtain a real-time current of each converter; obtaining a mean current by averaging the real-time current of each secondary converter and the real-time current of the primary converter, and transferring the mean current to each secondary converter; obtaining the differential-mode current corresponding to each secondary converter according to the mean current and the real-time current of each secondary converter; performing a circulation current control on the mean current and the differential-mode current of each secondary converter based on a d-q coordinate system to generate a mean-current conditioning signal and a differential-mode current conditioning signal, thereby controlling each secondary converter; and obtaining a sum of the differential-mode current conditioning signal of the secondary converters and negating the sum to obtain a differential-mode current conditioning signal of the primary converter, thereby controlling the primary converter. | 2013-10-24 |
20130279223 | SENSING AND CONTROL FOR IMPROVING SWITCHED POWER SUPPLIES - A power converter and a method of operation thereof is disclosed including an input, an output, a sensor unit, a switched power converter, and a processor module. The power converter may convert an input power into an output power. The power converter may sense real-time measurements of the input power and the output power to determine a real-time calculated efficiency. The power converter may chop the input power into sized and positioned portions of the input power based on a plurality of determined operating parameters. The power converter may determine the operating parameters based on the real-time calculated efficiency and on a plurality of other operating factors/conditions. | 2013-10-24 |
20130279224 | EFFICIENCY DYNAMIC POWER CONVERTER - A power converter and a method of operation thereof is disclosed including an input, an output, a sensor unit, a switched power converter, and a processor module. The power converter may convert an input power into an output power. The power converter may sense real-time measurements of the input power and the output power to determine a real-time calculated efficiency. The power converter may chop the input power into sized and positioned portions of the input power based on a plurality of determined operating parameters. The power converter may determine the operating parameters based on the real-time calculated efficiency and on a plurality of other operating factors/conditions. | 2013-10-24 |
20130279225 | APPARATUS FOR CONTROLLING INVERTER CURRENT & METHOD OF OPERATING THE SAME - Provided is an apparatus for controlling an inverter current, and more particularly, to a current controlling apparatus for controlling current of a switching element of an inverter that outputs a 3-phase alternating current. The apparatus for controlling an inverter current includes: an inverter comprising a plurality of current detection switching elements capable of detecting switched and output current, converting a direct current voltage into a 3-phase alternating current by turning the plurality of current detection switching elements on and off; an AD converter for directly receiving an input of an output current of an output terminal of each of the plurality of current detection switching elements as a detection current and converting the detection current into a detection signal value in digital form; and a control unit for controlling on and off of the plurality of current detection switching elements by using the detection signal value. | 2013-10-24 |
20130279226 | VARIABLE INPUT CONTROL FOR IMPROVING SWITCHED POWER SUPPLIES - A power converter and a method of operation thereof is disclosed including an input, an output, a sensor unit, a switched power converter, and a processor module. The power converter may convert an input power into an output power. The power converter may sense real-time measurements of the input power and the output power to determine a real-time calculated efficiency. The power converter may chop the input power into sized and positioned portions of the input power based on a plurality of determined operating parameters. The power converter may determine the operating parameters based on the real-time calculated efficiency and on a plurality of other operating factors/conditions. | 2013-10-24 |
20130279227 | CAPACITOR EMBEDDED BETWEEN BUSBARS, ELECTRIC POWER DEVICE AND ELECTRIC POWER CONVERSION DEVICE - The present invention provides an inter-bus-bar built-in capacitor capable of reducing the size of a capacitor used in an inverter or the like or downsizing the capacitor, and provides power equipment as well as a power converting apparatus. The inter-bus-bar built-in capacitor is provided between a pair of opposing bus bars and includes a high-dielectric-constant material which has a relative dielectric constant of at least 50 when a voltage of 1,000 V is applied at a temperature of 25° C. Thus, it is possible to provide the inter-bus-bar built-in capacitor capable of reducing the size of a capacitor used in an inverter or the like or downsizing the capacitor and provide the power equipment as well as the power converting apparatus. | 2013-10-24 |
20130279228 | SYSTEM AND METHOD FOR IMPROVING LOW-LOAD EFFICIENCY OF HIGH POWER CONVERTERS - Systems and methods for improving low-load efficiency of power converters are provided. The power converter can include one or more bridge circuits having multiple switching modules, such as insulated gate bipolar transistor (IGBT) modules, connected in parallel within the same bridge circuit. The power converter is configured to convert power from an input power source, such as a photovoltaic array or a wind turbine, into output power at a grid frequency. To avoid excessive switching losses at low load conditions, the power converter can be controlled to selectively operate a subset of the switching modules within the same bridge circuit based on a load condition for the power converter. The remaining switching modules in the bridge circuit can be disabled. | 2013-10-24 |
20130279229 | POWER INVERTER CIRCUIT - A power inverter circuit | 2013-10-24 |
20130279230 | Power Module - Provided is a power conversion device including an insulating member manufactured such that a thickness di (mm) of the insulating member made from a resin, provided between a heat dissipating surface of a conductor plate bonded to a power semiconductor device and a heat dissipating plate that dissipates the heat of the power semiconductor device satisfies a relation of di>(1.36×10-8×Vt2+3.4×10-5×Vt−0.015)×εr, where a relative permittivity of the insulating member is Er and a surge voltage generated between the conductor plate and the heat dissipating plate accompanied by an ON/OFF switching operation of the power semiconductor device is Vt (V). The conductor plate of the power semiconductor device, the insulating member, and the heat dissipating plate are bonded by thermocompression bonding. | 2013-10-24 |
20130279231 | Power Limiting in a Content Search System - A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic. | 2013-10-24 |
20130279232 | APPARATUS, SYSTEM, AND METHOD FOR TRANSFERRING HEAT FROM MEMORY COMPONENTS - The apparatus to transfer heat from memory components includes a first non-volatile memory component and a second non-volatile memory component. The apparatus includes a heat spreading material in thermal communication with the first non-volatile memory component and the second non-volatile memory component. The heat spreading material is configured to transfer heat from the first non-volatile memory component and the second non-volatile memory component. | 2013-10-24 |
20130279233 | VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines. | 2013-10-24 |
20130279234 | ANTIFUSE UNIT CELL OF NONVOLATILE MEMORY DEVICE FOR ENHANCING DATA SENSE MARGIN AND NONVOLATILE MEMORY DEVICE WITH THE SAME - Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal. | 2013-10-24 |
20130279235 | PHOTON ECHO QUANTUM MEMORY AND METHOD - A quantum memory and method are proposed. The quantum memory includes an ensemble of atoms embedded in a storage medium and at least one light source for emitting towards the storage medium first, second and third light pulses, the first light pulse carrying information to be stored. The at least one light source is adapted for emitting second and third light pulses which are such that a photon echo substantially carrying information stored by the first light pulse is emitted by the ensemble of atoms after emission of the third light pulse. | 2013-10-24 |
20130279236 | METHOD AND SYSTEM FOR UTILIZING PEROVSKITE MATERIAL FOR CHARGE STORAGE AND AS A DIELECTRIC - Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor. | 2013-10-24 |
20130279237 | READING CIRCUIT FOR A RESISTIVE MEMORY CELL - A reading circuit for a resistive memory cell is provided, the circuit including a current source, a precharge switch, a comparator circuit including a first input node (in-node), and a second in-node, the precharge switch configured to couple the current source to the first in-node to apply a precharge voltage during a first reading time period, and to decouple the current source during a second reading time period, the comparator circuit configured to operate during a third reading time period, a memory cell access switch to enable a current flow at least partially during the second and the third reading time periods through a memory cell, the comparator circuit configured to compare a voltage at the first in-node with a reference voltage at the second in-node and to determine a programming state of the memory cell based on the voltage at the first in-node during the third reading time period. | 2013-10-24 |
20130279238 | PROGRAMMING AN ARRAY OF RESISTANCE RANDOM ACCESS MEMORY CELLS USING UNIPOLAR PULSES - Subject matter disclosed herein relates to a memory device, and more particularly to programming a non-volatile memory device. | 2013-10-24 |
20130279239 | Memory Cells, Methods of Forming Memory Cells, and Methods of Programming Memory Cells - Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another. | 2013-10-24 |
20130279240 | HETERO-SWITCHING LAYER IN A RRAM DEVICE AND METHOD - A non-volatile memory device structure includes first electrodes comprising conductive silicon-containing material, a plurality of resistive switching material stacks comprising first resistive switching material and second resistive switching material overlying the first electrode, wherein the first resistive switching material comprises a first resistance switching voltage and the second resistive switching material comprises a second resistance switching voltage less than the first amplitude, second electrodes comprising metal material overlying and electrically coupled to the plurality of resistive switching material stacks, wherein a plurality of memory elements are formed from the first plurality of electrodes, the plurality of resistive switching material stacks, and the second plurality of electrodes. | 2013-10-24 |
20130279241 | CIRCUITS AND METHODS FOR REDUCING MINIMUM SUPPLY FOR REGISTER FILE CELLS - A register file employing a shared supply structure to improve the minimum supply voltage. | 2013-10-24 |
20130279242 | VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY - Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges. | 2013-10-24 |
20130279243 | METHOD TO REDUCE READ ERROR RATE FOR SEMICONDUCTOR RESISTIVE MEMORY - During Magnetic Random Access Memory (MRAM) write operation with opposite electrical current direction through the Magnetic tunnel junction (MTJ), two different resistance of the MTJ can be stored at the MRAM cell as logic data “1” (data_1) and logic data “0” (data_0). The data_1 and data_0 can be read out by sensing the difference in resistance of the MTJ. However, due to the process uniformity, the distribution of resistance value for data_1 (R1) and the distribution of resistance value for data_0 (R0) can be overlapped. Those cells with the distribution of resistance value located in the overlapped region will produce a read error. An additional read and/or write cycle is added to the normal read or write operation to reduce read error rate. Multiple electrical reference current for read operation is added in order to widen the process window and manufacturing margin. | 2013-10-24 |
20130279244 | HIERARCHICAL MEMORY MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) ARCHITECTURE - A hierarchical memory magnetoresistive random-access memory architecture is disclosed. In a particular embodiment, an apparatus includes a first magnetoresistive random-access memory (MRAM) device corresponding to a first level in a hierarchical memory system. The apparatus includes a second MRAM device corresponding to a second level in the hierarchical memory system. The first MRAM device has a first access latency and includes a first magnetic tunnel junction (MTJ) device having a first physical configuration. The second MRAM device has a second access latency and includes a second WI device having a second physical configuration. The first access latency is less than the second access latency. | 2013-10-24 |
20130279245 | ADAPTIVE RESISTIVE DEVICE AND METHODS THEREOF - A system that incorporates teachings of the subject disclosure may include, for example, a device including a nanoelectrode having a gap, and a resistive change material located in the gap, wherein an application of a voltage potential across first and second terminals of the nanoelectrode causes the resistive change material to modify at least one non-volatile memory state of the resistive change material. Additional embodiments are disclosed. | 2013-10-24 |
20130279246 | MEMORY SYSTEM AND RELATED METHOD OF OPERATION - A memory system comprises a nonvolatile memory and a phase change memory. The memory system can be operated by reading operation information of the nonvolatile memory from the phase change memory, adjusting voltage parameters of the nonvolatile memory based on the read operation information, and performing an operation of the nonvolatile memory based on the adjusted voltage parameters. | 2013-10-24 |
20130279247 | SOLID MEMORY - Recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of record. In one embodiment, the above problem is solved by preparing a solid memory having a superlattice structure of thin films including Ge and thin films including Sb. The solid memory can realize the number of times of repeated recording and erasing of 10 | 2013-10-24 |
20130279248 | Data Retention in Nonvolatile Memory with Multiple Data Storage Formats - In a nonvolatile memory that stores data in two or more different data storage formats, such as binary and MLC, a separation scheme is used to distribute blocks containing data in one data storage format (e.g. binary) so that they are separated by at least some minimum number of blocks using another data storage format (e.g. MLC). | 2013-10-24 |
20130279249 | OPERATING METHOD OF MEMORY SYSTEM INCLUDING NAND FLASH MEMORY, VARIABLE RESISTANCE MEMORY AND CONTROLLER - An operating method is for a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the NAND flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the NAND flash memory when the accumulated data is a super page of data. A super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory. | 2013-10-24 |
20130279250 | NONVOLATILE MEMORY DEVICE WITH FLAG CELLS AND USER DEVICE INCLUDING THE SAME - A nonvolatile memory device includes a flag cell configured to store flag information, a plurality of dummy cells adjacent to the flag cell, and program control logic configured to control a program operation on the flag cell and a dummy program operation on the plurality of dummy cells. When the program operation on the flag cell is performed, the program control logic performs the dummy program operation on at least one of the plurality of dummy cells. | 2013-10-24 |
20130279251 | NOVEL SHIELDING 2-CYCLE HALF-PAGE READ AND PROGRAM SCHEMES FOR ADVANCED NAND FLASH DESIGN - The present invention provides a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into 3 periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period. | 2013-10-24 |
20130279252 | DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT - Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition. | 2013-10-24 |
20130279253 | SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD OF ID CODES AND UPPER ADDRESSES - A semiconductor chip D | 2013-10-24 |
20130279254 | SEMICONDUCTOR MEMORY STORAGE APPARATUS HAVING CHARGE STORAGE LAYER AND CONTROL GATE - According to one embodiment, a semiconductor memory storage apparatus includes an array, a sense amplifier, and a controller. The array includes a memory cell. The sense amplifier includes a first latch and a second latch. The first latch and the second latch are capable of storing a data read out from the memory cell. The controller performs a first operation, a second operation, and a third operation. In the first operation, the controller transfers an inverted data in the first latch to the first node and transfers the data in the second latch. In the second operation, the controller transfers the data in the first latch to the first node and transfers an inverted data in the second latch. | 2013-10-24 |
20130279255 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line. | 2013-10-24 |
20130279256 | Soft Erase Operation For 3D Non-Volatile Memory With Selective Inhibiting Of Passed Bits - An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits. | 2013-10-24 |
20130279257 | Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current - An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively. | 2013-10-24 |
20130279258 | PROGRAM CONDITION DEPENDENT BIT LINE CHARGE RATE - Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may be completion of a program loop. As another example, the program condition may be a certain program state completing or nearly completing programming. As one example, the bit lines may be charged at a faster rate prior to the program condition occurring than after the program condition. As another example, the bit lines may be charged at a slower rate prior to the program condition than after the program condition. Charging the unselected bit lines at a slower rate may reduce current consumption. Charging the unselected bit lines at a faster rate may allow for faster programming. | 2013-10-24 |
20130279259 | HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC - Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film. | 2013-10-24 |
20130279260 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE DEVICE, AND MEMORY SYSTEM - A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer. | 2013-10-24 |
20130279261 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURAL MEMORY CELLS AND A DUMMY CELL COUPLED TO AN END OF A MEMORY CELL - A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells. | 2013-10-24 |
20130279262 | NONVOLATILE MEMORY DEVICES, CHANNEL BOOSTING METHODS THEREOF, PROGRAMMING METHODS THEREOF, AND MEMORY SYSTEMS INCLUDING THE SAME - Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings. | 2013-10-24 |
20130279263 | NONVOLATILE MEMORY AND METHOD FOR IMPROVED PROGRAMMING WITH REDUCED VERIFY - A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V | 2013-10-24 |
20130279264 | NONVOLATILE MEMORY DEVICE, SYSTEM AND PROGRAMMING METHOD WITH DYNAMIC VERIFICATION MODE SELECTION - Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition. | 2013-10-24 |
20130279265 | Method and Apparatus for Reducing Erase Time of Memory By Using Partial Pre-Programming - Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells. | 2013-10-24 |
20130279266 | COMPLEMENTARY ELECTRICAL ERASABLE PROGRAMMABLE READ ONLY MEMORY - Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is disclosed. CEEPROM cell comprises a pair of non-volatile memory elements and one access transistor. The two elements of the non-volatile memory pair are configured to be one with high electrical conductance and the other with low electrical conductance. The positive voltage V | 2013-10-24 |
20130279267 | METHODS AND SYSTEMS FOR ERASE BIASING OF SPLIT-GATE NON-VOLATILE MEMORY CELLS - Methods and systems are disclosed for erasing split-gate non-volatile memory (NVM) cells using select-gate erase voltages that are adjusted to reduce select-gate to control-gate break-down failures. The adjusted select-gate erase voltages provide bias voltages on the select-gates that are configured to have the same polarity as the control-gate erase voltages applied during erase operations and that are different from select-gate read voltages applied during read operations. Certain additional embodiments use discrete charge storage layers for the split-gate NVM cells and include split-gate NVM cells having gap dielectric layer thicknesses that are dependent upon control gate dielectric layer widths. | 2013-10-24 |
20130279268 | EEPROM CELL WITH STORAGE CAPACITOR - In an EEPROM cell, as a storage capacitor is added between a control plate and a tunneling plate, after the storage capacitor is charged for a time that is relatively smaller than a time necessary for writing or erasing data of the EEPROM cell, the EEPROM cell that can perform operation of writing or erasing data of the EEPROM cell using a charge voltage that is stored at the storage capacitor is provided. Therefore, operation of writing or erasing data of the EEPROM cell within a short time using the EEPROM cell can be performed, and thus entire productivity of the EEPROM can be improved. | 2013-10-24 |
20130279269 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes two or more memory chips electrically coupled. Each of the memory chips includes global lines, a MUX unit, a selection unit, and an output unit. The global lines transmit data stored in memory cells. The MUX unit receives the data loaded onto the global lines to output a test data. The selection unit is inserted into two or more of the global lines and configured to output the test data instead of the data loaded onto the two or more global lines, in a test mode. The output unit is coupled to the global lines and is configured to output the data in a normal mode, and output the test data received from any one of the two or more global lines connected to the selection unit to an I/O pad based on information about the memory chip in a test mode. | 2013-10-24 |
20130279270 | MEMORY SYSTEM AND CONTROL METHOD THEREFOR - A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices. | 2013-10-24 |
20130279271 | PIPE REGISTER CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A pipe register circuit includes an address storage section configured to temporarily and sequentially store address signals input from an external in correspondence with a read command signal input together with the address signals, and an address output control section configured to generate an address output control signal for allowing the address signals stored in the address storage section to be output in correspondence with CAS latency, and output the address output control signal to the address storage section. | 2013-10-24 |
20130279272 | SEMICONDUCTOR DEVICE HAVING FUSE CIRCUIT - A semiconductor device includes a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a column command signal, and a plurality of fuse circuits configured to store repair addresses for a column repair and to output stored repair addresses in response to the enable pulse signal. | 2013-10-24 |
20130279273 | LATCH CIRCUIT, NONVOLATILE MEMORY DEVICE AND INTEGRATED CIRCUIT - A latch circuit may include a plurality of latches configured to operate in response to power supplied to a pull-up power supply node and a pull-down power supply node, a delay unit configured to generate a 1st delayed reset signal and a 2nd delayed reset signal by delaying a 1st reset signal and a 2nd reset signal, a power supply unit configured to supply identical power to the pull-up power supply node and the pull-down power supply node in response to the activated 1st reset signal or the activated 2nd reset signal, a 1st reset unit configured to reset a plurality of latches to a 1st level in response to the 1st delayed reset signal and a 2nd reset unit configured to reset the plurality of latches to a 2nd level in response to the 2nd delayed reset signal. | 2013-10-24 |
20130279274 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode. | 2013-10-24 |
20130279275 | SEMICONDUCTOR DEVICE - A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain. | 2013-10-24 |
20130279276 | SEPARATE MICROCHANNEL VOLTAGE DOMAINS IN STACKED MEMORY ARCHITECTURE - Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels. | 2013-10-24 |
20130279277 | CAPACITORLESS DRAM ON BULK SILICON - A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer. | 2013-10-24 |
20130279278 | Memory Component with Terminated and Unterminated Signaling Inputs - A memory component has a signaling interface, data input/output (I/O) circuitry, command/address (CA) circuitry and clock generation circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. The clock generation circuitry generates the first clock signal with a phase that establishes alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal. | 2013-10-24 |
20130279279 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fuse unit connected to a detection node and configured to be programmed in response to a first voltage supplied through the detection node, an output unit connected to the detection node and configured to output a fuse information signal indicating whether the fuse unit is programmed or not, and a blocking unit configured to block the first voltage supplied through the detection node in response to the fuse information signal. | 2013-10-24 |
20130279280 | STACKED MEMORY DEVICE WITH REDUNDANT RESOURCES TO CORRECT DEFECTS - A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit includes a partial bank of redundant memory cells, wherein an aggregation of the partial bank of redundant memory cells in each of the circuit layers of the stack includes at least one full bank of redundant memory cells and wherein the redundant resources circuit is configured to replace at least one defective bank of memory cells formed on any of the circuit layers in the stack with at least a portion of the partial bank of redundant memory cells formed on any of the circuit layers in the stack. | 2013-10-24 |
20130279281 | SEMICONDUCTOR MEMORY INTEGRATED DEVICE HAVING A PRECHARGE CIRCUIT WITH THIN-FILM TRANSISTORS GATED BY A VOLTAGE HIGHER THAN A POWER SUPPLY VOLTAGE - Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage. | 2013-10-24 |
20130279282 | E-FUSE ARRAY CIRCUIT - An e-fuse array circuit includes a first select transistor configured to have a gate terminal connected to a first select line and have a first terminal connected to a first bit line, a first e-fuse transistor configured to have a gate terminal connected to a common program/read line and have a first terminal connected to a second terminal of the first select transistor, a second select transistor configured to have a gate terminal connected to a second select line and have a first terminal connected to the first bit line, and a second e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the second select transistor. | 2013-10-24 |
20130279283 | MEMORY DEVICES AND MEMORY CONTROLLERS - A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals. | 2013-10-24 |
20130279284 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR REFRESHING MEMORY CELLS - A semiconductor memory device is provided. The semiconductor memory device includes a memory block including a plurality of memory cells; a default refresh controller configured to receive a refresh command from a host, to generate a default refresh signal, and to control the memory cells to be refreshed; and a weak cell refresh controller configured to receive the default refresh signal, to generate a weak cell refresh signal, and to control a weak cell among the memory cells to be refreshed. The weak cell may be refreshed at least one more time during a refresh period during which all of the memory cells are refreshed by the default refresh controller. The semiconductor memory device performs at least one more refresh on a weak cell having a data retention time shorter than a refresh period apart from a normal default refresh, thereby preventing data loss. | 2013-10-24 |
20130279285 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array region and a column decoder. The memory cell array region includes a plurality of memory cell arrays that are arranged in row and column directions. The column decoder includes a first column select line (CSL) driver and a second CSL driver that are disposed adjacent to a first edge of the memory cell array region extending in the row direction and that have different physical layouts. | 2013-10-24 |
20130279286 | Mixing System - A liquid transport system including a bag adapted to hold fluids, the bag being constructed of a flexible fabric. The bag has a top portion, a bottom portion and a sidewall portion forming an interior and exterior. The system includes a discharge port, a fill port and a series of injector ports on the bag providing fluid access to the interior of the bag from the exterior, where each of the ports are sealingly closable. The discharge port and the fill port are adapted to allow product to flow into and out of the bag, and the injector ports are adapted to accommodate an injector probe. | 2013-10-24 |
20130279287 | HAND-HOLDABLE MIXING CONTAINER - A device for mixing having a housing with at least one wall and a closed bottom, a lid structured to be removably attached to the housing, and a mixing element mounted on one of the housing and the top, the mixing element having a first end mounted on at least one of the housing and the top and a second end that is coupled to the first end. The housing includes a storage component that is configured to be removably attached to the closed bottom of the housing. | 2013-10-24 |
20130279288 | Frosty swirl machine - A frosty swirl machine includes a housing, a funnel, an auger for swirling ice-cream with other additives to become a mixture, a driving unit, and a protective cap. The protective cap has a passage opening movably mounted at a mixture outlet of the funnel, in such a manner that the protective cap is capable of moving between a opened position and a closed position, wherein in the opened position, the protective cap is moved to align the passage opening with the mixture outlet of the funnel so as to allow the mixture to pour out of the funnel through the mixture outlet and the passage opening, wherein in the closed position, the protective cap is moved to block the mixture outlet so as to prevent the mixture from being poured out of the funnel. | 2013-10-24 |
20130279289 | STIRRING INSTALLATION AND METHOD - The invention relates to a stirring installation ( | 2013-10-24 |
20130279290 | DEVICE AND METHOD FOR DEGHOSTING VARIABLE DEPTH STREAMER DATA - Computing device, computer instructions and method for deghosting seismic data related to a subsurface of a body of water. The method may include receiving input seismic data recorded by seismic receivers that located at different depths (z | 2013-10-24 |
20130279291 | ACQUIRING NEAR-ZERO OFFSET SURVEY DATA - To acquire near-zero offset survey data, a survey source and a first streamer attached to the survey source are provided, where the first streamer has at least one survey receiver. A second streamer separate from the survey source and the first streamer includes survey receivers. Near-zero offset data is measured using the at least one survey receiver of the first streamer. | 2013-10-24 |
20130279292 | SEISMIC DATA PROCESSING INCLUDING PREDICTING MULTIPLES USING A REVERSE TIME DEMIGRATION - Methods and systems for generating a stable reverse time demigration (RTDM) equation for predicting wave phenomena such as reflections, refractions and multiples are described. A coupling term is added to an RTDM equation and reflectivity associated with the coupling term is replaced with a pseudo-density function derived from a nonlinear equation. The resultant coupled and stabilized RTDM equation is then used to predict the desired wave phenomena based on the applied seismic image. | 2013-10-24 |
20130279293 | VECTORIZATION OF FAST FOURIER TRANSFORM FOR ELASTIC WAVE PROPOGATION FOR USE IN SEISMIC UNDERWATER EXPLORATION OF GEOGRAPHICAL AREAS OF INTEREST - Numerical simulations of elastic wave propagation algorithms are critical components for seismic imaging and inversion. Finite-difference schemes yield good efficiency but cannot ensure the accuracy of the high frequency component. Pseudo-spectral algorithms are accurate up to the Nyquist frequency, but its efficiency depends on the optimization of the fast Fourier transform (FFT) algorithm. The conventional FFT algorithms are optimized for signal processing, in which problems are generally one dimensional time series. For 3D wave propagation, FFT algorithms have the potential to be further optimized. Under current computer hardware architecture, a vectorization scheme for high dimensional FFTs is presented. Compared to conventional numerical scheme implementations, the systems and methods disclose herein has the best performance on the slowest or higher dimensions of data. For elastic wave propagation, vectorization improves the efficiency by more than a factor of two when compared to standard FFT algorithms. | 2013-10-24 |
20130279294 | Nonlinear imaging with dual band pulse complexes - The invention presents methods and instrumentation for measurement or imaging of a region of an object with waves of a general nature, for example electromagnetic (EM) and elastic (EL) waves, where the material parameters for wave propagation and scattering in the object depend on the wave field strength. The invention specially addresses suppression of 3 | 2013-10-24 |
20130279295 | DUAL FREQUENCY ULTRASONIC LOCATIONING SYSTEM - A dual frequency ultrasonic locationing system includes an emitter operable to emit two different ultrasonic frequencies simultaneously in one ultrasonic burst. A receiver with at least two microphones is operable to receive the ultrasonic burst. A correlator is operable to correlate the signals obtained from each microphone to derive a time difference of arrival of the ultrasonic burst at each microphone. The time difference of arrival of the ultrasonic signal from the emitter impinging on each microphone of the receiver is utilized to determine a location of the emitter. | 2013-10-24 |
20130279296 | TRACKING SYSTEM FOR A PIPELINE - A tracking system for use with a pipeline includes a scraper having signal generation capability for generating acoustic signals, a plurality of acoustic pressure sensors positioned at intervals along the path traveled by the scraper, and a plurality of local processors positioned at intervals along the path traveled by the scraper. Each of the local processors is in communication with a respective acoustic pressure sensor. A central processor is in communication with the local processors and determines the location of the scraper using time-stamped acoustic signals received by the pressure sensors and a speed of sound in a fluid within the pipeline. | 2013-10-24 |
20130279297 | ORIENTATION OF AN ULTRASONIC SIGNAL - A system and method for orientation of an ultrasonic signal includes at least two emitters in a mobile device that includes an orientation sensor that can determine a device orientation. A receiver at a fixed, known point includes at least two microphones operable to receive an ultrasonic signal from the device. The mobile device can drive the emitters to produce an ultrasonic signal that is oriented towards the receiver. A location engine can establish a location of the mobile device using the time delay of arrival of an ultrasonic burst from the mobile device impinging on each microphone of the receiver. In response to the location and/or the orientation, the mobile device operable to drive the emitters to produce a signal that is oriented towards the receiver. | 2013-10-24 |
20130279298 | MONITORING OF UNDERWATER MOORING LINES - In some aspects of the inventive subject matter, there is provided a monitor for monitoring at least one operational condition of an underwater mooring line, the monitor comprising an elongate main body, a protective shroud, at least one operational condition sensor for monitoring the, or each, operational condition, at least one acoustic transmitter, and (in some instances) a source of electrical power for powering the operation of the sensor and transmitter. The main body has at first and second ends respectively first and second mooring line connections (each configured for connection to a respective mooring line) and an intermediate portion. In use, the intermediate section is under tension between the first and second ends when the mooring line is under load. The, or each, operational condition sensor is attached to the intermediate section, the sensor having a signal output for providing a signal regarding the sensed operational condition. | 2013-10-24 |
20130279299 | Underwater Navigation - An underwater navigation system comprising a transmitter having an electrically insulted magnetic coupled antenna for transmitting an electromagnetic and/or magneto-inductive signal, a receiver having an electrically insulated magnetic coupled antenna for receiving an electromagnetic and/or magneto-inductive signal from the transmitter, and determining means for determining the position of the receiver relative to the transmitter using the received electromagnetic and/or magneto-inductive signal. | 2013-10-24 |
20130279300 | INFORMATION-PROVIDING SYSTEM, PORTABLE TERMINAL DEVICE, SERVER, AND PROGRAM - Provided is an information-providing system whereby a variety of information can be provided using a sound to a portable terminal device used by a user. The information-providing system includes a sound output device outputting, as a sound wave, identifying information modulated into a sound signal, an identifying-information resolution server, connected to an information-communication network, for identifying, based on the identifying information, address information for accessing a content server connected to an information-communication network; and a portable terminal device including a sound receiving section for receiving the sound wave outputted by the sound-emitting device, a demodulating section for demodulating the identifying information from the received sound wave, a resolution section for sending the demodulated identifying information to the identifying-information resolution server and acquiring the address information, and an accessing section for accessing the content server using the acquired address information. | 2013-10-24 |
20130279301 | INFORMATION DISPLAY DEVICE AND ELECTRONIC TIMEPIECE - An information display device of the present invention includes an hour plate having an opening, a rotor which is rotatably placed below the hour plate and has a display section which is partially exposed corresponding to the opening of the hour plate, and a braking member which gives a load to the rotor when the rotation of the rotor is stopped, and reduces the load on the rotor when the rotor is rotating. | 2013-10-24 |