43rd week of 2008 patent applcation highlights part 67 |
Patent application number | Title | Published |
20080263292 | SYSTEM AND METHOD FOR MANAGNG MEMORY COMPRESSION TRANSPARENT TO AN OPERATING SYSTEM - In a computer system having an operating system and a compressed main memory defining a physical memory and a real memory characterized as an amount of main memory as seen by a processor, and including a compressed memory hardware controller device for controlling processor access to the compressed main memory, there is provided a system and method for managing real memory usage comprising: a compressed memory device driver for receiving real memory usage information from the compressed memory hardware controller, the information including a characterization of the real memory usage state: and, a compression management subsystem for monitoring the memory usage and initiating memory allocation and memory recovery in accordance with the memory usage state, the subsystem including mechanism for adjusting memory usage thresholds for controlling memory state changes. Such a system and method is implemented in software operating such that control of the real memory usage in the computer system is transparent to the operating system. | 2008-10-23 |
20080263293 | Method for Selectively Performing a Secure Data Erase to Ensure Timely Erasure - A method and computer program product are provided to ensure a timely secure data erase by determining an erasure deadline for each physical volume of a plurality of physical volumes and calculating a remaining time for each physical volume. The remaining time is calculated for each physical volume by comparing a current date to the erasure deadline of each physical volume respectively. The physical volumes may then be sorted based on the remaining time and the physical volume with a shortest calculated remaining time will be selectively secure data erased. | 2008-10-23 |
20080263294 | Method for Determining Allocation of Tape Drive Resources for a Secure Data Erase Process - A method and computer program product are provided to ensure a timely secure data erase by determining whether allocating an additional tape drive would improve secure data erase performance by evaluating a quantity of physical volumes to be secure data erased, a maximum queued threshold, an average time to an erasure deadline and a minimum expiration threshold. An additional tape drive is allocated for the secure data erase process when it is determined that allocating an additional tape drive would improve secure data erase performance. | 2008-10-23 |
20080263295 | Methods, apparatus, and program products for improved finalization - Apparatus, methods, and computer program products are disclosed that improve management of a dynamic memory area. One aspect is a method that reclaims memory referenced by a finalizable-object that has been instantiated from a class definition that incorporates at least one parent class and one or more class-extensions into a class hierarchy. The method includes marking for retention a related memory reachable from a reference field of the finalizable-object, and adding the finalizable-object to a finalization set for subsequent invocation of a non-trivial finalize-method. The method also determines whether the portion of the finalizable-object that includes the reference field to the related memory is a class-extension that has a finalizer-free characteristic and conditions the marking for retention on that determination. Thus, a portion the finalizable-object's related memory can be more quickly reclaimed from a dynamic memory area. | 2008-10-23 |
20080263296 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR STORING AN INFORMATION BLOCK - A method for storing an information block that includes determining to store a current version of an information block stored in a memory unit. The checking if a current version of the information is already stored in a storage unit. The current version of the information block is sent from the memory unit to the storage unit if the answer is negative. Generating storage unit location information indicative of a location, at the storage unit, of the current version of the information block if the answer is positive. | 2008-10-23 |
20080263297 | System, method, and software for enforcing information retention using uniform retention rules - Methods, systems, and software for enforcing archival of data objects into archive objects and managed destruction of the archive objects are disclosed. In some cases, the computer techniques include enforcing a retention rule, such as a retention date and archive properties, and a destruction indication, such as an expiration date, of data identified for archival. The data objects are archived under hierarchical paths in a long-term storage system according to retention-related properties of the data objects and the retention rules. Further, the archived data can be destroyed according to destruction indications. Once archived, destruction of the data may be prevented by a hold applied to the data. | 2008-10-23 |
20080263298 | Semiconductor device controlling debug operation of processing unit in response to permission or prohibition from other processing unit - A semiconductor device includes a volatile memory for storing a first instruction group, a first processing unit for executing the first instruction group, a nonvolatile memory for storing a second instruction group, a second processing unit for executing a second instruction group, a control signal output unit for outputting a control signal to specify permission or prohibition of executing a debugging function to the first processing unit, and a debug control unit for controlling execution of the debugging function by the first processing unit based on the control signal. | 2008-10-23 |
20080263299 | Storage System and Control Method Thereof - A storage system and a control method thereof that can avoid performance degradation of a write command from a host are provided. In the storage system, when a request for conversion from snapshot to actual data copy is received, first, a copy difference table is scanned from its leading bit without deleting a pair of original volume and snapshot in a pair table, non-copy data is copied from the original volume to a pool volume, a corresponding bit in the copy difference table is changed to a copied one after the copying is completed, and a corresponding bit in the data match difference table is changed to match. Regarding all bits in the copy difference table, the above-mentioned processed is completed, and thereafter backup type of the pair table is changed to actual data copy. | 2008-10-23 |
20080263300 | Storage Media - A storage media for storing data and comprising an integral controller configured to control access to the data depending on the location of the storage media. The storage media may further comprise means to determine its location, e.g. such as a GPS receiver or a cellular network positioning solution. Alternatively, the location may be provided by an external device. | 2008-10-23 |
20080263301 | KEY-CONTROLLED OBJECT-BASED MEMORY PROTECTION - A method, system, and program key-controlled object-based memory protection are provided. A processing unit includes an authority check for controlling access by the processing unit to pages of memory according to whether a hardware protection key set currently loaded in an authority mask register allows access to the pages. In particular, each page of memory is assigned a page key number that indexes into the hardware protection key set. The currently loaded hardware protection key set specifies those page key numbers that are currently accessible to the processing unit for the execution context. Each hardware key within the hardware protection key set may be associated with a particular data object or group of data objects. Thus, effectively, the currently loaded hardware protection key set identifies which data objects or groups of data objects are currently accessible. Software keys are assigned to data objects and dynamically mapped to hardware protection key sets, such that when a module is called, the software keys assigned to that module are mapped to the hardware protection key set to be loaded for controlling current access to memory. | 2008-10-23 |
20080263302 | Non-volatile memory circuit, system, and method - A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command. | 2008-10-23 |
20080263303 | LINEAR COMBINER WEIGHT MEMORY - A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight value. The second register is operable to store a second in-phase weight value and be written with the second in-phase weight value while the first in-phase weight value is read from the first register. The third register is operable to store a first quadrature weight value. The fourth register is operable to store a second quadrature weight value and be written with the second quadrature weight value while the first quadrature weight value is read from the third register. | 2008-10-23 |
20080263304 | LATENCY ALIGNED VOLUME PROVISIONING METHODS FOR INTERCONNECTED MULTIPLE STORAGE CONTROLLER CONFIGURATION - A system is composed of multiple storage control modules, which are connected to each other via interconnects. The aforesaid interconnects connecting the storage control modules may cause certain extra latency. Each storage control module may have data preservation module, which can preserve data stored by host computers. The system incorporates a latency table and provides a volume according to the latency table in accordance with a request from a host computer or an administrator. The latency table is dynamically created or statically stored in the inventive system. | 2008-10-23 |
20080263305 | REMOVE-ON-DELETE TECHNOLOGIES FOR SOLID STATE DRIVE OPTIMIZATION - Technologies for identifying data stored on a solid state drive (“SSD”) device that correspond to data associated with a delete event, and marking the deleted data stored on the SSD as invalid such that the SSD can avoid unnecessary operations on the invalid data. Included are interfaces operable to communicate invalid data information and providing a remove-on-delete command that provides invalid data information sufficient to identify the SSD data to be marked as invalid. | 2008-10-23 |
20080263306 | Information processing apparatus having virtualization function, method of virtualization, and computer-readable recording medium - An information processing apparatus having a virtualization function for creating a virtual disk based on a logical volume selected from a plurality of storage areas comprises a host device for performing information processing on a storage device, and a virtualization switch for connecting the host device to the storage device via a path. The host device includes a controller which computes information necessary for virtualization by acquiring information concerning the physical configuration of the storage device and information concerning the path from an information storing unit provided in a virtualization switch, selects specific logical volumes that match a pre-specified logical volume selection criterion, registers the selected logical volumes into a virtual storage pool, and creates the virtual disk by selecting a logical volume from the virtual storage pool. There is provided a method of virtualization which is implemented using the information processing apparatus, etc. | 2008-10-23 |
20080263307 | INFORMATION PROCESSING APPARATUS AND METHOD, AND PROGRAM - Disclosed herein is an information processing apparatus, including: setting means for setting, a maximum transfer size; calculation means for subtracting a second data amount from a first data amount to calculate a third data amount; boundary determination means for determining whether this transfer will involve a page boundary being extended across; buffer boundary determination means for determining whether this transfer will involve a buffer size being exceeded; transfer size determination means for determining whether or not the third data amount is equal to or less than the maximum transfer size; and determination means for determining a data amount of data to be transferred within limits of the third data amount, based on a first determination made by the boundary determination means, a second determination made by the buffer boundary determination means, and a third determination made by the transfer size determination means. | 2008-10-23 |
20080263308 | STORAGE ALLOCATION MANAGEMENT IN SWITCHES UTILIZING FLOW CONTROL - A computer program product and system for managing allocation of storage in a switch utilizing flow control are provided. The switch includes a plurality of ports and an internal storage divided into a plurality of storage units. The computer program product and system provide for monitoring an average number of storage units used by each of the plurality of ports over a predetermined time period, setting a threshold for the average number of storage units used by each of the plurality of ports, and allocating one or more available storage units assigned to a first port to a second port in response to storage allocation management being enabled for the second port and the average number of storage units used by the second port exceeding the threshold for the second port. | 2008-10-23 |
20080263309 | Creating a Physical Trace from a Virtual Trace - In an embodiment, virtual trace records are read and physical trace records are created and displayed. The virtual trace records are associated with virtual processors allocated to logical partitions in a logically-partitioned computer system. Each of the virtual trace records has a wait timestamp, specifying a time at which a virtual processor began waiting to be dispatched and a wait time delta, specifying an amount of time that the virtual processor waited to be dispatched. An execute timestamp is created in each of the virtual trace records, which specifies a time at which the virtual processor was dispatched. The virtual trace records are sorted for each of the virtual processors by the execute timestamp. Physical trace records are created based on the sorted virtual trace records. Each physical trace record describes a dispatch of one of the virtual processors to one of the physical processors. | 2008-10-23 |
20080263310 | PARALLEL INSTALLATION OF LOGICAL PARTITIONS - An apparatus and method provide parallel installation of logical partitions on a computer system. The function of a hardware maintenance console is built into a logical partition configuration mechanism that resides in the system firmware. A virtual local area network (VLAN) is used by the logical partition configuration mechanism to define an I/O bridge that allows installing multiple logical partitions in parallel. Because multiple logical partitions may be installed in parallel, the time required to install logical partitions is greatly reduced. | 2008-10-23 |
20080263311 | PARALLEL INSTALLATION OF LOGICAL PARTITIONS - An apparatus and method provide parallel installation of logical partitions on a computer system. The function of a hardware maintenance console is built into a logical partition configuration mechanism that resides in the system firmware. A virtual local area network (VLAN) is used by the logical partition configuration mechanism to define an I/O bridge that allows installing multiple logical partitions in parallel. Because multiple logical partitions may be installed in parallel, the time required to install logical partitions is greatly reduced. | 2008-10-23 |
20080263312 | PARALLEL INSTALLATION OF LOGICAL PARTITIONS - An apparatus and method provide parallel installation of logical partitions on a computer system. The function of a hardware maintenance console is built into a logical partition configuration mechanism that resides in the system firmware. A virtual local area network (VLAN) is used by the logical partition configuration mechanism to define an I/O bridge that allows installing multiple logical partitions in parallel. Because multiple logical partitions may be installed in parallel, the time required to install logical partitions is greatly reduced. | 2008-10-23 |
20080263313 | Pretranslating Input/Output Buffers In Environments With Multiple Page Sizes - Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports more than one memory page size, identifying pretranslation page frame numbers for the buffer in dependence upon the pretranslation page size, pretranslating the pretranslation page frame numbers to physical page numbers, and storing the physical page numbers in association with the pretranslation page size. Typical embodiments also include accessing the buffer, including translating a virtual memory address in the buffer to a physical memory address in dependence upon the physical page numbers and the pretranslation page size and accessing the physical memory of the buffer at the physical memory address. | 2008-10-23 |
20080263314 | ADDRESS TRANSLATION APPARATUS WHICH IS CAPABLE OF EASILY PERFORMING ADDRESS TRANSLATION AND PROCESSOR SYSTEM - An address translation apparatus includes first to third retention units, a comparison unit, and a translation unit. The first retention unit retains a multi-bit first address. The second retention unit retains a multi-bit second address different from the first address. The third retention unit retains first information indicating which bit is a translation target in the multi bits of the first address. The comparison unit compares a multi-bit third address input from outside and the first address. The translation unit translates the bit indicated by the first information in the multi bits of the third address to obtain a fourth address such that the bit indicated by the first information coincides with the second address, when the third address coincides with the first address based on comparison result of the comparison unit. | 2008-10-23 |
20080263315 | COMPUTER MEMORY ADDRESSING MODE EMPLOYING MEMORY SEGMENTING AND MASKING - A computer addressing mode and memory access method rely on a memory segment identifier and a memory segment mask for indicating memory locations. In this addressing mode, a processor receives an instruction comprising the memory segment identifier and memory segment mask. The processor employs a two-level address decoding scheme to access individual memory locations. Under this decoding scheme, the processor decodes the memory segment identifier to select a particular memory segment. Each memory segment includes a predefined number of memory locations. The processor selects memory locations within the memory segment based on mask bits set in the memory segment mask. The disclosed addressing mode is advantageous because it allows non-consecutive memory locations to be efficiently accessed. | 2008-10-23 |
20080263316 | Splash Tables: An Efficient Hash Scheme for Processors - A computer implemented method, data processing system, and computer usable program code are provided for storing data items in a computer. A plurality of hash functions of data values in a data item are computed. A corresponding memory location is determined for one of the plurality of hash functions. The data item and a key portion and a payload portion of all data items are stored contiguously within the memory location. | 2008-10-23 |
20080263317 | DATAPIPE DESTINATION AND SOURCE DEVICES - An integrated circuit ( | 2008-10-23 |
20080263318 | Timed ports - A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time value matches the trigger time value and, provided that said match is detected, to transfer data between the port and an external environment and alter a ready signal to indicate the transfer. The internal environment comprises: an execution unit for transferring data between the at least one port and the internal environment; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions. The scheduling includes scheduling one or more of said threads for execution in dependence on the ready signal. | 2008-10-23 |
20080263319 | UNIVERSAL DIGITAL BLOCK WITH INTEGRATED ARITHMETIC LOGIC UNIT - An array of universal digital blocks include programmable logic device sections that have uncommitted user programmable logic functions and structural datapath sections that include dedicated and highly configurable arithmetic operators. A routing channel matrix programmably connects to different programmable logic device sections and datapath sections in the different universal digital blocks. | 2008-10-23 |
20080263320 | Executing a Scatter Operation on a Parallel Computer - Executing a scatter operation on a parallel computer includes: configuring a send buffer on a logical root, the send buffer having positions, each position corresponding to a ranked node in an operational group of compute nodes and for storing contents scattered to that ranked node; and repeatedly for each position in the send buffer: broadcasting, by the logical root to each of the other compute nodes on a global combining network, the contents of the current position of the send buffer using a bitwise OR operation, determining, by each compute node, whether the current position in the send buffer corresponds with the rank of that compute node, if the current position corresponds with the rank, receiving the contents and storing the contents in a reception buffer of that compute node, and if the current position does not correspond with the rank, discarding the contents. | 2008-10-23 |
20080263321 | Universal Register Rename Mechanism for Targets of Different Instruction Types in a Microprocessor - A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating a floating point register (FPR) can be renamed along with an instruction that is updating a general purpose register (GPR) or vector multimedia extensions (VMX) instructions register (VR) using the same rename structure because the number of architected states for GPR is the same as the number of architected states for FPR and VR. Each destination tag (DTAG) is assigned to one destination. A floating point instruction may be assigned to a DTAG, and then a fixed point instruction may be assigned to the next DTAG and so forth. With a universal rename mechanism, significant silicon and power can be saved by having only one rename structure for all instruction types. | 2008-10-23 |
20080263322 | MAC ARCHITECTURE FOR PIPELINED ACCUMULATIONS - A programmable accumulation module ( | 2008-10-23 |
20080263323 | Reconfigurable Computing Architectures: Dynamic and Steering Vector Methods - A reconfigurable processor including a plurality of reconfigurable slots, a memory, an instruction queue, a configuration selection unit, and a configuration loader. The plurality of reconfigurable slots are capable of forming reconfigurable execution units. The memory stores a plurality of steering vector processing hardware configurations for configuring the reconfigurable execution units. The instruction queue stores a plurality of instructions to be executed by at least one of the reconfigurable execution units. The configuration selection unit analyzes the dependency of instructions stored in the instruction queue to determine an error metric value for each of the steering vector processing hardware configurations indicative of an ability of a reconfigurable slot configured with the steering vector processing hardware configuration to execute the instructions in the instruction queue, and chooses one of the steering vector processing hardware configurations based upon the error metric values. The configuration loader determines whether one or more of the reconfigurable slots are available and reconfigures at least one of the reconfigurable slots with at least a part of the chosen steering vector processing hardware configuration responsive to at least one of the reconfigurable slots being available. | 2008-10-23 |
20080263324 | DYNAMIC CORE SWITCHING - A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode. | 2008-10-23 |
20080263325 | SYSTEM AND STRUCTURE FOR SYNCHRONIZED THREAD PRIORITY SELECTION IN A DEEPLY PIPELINED MULTITHREADED MICROPROCESSOR - A microprocessor and system with improved performance and power in simultaneous multithreading (SMT) microprocessor architecture. The microprocessor and system includes a process wherein the processor has the ability to select instructions from one thread or another in any given processor clock cycle. Instructions from each, thread may be assigned selection priorities at multiple decision points in a processor in a given cycle dynamically. The thread priority is based on monitoring performance behavior and activities in the processor. In the exemplary embodiment, the present invention discloses a microprocessor and system for synchronizing thread priorities among multiple decision points throughout the micro-architecture of the microprocessor. This system and method for synchronizing thread priorities allows each thread priority to he in sync and aware of the status of other thread priorities at various decision points within the microprocessor. | 2008-10-23 |
20080263326 | METHOD AND APPARATUS FOR AN EFFICIENT MULTI-PATH TRACE CACHE DESIGN - A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced. | 2008-10-23 |
20080263327 | Automatically selecting firmware instructions for an operating system - Embodiments of the present invention pertain to automatically selecting firmware instructions for an operating system. According to one embodiment, at least a part of a first subset of firmware instructions on a computer system is executed. An automatic determination of whether the first subset of firmware instructions supports an operating system the computer system will execute is made. If the first subset of firmware instructions does not support the operating system, a second subset of firmware instructions that does support the operating system is automatically caused to execute without requiring human intervention. A single firmware includes the first subset and the second subset of firmware instructions for different operating systems. | 2008-10-23 |
20080263328 | ORTHOGONAL REGISTER ACCESS - Embodiments of the invention relate to a method and system for accessing a set of parallel registers orthogonally. A decoder may be used to select a particular row or column of the set of parallel registers to perform register operations in a parallel fashion corresponding to the selected row or in an orthogonal fashion corresponding to the selected column. Thus, when a particular row is selected, a register operation may be carried out for each bit of the selected row to produce a parallel register output, such as by reading/writing each bit of the selected row to a parallel register. On the other hand, when a particular column is selected, a register operation may be carried out for each bit of the selected column, such as by reading/writing each bit of the selected column to an orthogonal register. The orthogonal register access allows for fast and efficient access to a particular bit in the set of parallel registers. | 2008-10-23 |
20080263329 | Parallel-Prefix Broadcast for a Parallel-Prefix Operation on a Parallel Computer - A parallel-prefix broadcast for a parallel-prefix operation on a parallel computer includes: configuring, on each node, a parallel-prefix contribution buffer for storing the node's parallel-prefix contribution; configuring, on each node, a parallel-prefix results buffer for storing results of a operation, the results buffer having a position for each node that corresponds to node's rank; and repeatedly for each position in the results buffer: processing in parallel by each node, including: determining, by the node, whether the current position in the results buffer is to include the node's contribution, if the current position is not to include the contribution, contributing the identity element, and if the current position is to include the contribution, contributing the contribution, performing, by each node, the operation using the contributed identity elements and the contributed contributions, yielding a result from the operation, and storing, by each node, the result in the position in the results buffer. | 2008-10-23 |
20080263330 | Clocked ports - A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal. | 2008-10-23 |
20080263331 | Universal Register Rename Mechanism for Instructions with Multiple Targets in a Microprocessor - A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type of destination(s) that is/are being updated by such a particular instruction. For example, a common DTAG can be assigned to a fixed point unit instruction (FXU) that updates general purpose register (GPR), fixed point exception register (XER), and condition code register (CR) destinations. During flush time, the DTAGs in the recovery link may be used to restore the information indicating that the youngest instruction updates a particular architected register. By using a single, universal rename structure for all types of destinations, a large saving in silicon and power can be realized without the need to sacrifice performance. | 2008-10-23 |
20080263332 | Data Processing Apparatus and Method for Accelerating Execution Subgraphs - A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph. The evaluation of each output function generates an output operand for storing in the operand store, and each output operand corresponds to an output that would have been generated had the sequence of individual program instructions corresponding to the computational subgraph have been executed by the processing logic. Configuration storage stores a single look-up table (LUT) configuration for each output function, and for each output function to be evaluated, the accelerator logic is configured dependent on the associated single LUT configuration from the configuration storage, such that on receipt of the input operands of the computational subgraph, the accelerator logic will generate the output operand. This technique has been found to provide a particularly efficient accelerator logic for evaluating output functions associated with computational subgraphs. | 2008-10-23 |
20080263333 | DOCUMENT PROCESSING METHOD - The present invention discloses a method for processing document data to achieve document interoperation, and the method comprises: by an application, performing an operation on abstract unstructured information by issuing instruction(s) to a platform software; and by the said platform software, receiving the said instruction and performing the operation on storage data corresponded to the abstract unstructured information according to the said instruction; wherein said abstract unstructured information are independent of a way in which said storage data are stored. | 2008-10-23 |
20080263334 | DYNAMICALLY CONFIGURABLE AND RE-CONFIGURABLE DATA PATH - An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory. | 2008-10-23 |
20080263335 | Representation of Modal Intervals within a Computer - A modal interval representation having improved computational utility is provided. The modal interval representation generally includes a binary quantifier, and a set theoretical interval for select permutations of marks of a pair of marks of an IEEE standard 754 digital scale. The set theoretical interval includes combinations of real numbers, infinities, signed zeros, and pseudo-numbers, with select permutations of the marks comprising bounded, unbounded, pointwise and indefinite modal intervals. | 2008-10-23 |
20080263336 | Processor Having Efficient Function Estimate Instructions - High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic. | 2008-10-23 |
20080263337 | INSTRUCTIONS FOR ORDERING EXECUTION IN PIPELINED PROCESSES - Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Memory write operations local to a CPU are allowed to occur in an arbitrary order, and constraints are placed on shared memory operations. Multiple sets of instructions are provided in which order of execution of the instructions is maintained through the use of CPU registers, write buffers in conjunction with assignment of sequence numbers to the instruction, or a hierarchical ordering system. The system ensures that an earlier designated instruction has reach a specified state of execution prior to a latter instruction reaching a specified state of execution. The ordering of operations allows memory operations local to a CPU to occur in conjunction with other memory operations that are not affected by such execution. | 2008-10-23 |
20080263338 | EXCEPTION OPERATION APPARATUS, METHOD AND COMPUTER PROGRAM FOR CONTROLLING DEBUGGING APPARATUS, AND TELEVISION AND CELLULAR PHONE PROVIDING THE SAME - In order to automatically activate a debugger while maintaining the status of the machine as it was just before execution of the instruction which has raised an exception even in a case in which a break point is not set beforehand, a computer, which executes a program to be debugged, analyzes an exception raised on the computer, and replaces an instruction with another instruction for activating a debugger if the exception has been raised due to the instruction that conducts an abnormal operation and is stored in a memory space. After this, the computer selects and switches to a task to be processed based on the status of each of the tasks, or resumes an operation which has been suspended due to the exception. Then, when the computer executes the instruction for activating the debugger, the debugger detects this execution and is activated. | 2008-10-23 |
20080263339 | Method and Apparatus for Context Switching and Synchronization - A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread. | 2008-10-23 |
20080263340 | Method and Device for Analyzing a Signal from a Computer System Having at Least Two Execution Units - A method and device for analyzing a signal from a computer system having at least two execution units, in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, characterized in that, in the computer system, a mode signal and/or changes in the mode signal, which are indicative of the current operating mode, are generated, and at least the changes in the mode signal and/or this mode signal itself are made available outside of the computer system for analysis purposes. | 2008-10-23 |
20080263341 | Data processing apparatus and method for generating prediction data - A data processing apparatus and method are provided for generating prediction data. The data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry is responsive to a received event to generate prediction data used by the processing circuitry. The prediction circuitry includes a history storage having a plurality of counter entries for storing count values, and index circuitry for identifying, dependent on the received event, at least one counter entry and for causing the history storage to output the count value stored in that at least one counter entry, with the prediction data being derived from the output count value. Further update control circuitry is provided for modifying at least one count value stored in the history storage in response to update data generated by the processing circuitry. The update control circuitry has a priority dependent modification mechanism such that the modification to the at least one count value is dependent on the priority of the processing operation with which that update data is associated. As a result, the prediction data output for a received event associated with a high priority operation is more accurate than the prediction data output for a received event associated with a low priority operation. | 2008-10-23 |
20080263342 | Apparatus and method for handling exception signals in a computing system - Described is method and apparatus for handling exception signals in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. An exception handling unit selectively handles some exception signals with respect to a target state and handles others with respect to a subject state derived from the target state. Signal handling sub-units are arranged to process the exception signal with respect to the target state and output a request either to return to execution or to pass on the exception signal. A delivery path selection unit is arranged to determine a delivery path of the exception signal to a selected group of the plurality of signal handling sub-units. A signal control unit is arranged to deliver the exception signal in turn to each of the selected group of signal handling sub-units. | 2008-10-23 |
20080263343 | Multi-Channel Algorithm Infrastructure for Programmable Hardware Elements - System and method for implementing multi-channel operations in a programmable hardware element (PHE). A hardware configuration program, including a processing function, inputs and outputs of the processing function, a plurality of channels, and channel scanning functionality for the plurality of channels, is specified. A PHE is configured with the hardware configuration program, including implementing the processing function and the channel scanning functionality on the PHE. A respective state and configuration of each of the plurality of channels is stored in a memory of the PHE to enable logic-sharing between each of the plurality of channels. The PHE is operated, including performing channel scanning on the plurality of channels, and updating the configuration of one or more of the channels in the memory of the PHE without interrupting the channel scanning, without taking any of the channels offline, and/or without interrupting a continuity of an output of the PHE. | 2008-10-23 |
20080263344 | Pre-Loading Data - A battery-powered device comprising: a memory storing software essential to the provision of normal functions of the device; a first processing section ( | 2008-10-23 |
20080263345 | Dual boot strategy to authenticate firmware in a computing device - Methods for authenticating firmware in a computing device include partitioning functions critical to the intended role of the computing device so that, upon successful authentication of the firmware, all functions of the device are made operational. Otherwise, the computing device behaves in a diagnostic mode of operation to assist users in troubleshooting to eventually authenticate firmware. At least first and second sets of firmware are loaded at various times into a controller of the computing device with the first set occurring without verification of trustworthiness, while the second set occurs upon authentication of the first. The second is used to authenticate a remainder set of firmware. Particular computing devices contemplate laser printers, mobile phones, PDA's, gaming consoles, etc. Firmware downloads, error messaging, hash comparisons, signature table construction, page-in techniques, computer program products, and particular computing arrangements are other noteworthy features, to name a few. | 2008-10-23 |
20080263346 | Method and device for securely sending bootstrap message in device management - A method and device for securely sending a bootstrap message from a server (i.e., a device management (DM )server) to a device in a device management system, the method comprising acquiring first information by the device, receiving, by the device, a bootstrap message from the server, acquiring, by the device, second information from the received bootstrap message, and verifying the bootstrap message by the device, whereby it is effective to securely send the bootstrap message from the server to the device by checking up whether the first information is identical to the second information. | 2008-10-23 |
20080263347 | NETWORK DEVICE AND REBOOTING METHOD THEREOF - A network device connected to a server includes a firmware upgrading determining module, a communication module, a storage module, a reboot determining module, and a reboot scheduling module. The firmware upgrading determining module determines whether current firmware of the network device needs to be upgraded. The communication module downloads the newest firmware from the server, and upgrades the current firmware if the current firmware needs to be upgraded. The storage module saves a reboot flag and a preset reboot time window. The reboot determining module determines whether the network device needs to be rebooted immediately according to the reboot flag, and determines whether the network device has a preset reboot time window. The reboot scheduling module determines what time to reboot during the reboot time window if the network device does not need to be rebooted immediately and the network device has a preset reboot time window. | 2008-10-23 |
20080263348 | Dynamic asymmetric partitioning of program code memory in network connected devices - A novel asymmetric memory partitioning mechanism for providing resolving and reducing memory limitations when an increase in software image size is required. Two partitions are created in non-volatile memory, one smaller than the other. The smaller partition stores a degenerated version of the full-functionality software comprising only essential program code for booting the device and repeating the download and installation procedures until the full-functionality software image is successfully installed in non-volatile memory. The larger portion stores a full-functionality version of the software comprising both essential and non-essential program code. The mechanism also provides the capability of converting devices already deployed in the field. The legacy symmetrical partitioning of the memory in these devices is removed and replaced with asymmetrical partitioning, wherein the smaller partition stores the degenerated software image and the larger partition stores the full-functionality software image. | 2008-10-23 |
20080263349 | BOOTING SYSTEM, BOOT PROGRAM, AND METHOD THEREFOR - A booting system, a boot program, and a method therefor are provided. A boot source device and a boot target device are connected to each other via a transfer interface. The transfer interface is an interface where booting is supported by a BIOS of the boot target device. The boot source device transfers a first object corresponding to booting data which allows the boot target device to establish and use a connection including an interface other than the transfer interface, which is not supported by the BIOS, via the transfer interface. After the boot target device is enabled to use the interface other than the transfer interface, the boot source device transfers a second object corresponding to booting data for booting up an OS of the boot target device or the like via the transfer interface and transfer interfaces and to the boot target device to boot the boot target device. | 2008-10-23 |
20080263350 | UPDATE IN-USE FLASH MEMORY WITHOUT EXTERNAL INTERFACES - A method, apparatus and program storage device for updating a non-volatile memory in an embedded system is provided. The invention includes detaching the non-volatile memory from all expectable non-volatile memory references, creating a temporary, volatile-memory file system for allocation of volatile memory space as needed for the non-volatile memory update process, copying all procedural code required to perform the non-volatile memory update into the volatile memory, changing the system search path definitions temporarily to point to the volatile memory, and performing the non-volatile memory update. | 2008-10-23 |
20080263351 | METHOD FOR CENTRALIZED DYNAMIC LINK CONFIGURATION - A method for centralized dynamic link configuration (CDLC), performed by a processor and a chipset is provided. In the method, the processor first notifies the chipset of CDLC enablement. The chipset then issues a command to the processor after receiving notification of CDLC enablement. The processor broadcasts a preparation completion signal after receiving the command. The chipset asserts a signal and activates a timer to start counting after receiving the preparation completion signal. The processor configures devices of the processor, corresponding to a bus, according to one of multiple sets of first link management mode (LMM) configuration parameters in a first LMM register of the processor, indicated by first link management action field (LMAF) code in a first LMAF register of the processor, after detecting that the signal is asserted. The chipset configures devices of the chipset, corresponding to the bus, according to one of multiple sets of second LMM configuration parameters in a second LMM register of the chipset, indicated by second LMAF code in a second LMAF register of the chipset, when asserting the signal. The chipset de-asserts the signal when the timer reaches a predetermined value. | 2008-10-23 |
20080263352 | Authentication system and method - A security protocol for use by computing devices communicating over an unsecured network is described. The security protocol makes use of secure data provided to a peripheral memory device from a server via a secure connection. When the peripheral memory device is coupled to a computing device that attempts to establish a secure connection to the server, the secure data is used to verify that the server is authentic. Similarly, the secure data assists the server in verifying that the request to access the server is not being made by a malicious third party. | 2008-10-23 |
20080263353 | AUTOCONFIGURED PREFIX DELEGATION BASED ON DISTRIBUTED HASH - In one embodiment, a method comprises detecting, by a router, an unsolicited first router advertisement message from an attachment router that provides an attachment link used by the router, the first router advertisement message specifying a first IPv6 address prefix owned by the attachment router and usable for address autoconfiguration on the attachment link; detecting, by the router, an unsolicited delegated IPv6 address prefix from the attachment router and that is available for use by the router; and automatically selecting by the router a second IPv6 address prefix based on concatenating a suffix to the delegated IPv6 address prefix, including dynamically generating the suffix based on a prescribed distributed hash operation executed by the router, the second IPv6 address prefix for use on at least one ingress link of the router. | 2008-10-23 |
20080263354 | AUTHENTICATION OF DATA TRANSMITTED IN A DIGITAL TRANSMISSION SYSTEM - A method of authenticating data transmitted in a digital transmission system, in which the method comprises the steps, prior to transmission, of determining at least two encrypted values for at least some of the data, each encrypted value being determined using a key of a respective encryption algorithm, and outputting said at least two encrypted values with said data. | 2008-10-23 |
20080263355 | Method and System for Encrypting Files Based on Security Rules - The present disclosure is directed to a method and system for encrypting files based on security rules. In accordance with a particular embodiment of the present disclosure, a request to store a file on a storage device is received. At least one security parameter associated with a security profile of the file is identified. It is determined whether to encrypt the file by applying at least one security rule to the security parameter. The security rule includes selection criteria. The file is encrypted if the security rule indicates the file should be encrypted. The file is stored on the storage device. | 2008-10-23 |
20080263356 | SECURITY ENFORCEMENT POINT INSPECTION OF ENCRYPTED DATA IN AN ENCRYPTED END-TO-END COMMUNICATIONS PATH - Embodiments of the present invention address deficiencies of the art in respect to security function processing of encrypted data in a security enforcement point and provide a method, system and computer program product for security enforcement point inspection of a traversing encrypted data in a secure, end-to-end communications path. In an embodiment of the invention, a method for security enforcement point inspection of encrypted data in a secure, end-to-end communications path can be provided. The method can include establishing a persistent secure session with a key server holding an SA for an end-to-end secure communications path between endpoints, receiving the SA for the end-to-end secure communications path over the persistent secure session, decrypting an encrypted payload for the end-to-end secure communications path using session key data in the SA, and performing a security function on the decrypted payload. | 2008-10-23 |
20080263357 | Identity-based-encryption extensions formed using multiple instances of an identity based encryption scheme - IBE extensions to IBE schemes may be provided by creating multiple instances of the same IBE scheme, where each instance has an associated IBE master key and corresponding IBE public parameters. During encryption, an IBE extension identity for each instance of the IBE scheme may be mapped to a corresponding component identity. A message may be encrypted using the component identities to create multiple ciphertexts. The ciphertexts can be combined and sent to a recipient. The recipient can request a private key. The private key may be generated by mapping the IBE extension identity into a component identity in each instance, by extracting private keys for each of the component identities, and by combining the private keys into a single IBE extension private key. | 2008-10-23 |
20080263358 | SYSTEM AND METHOD FOR LIMITING SPYWARE ACTIVITY - A system and method of detecting and limiting unsolicited data uploads. Downloaded content such as web pages and emails are scanned for web forms and/or links. A watermark is added where appropriate and the modified downloaded content is forwarded to the person who requested the content. A check is made to determine whether information received from a user includes appropriate watermarks. If so, the watermark is removed and the information is forwarded to its destination. | 2008-10-23 |
20080263359 | Water mark embedding and extraction - A watermarking key consisting of a sequence of elements is embedded into a data sequence. Each element may take on two or more values. In order to embed a watermarking key, first a reference sequence is divided into blocks. Each element of the watermarking key is associated with a respective block of the reference sequence. A watermarked sequence is then generated by shifting the associated blocks by a degree determined by the value of the respective associated element of the watermarking key. | 2008-10-23 |
20080263360 | Generating and matching hashes of multimedia content - Hashes are short summaries or signatures of data files which can be used to identify the file. Hashing multimedia content (audio, video, images) is difficult because the hash of original content and processed (e.g. compressed) content may differ significantly. The disclosed method generates robust hashes for multimedia content, for example, audio clips. The audio clip is divided ( | 2008-10-23 |
20080263361 | Cryptographically strong key derivation using password, audio-visual and mental means - A security system that uses a cryptographic key derived from human interaction with media. The system employs a set of parameters that includes user responses to graphical media and/or audio data, among other parameters. The architecture adds a fourth dimension to the conventional authentication means in order to make at least an offline attack on the key much more difficult. In addition to a standard set of parameters such as password, salt (random bits inserted into the encryption process) and iteration count, the system further utilizes information in the form of “what the user does” by presenting and prompting the user to interact with media in some way. The media can include audio information, video information, and/or image information, for example. | 2008-10-23 |
20080263362 | METHOD AND APPARATUS OF SECURE AUTHENTICATION FOR SYSTEM ON CHIP (SOC) - A SoC may be utilized to authenticate access to one or more secure functions. A password may be generated within the SoC which is unique to each SoC instance and unique to each iteration of authentication. The SoC may challenge external entities attempting access to provide a matching password. A random number sample may be generated within the SoC and stored. A chip ID, secret word and a table of keys with key indices are also stored in memory. Two or more of the stored items may be passed to a hash function to generate the password. The external entity may generate and return the password utilizing information communicated from the SoC during each authentication operation as well as information known a priori. The SoC may compare the returned password with the internally generated password and may grant access to the secure functions. | 2008-10-23 |
20080263363 | Portable Data Encryption Device with Configurable Security Functionality and Method for File Encryption - A portable encryption device with logon access controlled by an encryption key, with an on board cryptographic processor for reconstituting the encryption key from a plurality of secrets generated by a secret sharing algorithm, optionally shrouded with external secrets using an invertible transform resistant to quantum computing attacks. Another embodiment provides file decryption controlled by a file encryption key, with the on board cryptographic processor reconstituting the file encryption key from a version of the file encryption key which has been shrouded with a network authorization code. A method for encryption of a plaintext file by hashing, compressing, and encrypting the plaintext file, hashing the ciphertext, hashing the plaintext hash and the ciphertext hash, and sealing the ciphertext together with the resulting hash. A portable encryption device for performing the method is also disclosed. | 2008-10-23 |
20080263364 | System and method for providing access to a computer resource - There is provided a device and method for providing access to a computer resource. An exemplary device that is adapted to provide access to a computer resource comprises a Universal Serial Bus (USB) security token having a pressure sensor that is adapted to detect pressure applied to the USB security token, and a structure that is adapted to create authentication information to be provided to the computer resource in response to a detection of pressure by the pressure sensor. An exemplary method of providing access to a computer resource comprises detecting an application of pressure to a USB security token, and providing authentication information to the computer resource in response to the detection of the application of pressure to the USB security token. | 2008-10-23 |
20080263365 | INTEGRATING LEGACY APPLICATION/DATA ACCESS WITH SINGLE SIGN-ON IN A DISTRIBUTED COMPUTING ENVIRONMENT - The present invention provides methods, systems, computer program products, and methods of doing business whereby legacy host application/system access is integrated with single sign-on in a modern distributed computing environment. A security token used for signing on to the modern computing environment is leveraged, and is mapped to user credentials for the legacy host environment. These user credentials are programmatically inserted into a legacy host data stream, thereby giving the end user the look and feel of seamless access to all applications/systems, including not only modern computing applications/systems but also those residing on (or accessible through) legacy hosts. In addition to providing users with the advantages of single sign-on, the disclosed techniques enable limiting the number of user identifiers and passwords an enterprise has to manage. | 2008-10-23 |
20080263366 | SELF-VERIFYING SOFTWARE TO PREVENT REVERSE ENGINEERING AND PIRACY - Reverse engineering and piracy of software is prevented by encrypting code blocks of a program. A program is modified to include additional protective code, including a protective code launcher which is launched with the program. Decryption and execution code is also provided for the protective code launcher and one or more code blocks of the program. A given code block is encrypted using a key which is based on a previous code block, and the previous code block is encrypted using a key which is based on a further previous code block, and so forth. If a hacker modifies the program, such as to avoid a message which requires the user to purchase the program, the program will be disabled. The program can also be encrypted based on computer hardware such as a hard disk serial number so that it will only operate on a particular computer. | 2008-10-23 |
20080263367 | DIGITAL CONTENT PROTECTION SYSTEM - The media inherent key storing unit | 2008-10-23 |
20080263368 | COMPUTER SYSTEM, MANAGEMENT TERMINAL, STORAGE SYSTEM AND ENCRYPTION MANAGEMENT METHOD - To provide a computer system in which an encryption-decryption process performed by one encryption-decryption module can be moved to the other encryption-decryption module without stopping the process for a read/write request from a host computer. The computer system has a host computer | 2008-10-23 |
20080263369 | METHOD AND APPARATUS FOR ENCRYPTING AND PROCESSING DATA IN FLASH TRANSLATION LAYER - A method for preventing a user from interpreting optional stored data information even when the user extracts the optional stored data, and an apparatus thereof. The apparatus for encrypting and processing data in a flash translation layer includes a flash memory and a controller. The flash translation layer searches at least one page of the flash memory storing the data when a write of optional data is requested from the controller, generates, corresponding to respective searched pages, a page key according to a predetermined encrypting function when the searched page supports an encryption, and encrypts and stores the data by the page key in the respective searched pages. | 2008-10-23 |
20080263370 | Cryptographic Role-Based Access Control - A hierarchical tree structure is used to facilitate the communication of encrypted keys to particular users having access to the tree. All users are in communication with a root node, but the information content of the material at the root node is decipherable only by the intended users of this information. Protected data is encrypted using a variety of data-keys specific to the data. These data-keys are encrypted using a combination of node-keys that are specific to particular users or groups of users. Users having access to the node-key associated with a particular encrypted data-key are able to decipher the data associated with the data-key; users without access to the particular node-key are unable to decrypt the data-key, and thus unable to decipher the data. The hierarchical tree is preferably structured based on a similarity of access rights among users, to minimize the overhead associated with providing user-specific access rights. | 2008-10-23 |
20080263371 | PROTECTED VOLUME ON A DATA STORAGE DEVICE WITH DUAL OPERATING SYSTEMS AND CONFIGURABLE ACCESS AND ENCRYPTION CONTROLS - A method provides a protected region of a data storage device associated with a computational device, where data in the protected region is primarily protected by preventing access without proper access authorization. The method comprises the steps of providing, in an unprotected region of the data storage device, a first operating system and associated operating system data; monitoring operating system data accessed by the computational device until a predetermined functionality becomes available; storing, in the protected region, the monitored operating system data; providing, in the protected region, a second operating system; transferring control of the computational device from the first operating system to the second operating system; storing data in the protected region; and preventing access to the stored data in the protected region without access authorization. In a further embodiment of the method, the second operating system optionally provides a second level of security by preventing decryption of data stored in the protected region without decryption authorization. | 2008-10-23 |
20080263372 | Method and apparatus for transmitting content data and recording and/or reproducing apparatus - A data transmission method and apparatus for transmitting data, such as encrypted content data. A device that is to be a destination of transmission is authenticated. If the device has not been authenticated, encrypted data read out from a storage unit is decrypted to give decoded data which then is re-encrypted based on innate key data acquired from the device that is to be the destination of transmission to give re-encrypted data. The re-encrypted data is then transmitted to the device that is to be a destination of transmission. | 2008-10-23 |
20080263373 | Token based power control mechanism - A token-based power control mechanism for an apparatus including a power controller and a plurality of processing devices. The power controller may detect a power budget allotted for the apparatus. The power controller may convert the allotted power budget into a plurality of power tokens, each power token being a portion of the allotted power budget. The power controller may then assign one or more of the plurality of power tokens to each of the processing devices. The assigned power tokens may determine the power allotted for each of the processing devices. The power controller may receive one or more requests from the plurality of processing devices for one or more additional power tokens. In response to receiving the requests, the power controller may determine whether to change the distribution of power tokens among the processing devices. | 2008-10-23 |
20080263374 | SYSTEM AND METHOD FOR MODELING A POWER OVER ETHERNET COMPONENT IN A COMPUTING DEVICE PLATFORM USING A COMMON INFORMATION MODEL - A system and method for modeling a power over Ethernet component using a common information model. With the profiling of components based on the common information model, a remote agent can query status/capabilities or configure a power over Ethernet component based on messaging that is consistent with a power over Ethernet common information model schema. | 2008-10-23 |
20080263375 | Method And System For Managing Activities In A Battery Powered Device - A method for managing activities in a battery powered device includes receiving activity information, a start time that is different from a present time, and either a duration or an end time for performing the desired activity. The method also includes determining a required energy amount needed for performing the desired activity, determining an available energy amount for the battery powered device, determining a projected energy consumed by the battery powered device from the present time to the start time, and determining a residual energy of the battery powered device based on a difference of the device's available energy amount and a sum of the required energy and projected energy consumed by the battery powered device from the present time to the start time. An indication is provided that includes information relating to the desired activity and to whether the determined residual energy is sufficient to perform the desired activity. | 2008-10-23 |
20080263376 | Frequency and voltage scaling architecture - A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others. | 2008-10-23 |
20080263377 | METHOD AND APPARATUS FOR ON-DEMAND POWER MANAGEMENT - An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system. | 2008-10-23 |
20080263378 | System and method for protecting disk drive password when bios causes computer to leave suspend state - To unlock a HDD when a computer is in the suspend state, at both BIOS and the HDD a secret is combined with a password to render a new one-time password. BIOS sends its new one-time password to the HDD which unlocks itself only if a match is found. The new one-time password is then saved as an “old” password for subsequent combination with the secret when coming out of subsequent suspend states. In this way, if a computer is stolen the thief cannot sniff the bus between BIOS and the HDD to obtain a password that is of any use once the computer ever re-enters the suspend state. | 2008-10-23 |
20080263379 | WATCHDOG TIMER DEVICE AND METHODS THEREOF - To detect a non-responsive condition at a processor, a counter is associated with an operation at a first stage of an instruction pipeline. A value stored in the counter is periodically adjusted towards a threshold value. An error indicator is provided in response to the value stored in the counter reaching the threshold value thereby indicating that a defined amount of time expired before a subsequent stage has completed processing of the operation. However, if the subsequent stage completes processing of the operation prior to the value stored in the counter reaching the threshold, the counter is automatically disassociated with the operation and can, therefore, be associated with another operation at the first stage of the pipeline. Accordingly, the counter does not use an explicit instruction that is responsible for resetting its value. | 2008-10-23 |
20080263380 | GPS TIME SYNCRONIZATION FOR DATA DEVICE - A method is presented to improve the accuracy of time synchronization of data. The invention consists of a timing module compromising a GPS interface with ability controller-based timing standard, high speed inputs and outputs and an asynchronous interface to an external processor system. It attaches a time-stamp referenced to an absolute time standard to transitions on the high speed inputs and a means for delivering these time stamps referenced to the high speed input to a computer or network. Alternatively the computer or network can specify a high speed output and an absolute time for an output transition and the timing module can deliver the specified output transition at the specified absolute time. Compared to existing systems of time synchronization, it will improve the accuracy of the timed data from the current Ethernet tolerance of up to 5 milliseconds to a possible tolerance of 250 nanoseconds. | 2008-10-23 |
20080263381 | DYNAMIC PHASE ALIGNMENT - A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of the clock signal. A further variation may limit the relative delay period to one-half clock cycle and may use a double inversion of the clock signal. | 2008-10-23 |
20080263382 | METHOD AND APPARATUS FOR ON-DEMAND POWER MANAGEMENT - An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system. | 2008-10-23 |
20080263383 | FREQUENCY MODIFICATION TECHNIQUES THAT ADJUST AN OPERATING FREQUENCY TO COMPENSATE FOR AGING ELECTRONIC COMPONENTS - A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced. | 2008-10-23 |
20080263384 | SYSTEM AND METHOD FOR PRIORITIZATION OF CLOCK RATES IN A MULTI-CORE PROCESSOR - A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval T | 2008-10-23 |
20080263385 | Memory Device with Error Correction Based on Automatic Logic Inversion - A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices. | 2008-10-23 |
20080263386 | DYNAMICALLY REROUTING NODE TRAFFIC ON A MASSIVELY PARALLEL COMPUTER SYSTEM USING HINT BITS - A method and apparatus for dynamically rerouting node processes on the compute nodes of a massively parallel computer system using hint bits to route around failed nodes or congested networks without restarting applications executing on the system. When a node has a failure or there are indications that it may fail, the application software on the system is suspended while the data on the failed node is moved to a backup node. The torus network traffic is routed around the failed node and traffic for the failed node is rerouted to the backup node. The application can then resume operation without restarting from the beginning. | 2008-10-23 |
20080263387 | FAULT RECOVERY ON A PARALLEL COMPUTER SYSTEM WITH A TORUS NETWORK - An apparatus and method for overcoming a torus network failure in a parallel computer system. A mesh routing mechanism in the service node of the computer system configures the nodes from a torus to a mesh network when a failure occurs in the torus network. The mesh routing mechanism takes advantage of cutoff registers in each node to route node to node data transfers around the faulty node or network connection. | 2008-10-23 |
20080263388 | METHOD AND APPARATUS FOR MANAGING CUSTOMER TOPOLOGIES - A method and apparatus for managing customer topologies on packet networks are disclosed. For example, the method creates at least two event correlation instances for at least one customer topology, where a first event correlation instance resides in a primary availability management server, and a second event correlation instance resides in a secondary availability management server. The method also creates a test node for the first event correlation instance, where the test node provides at least one test message. The method then receives at least one response generated by the first event correlation instance that is responsive to the at least one test message, where the at least one response is received by the second event correlation instance. The method then performs a fail-over to the second event correlation instance from the first event correlation instance if a failure is detected from the at least one response. | 2008-10-23 |
20080263389 | SYSTEM FOR MONITORING ENUM PERFORMANCE - A system for monitoring tElephone NUmber Mapping (ENUM) performance is disclosed. A system that incorporates teachings of the present disclosure may include, for example, an ENUM system having a subsystem to monitor one or more operations of the ENUM system, and generate a fault notice responsive to detecting one or more faults in the operations monitored. Additional embodiments are disclosed. | 2008-10-23 |
20080263390 | Cluster system and failover method for cluster system - Even when a large number of guest OSs exist, a failover method meeting high availability needed by the guest OSs is provided for the each guest OS. In the event of a physical or logical change of a system, or change of operation states, a smooth failover method can be realized by preventing the consumption of resource amounts due to excessive failover methods, and the occurrence of systemdown due to an inadequate failover method. In a server virtualization environment, in a cluster configuration having a failover method due to hot standby and cold standby, by selecting a failover method meeting high availability requirements specifying performance during failover of applications on the guest OSs, a suitable cluster configuration is realized. Failure monitoring is realized by quantitative heartbeat. | 2008-10-23 |
20080263391 | Apparatus, System, and Method For Adapter Card Failover - An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure. | 2008-10-23 |