42nd week of 2010 patent applcation highlights part 14 |
Patent application number | Title | Published |
20100264402 | USE OF SACK GEOMETRY TO IMPLEMENT A SINGLE QUBIT PHASE GATE - An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the υ=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two σ-quasiparticles. which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the υ=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a π/8 gate may be effected. | 2010-10-21 |
20100264403 | NANOROD THIN-FILM TRANSITORS - A method for forming an electronic switching device on a substrate, wherein the method comprises depositing the active semiconducting layer of the electronic switching device onto the substrate from a liquid dispersion of ligand-modified colloidal nanorods, and subsequently immersing the substrate into a growth solution to increase the diameter and/or length of the nanorods on the substrate, and wherein the as-deposited nanorods are aligned such that their long-axis is aligned preferentially in the plane of current flow in the electronic switching device. | 2010-10-21 |
20100264404 | ORGANIC ELECTRONIC DEVICE, METHOD FOR PRODUCTION THEREOF, AND ORGANIC SEMICONDUCTOR MOLECULE - An organic electronic device which has stable physical properties and which allows easy production is provided. The organic electronic device has a conductive path including fine particles, a first organic semiconductor molecule which has a first conductive type and binds at least two of the fine particles together, and a second organic semiconductor molecule which has a second conductive type and is captured in a state of noncovalent bond in a molecule recognition site that exists among the fine particles. | 2010-10-21 |
20100264405 | TRANSITION METAL COMPLEXES WITH BRIDGED CARBENE LIGANDS AND USE THEREOF IN OLEDS - Bridged cyclometalated carbene complexes, a process for preparing the bridged cyclometalated carbene complexes, the use of the bridged cyclometalated carbene complexes in organic light-emitting diodes, organic light-emitting diodes comprising at least one inventive bridged cyclometalated carbene complex, a light-emitting layer comprising at least one inventive bridged cyclometalated carbene complex, organic light-emitting diodes comprising at least one inventive light-emitting layer and devices which comprise at least one inventive organic light-emitting diode. | 2010-10-21 |
20100264406 | LIGHT EMITTING DEVICE MATERIAL AND LIGHT EMITTING DEVICE - A light emitting device material containing a pyrromethene compound represented by the general formula (1). It realized a luminescent element having a high luminescent efficiency and excellent color purity. Also provided is a luminescent element employing the materials. | 2010-10-21 |
20100264407 | ORGANIC EL DEVICE - The organic EL device of the present invention includes an anode, a cathode (e.g., an Al layer ( | 2010-10-21 |
20100264408 | Organic Thin Film Transistors, Active Matrix Organic Optical Devices and Methods of Making the Same - A method of manufacturing an organic thin film transistor, comprising: providing a substrate comprising source and drain electrodes defining a channel region; forming a patterned layer of insulting material defining a well surrounding the channel region; depositing a protective layer in the well; subjecting exposed portions of the patterned layer of insulating material to a de-wetting treatment to lower the wettability of the exposed portions; removing the protective layer; and depositing organic semiconductive material from solution into the well. | 2010-10-21 |
20100264409 | MOLECULAR DEVICE, IMAGING DEVICE, PHOTOSENSOR, AND ELECTRONIC APPARATUS - A molecular device includes a gold electrode, cytochrome c552 or a derivative or variant thereof immobilized on the gold electrode, and an electron transfer protein coupled to the cytochrome c552 or the derivative or variant thereof. Electrons or holes, or both, are transferred through the electron transfer protein by transition of electrons between molecular orbitals of the electron transfer protein. | 2010-10-21 |
20100264410 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A method for manufacturing a thin film transistor includes the steps of covering a gate electrode patterned on a substrate with a gate insulating film, forming an organic semiconductor layer and an electrode film on the gate insulating film in that lamination order, and forming a negative type photoresist film on the substrate provided with the organic semiconductor layer and the electrode film and forming a resist pattern, which serves as a mask for forming a source-drain by etching the electrode film, through back surface exposure from the substrate side by using the gate electrode as a light-shielding mask and the following development treatment. | 2010-10-21 |
20100264411 | Oxide Semiconductor Light Emitting Device - There is provided a ZnO based compound semiconductor light emitting device which can emit light with high efficiency and from an entire surface while using ZnO based compound semiconductor which can be expected with higher light emitting efficiency than that of a GaN based compound. On an insulating substrate ( | 2010-10-21 |
20100264412 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a transistor including an oxide layer which includes Zn and does not include a rare metal such as In or Ga. Another object is to reduce an off current and stabilize electric characteristics in the transistor including an oxide layer which includes Zn. A transistor including an oxide layer including Zn is formed by stacking an oxide semiconductor layer including insulating oxide over an oxide layer so that the oxide layer is in contact with a source electrode layer or a drain electrode layer with the oxide semiconductor layer including insulating oxide interposed therebetween, whereby variation in the threshold voltage of the transistor can be reduced and electric characteristics can be stabilized. | 2010-10-21 |
20100264413 | Replacement of Scribeline Padframe with Saw-Friendly Design - An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure. | 2010-10-21 |
20100264414 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING SAME - In the current manufacturing process of LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by the voltage-application test (high-temperature and high-humidity test) in an environment of high temperature (such as an approximate range from 85 to 130° C.) and high humidity (such as about 80% RH). For that test, the inventors of the present invention found the phenomenon of occurrence of separation of titanium nitride film as the anti-reflection film from upper film and of generation of cracks in the titanium nitride film at an edge part of upper surface of the aluminum-based bonding pad applied with a positive voltage during the high-temperature and high-humidity test caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. An invention of the present application is to remove the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad. | 2010-10-21 |
20100264415 | INTERCONNECTING STRUCTURE PRODUCTION METHOD, AND INTERCONNECTING STRUCTURE - An interconnecting structure production method includes providing a substrate, forming a semiconductor layer on the substrate, forming a doped semiconductor layer on the semiconductor layer, the doped semiconductor layer containing a dopant, forming an oxide layer in a surface of the doped semiconductor layer by heating the surface of the doped semiconductor layer in atmosphere of an oxidizing gas with a water molecule contained therein, forming an alloy layer on the oxide layer, and forming an interconnecting layer on the alloy layer. | 2010-10-21 |
20100264416 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - Provided is a crystalline silicon thin film semiconductor device which is capable of reducing off-state leakage current and has excellent current rising characteristics. The thin film transistor includes a semiconductor layer formed of an amorphous silicon layer and a crystalline silicon layer. A drain electrode is provided in direct contact with the crystalline silicon layer of the semiconductor layer, to thereby improve the current rising characteristics. | 2010-10-21 |
20100264417 | THIN-FILM TREANSISTOR ARRAY PANEL AND METHOD OF FABRICATING THE SAME - A thin-film transistor array panel and a manufacturing method thereof are provided for one or more embodiments. The thin-film transistor array panel may include: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode; a source electrode and a drain electrode formed on the gate insulating layer; and a flatness layer formed on the source electrode and the drain electrode, wherein the drain electrode has a higher height than the flatness layer. | 2010-10-21 |
20100264418 | CONTROL SUBSTRATE AND CONTROL SUBSTRATE MANUFACTURING METHOD - A control substrate comprising:
| 2010-10-21 |
20100264419 | FIELD-EFFECT TRANSISTOR - A field-effect transistor includes at least a channel layer, a gate insulating layer, a source electrode, a drain electrode, and a gate electrode, which are formed on a substrate. The channel layer is made of an amorphous oxide material that contains at least In and B, and the amorphous oxide material has an element ratio B/(In+B) of 0.05 or higher and 0.29 or lower. | 2010-10-21 |
20100264420 | Semiconductor Device and Manufacturing Method Thereof - An object is to obtain a semiconductor device with improved characteristics by reducing contact resistance of a semiconductor film with electrodes or wirings, and improving coverage of the semiconductor film and the electrodes or wirings. The present invention relates to a semiconductor device including a gate electrode over a substrate, a gate insulating film over the gate electrode, a first source or drain electrode over the gate insulating film, an island-shaped semiconductor film over the first source or drain electrode, and a second source or drain electrode over the island-shaped semiconductor film and the first source or drain electrode. Further, the second source or drain electrode is in contact with the first source or drain electrode, and the island-shaped semiconductor film is sandwiched between the first source or drain electrode and the second source or drain electrode. Moreover, the present invention relates to a manufacturing method of the semiconductor device. | 2010-10-21 |
20100264421 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - This invention provides a semiconductor device having high operation performance and high reliability. An LDD region | 2010-10-21 |
20100264422 | Thin film semiconductor device, display device using such thin film semiconductor device and manufacturing method thereof - A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors. | 2010-10-21 |
20100264423 | Thinned Semiconductor Components Having Lasered Features And Methods For Fabricating Semiconductor Components Using Back Side Laser Processing - A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness; laser processing the back side of the thinned substrate to form at least one lasered feature on the back side; and dicing the substrate into a plurality of components having the lasered feature. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate. A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate. | 2010-10-21 |
20100264424 | GaN LAYER CONTAINING MULTILAYER SUBSTRATE, PROCESS FOR PRODUCING SAME, AND DEVICE - A GaN layer-containing multilayer substrate employing as a substrate a single crystal that can be made to have a large diameter, a process for producing same, and a device employing the multilayer substrate. The process for producing a multilayer substrate of the present invention includes a germanium growing step of heteroepitaxially growing a germanium layer above a (111) silicon substrate by chemical vapor deposition, a heat treatment step of carrying out a heat treatment of the obtained germanium layer above the silicon substrate in a temperature range of 700° C. to 900° C., and subsequently a GaN growing step of heteroepitaxially growing a GaN layer above the germanium layer. | 2010-10-21 |
20100264425 | TRANSISTORS FOR REPLACING METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS IN NANOELECTRONICS - Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design. | 2010-10-21 |
20100264426 | DIAMOND CAPACITOR BATTERY - In one embodiment, a charge storage device can include: a first node having a plurality of n-type diamond layers connected together; and a second node having a plurality of p-type diamond layers connected together, the plurality of p-type diamond layers being interleaved with the plurality of n-type diamond layers, where each of the plurality of diamond layers is formed using chemical vapor deposition (CVD). | 2010-10-21 |
20100264427 | Bipolar Junction Transistor Guard Ring Structures and Method of Fabricating Thereof - Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer. | 2010-10-21 |
20100264428 | SILICON BIOSENSOR AND METHOD OF MANUFACTURING THE SAME - A silicon biosensor and a method of manufacturing the same are provided. The silicon biosensor includes: a light emitting layer emitting light according to injected electrons and holes and changing a wavelength of the light depending on whether a biomaterial is absorbed by the light emitting layer; an electron injection layer injecting the electrons into the light emitting layer; and a hole injection layer injecting the holes into the light emitting layer. Accordingly, it is possible to produce low price biosensors in large quantities. | 2010-10-21 |
20100264429 | LIGHT EMITTING DEVICE AND ELECTRONIC DEVICE USING THE SAME - A light emitting device and an electronic device using the same are provided. The light emitting device includes a light emitting chip having a wavelength between 460 nm and 650 nm and phosphor powders, in which the phosphor powders can be stimulated by light emitted from the chip to emit light with a wavelength between 700 nm and 1200 nm. The phosphor powders are selected from the group consisting of Cu-doped CdS, Cu-doped SeS, Cu-doped CdTe and combinations thereof. | 2010-10-21 |
20100264430 | ORGANIC LIGHT EMITTING DEVICE - Provided is an organic light emitting device having a simple structure and enabling cost reduction. An organic light emitting device | 2010-10-21 |
20100264431 | YELLOW LIGHT EMITTING DIODE AND LIGHT EMITTING DEVICE HAVING THE SAME - An exemplary yellow light emitting diode (LED) includes a substrate, a LED die, a phosphor layer and an encapsulant. The LED die is arranged on the substrate and comprises an indium gallium aluminum nitride represented by the formula In | 2010-10-21 |
20100264432 | LIGHT EMITTING DEVICE WITH HIGH COLOR RENDERING INDEX AND HIGH LUMINESCENCE EFFICIENCY - A light emitting device comprises two light-emitting diode (LED) groups, a group of luminophor layers, and an input terminal. The first LED group includes at least one blue LED emitting light having a dominant wavelength in a range between 400 nm and 480 nm, and the second LED group includes at least one red-orange LED emitting light having a dominant wavelength in a range between 610 nm and 630 nm. The group of luminophor layers, which are selected from one of silicates, nitrides, and nitrogen oxides, are positioned above the first LED group and partially converts the light emitted by the first LED group into light having a dominant wavelength in a range between 500 nm and 555 nm. The input terminal is connected to the two LED groups for providing desired electric energy thereto. | 2010-10-21 |
20100264433 | SYSTEM FOR DISPLAYING IMAGES - A system for displaying images is provided. The system includes a tandem electroluminescent device having a first electrode. N electroluminescent units are disposed on the first electrode in sequence, wherein N is an integral and not less than | 2010-10-21 |
20100264434 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip is disclosed which emits electromagnetic radiation from its front side ( | 2010-10-21 |
20100264435 | White light-emitting diode package structure for simplifying package process and method for making the same - A white light-emitting diode package structure for simplifying package process includes a substrate unit, a light-emitting unit, a phosphor unit and a conductive unit. The light-emitting unit is disposed on the substrate, and the light-emitting unit has a positive conductive layer and a negative conductive layer. The phosphor unit has a phosphor layer formed on the light-emitting unit and at least two openings for respectively exposing one partial surface of the positive electrode layer and one partial surface of the negative electrode layer. The conductive unit has at least two conductive wires respectively passing through the two openings in order to electrically connect the positive electrode layer with the substrate unit and electrically connect the negative electrode layer with the substrate unit. | 2010-10-21 |
20100264436 | PLCC Package With A Reflector Cup Surrounded By A Single Encapsulant - In an embodiment the invention provides a LFCC package comprising first, second and third lead frames, a light source, and an encapsulant. The first lead frame comprises two tongues and a reflector cup. The first, second and third lead frames are attached to the encapsulant. The light source is mounted at the bottom of the inside of the reflector cup. The light source is electrically connected to the second and third lead frames by wire bonds. The reflector cup is surrounded on at least four sides by the encapsulant, the encapsulant being an integral single piece structure. | 2010-10-21 |
20100264437 | PLCC Package With A Reflector Cup Surrounded By An Encapsulant - In an embodiment, the invention provides a PLCC package comprising first and second lead frames, a plastic structural body, a light source, an encapsulant, and an optical lens. The first lead frame comprises two tongues and a reflector cup. The first and second lead frames are attached to the plastic structural body. The light source is mounted and electrically connected at the bottom of the inside of the reflector cup. The light source is also electrically connected to the second lead frame by a wire bond. The reflector cup is surrounded on at least four sides by the encapsulant, the encapsulant having a domed portion that functions as the optical lens, the encapsulant being an integral single piece structure. | 2010-10-21 |
20100264438 | Light emitting device - The light emitting device has a light emitting element | 2010-10-21 |
20100264439 | LED PACKAGE STRUCTURE - A light emitting diode (LED) package structure includes a substrate having a chip disposal area and a recession, a chip installed in the chip disposal area, a silicon connecting element installed at the recession, and a silicon lens disposed at a position corresponding to the recession and coupled to the silicon connecting element, such that the silicon connecting element in the recession can assure the silicon lens to be secured onto the substrate to prevent the silicon lens from falling out. | 2010-10-21 |
20100264440 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed are a semiconductor light emitting device. The semiconductor light emitting device comprises a light emitting structure comprising a IH-V group compound semiconductor, a reflective layer comprising mediums, which are different from each other and alternately stacked under the light emitting structure, and a second electrode layer under the reflective layer. | 2010-10-21 |
20100264441 | LIGHT EMITTING ELEMENT AND FABRICATING METHOD THEREOF - The light emitting element includes a substrate; a first block pattern formed on the substrate; a light emitter including a first semiconductor pattern of a first conductivity type, a light emitting pattern, and a second semiconductor pattern of a second conductivity type, sequentially stacked on the substrate having the first block pattern formed thereon, the light emitter having a first portion formed on the first block pattern, and a second portion formed between two adjacent first block patterns, the second portion formed lower than the first portion to define a recessed region, and a second block pattern formed on the light emitter to fill the recessed region. | 2010-10-21 |
20100264442 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a vertical-type light emitting device and a method of manufacturing the same. The light emitting device includes a p-type semiconductor layer, an active layer, and an n-type semi-conductor layer that are stacked, a cover layer disposed on a p-type electrode layer to surround the p-type electrode layer, a conductive support layer disposed on the cover layer, and an n-type electrode layer disposed on the n-type semiconductor layer. | 2010-10-21 |
20100264443 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device having high reliability and excellent light distribution characteristics is provided. Specifically, a semiconductor light emitting device | 2010-10-21 |
20100264444 | LED AND METHOD OF MANUFACTURING THE SAME - An LED can include a pair of electrode members, and an LED chip joined to a chip mount portion disposed at the extremity of one of the pair of electrode members. The LED chip can be electrically connected to the pair of electrode members. A transparent resin portion can include a wavelength conversion material mixed therein, the transparent resin portion formed in such a manner as to surround the LED chip, wherein the LED chip is positioned offset toward one side in the transparent resin portion, and wherein the wavelength conversion material mixed in the transparent resin portion has a higher density around the LED chip within the transparent resin portion. | 2010-10-21 |
20100264445 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate. | 2010-10-21 |
20100264446 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate. | 2010-10-21 |
20100264447 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate. | 2010-10-21 |
20100264448 | LIGHT EMTTING DEVICE - Disclosed herein is a light emitting device. The light emitting device includes a light emitting diode disposed on a substrate to emit light of a first wavelength. A transparent molding part encloses the LED, a lower wavelength conversion material layer is disposed on the transparent molding part, and an upper wavelength conversion material layer is disposed on the lower wavelength conversion material layer. The lower wavelength conversion material layer contains a phosphor converting the light of the first wavelength into light of a second wavelength longer than the first wavelength, and the upper wavelength conversion material layer contains a phosphor converting the light of the first wavelength into light of a third wavelength, which is longer than the first wavelength but shorter than the second wavelength. Light produced via wavelength conversion is prevented from being lost by the phosphor. Light emitting devices including a multilayer reflection mirror are also disclosed. | 2010-10-21 |
20100264449 | LIGHT EMITTING APPARATUS - A light emitting apparatus includes a light emitting device mounted on a base. First and second leads are electrically connected to the light emitting device. A first resin molding member formed of thermosetting resin covers at least partially the base and the first and second leads so that the first resin molding member is formed integrally with the base and the first and second leads. A second resin molding member formed of thermosetting resin is in contact with at least a part of the first resin molding member and covers the light emitting device. A recessed portion is formed in the first resin molding member on a light emitting device mount surface side of the base to open upward and to have a side surface. A protection device is mounted on the first lead or the second lead. The protection device is covered by the first resin molding member. | 2010-10-21 |
20100264450 | LIGHT SOURCE - Embodiments of a light source are disclosed herein. An embodiment of the light source comprises a first terminal and a second terminal. The first terminal comprises a first terminal first portion and a first terminal second portion, wherein at least a portion of the first terminal second portion is located on a first plane, the first terminal second portion comprising at least two contacts separated by a space. A second terminal comprises a second terminal first portion and a second terminal second portion. The second terminal first portion is located proximate the first terminal first portion. The second terminal second portion is located substantially on the first plane and in the space. A light emitter is affixed to the first terminal first portion, the light emitter is electrically connected to the first terminal first portion. A connection exists between the light emitter and the second terminal first portion. | 2010-10-21 |
20100264451 | Light Emitting Diode with High Power - A light emitting diode includes a base, a dispersing member, a chip, a pole, a cover, an electrode, and a lens. The base is capable of conducting heat and insulated from electricity. The base has a first surface and a second surface opposite to the first surface. The dispersing member is disposed on a first surface of the base. The chip is disposed on a second surface of the base. The pole runs through the base, and two ends of the pole are connected to the dispersing member and the chip correspondingly. The cover to allow light to run therethrough is disposed on the second surface of the base and covers the chip. The electrode is disposed on the second surface the base and electrically connected to a circuit inside the base. The circuit electrically connected to the chip. The lens seals the cover. | 2010-10-21 |
20100264452 | Methods for high temperature processing of epitaxial chips - High temperature semiconducting materials in a freestanding epitaxial chip enables the use of high temperature interconnect and bonding materials. Process materials can be used which cure, fire, braze, or melt at temperatures greater than 400 degrees C. These include, but are not limited to, brazing alloys, laser welding, high-temperature ceramics and glasses. High temperature interconnect and bonding materials can additionally exhibit an index of refraction intermediate to that of the freestanding epitaxial chip and its surrounding matrix. High index, low melting point glasses provide a hermetic seal of the semiconductor device and also index match the freestanding epitaxial chip thereby increasing extraction efficiency. In this manner, a variety of organic free semiconducting devices, such as solid-sate lighting sources, can be created which exhibit superior life, efficiency, and environmental stability. | 2010-10-21 |
20100264453 | SEMICONDUCTOR CHIP PAD STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor chip pad structure and a method for manufacturing the same, wherein a flat area at the center of the terminal pad and a roughened area at the periphery thereof are provided by use of the mask photolithograph technique and the roughening process. The central area provides a sufficient adhering force for the ball bond while the peripheral area prevents the wire-bonding vibrating energy from the lateral transmission to the external side of the terminal pad. In this way, the ball bond for the terminal pad may meet the wire-bonding requirements. Moreover, the ball bond quality is ensured. | 2010-10-21 |
20100264454 | SEMICONDUCTOR LIGHT EMITTING DEVICE GROWING ACTIVE LAYER ON TEXTURED SURFACE - In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface. | 2010-10-21 |
20100264455 | SEMICONDUCTOR DEVICE - On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed. | 2010-10-21 |
20100264456 | Capacitor Structure in Trench Structures of Semiconductor Devices and Semiconductor Devices Comprising Capacitor Structures of this Type and Methods for Fabricating the Same - A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor device. | 2010-10-21 |
20100264457 | ELECTROSTATIC DISCHARGE PROTECTION - An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) having a first voltage potential, a first power supply potential and a second power supply potential. The ESD circuit includes a first NPN bipolar transistor having a first N-doped junction, a second N-doped junction and a third P-doped base junction. The first N-doped junction is coupled to the first voltage potential and the second N-doped junction is coupled to the first power supply potential. The ESD circuit also includes a first PNP bipolar transistor having a first P-doped junction, a second P-doped junction and a third N-doped base junction. The first P-doped junction is coupled to the first voltage potential and the second P-doped junction is coupled to the second power supply potential. The third P-doped base junction of the first NPN bipolar transistor is coupled to the third N-doped base junction of the first PNP bipolar transistor. | 2010-10-21 |
20100264458 | METHOD FOR MANUFACTURING HETEROSTRUCTURES - A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure. | 2010-10-21 |
20100264459 | Infrared sensor IC, and infrared sensor and manufacturing method thereof - An infrared sensor IC and an infrared sensor, which are extremely small and are not easily affected by electromagnetic noise and thermal fluctuation, and a manufacturing method thereof are provided. A compound semiconductor that has a small device resistance and a large electron mobility is used for a sensor ( | 2010-10-21 |
20100264460 | THICK PSEUDOMORPHIC NITRIDE EPITAXIAL LAYERS - In various embodiments, a semiconductor device includes an aluminum nitride single-crystal substrate, a pseudomorphic strained layer disposed thereover that comprises at least one of AlN, GaN, InN, or an alloy thereof, and, disposed over the strained layer, a semiconductor layer that is lattice-mismatched to the substrate and substantially relaxed. | 2010-10-21 |
20100264461 | N-polar aluminum gallium nitride/gallium nitride enhancement-mode field effect transistor - A novel enhancement mode field effect transistor (FET), such as a High Electron Mobility Transistors (HEMT), has an N-polar surface uses polarization fields to reduce the electron population under the gate in the N-polar orientation, has improved dispersion suppression, and low gate leakage. | 2010-10-21 |
20100264462 | SEMICONDUCTOR INCLUDING LATERAL HEMT - A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer. | 2010-10-21 |
20100264463 | SEMICONDUCTOR HETEROSTRUCTURE AND METHOD FOR FORMING SAME - The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a | 2010-10-21 |
20100264464 | IMAGE SENSOR PHOTODIODE ARRANGEMENT - The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a surface of the photodiode are discharged to the power voltage terminal through the channel. | 2010-10-21 |
20100264465 | SRAM Cell with Different Crystal Orientation than Associated Logic - An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation. | 2010-10-21 |
20100264466 | GATE SELF-ALIGNED LOW NOISE JFET - The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation. | 2010-10-21 |
20100264467 | TRANSISTOR COMPONENT HAVING A SHIELDING STRUCTURE - A transistor component having a shielding structure. One embodiment provides a source terminal, a drain terminal and control terminal. A source zone of a first conductivity type is connected to the source terminal. A drain zone of the first conductivity type is connected to the drain terminal. A drift zone is arranged between the source zone and the drain zone. A junction control structure is provided for controlling a junction zone in the drift zone between the drain zone and the source zone, at least including one control zone. A shielding structure is arranged in the drift zone between the junction control structure and the drain zone and at least includes a shielding zone of a second conductivity type being complementarily to the first conductivity type. The shielding zone is connected to a terminal for a shielding potential. The at least one control zone and the at least one shielding zone have different geometries or different orientations in a plain that is perpendicular to a current flow direction of the component. | 2010-10-21 |
20100264468 | Method Of Fabrication Of A FinFET Element - The present disclosure provides a FinFET element and method of fabricating a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, the method of fabrication the Ge-FinFET element includes forming silicon fins on a substrate and selectively growing an epitaxial layer including germanium on the silicon fins. A Ge-condensation process may then be used to selectively oxidize the silicon of the Si-fin and transform the Si-fin to a Ge-fin. The method of fabrication provided may allow use of SOI substrate or bulk silicon substrates, and CMOS-compatible processes to form the Ge-FinFET element. | 2010-10-21 |
20100264469 | MOSFET INCLUDING EPITAXIAL HALO REGION - A metal oxide semiconductor field effect transistor structure and a method for fabricating the metal oxide semiconductor field effect transistor structure provide for a halo region that is physically separated from a gate dielectric. The structure and the method also provide for a halo region aperture formed horizontally and crystallographically specifically within a channel region pedestal within the metal oxide semiconductor field effect transistor structure. The halo region aperture is filled with a halo region formed using an epitaxial method, thus the halo region may be formed physically separated from the gate dielectric. As a result, performance of the metal oxide semiconductor field effect transistor is enhanced. | 2010-10-21 |
20100264470 | NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME - NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer. | 2010-10-21 |
20100264471 | Enhancing MOSFET performance with stressed wedges - The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located above the gate structure or at or near the source and drain regions. Specifically, a dielectric layer in on the MOSFET and at least one stress-inducing wedge is pressed into the dielectric layer to induce a stress in the channel of the MOSFET. The at least one stress-inducing wedge is located above the gate of an n-channel MOSFET (nMOSFET) and the at least one stress-inducing wedge is located in or near the source and drain regions, but not above the gate of a p-channel MOSFET (pMOSFET). The former creates tensile stress in the channel of an nMOSFET and then enhance the performance of the nMOSFET. The latter produces compressive stress in the channel of a pMOSFET and then enhance the performance of the pMOSFET. | 2010-10-21 |
20100264472 | PATTERNING METHOD, AND FIELD EFFECT TRANSISTORS - A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor. | 2010-10-21 |
20100264473 | ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 2010-10-21 |
20100264474 | SOLID-STATE IMAGE PICKUP DEVICE, ELECTRONIC APPARATUS USING SUCH SOLID-STATE IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE - A back-illuminated type solid-state image pickup device ( | 2010-10-21 |
20100264475 | MAGNETIC TUNNEL JUNCTION TRANSISTOR - A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least partially, between the source electrode and the drain electrode. The magnetoelectric region of the insulating material, when energized, is configured to change magnetic state of the insulating material. The gate electrode is positioned proximate the magnetoelectric region of the insulating material. | 2010-10-21 |
20100264476 | FERROELECTRIC MEMORY AND ITS MANUFACTURING METHOD - To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer | 2010-10-21 |
20100264477 | Semiconductor Devices - Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device is implanted with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the second implantation process is different than the first implantation process. | 2010-10-21 |
20100264478 | METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE - A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material. | 2010-10-21 |
20100264479 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory. | 2010-10-21 |
20100264480 | USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line. | 2010-10-21 |
20100264481 | Nonvolatile Memory Devices and Related Methods - Nonvolatile memory devices and methods of fabricating the same are provided. A semiconductor substrate is provided having a cell field region and a high-voltage field region. Device isolation films are provided on the substrate. The device isolation films define active regions of the substrate. A cell gate-insulation film and a cell gate-conductive film are provided on the cell field region of the substrate including the device isolation films. A high-voltage gate-insulation film and a high-voltage gate-conductive film are provided on the high-voltage field region of the substrate including the device isolation films. The device isolation film on the high-voltage field region of the substrate is at least partially recessed to provide a groove therein. | 2010-10-21 |
20100264482 | MEMORY CELLS CONFIGURED TO ALLOW FOR ERASURE BY ENHANCED F-N TUNNELING OF HOLES FROM A CONTROL GATE TO A CHARGE TRAPPING MATERIAL - Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material. | 2010-10-21 |
20100264483 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor storage device and method of manufacturing same at a lower cost by without forming a photolithographic resist. Second impurity regions are arranged in such a manner that second impurity regions adjacent along the column direction are joined together. A select gate electrode is arranged into a ring shape so as to surround the second impurity regions, and is electrically connected to a word line. A first control gate electrode is arranged into a ring shape on the outer peripheral side of the select gate electrode, and a second control gate electrode is arranged into a ring shape on the inner peripheral side of the select gate electrode. A pair of first and second bit lines corresponding to every row are placed on the memory cells of the device, a first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction, and a second bit line is electrically connected to the other of the first impurity regions that are adjacent along the row direction. | 2010-10-21 |
20100264484 | SEMICONDUCTOR DEVICE - In a vertical transistor comprising a pillar-shaped semiconductor layer and a gate electrode formed to around the pillar-shaped semiconductor layer, it is difficult to form a transistor having a gate length greater than that of the vertical transistor. The present invention provides a semiconductor device which comprises two vertical transistors comprising first and second pillar-shaped semiconductor layers each formed on a first diffusion layer on a substrate. The vertical transistors have a common gate electrode. A first upper diffusion layer formed on a top of the first pillar-shaped semiconductor layer is connected to a source electrode, and a second upper diffusion layer formed on a top of the second pillar-shaped semiconductor layer is connected to a drain electrode. The vertical transistors are connected in series to operate as a composite transistor having a gate length two times greater than that of each of the vertical transistors. | 2010-10-21 |
20100264485 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a first semiconductor layer of a second conductive type in a lower portion of the first columnar semiconductor layer; forming a first insulating film around a lower sidewall of the first columnar silicon layer; forming a gate insulating film and a gate electrode around the first columnar silicon layer; forming a sidewall-shaped second insulating film to surround an upper sidewall of the first columnar silicon layer; forming a semiconductor layer of a first conductive type between the first semiconductor layer of the second conductive type and a second semiconductor layer of the second conductive type; and forming a metal-semiconductor compound on an upper surface of the first semiconductor layer of the second conductive type. | 2010-10-21 |
20100264486 | FIELD PLATE TRENCH MOSFET TRANSISTOR WITH GRADED DIELECTRIC LINER THICKNESS - An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region. | 2010-10-21 |
20100264487 | Method of Manufacturing a Trench Transistor Having a Heavy Body Region - A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body. | 2010-10-21 |
20100264488 | Low Qgd trench MOSFET integrated with schottky rectifier - An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trench gates sidewalls for reducing Qgd; a source dopant region disposed below a bottom surface of all trench gates for functioning as a current path for preventing a resistance increased caused by the body dopant regions. | 2010-10-21 |
20100264489 | SEMICONDUCTOR DEVICE - A transistor contains a first semiconductor layer of a first conductivity type and a drift layer having a pillar structure in which a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type are alternately disposed in a direction parallel to a surface of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type and the fifth semiconductor layer of the second conductivity type are alternately disposed and parallel to the drift layer. The fifth semiconductor layer has a larger amount of impurities than the fourth semiconductor layer. The sixth semiconductor layer of the first conductivity type and the seventh semiconductor layer of the second conductivity type are alternately disposed and parallel to the fourth and the fifth semiconductor layers. The seventh semiconductor layer has a smaller amount of impurities than the sixth semiconductor layer. | 2010-10-21 |
20100264490 | LDMOS WITH SELF ALIGNED VERTICAL LDD BACKSIDE DRAIN - A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region. | 2010-10-21 |
20100264491 | HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE AND HIGH VOLTAGE INTEGRATED CIRCUIT - A high breakdown voltage semiconductor device, in which a semiconductor layer is formed on a semiconductor substrate across a dielectric layer, includes a drain layer on the semiconductor layer, a buffer layer formed so as to envelop the drain layer, a source layer, separated from the drain layer, and formed so as to surround a periphery thereof, a well layer formed so as to envelop the source layer, and a gate electrode formed across a gate insulating film on the semiconductor layer, wherein the planar shape of the drain layer | 2010-10-21 |
20100264492 | Semiconductor on Insulator Semiconductor Device and Method of Manufacture - A semiconductor on insulator semiconductor device has metal or silicide source and drain contact regions ( | 2010-10-21 |
20100264493 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device which includes a P-type Si substrate, an ESD protection element, and a protected element. The ESD protection element includes a source N-type diffusion region, and a high-concentration P-type diffusion region formed from under the source N-type diffusion region to at least under part of a gate electrode, covering the source N-type diffusion region within the P-type Si substrate, and having a higher P-type impurity concentration than the P-type Si substrate. The protected element includes a drain N-type diffusion region, and a low-concentration P-type diffusion region that is in contact with the drain N-type diffusion region within the P-type Si substrate. The drain electrode of the ESD protection element and the drain electrode of the protected element are connected, and the high-concentration P-type diffusion region | 2010-10-21 |
20100264494 | RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION - Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure. | 2010-10-21 |
20100264495 | High-K Metal Gate CMOS - A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal. | 2010-10-21 |
20100264496 | SRAM MEMORY CELL PROVIDED WITH TRANSISTORS HAVING A VERTICAL MULTICHANNEL STRUCTURE - A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k≧1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate. | 2010-10-21 |
20100264497 | Multiple Vt Field-Effect Transistor Devices - Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate. | 2010-10-21 |
20100264498 | MANUFACTURING A MEMS ELEMENT HAVING CANTILEVER AND CAVITY ON A SUBSTRATE - Method for manufacturing a capacitor on a substrate, the capacitor including a first electrode ( | 2010-10-21 |
20100264499 | MEMS DEVICE AND METHOD OF FABRICATING THE SAME - A MEMS device includes a chip carrier having an acoustic port extending from a first surface to a second surface of the chip carrier, a MEMS die disposed on the chip carrier to cover the acoustic port at the first surface of the chip carrier, and an enclosure bonded to the chip carrier and encapsulating the MEMS die. | 2010-10-21 |
20100264500 | METHOD OF FABRICATING STRUCTURES - A method of processing a stack, the method including depositing a fusible material on a first hardmask layer, the first hardmask layer disposed on a surface of a pre-processed stack, the pre-processed stack being disposed on at least a portion of a substrate; heating the fusible material layer to a temperature at or above its melting point to cause it to form a fusible material sphere, the fusible material sphere disposed on less than the entire first hardmask layer; etching the first hardmask layer, wherein the fusible material sphere prevents a portion of the first hardmask layer from etching, thereby forming a second hardmask layer; and etching the pre-processed stack, wherein at least the second hardmask layer prevents a portion of the pre-processed stack from etching, thereby forming a stack. | 2010-10-21 |
20100264501 | METHOD FOR MANUFACTURING MAGNETIC STORAGE DEVICE AND MAGNETIC STORAGE DEVICE - Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode. Also disclosed is a magnetic storage device comprising an interlayer insulating film provided with a wiring layer, an insulating film formed on the interlayer insulating film, an opening formed in the insulating film so that the wiring layer is exposed therefrom, a barrier metal layer provided so as to cover the inner surface of the opening, a lower electrode formed on the barrier metal so as to fill the opening, and a TMR element formed on the lower electrode. | 2010-10-21 |