| 42nd week of 2011 patent applcation highlights part 42 |
| Patent application number | Title | Published |
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| 20110256634 | SENSOR MEASURING METHOD AND SENSING APPARATUS - A method of performing a measurement with a sensor having a sensing surface and at least one capture molecule attached to the sensing surface for forming a binding pair with an analyte of interest, the binding pair having a flexible spatial orientation, the method comprising capturing the analyte of interest with the capture molecule, thereby forming the binding pair in an initial spatial orientation; applying a first electromagnetic force to the sensing surface to alter the spatial orientation of the binding pair; and performing a sensor measurement with the binding pair in the altered spatial orientation. A sensor apparatus implementing this method is also disclosed. | 2011-10-20 |
| 20110256635 | SOLUBLE HUMAN ST-2 ANTIBODIES AND ASSAYS - Provided herein are antibodies and antigen-binding antibody fragments that bind to human soluble Growth Stimulation-Expressed Gene 2 (ST2) protein, kits containing these antibodies and antibody fragments, and methods of using these antibodies and antibody fragments. | 2011-10-20 |
| 20110256636 | METHODS AND REAGENTS FOR DIAGNOSING RHEUMATOID ARTHRTIS - Methods for diagnosing rheumatoid arthritis (RA) are disclosed, using measurement of the CCL8 protein level in a test sample from a subject. Testing for CCL8 as an indicator of RA can be combined with testing for other indicators of RA, including clinical assessments, imaging or other RA markers such as Rheumatoid factor (RF). CCL8 testing can be used for discriminating RA from other diseases or conditions, evaluating the severity of RA. Related diagnostic reagents, kits, pharmaceutical compositions, and methods for identifying a candidate substance as a therapeutic agent for treating rheumatoid arthritis are also described. | 2011-10-20 |
| 20110256637 | Target Detection Using a Single-Stranded, Self-Complementary, Triple-Stem DNA Probe - Provided are novel single-stranded oligonucleotide probes that have a triple-stem configuration in the absence of target binding to the target binding sequence. The probes also have a fluorophore and a quencher. In the absence of target binding to the target binding sequence, these single-stranded oligonucleotide probes are capable of forming self-complementary duplexes such that the probe is in the triple-stem configuration and the fluorophore is positioned adjacent the quencher. In the presence of target binding to the target binding sequence, formation of the self-complementary duplexes is inhibited such that the probe is configured to position the fluorophore away from the quencher such that a signal of the fluorophore is detectable. Also provided are methods of using the probes. | 2011-10-20 |
| 20110256638 | DOWNWARD OR VERTICAL FLOW DIAGNOSTIC DEVICE AND ASSAY - A downward or vertical flow-through rapid diagnostic device and assay are provided. The device comprises a test area and reagent storage area, which are linked via a channel. The test area further comprises a reaction zone and an absorbent zone. A capture reagent is immobilized on the reaction zone to detect a target analyte in the fluid test sample. The fluid test sample flows downward or vertically through the reaction zone and into the absorbent zone, with the capture reagent and target analyte forming a two-membered complex that is concentrated in the reaction zone. The reagent storage area comprises a breakable cartridge positioned directly and vertically above the test area and a channel. A reagent used in the assay is housed in the breakable cartridge. Once liberated, the reagent passes through the channel and flows to test area for depositing on the reaction zone. The storage of predetermined amounts of reagents in the diagnostic device reduces the number of manual operations required to produce a result. | 2011-10-20 |
| 20110256639 | ASSESSMENT OF PROTEIN DEGRADATION BY MEASUREMENT OF ISOMERISED NEO-EPITOPE CONTAINING FRAGMENTS - A method of immunoassay for fragments of a protein such as type II collagen in a biological sample detects fragments having a first epitope containing an isomerised amino acid residue and a second epitope generated by cleavage of the protein by the use of respective antibodies binding each of the two epitopes. | 2011-10-20 |
| 20110256640 | ASSAY FOR TROPONIN I USING MAGNETIC LABELS - The present invention relates to a method for measuring Troponin I in a sample comprising the steps of providing a sample, contacting the sample with a monoclonal anti-Troponin I antibody coupled to a magnetic label, contacting the sample with a polyclonal anti-Troponin I antibody coupled to a sensor surface and detecting the magnetic label on the sensor surface. The invention further relates to a device and a cartridge for measuring Troponin I in a sample. | 2011-10-20 |
| 20110256641 | Methods and Systems for Detecting Free IgE - The present disclosure provides methods, systems, and kits for detecting IgE antibodies available to bind to the Fc epsilon receptor in a biological sample from a subject receiving anti-IgE therapy. These methods, systems, and kits find use in monitoring anti-IgE therapy and determining its efficacy. | 2011-10-20 |
| 20110256642 | MANUFACTURING METHOD OF MAGNETO-RESISTANCE EFFECT ELEMENT - The present invention provides a manufacturing method of a magneto-resistance effect element, in which the step coverage of a formed film can be enlarged and also the film can be deposited in a low temperature range. In an embodiment of the present invention, an insulating protective layer is formed on a multilayered structure by a plasma CVD apparatus in which a plasma source and a film deposition chamber are separated from each other by a partition wall plate. According to the present method, it is possible to deposit the protective layer without inviting the degradation of a magnetic characteristic and also to perform low temperature film deposition even at a temperature lower than 150° C. Hence, it is possible to deposit the protective layer while leaving resist and also to reduce the number of steps in the manufacturing of the magneto-resistance effect element having a multilayered structure. | 2011-10-20 |
| 20110256643 | METHOD FOR DETACHING LAYERS WITH LOW MAGNETIC PERMEABILITY - A method for detaching a first material layer from a second material layer includes following steps: forming a high-magnetic-permeability material layer on a first material layer comprised of low-magnetic-permeability material; removing a portion of the high-magnetic-permeability material layer to expose a portion of the first material layer; epitaxially growing a second material layer comprised of low-magnetic-permeability material on the exposed portion of the first material layer and the high-magnetic-permeability material layer; cooling the first and second material layers; heating the high-magnetic-permeability material layer, thus detaching the first material layer from the second material layer. | 2011-10-20 |
| 20110256644 | MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS - Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone. | 2011-10-20 |
| 20110256645 | MULTIPLE PRECURSOR SHOWERHEAD WITH BY-PASS PORTS - A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, the apparatus a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. In one embodiment, the showerhead includes one or more cleaning gas conduits configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. In one embodiment, the showerhead includes a plurality of metrology ports configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. As a result, the processing chamber components can be cleaned more efficiently and effectively than by introducing cleaning gas into the chamber only through the processing gas channels. | 2011-10-20 |
| 20110256646 | METHOD FOR MANUFACTURING LED PACKAGE AND SUBSTRATE THEREOF - In a method for manufacturing a LED package, a substrate of the LED package is formed by thermally pressing at least one insulating plate over an electrode plate and then grinding the insulating plates to expose the electrode plate. | 2011-10-20 |
| 20110256647 | METHODS OF MANUFACTURING ELONGATED LENSES FOR USE IN LIGHT EMITTING APPARATUSES - A method of manufacturing an elongated lens for a light emitting apparatus includes forming an elongated lens having an exterior surface, and applying a photoluminescent material to the exterior surface of the lens. | 2011-10-20 |
| 20110256648 | Method of Making Double-sided Wavelength Converter and Light Generating Device Using Same - A method of forming a light conversion element includes providing a semiconductor construction having a first photoluminescent element epitaxially grown together with a second photoluminescent element. A first region is etched in the first photoluminescent element from a first side of the semiconductor construction and a second region is etched in the second photoluminescent element from a second side of the semiconductor construction. In some embodiments the wavelength converter is attached to an electroluminescent element, such as a light emitting diode (LED). | 2011-10-20 |
| 20110256649 | PIXEL PERFORMANCE IMPROVEMENT BY USE OF A FIELD SHIELD - A pixel cell ( | 2011-10-20 |
| 20110256650 | ELECTRO-OPTICAL DEVICE AND AN ELECTRONIC APPARATUS - An electro-optical device that drives each of plural pixels individually arranged in two dimensions so as to display information, is provided with a group of pixels displaying the information within an effective display region among the plural pixels arranged in two dimensions. A group of plural pseudo-pixels that do not contribute to the display of the information are located adjacent to a group of pixels within the effective display region. A bank layer separates a pixel in the group of the plural pseudo-pixels from a pixel in the group of pixels in the effective display region, and shields light leaked from a space between pixels located adjacently each other within the effective display region. | 2011-10-20 |
| 20110256651 | METHOD FOR FABRICATING LIGHT-EMITTING DEVICES WITH VERTICAL LIGHT-EXTRACTION MECHANISM - A light-emitting device comprises a lattice structure to minimize the horizontal waveguide effect by reducing light traveling distance in the light-absorption medium of the light-emitting devices, and to enhance light extraction from the light-emitting layer. The lattice structure includes sidewalls and/or rods embedded in the light-absorption medium and dividing the light-absorption medium into a plurality of area units. The area units are completely isolated or partially separated from each other by the sidewalls. Also provided is a method of fabricating a light-emitting device that comprises a lattice structure, which lattice structure includes sidewalls and/or rods embedded in the light-absorption medium and dividing the light-absorption medium into a plurality of area units. | 2011-10-20 |
| 20110256652 | METHOD FOR FORMING A TRANSDUCER - A method for forming a transducer including the step of providing a semiconductor-on-insulator wafer including first and second semiconductor layers separated by an electrically insulating layer, wherein the first layer is formed or provided by hydrogen ion delamination of a starting wafer. The method further includes doping the first layer to form a piezoresistive film and etching the piezoresistive film to form at least one piezoresistor. The method also includes depositing or growing a metallization layer on the semiconductor-on-insulator wafer, the metallization layer including an electrical connection portion that is located on or is electrically coupled to the piezoresistor. The method includes removing at least part of the second semiconductor layer to form a diaphragm, with the at least part of the piezoresistor being located on the diaphragm, and joining the wafer to a package by melting a high temperature braze material or a glass frit material. | 2011-10-20 |
| 20110256653 | Thermoelectric Modules and Methods for Manufacturing Thermoelectric Modules - A method for manufacturing a thermoelectric module that involves obtaining a first printed circuit board having a first dielectric layer sandwiched between a first metallic substrate and a first electrical conductive layer, obtaining a second printed circuit board that comprises a second dielectric layer sandwiched between a second metallic substrate and a second electrical conductive layer, and positioning a plurality of N-type and P-type thermoelectric elements having first ends and second ends between the first and second electrical conduction layers so that the first ends of the thermoelectric elements are situated on the first electrical conductive layer and the second ends of the thermoelectric elements are situated on the second electrical conductive layer and arranged to form an electrical circuit that alternates between the N-type and P-type thermoelectric elements. | 2011-10-20 |
| 20110256654 | DOUBLE-SIDED REUSABLE TEMPLATE FOR FABRICATION OF SEMICONDUCTOR SUBSTRATES FOR PHOTOVOLTAIC CELL AND MICROELECTRONICS DEVICE MANUFACTURING - This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles. | 2011-10-20 |
| 20110256655 | LOW VOLTAGE LOW LIGHT IMAGER AND PHOTODETECTOR - Highly efficient, low energy, low light level imagers and photodetectors are provided. In particular, a novel class of Della-Doped Electron Bombarded Array (DDEBA) photodetectors that will reduce the size, mass, power, complexity, and cost of conventional imaging systems while improving performance by using a thinned imager that is capable of detecting low-energy electrons, has high gain, and is of low noise. | 2011-10-20 |
| 20110256656 | Chemical Bath Deposition Apparatus for Fabrication of Semiconductor Films through Roll-to-Roll Processes - A chemical bath deposition method and a system are presented to prepare different thin films on continuous flexible substrates in roll-to-roll processes. In particular, they are useful to deposit CdS or ZnS buffer layers in manufacture of thin film solar cells. This method and the deposition system deposit thin films onto vertically travelling continuous flexible workpieces delivered by a roll-to-roll system. The thin films are deposited with continuously spraying the reaction solutions from their freshly mixed styles to gradually aged forms until the designed thickness is obtained. The substrates and the solutions are heated to a reaction temperature. During the deposition processes, the front surfaces of the flexible substrates are totally covered with the sprayed solutions but the substrate backsides are remained dry. The reaction ambience inside the reactor can be isolated from the outside atmosphere. The apparatus is designed to generate a minimum amount of waste solutions for chemical treatments. | 2011-10-20 |
| 20110256657 | METHOD OF ENCAPSULATING PHOTOVOLTAIC PANEL - Melted encapsulant is extruded directly onto the photovoltaic panel to encapsulate a photovoltaic panel. | 2011-10-20 |
| 20110256658 | METHOD FOR PRODUCING PHOTOVOLTAIC CELL - In a method for producing a photovoltaic cell, the improvement comprising:
| 2011-10-20 |
| 20110256659 | METHOD FOR MANUFACTURING SOLAR CELL, ETCHING DEVICE, AND CVD DEVICE - A solar cell manufacturing method according to the present invention is a solar cell manufacturing method that forms a transparent conductive film of ZnO as an electric power extracting electrode on a light incident side, the method comprises at least in a following order: a process A forming the transparent conductive film on a substrate by applying a sputtering voltage to sputter a target made of a film formation material for the transparent conductive film; a process B forming a texture on a surface of the transparent conductive film; a process C cleaning the surface of the transparent conductive film on which the texture has been formed using an UV/ozone; and a process D forming an electric power generation layer on the transparent conductive film. | 2011-10-20 |
| 20110256660 | METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A method of manufacturing a photoelectric conversion device, comprises forming a first insulating film on a semiconductor substrate, forming a gate electrode by forming an electrically conductive layer on the first insulating film and patterning the electrically conductive layer, etching an exposed surface of the first insulating film, forming a charge accumulation region of a photoelectric converter by implanting impurity ions of a first conductivity type into the semiconductor substrate through a thinned portion of the first insulating film formed by the etching, removing the thinned portion, forming a second insulating film covering the semiconductor substrate and the gate electrode, and forming a surface region of the photoelectric converter by implanting impurity ions of a second conductivity type opposite to the first conductivity type into the semiconductor substrate through the second insulating film. | 2011-10-20 |
| 20110256661 | Method for Improved Patterning Accuracy for Thin Film Photovoltaic Panels - A method for patterning a thin film photovoltaic panel on a substrate characterized by a compaction parameter. The method includes forming molybdenum material overlying the substrate and forming a first plurality of patterns in the molybdenum material to configure a first patterned structure having a first inter-pattern spacing. Additionally, the method includes forming a precursor material comprising at least copper bearing species and indium bearing species overlying the first patterned structure. Then the substrate including the precursor material is subjected to a thermal processes to form at least an absorber structure. | 2011-10-20 |
| 20110256662 | CHIP EMBEDDED SUBSTRATE AND METHOD OF PRODUCING THE SAME - A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip. | 2011-10-20 |
| 20110256663 | High Speed, High Density, Low Power Die Interconnect System - A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias. | 2011-10-20 |
| 20110256664 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOUNTABLE INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect over the base circuit assembly, the inner interconnect on the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and the outer interconnect. | 2011-10-20 |
| 20110256665 | STACKED WAFER MANUFACTURING METHOD - A manufacturing method for a stacked wafer composed of a mother wafer and a stacking wafer bonded together. The mother wafer has a plurality of first semiconductor devices and the stacking wafer has a plurality of second semiconductor devices respectively corresponding to the first semiconductor devices. The manufacturing method includes the steps of bonding the front side of a substrate through a bonding layer to the front side of the stacking wafer, next grinding the back side of the stacking wafer to reduce the thickness of the stacking wafer to a predetermined thickness, next stacking the unit of the stacking wafer and the substrate bonded together on the mother wafer in the condition where the back side of the stacking wafer is opposed to the front side of the mother wafer, thereby bonding electrodes exposed to the back side of each second semiconductor device to electrodes of each first semiconductor device formed on the front side of the mother wafer, and finally grinding the substrate bonded to the front side of the stacking wafer to thereby remove the substrate. | 2011-10-20 |
| 20110256666 | THERMOSETTING DIE BOND FILM, DICING DIE BOND FILM AND SEMICONDUCTOR DEVICE - The present invention provides a thermosetting type die bond film that can be preferably broken by tensile force. It is a thermosetting type die bond film used for a method of obtaining a semiconductor element from a semiconductor wafer by forming a reforming region by irradiating the semiconductor wafer with a laser beam and then breaking the semiconductor wafer in the reforming region or a method of obtaining a semiconductor element from a semiconductor wafer by forming grooves that do not reach the backside of the semiconductor wafer on a surface thereof and then exposing the grooves from the backside by grinding the backside of the semiconductor wafer, wherein the elongation rate at break at 25° C. before thermal curing is larger than 40% and 500% or less. | 2011-10-20 |
| 20110256667 | STACKED WAFER MANUFACTURING METHOD - A manufacturing method for a stacked wafer configured by bonding a mother wafer having a plurality of first semiconductor device and a stacking wafer having a plurality of second semiconductor devices. The manufacturing method includes the steps of attaching a protective member to the front side of the stacking wafer to protect the second semiconductor devices, next grinding the back side of the stacking wafer, next bonding the front side of a reinforcing wafer through a bonding layer to the back side of the stacking wafer, next dividing the stacking wafer together with the reinforcing wafer into the plural second semiconductor devices, next bonding the front side of each second semiconductor device to the front side of the mother wafer to thereby connect the electrodes of each second semiconductor device to the electrodes of the corresponding first semiconductor device of the mother wafer, and finally grinding the reinforcing wafer bonded to the back side of each second semiconductor device to thereby remove the reinforcing wafer. | 2011-10-20 |
| 20110256668 | METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor apparatus includes forming back surface electrode | 2011-10-20 |
| 20110256669 | DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for protecting a back surface of a semiconductor element flip chip-connected onto an adherend, and a dicing tape, the dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material, the film for flip chip type semiconductor back surface being formed on the pressure-sensitive adhesive layer, in which the pressure-sensitive adhesive layer is a radiation-curable pressure-sensitive adhesive layer whose pressure-sensitive adhesive force toward the film for flip chip type semiconductor back surface is decreased by irradiation with a radiation ray. | 2011-10-20 |
| 20110256670 | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDER PADDLE LEADFINGERS - A method for manufacturing an integrated circuit package system includes: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing a bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle. | 2011-10-20 |
| 20110256671 | SEMICONDUCTOR MEMORY MODULE WITH REVERSE MOUNTED CHIP RESISTOR - A semiconductor memory module having a reverse mounted chip resistor, and a method of fabricating the same are provided. By reverse mounting the chip resistor on the semiconductor memory module, the resistive material is protected, thereby preventing open circuits caused by damage to the resistive material. Also, a chip-resistor connection pad of a module substrate is formed to extend higher from the module substrate than other connection pads connected to other elements. Thus, the resistive material of the chip resistor does not contact the module substrate, thereby preventing poor alignment and defective connections. | 2011-10-20 |
| 20110256672 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof. | 2011-10-20 |
| 20110256673 | DEPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaO | 2011-10-20 |
| 20110256674 | Two-way Halo Implant - A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion implantation is performed perpendicularly to the transistor gates in order to embed the dopant into the silicon body on the surface of the semiconductor wafer. The two-way halo both reduces the channeling effect by allowing ion implantation beneath the transistor gate, and reduces the halo shadowing effect resulting from halo implanting which is done parallel to the transistor gates. | 2011-10-20 |
| 20110256675 | SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs - A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device. | 2011-10-20 |
| 20110256676 | Methods of Manufacturing a Semiconductor Device - Methods of manufacturing a semiconductor device include forming integrated structures of polysilicon patterns and hard mask patterns on a substrate divided into at least an NMOS forming region and a PMOS forming region. A first preliminary insulating interlayer is formed on the integrated structures. A first polishing of the first preliminary insulating interlayer is performed until at least one upper surface of the hard mask patterns is exposed, to form a second preliminary insulating interlayer. The second preliminary insulating interlayer is etched until the upper surfaces of the hard mask patterns are exposed, to form a third preliminary insulating interlayer. A second polishing of the hard mask patterns and the third preliminary insulating interlayer is performed until the polysilicon patterns are exposed to form an insulating interlayer. The polysilicon patterns are removed to form an opening. A metal material is deposed to form a gate electrode pattern in the opening. | 2011-10-20 |
| 20110256677 | NOVEL POLY RESISTOR AND POLY EFUSE DESIGN FOR REPLACEMENT GATE TECHNOLOGY - Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation region, wherein the recess is defined by a concave surface of the isolation region; and forming a first gate structure over the substrate surface and a second gate structure over the concave surface of the isolation region. | 2011-10-20 |
| 20110256678 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed. A method for manufacturing a semiconductor device includes forming a device isolation structure for defining an active region, forming a buried word line traversing the active region, forming one or more insulation film patterns over the buried word line, forming a line pattern including a first conductive material at a position between the insulation film patterns, and forming a plurality of storage node contacts (SNCs) by isolating the line pattern. As a result, when forming a bit line contact and a storage node contact, a fabrication margin is increased. | 2011-10-20 |
| 20110256679 | NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL - A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well. | 2011-10-20 |
| 20110256680 | NAND FLASH MEMORY ARRAY WITH CUT-OFF GATE LINE AND METHODS FOR OPERATING AND FABRICATING THE SAME - A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process. | 2011-10-20 |
| 20110256681 | MOS Devices with Improved Source/Drain Regions with SiGe - A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device. | 2011-10-20 |
| 20110256682 | Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device - A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment includes a UV radiation in the presence of O | 2011-10-20 |
| 20110256683 | METHOD OF MANUFACTURING A HIGH-PERFORMANCE SEMICONDUCTOR DEVICE - The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition. | 2011-10-20 |
| 20110256684 | FIELD EFFECT TRANSISTOR USING OXIDE FILM FOR CHANNEL AND METHOD OF MANUFACTURING THE SAME - The present invention provides a field effect transistor including an oxide film as a semiconductor layer, wherein the oxide film includes one of a source part and a drain part to which one of hydrogen and deuterium is added. | 2011-10-20 |
| 20110256685 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A film structure including at least one film is formed on a face of a semiconductor substrate and then a first mask with a pattern is formed on the film structure. A second mask is formed so as to cover the first mask over a bevel region. The film structure is etched using the first and second masks and thereafter the remaining first and second masks are removed away. | 2011-10-20 |
| 20110256686 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole. | 2011-10-20 |
| 20110256687 | Method for Fabricating Through Substrate Microchannels - A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the bottom of the trenches and to remove the material enclosed by the trench to form the large microchannels. A method of simultaneously forming large and small microchannels. A method of forming structures on the backside of the substrate around a microchannel to mate with another device. | 2011-10-20 |
| 20110256688 | SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench. | 2011-10-20 |
| 20110256689 | OPTICAL DEVICE WAFER PROCESSING METHOD AND LASER PROCESSING APPARATUS - An optical device wafer processing method including a laser processed groove forming step of applying a laser beam for performing ablation to the front side or back side of a substrate of an optical device wafer along streets, thereby forming a laser processed groove as a break start point on the front side or back side of the substrate along each street, and a wafer dividing step of applying an external force to the optical device wafer after performing the laser processed groove forming step to thereby break the wafer along each laser processed groove, thereby dividing the wafer into individual optical devices. In performing the laser processed groove forming step, an etching gas atmosphere for etching a modified substance produced by applying the laser beam to the substrate is generated, whereby an etching gas in the etching gas atmosphere is converted into a plasma by the application of the laser beam to thereby etch away the modified substance. | 2011-10-20 |
| 20110256690 | INTEGRATED CIRCUIT WAFER DICING METHOD - An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits on a wafer substrate, forming a patterned protective layer on the integrated circuits, and etching through the wafer substrate to form a plurality of integrated circuit dies by using the patterned protective layer as a mask. The patterned protective layer is preferably a patterned photoresist layer. The step of forming the patterned protective layer includes covering the wafer substrate with a photoresist layer, exposing the photoresist layer by using a photomask, and developing the exposed photoresist layer to form the patterned protective layer. The etching process can be dry etching or wet etching. | 2011-10-20 |
| 20110256691 | REMOVAL OF SURFACE DOPANTS FROM A SUBSTRATE - A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed. Substrates so treated do not form toxic compounds when stored or transported outside process equipment. | 2011-10-20 |
| 20110256692 | MULTIPLE PRECURSOR CONCENTRIC DELIVERY SHOWERHEAD - A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, the apparatus provides a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. In one embodiment, a plurality of concentric tube assemblies are disposed within the showerhead to separately deliver a first gas from a first gas channel and a second gas from a second gas channel into the processing volume of the chamber. In one embodiment, the showerhead further includes a heat exchanging channel through which the plurality of concentric tube assemblies is disposed. | 2011-10-20 |
| 20110256693 | Method for Synthesis of High Quality Large Area Bulk Gallium Based Crystals - A large area nitride crystal, comprising gallium and nitrogen, with a non-polar or semi-polar large-area face, is disclosed, along with a method of manufacture. The crystal is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation. | 2011-10-20 |
| 20110256694 | Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-On-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 2011-10-20 |
| 20110256695 | BEAM HOMOGENIZER, LASER IRRADIATION APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The energy distribution of the beam spot on the irradiated surface changes due to the change in the oscillation condition of the laser or before and after the maintenance. The present invention provides an optical system for forming a rectangular beam spot on an irradiated surface including a beam homogenizer for homogenizing the energy distribution of the rectangular beam spot on the irradiated surface in a direction of its long or short side. The beam homogenizer includes an optical element having a pair of reflection planes provided oppositely for reflecting the laser beam in the direction where the energy distribution is homogenized and having a curved shape in its entrance surface. The entrance surface of the optical element means a surface of the optical element where the laser beam is incident first. | 2011-10-20 |
| 20110256696 | SEMICONDUCTOR DEVICE FOR PREVENTING THE LEANING OF STORAGE NODES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal structure. The BN layer forming the support patterns has compressive stress as opposed to tensile stress and can therefore withstand cracking in the support patterns. | 2011-10-20 |
| 20110256697 | RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME - A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness. | 2011-10-20 |
| 20110256698 | STEPPED MASKING FOR PATTERNED IMPLANTATION - An improved method of moving a mask to perform a pattern implant of a substrate is disclosed. The mask has a plurality of apertures, and is placed between the ion source and the substrate. After the substrate is exposed to the ion beam, the mask is indexed to a new position relative to the substrate and a subsequent implant step is performed. Through the selection of the aperture size and shape, the index distance and the number of implant steps, a variety of implant patterns may be created. In some embodiments, the implant pattern includes heavily doped horizontal stripes with lighter doped regions between the stripes. In some embodiments, the implant pattern includes a grid of heavily doped regions. In other embodiments, the implant pattern is suitable for use with a bus-bar structure. | 2011-10-20 |
| 20110256699 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a silicon carbide semiconductor device which is capable of obtaining the silicon carbide semiconductor device having a high forward current and a low reverse leakage current by a simple method. The method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a film made of a first electrode material on one surface of a silicon carbide substrate, and forming an ohmic electrode by performing heat treatment at a temperature range of 930 to 950° C.; and forming a film made of a second electrode material on the other surface of the silicon carbide substrate, and forming a Schottky electrode by performing heat treatment. | 2011-10-20 |
| 20110256700 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device capable of simplifying a fabrication process is provided. The method includes providing a substrate on which first and second regions are defined, forming an interlayer insulating film including first and second trenches on the substrate, the first and second trenches being formed in the first and second regions, respectively, forming a work function adjusting metal film on an upper surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench, forming a mask film on the interlayer insulating film to fill in the first and second trenches, the mask film including a developable material, forming a mask pattern by developing the mask film, the mask pattern exposing the work function adjusting metal film formed in the first region, removing the work function adjusting metal film formed in the first region by using the mask pattern, removing the mask pattern, and forming a first metal gate in the first trench and a second metal gate in the second trench. | 2011-10-20 |
| 20110256701 | METHOD FOR TUNING THE WORK FUNCTION OF A METAL GATE OF THE PMOS DEVICE - The present application discloses a method for tuning the work function of a metal gate of the PMOS device, comprising the steps of depositing a layer of metal nitride or a metal on a layer of high-k gate dielectric by physical vapor deposition (PVD), as a metal gate; doping the metal gate with dopants such as Al, Pt, Ru, Ga, Ir by ion implantation; and driving the doped metal ions to the interface between the high-k gate dielectric and interfacial SiO | 2011-10-20 |
| 20110256702 | THIN FILM TRANSISTOR AND DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THEREOF - The present invention discloses a display device and a manufacturing method thereof by which a manufacturing process can be simplified. Further, the present invention discloses technique for manufacturing a pattern such as a wiring into a desired shape with good controllability. A method for forming a pattern for constituting the display device according to the present invention comprises the steps of forming a first region and a second region; discharging a composition containing a pattern formation material to a region across the second region and the first region; and flowing a part of the composition discharged to the first region into the second region; wherein wettability with respect to the composition of the first region is lower than that of the second composition. | 2011-10-20 |
| 20110256703 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a substrate having an element region where a semiconductor element is formed; a via hole formed in a portion of the substrate adjacent to the element region; a conducting portion provided in the via hole via an insulating layer; and a buffer layer provided between the substrate and the insulating layer, wherein the buffer layer is made of a material in which a difference in thermal expansion coefficient between the substrate and the buffer layer is smaller than that between the substrate and the insulating layer. | 2011-10-20 |
| 20110256704 | METHOD FOR MANUFACTURING A METAL GATE ELECTRODE/HIGH K DIELECTRIC GATE STACK - A method of manufacturing a metal gate/high K dielectric gate stack includes the steps of: forming an interfacial layer of SiON or SiO | 2011-10-20 |
| 20110256705 | METHOD FOR FORMING A SPLIT GATE DEVICE - A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer. | 2011-10-20 |
| 20110256706 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion. | 2011-10-20 |
| 20110256707 | PROCESS FOR FABRICATING NON-VOLATILE STORAGE - Fabricating non-volatile storage includes creating gate stacks with hard masks on top of the gate stacks. The gate stacks include two polysilicon layers and a dielectric layer between the two polysilicon layers. A portion of the hard mask over each gate stack is removed, leaving two separate tapered sections of each of the hard masks positioned above an upper polysilicon layer of the gate stacks. After the removing the portion of the hard masks, fluorine is implanted into the upper polysilicon layer of the gate stacks. Metal is added on the top surface of the upper polysilicon layer of the floating gate stacks. A silicidation process for the metal and the upper polysilicon layer of the gate stacks is preformed and the remaining tapered sections of the hard mask are removed. Other control lines can then be added. | 2011-10-20 |
| 20110256708 | Methods of Manufacturing Flash Memory Devices by Selective Removal of Nitrogen Atoms - A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer. | 2011-10-20 |
| 20110256709 | LEVEL POSTURE SENSING CHIP AND ITS MANUFACTURING METHOD, LEVEL POSTURE SENSOR - The present invention discloses a gas pendulum style level posture sensing chip and its manufacturing method and a level posture sensor. The gas pendulum style level posture sensing chip includes: a semiconductor substrate; two sets of arm thermosensitive fuses formed on the surface of the semiconductor substrate, each set of the thermosensitive fuses including two thermosensitive fuses in parallel to each other, the two sets of thermosensitive fuses being vertical to each other; electrodes formed at the two ends of the thermosensitive fuses. For the level posture sensing chip and sensor provided by the present invention, the parallelism and verticality of the thermosensitive fuses is high in precision such that the more accurate measurement can be implemented. | 2011-10-20 |
| 20110256710 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - When a metal cap film is provided on an electric fuse, the break-ability of the electric fuse is reduced. A semiconductor device | 2011-10-20 |
| 20110256711 | MICROFEATURE WORKPIECES HAVING CONDUCTIVE INTERCONNECT STRUCTURES FORMED BY CHEMICALLY REACTIVE PROCESSES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide. | 2011-10-20 |
| 20110256712 | ETCHANT FOR ELECTRODE AND METHOD OF FABRICATING THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME - The present invention relates to an etchant for etching metal wiring, and the metal wiring etchant according to the present invention includes hydrogen peroxide at about 5 wt % to about 15 wt %, an oxidant at about 0.5 wt % to about 5 wt %, a fluoride-based compound at about 0.1 wt % to about 1 wt %, a nitrate-based compound at about 0.5 wt % to about 5 wt %, and a boron-based compound at about 0.05 wt % to about 1 wt %. | 2011-10-20 |
| 20110256713 | POLYHEDRAL OLIGOMERIC SILSESQUIOXANE BASED IMPRINT MATERIALS AND IMPRINT PROCESS USING POLYHEDRAL OLIGOMERIC SILSESQUIOXANE BASED IMPRINT MATERIALS - A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, wherein each of the one or more polymerizable group is bound to a different silicon atom of the one or more polyhedral silsesquioxane oligomers; and | 2011-10-20 |
| 20110256714 | SUBSTRATE STRUCTURE WITH DIE EMBEDDED INSIDE AND DUAL BUILD-UP LAYERS OVER BOTH SIDE SURFACES AND METHOD OF THE SAME - The present invention comprises a first substrate with a die formed on a die metal pad, a first and a second wiring circuits formed on the surfaces of the first substrate. A second substrate has a die opening window for receiving the die, a third wiring circuit is formed on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate. During the formation, laser is introduced to cut the backside of the first substrate and an opening hole is formed in the first substrate to expose a part of the backside of the Au or Au/Ag metal layer of chip/die. | 2011-10-20 |
| 20110256715 | BARRIER LAYER FOR COPPER INTERCONNECT - A copper interconnect includes a copper layer formed in a dielectric layer. A liner is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the liner and the dielectric layer. The barrier layer is a metal oxide. | 2011-10-20 |
| 20110256716 | Method of depositing a uniform barrier layer and metal seed layer with reduced overhang over a plurality of recessed semiconductor features - A method of depositing a metal seed layer with underlying barrier layer on a wafer substrate comprising a plurality of recessed device features. A first portion of the barrier layer is deposited on the wafer substrate without excessive build-up of barrier layer material on the openings to the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. Subsequently, a metal seed layer is deposited using the same techniques used to deposit the barrier layer, to avoid excessive build up of metal seed layer material on the openings to the features, with minimal sputtering of the barrier layer surface. | 2011-10-20 |
| 20110256717 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Provided are semiconductor devices and methods for fabricating the same. A method for fabricating a semiconductor device includes: forming an interlayer dielectric layer including an opening in which a lower conductive layer is exposed; forming a barrier layer on the interlayer dielectric layer and on the lower conductive layer the opening; forming an anti-seed generation region on a surface of the barrier layer which is provided on a top surface of the interlayer dielectric layer and an upper sidewall of the opening; and filling the opening with conductive material to form a conductive layer. | 2011-10-20 |
| 20110256718 | THIN FILMS - Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO | 2011-10-20 |
| 20110256719 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first contact opening having a relatively larger depth than a second contact opening to expose first and second contacts through an insulation layer, where the first and second contacts are located at different depths with respect to an upper surface of the insulation layer. Therefore, it is possible to prevent excessive over-etch of the second contact opening and minimize etching damage to the contact region exposed by the second contact opening. | 2011-10-20 |
| 20110256720 | Techniques for Impeding Reverse Engineering - Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer. | 2011-10-20 |
| 20110256721 | RUTHENIUM-CONTAINING PRECURSORS FOR CVD AND ALD - Disclosed are ruthenium-containing precursors and methods of using the same in CVD and ALD. | 2011-10-20 |
| 20110256722 | METHODS FOR FORMING ROUGHENED SURFACES AND APPLICATIONS THEREOF - Methods of forming a roughened metal surface on a substrate are provided, along with structures comprising such roughened surfaces. In preferred embodiments roughened surfaces are formed by selectively depositing metal or metal oxide on a substrate surface to form discrete, three-dimensional islands. Selective deposition may be obtained, for example, by modifying process conditions to cause metal agglomeration or by treating the substrate surface to provide a limited number of discontinuous reactive sites. The roughened metal surface may be used, for example, in the manufacture of integrated circuits. | 2011-10-20 |
| 20110256723 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first sacrificial hard mask layer over a semiconductor substrate including an etch layer, forming a first spacer over the first sacrificial hard mask layer, forming a first sacrificial hard mask pattern by etching the first sacrificial hard mask layer using the first spacer as an etch mask, forming a second spacer at both sidewalls of the first sacrificial hard mask pattern, partially isolating the second spacer, and forming a pad pattern over the second spacer. As a result, a line-and-space pattern such as a control gate of the NAND flash memory and a pad portion coupled to a drain contact in an X-decoder of a peripheral circuit region can be easily implemented. | 2011-10-20 |
| 20110256724 | GAS AND LIQUID INJECTION METHODS AND APPARATUS - A liquid injection system for a processing chamber includes a liquid injector that receives a liquid from a liquid supply and that selectively pulses the liquid into a conduit. A control module selects a number of pulses and a pulse width of the liquid injector. A gas supply supplies gas into the conduit. A sensor senses at least one of a first temperature and a first pressure in the conduit and that generates at least one of a first temperature signal and a first pressure signal, respectively. The control module confirms that the selected number of pulses occur based on the at least one of the first temperature signal and the first pressure signal. | 2011-10-20 |
| 20110256725 | STRUCTURE AND METHOD FOR THIN FILM DEVICE WITH STRANDED CONDUCTOR - Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD. | 2011-10-20 |
| 20110256726 | PLASMA ACTIVATED CONFORMAL FILM DEPOSITION - Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film. | 2011-10-20 |
| 20110256727 | METHOD OF FORMING SEMICONDUCTOR PATTERNS - Semiconductor patterns are formed by performing trimming simultaneously with the process of depositing the spacer oxide. Alternatively, a first part of the trimming is performed in-situ, immediately before the spacer oxide deposition process in the same chamber in which the spacer oxide deposition is performed whereas a second part of the trimming is performed simultaneously with the process of depositing the spacer oxide. Thus, semiconductor patterns are formed reducing PR footing during PR trimming with direct plasma exposure. | 2011-10-20 |
| 20110256728 | WAFER THINNING METHOD IN WAFER TREATING SYSTEM - A wafer thinning apparatus for treating wafers each having at least a circuit-forming surface thereof protected, by immersing the wafers in a treating solution. The apparatus includes a support table for receiving, as placed thereon, containers each containing a plurality of wafers in one of groups into which the wafers are sorted according to predetermined ranges of thickness, a treating tank for storing the treating solution and receiving the containers, a transport mechanism for transporting the containers between the support table and the treating tank, and a control unit for controlling the transport mechanism to transport the containers successively to the treating tank, and for changing an immersion time of the containers in the treating tank for each group. | 2011-10-20 |
| 20110256729 | Showerhead for CVD Depositions - A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer. | 2011-10-20 |
| 20110256730 | FINISHING METHOD FOR MANUFACTURING SUBSTRATES IN THE FIELD OF ELECTRONICS - The invention relates to a method for finishing the surface of semiconducting substrate that has a set of layers and a useful semiconducting layer on at least one of the faces of the substrate, wherein the useful layer has a rough free surface. The method smoothes out the rough free surface of the useful layer by creating a protective layer covering the surface of the useful layer with a thickness 1 to 3 times larger than the peak-to-valley distance of the surface of the useful layer, at least one polishing-oxidation sequence that includes the successive steps of polishing the surface of the protective layer, with the polishing being adjusted so as not to attack the useful layer, and performing a thermal oxidation with supply of oxygen gas of the substrate in order to transform a portion of the useful layer into an oxide layer and reduce the roughness of the surface of the useful layer. | 2011-10-20 |
| 20110256731 | METHOD FOR FABRICATING A GATE DIELECTRIC LAYER - A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer. | 2011-10-20 |
| 20110256732 | Pulsed Plasma to Affect Conformal Processing - A plasma processing method is provided. The plasma processing method includes using the after-glow of a pulsed power plasma to perform conformal processing. During the afterglow, the equipotential field lines follow the contour of the workpiece surface, allowing ions to be introduced in a variety of incident angles, especially to non-planar surfaces. In another aspect of the disclosure, the platen may be biased positively during the plasma afterglow to attract negative ions toward the workpiece. Various conformal processing steps, such as implantation, etching and deposition may be performed. | 2011-10-20 |
| 20110256733 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS - An insulating film having features such as a low dielectric constant, a low etching rate and a high insulating property is formed. An oxycarbonitride film having a predetermined thickness is formed on a substrate in a process vessel by performing a cycle a predetermined number of times, wherein the cycle includes steps of: (a) performing a set of steps a predetermined number of times to form a carbonitride layer having a predetermined thickness on the substrate; and (b) supplying an oxygen-containing gas into the process vessel to oxidize the carbonitride layer having the predetermined thickness, thereby forming an oxycarbonitride layer, wherein the set of steps includes: (a-1) supplying a gas containing an element into the process vessel accommodating the substrate under a condition where a CVD reaction is caused to form a layer containing the element on the substrate; (a-2) supplying a carbon-containing gas into the process vessel to form a carbon-containing layer on the layer containing the element, thereby forming a layer including the element and a carbon; and (a-3) supplying a nitrogen-containing gas into the process vessel to nitride the layer including the element and the carbon, thereby forming the carbonitride layer. | 2011-10-20 |
