42nd week of 2012 patent applcation highlights part 14 |
Patent application number | Title | Published |
20120261689 | SEMICONDUCTOR DEVICE PACKAGES AND RELATED METHODS - The packages include a plurality of spaced conductive standoffs electrically coupling the semiconductor die to, variously, a substrate and bottom package contacts. The conductive standoffs may be pillars or posts. The substrate includes at least one electrically isolated portion, which has exposed sidewalls. | 2012-10-18 |
20120261690 | LIGHT EMITTING DIODE WITH MICRO-STRUCTURE LENS - A light emitting diode (LED) with a micro-structure lens includes a LED die and a micro-structure lens. The micro-structure lens includes a convex lens portion, at least one concentric ridge structure surrounding the convex lens portion, and a lower portion below the convex lens portion and the at least one concentric ridge structure. The lower portion is arranged to be disposed over the LED die. A first optical path length from an edge of the LED die to a top center of the microstructure lens is substantially the same as a second optical path length from the edge of the LED die to a side of the micro-structure lens. | 2012-10-18 |
20120261691 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a light emitting device, including a base, an LED inversely mounted on the base. The LED includes a buffer layer, an LED chip on the buffer layer. The buffer layer includes a plurality of protrusions with complementary pyramid structure on a light-exiting surface of the LED. The present invention also provides a method for manufacturing a light emitting device, including: providing a substrate and forming a plurality of pyramid structures on the substrate; forming successively a buffer layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer and a contact layer on the substrate with the pyramid structures; forming an opening with a depth at least from the contact layer to a top of the n-type semiconductor layer, and forming a first electrode on the contact layer and a second electrode on a bottom of the opening; and removing the substrate. The light emitting device has a high luminous efficiency and the manufacturing method is easy to implement. | 2012-10-18 |
20120261692 | LED PACKAGE STRUCTURE - A LED package structure includes a substrate, a LED chip and a colloid. The substrate includes a first surface and a second surface. An opening is shaped from the first surface toward the second surface. A phosphor layer is coated on the bottom surface with two opposite parts of the bottom surface respectively neighboring to two opposite side walls of the opening exposed. A metal layer is coated on the two exposed opposite parts of the bottom surface, the two opposite side walls and the first surface. The LED chip is received in the opening and configured on the phosphor layer. The LED chip includes a pair of conductive pads electrically connecting to the metal layer. The colloid is filled between the LED chip and the metal layer to attach the substrate to the LED chip. | 2012-10-18 |
20120261693 | LIGHT-EMITTING DIODE DEVICE - A light-emitting diode device. In one embodiment, the light-emitting device includes a heat-dissipating mount and a light-emitting diode chip. The heat-dissipating mount has a cavity, wherein the cavity includes an embedded portion and an inclined surface connected with the embedded portion. The light-emitting diode chip includes a substrate partly embedded into the embedded portion. A lower region of a side surface of the substrate has a first unsmooth surface, the first unsmooth surface has an exposed portion protruding above the embedded portion, and a bottom edge of the lower region is connected to a bottom surface of the substrate. | 2012-10-18 |
20120261694 | ALUMINUM DEFICIENT alpha-SiAION PHOSPHORS, METHOD OF PREPARING THE SAME, AND LED CHIP PACKAGE USING THE SAME - The present disclosure provides α-SiAlON phosphors, a method of preparing the same, and an LED chip package using the same. The method includes weighing and mixing raw materials of Ca | 2012-10-18 |
20120261695 | LIGHT-EMITTING DEVICE - A light-emitting device includes a first electrode; a light-emitting stacked layer on the first electrode; a first contact layer on the light-emitting stacked layer, wherein the first contact layer includes a first contact link and a plurality of first contact lines connected to the first contact link; a first conductive post in the light-emitting stacked layer and electrically connecting the first electrode and the first contact layer; and a passivation layer between the first conductive post and the light-emitting stacked layer. | 2012-10-18 |
20120261696 | LIGHT EMITTING DIODE EPITAXIAL STRUCTURE AND MANUFACTURING METHOD THEREOF - A light emitting device (LED) epitaxial structure includes a substrate, a nitride semiconductor layer, a patterned oxide total-reflective layer, a first-type semiconductor layer, an active layer and a second-type semiconductor layer. The nitride semiconductor layer is formed on the substrate. The patterned oxide total-reflective layer is formed on the nitride semiconductor layer. An upper surface of the nitride semiconductor layer is partially exposed out from the oxide total-reflective layer. The first-type semiconductor layer is arranged on the exposed upper surface of the nitride semiconductor layer and covers the oxide total-reflective layer. The active layer is arranged on the first-type semiconductor layer. The second-type semiconductor layer is arranged on the active layer. | 2012-10-18 |
20120261697 | Wafer Level Packaging of Electronic Devices - Aspects of the invention include an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer. | 2012-10-18 |
20120261698 | DISPLAY APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A method includes forming a light absorbing layer, and forming a foundation layer before forming a lens portion such that the foundation layer covers a region where the lens portion is to be formed, wherein the foundation layer is in contact with the light absorbing layer and the lens portion once the lens portion is formed. | 2012-10-18 |
20120261699 | REFLECTING RESIN SHEET, LIGHT EMITTING DIODE DEVICE AND PRODUCING METHOD THEREOF - A reflecting resin sheet provides a reflecting resin layer at the side of a light emitting diode element. The reflecting resin sheet includes a release substrate and the reflecting resin layer provided on one surface in a thickness direction of the release substrate. The reflecting resin layer is formed corresponding to the light emitting diode element so as to be capable of being in close contact with the light emitting diode element. | 2012-10-18 |
20120261700 | PHOSPHOR REFLECTING SHEET, LIGHT EMITTING DIODE DEVICE, AND PRODUCING METHOD THEREOF - A phosphor reflecting sheet provides a phosphor layer on one side in a thickness direction of a light emitting diode element and provides a reflecting resin layer at the side of the light emitting diode element. The phosphor reflecting sheet includes the phosphor layer and the reflecting resin layer provided on one surface in the thickness direction of the phosphor layer. The reflecting resin layer is formed corresponding to the light emitting diode element so as to be disposed in opposed relation to the side surface of the light emitting diode element. | 2012-10-18 |
20120261701 | LIGHT EXTRACTION SUBSTRATE FOR ELECTROLUMINESCENT DEVICE AND MANUFACTURING METHOD THEREOF - A light extraction substrate for an electroluminescent device and a manufacturing method thereof, in which light extraction efficiency is increased. The light extraction substrate for an electroluminescent device includes a substrate and a light extraction layer formed on the substrate. The light extraction layer contains an oxide that has a wide band gap of 2.8 eV or more. The light extraction layer has a texture on the surface thereof. | 2012-10-18 |
20120261702 | LED, LED CHIP AND METHOD OF FORMING THE SAME - A method for manufacturing a light emitting diode chip is provided, comprising: providing a substrate, an upper surface of which comprising a plurality of micro-bulges formed thereon; forming a first type semiconductor layer, a light emitting layer and a second type semiconductor layer on the upper surface of the substrate successively; partially etching the second type semiconductor layer and the light emitting layer to form an electrode bonding area on the first type semiconductor layer; and forming a first electrode structure on the electrode bonding area and forming a second electrode structure on the second type semiconductor layer. A LED chip and a LED comprising the same are also provided. | 2012-10-18 |
20120261703 | Self-cooling solid-state emitters - A self-cooling emitter is a light emitting element embedded within a thermally conductive luminescent element which functions as a thermal cooling means and wavelength conversion of the light emitting element. The thermally conductive luminescent element exhibits a bulk thermal conductivity greater than | 2012-10-18 |
20120261704 | LIGHTING DEVICE WITH LIGHT SOURCE AND WAVELENGTH CONVERTING ELEMENT - The invention relates to a lighting ( | 2012-10-18 |
20120261705 | LIGHT EMITTING DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A light emitting device package capable of emitting uniform white light and a method for manufacturing the same are disclosed. The light emitting device package includes a package body, an electrode formed on at least one surface of the package body, a light emitting device mounted on the package body, and a phosphor layer enclosing the light emitting device while having a uniform thickness around the light emitting device. | 2012-10-18 |
20120261706 | LIGHT EMITTING DEVICE - A light emitting device includes first and second cladding layers and an active layer therebetween including first and second side surfaces and first and second gain regions, a second side reflectance is higher than a first side reflectance, a first end surface part of the first gain region overlaps a second end surface part of the second gain region in an overlapping plane, the first gain region obliquely extends from the first end surface to a third end surface, the second gain region obliquely extends from the second end surface to a fourth end surface, a first center line connecting the centers of the first and third end surfaces and a second center line connecting the centers of the second and fourth end surfaces intersect, and the overlapping plane is shifted from the intersection point toward the first side surface. | 2012-10-18 |
20120261707 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitting device includes: a support substrate; a metal layer provided on the support substrate; a semiconductor layer provided on the metal layer and including a light emitting layer; a contact layer containing a semiconductor, selectively provided between the semiconductor layer and the metal layer, and being in contact with the semiconductor layer and the metal layer; and an insulating film provided between the semiconductor layer and the metal layer at a position not overlapping the contact layer. | 2012-10-18 |
20120261708 | LIGHT EMITTING DIODE AND METHOD FOR PREPARING THE SAME - A light emitting diode includes a substrate comprising a plurality of first grooves and a plurality of first convex parts formed on a surface of the substrate, with the first groove formed between two neighboring first convex parts; a semiconductor structure formed on the substrate comprising a plurality of second convex parts corresponding to the plurality of first grooves and a plurality of second grooves corresponding to the plurality of first convex parts; a transparent conductive layer formed on the semiconductor structure and configured to transmit a current to the plurality of second convex parts; a first electrode electrically connected with the semiconductor structure; and a second electrode electrically connected with the transparent conductive layer. A method for preparing the light emitting diode is also provided. | 2012-10-18 |
20120261709 | LIGHT-EMITTING DIODE DIE PACKAGES AND ILLUMINATION APPARATUSES USING SAME - The present invention relates to an LED die package, which has a light-emitting diode die having a sapphire layer, a first doped layer doped with a p- or n-type dopant, and a second doped layer doped with a different dopant from that doped in the first doped layer. A surface of the sapphire layer opposite to the surface on which the first doped layer is disposed is formed with generally inverted-pyramidal-shaped recesses and overlaid with a phosphor powder layer. Each of the first and the second doped layers has an electrode-forming surface formed with an electrode, on which an insulation layer is disposed and formed with exposure holes for exposing the electrodes. The exposure holes are each filled with an electrically conductive linker. | 2012-10-18 |
20120261710 | ORGANIC LIGHT EMITTING DIODE LIGHTING APPARATUS - An organic light emitting diode (OLED) lighting apparatus includes a light emitting panel including an organic light emitting diode, a housing for housing the light emitting panel, a cover coupled to the housing and covering a front-side edge of the light emitting panel, a plurality of pins disposed between the housing and the light emitting panel and supporting an edge of the light emitting panel, and at least one contact bar disposed between the plurality of pins and a back-side edge of the light emitting panel. | 2012-10-18 |
20120261711 | ELECTRONIC DEVICE CONTACT STRUCTURES - Electronic devices involving contact structures, and related components, systems and methods associated therewith are described. The contact structures are particularly suitable for use in a variety of light-emitting devices, including LEDs. | 2012-10-18 |
20120261712 | Optoelectronic Device with Homogeneous Light Intensity - An optoelectronic device comprising: a first electrical supply conductor ( | 2012-10-18 |
20120261713 | ORGANIC LIGHT EMITTING DIODE LIGHTING APPARATUS - An organic light emitting diode (OLED) lighting apparatus is disclosed. In one embodiment, the apparatus includes i) a substrate main body including a light emitting area and a sealing area surrounding the light emitting area, ii) an OLED disposed on the light emitting area of the substrate main body, iii) a sealant disposed on the sealing area of the substrate main body and iv) an encapsulation substrate encapsulating the OLED, wherein the encapsulation substrate comprises first and second surfaces opposing each other. The apparatus may further include a heat dissipating wire configured to dissipate heat generated by the OLED. The heat dissipating wire includes a heat absorption portion disposed on the first surface of the encapsulation substrate and contacting the sealant, a heat dissipating portion disposed on the second surface, and a coupling portion interconnecting the absorption portion and the heat dissipating portion. | 2012-10-18 |
20120261714 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer. | 2012-10-18 |
20120261715 | POWER SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING THE SAME - A power semiconductor device includes: a drain region of a first conductive type; a drift region of a first conductive type formed on the drain region; a first body region of a second conductive type formed below an upper surface of the drift region; a second body region of a second conductive type formed below the upper surface of the drift region and in the first body region; a third body region of a second conductive type formed by protruding downwards from a lower end of the first body region; a source region of a first conductive type formed below the upper surface of the drift region and in the first body region; and a gate insulating layer formed on channel regions of the first body region and on the drift region between the first body regions. | 2012-10-18 |
20120261716 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a buffer layer, and a compound semiconductor layer. The buffer layer is configured by laminating two or more pairs of a first buffer and a second buffer. The first buffer is formed by laminating one or more pairs of an AlN layer and a GaN layer. The second buffer is formed of a GaN layer. A total Al composition of a pair of the first buffer and the second buffer on the compound semiconductor layer side is higher than that of a pair of the first buffer and the second buffer on the substrate side. | 2012-10-18 |
20120261717 | MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS - Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements. | 2012-10-18 |
20120261718 | Method And Structure For Compound Semiconductor Contact - The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region. | 2012-10-18 |
20120261719 | HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures. | 2012-10-18 |
20120261720 | METHOD FOR MANUFACTURING A HEMT TRANSISTOR AND CORRESPONDING HEMT TRANSISTOR - A method for manufacturing a HEMT transistor includes: realizing an undoped epitaxial layer on a substrate; realizing a barrier epitaxial layer on the undoped epitaxial layer so as to form a heterojunction; realizing source and drain structures, separated from one other, on the barrier epitaxial layer; depositing an insulating layer on the barrier epitaxial layer and on the source and drain structures; and photolithographic defining the insulating layer, defining first and second insulating portions in correspondence of the source and drain structures, respectively, and exposing a portion of the barrier epitaxial layer. The method further comprises: forming first and second spacers lying at the corners of the first and second insulating portions; and depositing a gate metal structure at least partially covering said first and second insulating portions, and said first and second spacers, said gate metal structure being a field plate of the HEMT transistor. | 2012-10-18 |
20120261721 | SEMICONDUCTOR STRUCTURES HAVING NUCLEATION LAYER TO PREVENT INTERFACIAL CHARGE FOR COLUMN III-V MATERIALS ON COLUMN IV OR COLUMN IV-IV MATERIALS - A semiconductor structure having: a column IV material or column IV-IV material; a nucleation layer of AlN layer or a column III nitride having more than 60% aluminum content on a surface of the column IV material or column IV-IV material and a layer of column III-V material over the nucleation layer, where the nucleation layer and the layer of column III-V material over the nucleation layer have different crystallographic structures. In one embodiment, the column III-V nucleation layer is a nitride and the column III-V material of the over the nucleation layer is a non-nitride such as, for example, an arsenide (e.g., GaAs), a phosphide (e.g., InP), or an antimonide (e.g. InSb), or alloys thereof. | 2012-10-18 |
20120261722 | Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells - A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed. | 2012-10-18 |
20120261723 | SEMICONDUCTOR DEVICE - A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch. | 2012-10-18 |
20120261724 | STACKABLE PROGRAMMABLE PASSIVE DEVICE AND A TESTING METHOD - A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value. | 2012-10-18 |
20120261725 | Stabilized Metal Silicides in Silicon-Germanium Regions of Transistor Elements - Generally, the present disclosure is directed to methods of stabilizing metal silicide contact regions formed in a silicon-germanium active area of a semiconductor device, and devices comprising stabilized metal silicides. One illustrative method disclosed herein includes performing an activation anneal to activate dopants implanted in an active area of a semiconductor device, wherein the active area comprises germanium. Additionally, the method includes, among other things, performing an ion implantation process to implant ions into the active area after performing the activation anneal, forming a metal silicide contact region in the active area, and forming a conductive contact element to the metal silicide contact region. | 2012-10-18 |
20120261726 | DIVOT ENGINEERING FOR ENHANCED DEVICE PERFORMANCE - An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface; a trench isolation structure disposed in the semiconductor substrate, the trench isolation structure having a trench isolation structure surface that is substantially planar to the substrate surface; and a gate feature disposed over the semiconductor substrate, wherein the gate feature includes a portion that extends from the substrate surface to a depth in the trench isolation structure, the portion being defined by a trench isolation structure sidewall and a semiconductor substrate sidewall, such that the portion tapers from a first width at the substrate surface to a second width at the depth, the first width being greater than the second width. | 2012-10-18 |
20120261727 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING LOCAL INTERCONNECT STRUCTURE THEREOF - A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth. | 2012-10-18 |
20120261728 | EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES - A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape. | 2012-10-18 |
20120261729 | SHALLOW-TRENCH-ISOLATION (STI)-BOUNDED SINGLE-PHOTON AVALANCHE PHOTODETECTORS - Techniques and apparatus for using single photon avalanche diode (SPAD) devices in various applications. | 2012-10-18 |
20120261730 | FLOATING DIFFUSION STRUCTURE FOR AN IMAGE SENSOR - An image sensor including a pixel array having a floating diffusion region of a pixel which is disposed in a substrate, the floating diffusion region to receive a charge from a photosensitive region. In an embodiment, a transfer gate disposed on the substrate, wherein a portion of the transfer gate forms a cavity extending through the transfer gate. In another embodiment, a cavity extending through a transfer gate exposes a floating diffusion region. | 2012-10-18 |
20120261731 | IMAGE SENSOR - An image sensor is disclosed. The image sensor includes a substrate, at least a color filter, and a microlens disposed on the color filter. The substrate includes a passivation layer thereon, and the color filter is disposed on the passivation layer, in which the color filter is truncated. | 2012-10-18 |
20120261732 | METHOD FOR FORMING A BACK-SIDE ILLUMINATED IMAGE SENSOR - A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) thinning the substrate from its rear surface; b) depositing, on the rear surface of the thinned substrate, an amorphous silicon layer of same conductivity type as the substrate but of higher doping level; and c) annealing at a temperature enabling to recrystallized the amorphous silicon to stabilize it. | 2012-10-18 |
20120261733 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a trench isolation. The trench isolation is formed in a surface of a semiconductor substrate to define an active region a well region, and a bottom of the trench isolation is positioned within the well region. The trench isolation includes a conductive wiring electrically connected to the well region and an insulating film which buries the conductive wiring in the bottom of the trench isolation. Semiconductor elements are disposed in the active region. | 2012-10-18 |
20120261734 | SEMICONDUCTOR MEMORY DEVICE - In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring. | 2012-10-18 |
20120261735 | SEMICONDUCTOR DEVICE HAVING A THIN FILM CAPACITOR AND METHOD FOR FABRICATING THE SAME - In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO.sub.2, HfO.sub.2, (Zr.sub.x, Hf.sub.1−x)O.sub.2 (02012-10-18 | |
20120261736 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device includes a substrate, a gate stack, a selecting gate, an erasing gate, a source region, and a drain region. The gate stack on the substrate includes from bottom to top a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a spacer that is located between sidewalls of the control gate and the inter-gate dielectric layer. A side of the floating gate adjacent to the erasing gate has a warp-around profile and a sharp corner protruding from a vertical surface of the spacer. The selecting and erasing gates are respectively located at first and second sides of the substrate of the gate stack. The source region is located in the substrate under the erasing gate. The drain region is located in the substrate at a side of the selecting gate. | 2012-10-18 |
20120261737 | TRENCH MOSFET WITH TRENCHED FLOATING GATES AND TRENCHED CHANNEL STOP GATES IN TERMINATION - A trench MOSFET comprising multiple trenched floating gates in termination area is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction of body regions in active area The trench MOSFET further comprises at least one trenched channel stop gate around outside of the trenched floating gates and connected to at least one sawing trenched gate extended into scribe line for prevention of leakage path formation between drain and source regions. | 2012-10-18 |
20120261738 | N-Well/P-Well Strap Structures - Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 2012-10-18 |
20120261739 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device including a first doped region of a first conductivity type, a second doped region of a second conductivity type, a gate, and a dielectric layer is provided. The first doped region is located in a substrate and has a trench. The second doped region is located at the bottom of the trench to separate the first doped region into a source doped region and a drain doped region. A channel region is located between the source doped region and the drain doped region. The gate is located in the trench. The dielectric layer covers the sidewall and the bottom of the trench and separates the gate and the substrate. | 2012-10-18 |
20120261740 | FLASH MEMORY AND METHOD FOR FABRICATING THE SAME - The present invention discloses a flash memory and a method for fabricating the same, and relates to the technical field of the semiconductor memory. The flash memory includes a buried oxygen layer on which a source terminal, a channel, and a drain terminal are disposed, wherein the channel is between the source terminal and the drain terminal, and a tunneling oxide layer, a polysilicon floating gate, a blocking oxide layer, and a polysilicon control gate are sequentially disposed on the channel, and a thin silicon nitride layer is disposed between the source terminal and the channel. The method includes: 1) performing a shallow trench isolation on a SOI silicon substrate to form an active region; 2) sequentially forming a tunneling oxide layer and a first polysilicon layer on the SOI silicon substrate to form a polysilicon floating gate, and forming a blocking oxide layer and a second polysilicon layer to form a polysilicon control gate; 3) etching the resultant structure to form a gate stack structure; 4) forming a drain terminal at one side of the gate stack structure, etching the silicon film at the other side of the gate stack structure, growing a thin silicon nitride layer, and then refilling the hole structure with silicon material, to form a source terminal. The method has the advantages of high programming efficiency, low power consumption, effectively preventing source-drain punchthrough effect. | 2012-10-18 |
20120261741 | Novel High Speed High Density NAND-Based 2T-NOR Flash Memory Design - A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip. | 2012-10-18 |
20120261742 | NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS - A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al | 2012-10-18 |
20120261743 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having plural memory cell regions featuring nonvolatile memory cells, each nonvolatile memory cell including a first insulating film formed over a semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and arranged adjacent with the control gate electrode through the second gate insulating film, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, wherein each of the nonvolatile memory cells of a first memory cell region and each of the nonvolatile memory cells of a second memory cell region are formed adjacent to one another such that a drain region is shared between them. | 2012-10-18 |
20120261744 | MICROELECTRONIC DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well. | 2012-10-18 |
20120261745 | SEMICONDUCTOR SWITCHING DEVICE EMPLOYING A QUANTUM DOT STRUCTURE - A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided. | 2012-10-18 |
20120261746 | Double-Trench Vertical Devices and Methods with Self-Alignment Between Gate and Body Contact - Methods and resulting device structures for power trench transistor fabrication, wherein a reachup pillar from the field plate trench is left in place to define the location of a self-aligned contact to the field plate. | 2012-10-18 |
20120261747 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a word line and a bit line on a substrate and the word line intersects the bit line, an insulating layer on the substrate and the insulating layer includes voids therein, and a passivation layer on the insulating layer and the passivation layer includes hydrogen atoms therein. The voids define diffusion pathways through which the hydrogen atoms in the passivation layer diffuse in a direction toward the substrate. | 2012-10-18 |
20120261748 | SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer. | 2012-10-18 |
20120261749 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; and a first area and a second area which are respectively provided on the semiconductor substrate. The first area includes: a first metal wiring formed in a first wiring layer above the semiconductor substrate and having a certain first width; a second metal wiring formed in a second wiring layer located in an upper layer of the first wiring layer and having the first width; and a first contact connecting the first metal wiring and the second metal wiring and having a second width equal to or less than the first width. The second area includes a third metal wiring having a film thickness from the first wiring layer to the second wiring layer and having a certain third width. | 2012-10-18 |
20120261750 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a drift diffusion region of a first conductivity type, a body diffusion region of a second conductivity type, a source diffusion region of the first conductivity type, an insulating film buried in a trench formed in an upper portion of the drift diffusion region and spaced apart from the body diffusion region, a drain diffusion region of the first conductivity type formed in an upper portion of the drift diffusion region and adjacent to the insulating film on the opposite side of the insulating film from the source diffusion region, and a gate electrode formed on a portion of the body diffusion region, the drift diffusion region, and a portion of the insulating film. The drift diffusion region includes a substrate inner region, and a surface region containing an impurity of the first conductivity type at a higher concentration than that of the substrate inner region. | 2012-10-18 |
20120261751 | RECTIFIER WITH VERTICAL MOS STRUCTURE - A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure. | 2012-10-18 |
20120261752 | POWER LDMOS DEVICE AND HIGH VOLTAGE DEVICE - A power LDMOS device including a substrate, source and drain regions, gates and trench insulating structures is provided. The substrate has a finger tip area, a finger body area and a palm area. The source regions are in the substrate in the finger body area and further extend to the finger tip area. The neighboring source regions in the finger tip area are connected. The outmost two source regions further extend to the palm area and are connected. The drain regions are in the substrate in the finger body area and further extend to the palm area. The neighboring drain regions in the palm area are connected. The source and drain regions are disposed alternately. A gate is disposed between the neighboring source and drain regions. The trench insulating structures are in the substrate in the palm area and respectively surround ends of the drain regions. | 2012-10-18 |
20120261753 | DMOS Transistor with a Slanted Super Junction Drift Structure - A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening. | 2012-10-18 |
20120261754 | MOSFET with Recessed channel FILM and Abrupt Junctions - MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created. | 2012-10-18 |
20120261755 | PIXEL STRUCTURE, DISPLAY PANEL, ELECTRO-OPTICAL APPARATUS, AND METHOD THEREOF - A pixel structure disposed on a substrate including a thin film transistor (TFT), a passivation layer, and a pixel electrode is provided. The TFT includes a gate, a dielectric layer, a channel layer, and a source/drain sequentially disposed on the substrate. The source/drain is disposed on a portion of the channel layer and has a semiconductor layer, a barrier layer and a metal layer. The barrier layer is disposed on a portion of the semiconductor layer. The metal layer is disposed on the barrier layer. The barrier layer is in contact with the semiconductor layer and the metal layer. Both of the metal layer and the barrier layer are positioned within a projection area of the semiconductor layer. The passivation layer covers the TFT and the dielectric layer and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening. | 2012-10-18 |
20120261756 | INTEGRATION OF FIN-BASED DEVICES AND ETSOI DEVICES - Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate. | 2012-10-18 |
20120261757 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 2012-10-18 |
20120261758 | METHOD OF FABRICATING A GATE DIELECTRIC LAYER - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate having a first active region; a first gate structure over the first active region, wherein the first gate structure comprises a first interfacial layer having a convex top surface; a first high-k dielectric over the first interfacial layer; and a first gate electrode over the first high-k dielectric. | 2012-10-18 |
20120261759 | Semiconductor device and method for manufacturing the same - A semiconductor device comprising: a semiconductor substrate; an STI embedded into the semiconductor substrate and having at least a semiconductor opening region; a channel region in the semiconductor opening region; a gate stack comprising a gate dielectric layer and a gate conductive layer and located above the channel region; and source/drain regions located on both sides of the channel region, and comprising first seed layers on opposite sides of the gate stack adjacent to the STI, wherein the upper surface of the STI is higher than or sufficiently closed to the upper surface of the gate dielectric layer. The semiconductor device and the method for manufacturing the same can enhance the stress of the channel region so as to improve device performance. | 2012-10-18 |
20120261760 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film. | 2012-10-18 |
20120261761 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. | 2012-10-18 |
20120261762 | DEVICE STRUCTURE, LAYOUT AND FABRICATION METHOD FOR UNIAXIALLY STRAINED TRANSISTORS - A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices. | 2012-10-18 |
20120261763 | Semiconductor Structure and Method for Manufacturing the Same - The present invention relates to a semiconductor and a method for manufacturing the same. The semiconductor structure comprises an NMOS device comprising a first gate structure and a PMOS device comprising a second gate structure; a first stress liner, at least formed on both sides of the first gate structure of said NMOS device; a second stress liner, at least formed on both sides of the second gate structure of said PMOS device; wherein said first stress liner is a spin-on glass (SOG) film with tensile stress, said second stress liner is formed of a material that can introduce compressive stress into the channel of the PMOS device. The present invention can reduce the difficulty of the process of manufacturing dual stress liner using the same material, e.g. nitride, and can reduce influence of nitride having a high dielectric constant upon the device interconnect delay while still maintaining the tensile strain advantage. | 2012-10-18 |
20120261764 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first conductive type semiconductor substrate; a first conductive type semiconductor region provided thereon in which first conductive type first pillar regions and second conductive type second pillar regions alternately arranged; second conductive type second semiconductor regions provided on second pillar regions in an element region to be in contact with first pillar regions therein; gate electrodes each provided on adjacent second semiconductor regions and on one of the first pillar region interposed therebetween; third semiconductor regions functioning as a first conductive type source region provided in parts of the second semiconductor regions located under side portions of the gate electrodes; and a second conductive type resurf region which is a part of a terminal region surrounding the element region and which is provided on first pillar regions and second pillar regions in the part of the terminal regions. | 2012-10-18 |
20120261765 | HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS USING A MASKING REGIME PRIOR TO GATE PATTERNING - In a replacement gate approach in sophisticated semiconductor devices, the placeholder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack. | 2012-10-18 |
20120261766 | Compensated Isolated P-WELL DENMOS Devices - An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. | 2012-10-18 |
20120261767 | METHOD AND STRUCTURE FOR REDUCING GATE LEAKAGE CURRENT AND POSITIVE BIAS TEMPERATURE INSTABILITY DRIFT - Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides. | 2012-10-18 |
20120261768 | SRAM CELL WITH ASYMMETRICAL PASS GATE - A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region ( | 2012-10-18 |
20120261769 | METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL - A semiconductor device comprises a semiconductor substrate and a select gate structure over a first portion of the semiconductor substrate. The select gate structure comprises a sidewall forming a corner with a second portion of the semiconductor substrate and a charge storage stack over an area comprising the second portion of the semiconductor substrate, the sidewall, and the corner. A corner portion of a top surface of the charge storage stack is non-conformal with the corner, and the corner portion of the top surface of the charge storage stack has a radius of curvature measuring approximately one-third of a thickness of the charge storage stack over the second portion of the substrate or greater. A control gate layer is formed over the charge storage stack. A portion of the control gate layer conforms to the corner portion of the top surface of the charge storage stack. | 2012-10-18 |
20120261770 | METAL GATE STRUCTURE - A metal gate structure includes a high-K gate dielectric layer, an N-containing layer, a work function metal layer, and an N-trapping layer. The N-containing layer is positioned between the work function metal layer and the high-K gate dielectric layer. The N-trapping layer is positioned between the work function metal layer and the high-K gate dielectric layer, and the N-trapping layer contains no nitrogen or low-concentration nitrogen. | 2012-10-18 |
20120261771 | SEMICONDUCTOR STRUCTURES WITH DUAL TRENCH REGIONS AND METHODS OF MANUFACTURING THE SEMICONDUCTOR STRUCTURES - Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure. | 2012-10-18 |
20120261772 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device comprises a gate stack, a source region, a drain region, a contact plug and an interlayer dielectric, the gate stack being formed on a substrate, the source region and the drain region being located on opposite sides of the gate stack and embedded in the substrate, the contact plug being embedded in the interlayer dielectric, wherein the contact plug comprises a first portion which is in contact with the source region and/or drain region, the upper surface of the first portion is flushed with the upper surface of the gate stack, and the angle between a sidewall and a bottom surface of the first portion is less than 90°. There is also provided a method for manufacturing a semiconductor device. Not only the contact area between the first portion and the source region and/or the drain region can be increased, which facilitates reducing the contact resistance; but also the distance between the top of the first portion and the top of the gate stack can be increased, which facilitates reducing the possibility of short circuit between the first portion and the gate stack. | 2012-10-18 |
20120261773 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM OF PROCESSING SUBSTRATE - Disclosed is a semiconductor device that comprises a gate insulating film formed on a semiconductor substrate; a first conductive metal-containing film formed on the gate insulating film; a second conductive metal-containing film, formed on the first metal-containing film, to which aluminum is added; and a silicon film formed on the second metal-containing film. | 2012-10-18 |
20120261774 | MEMS PACKAGE OR SENSOR PACKAGE WITH INTRA-CAP ELECTRICAL VIA AND METHOD THEREOF - A MEMS device structure including a lateral electrical via encased in a cap layer and a method for manufacturing the same. The MEMS device structure includes a cap layer positioned on a MEMS device layer. The cap layer covers a MEMS device and one or more MEMS device layer electrodes in the MEMS device layer. The cap layer includes at least one cap layer electrode accessible from the surface of the cap layer. An electrical via is encased in the cap layer extending across a lateral distance from the cap layer electrode to the one or more MEMS device layer electrodes. An isolating layer is positioned around the electrical via to electrically isolate the electrical via from the cap layer. | 2012-10-18 |
20120261775 | MEMS microphone device and method for making same - The present invention discloses a MEMS microphone device and its manufacturing method. The MEMS microphone device includes: a substrate including a first cavity; a MEMS device region above the substrate, wherein the MEMS device region includes a metal layer, a via layer, an insulating material region and a second cavity; a mask layer above the MEMS device region; a first lid having at least one opening communicating with the second cavity, the first lid being fixed above the mask layer; and a second lid fixed under the substrate. | 2012-10-18 |
20120261776 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC LAYERS HAVING INSERTION LAYERS FOR USE IN SPIN TRANSFER TORQUE MEMORIES - A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, a free layer, and at least one damping reduction layer. The free layer has an intrinsic damping constant. The nonmagnetic spacer layer is between the pinned layer and the free layer. The at least one damping reduction layer is adjacent to at least a portion of the free layer and configured to reduce the intrinsic damping constant of the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 2012-10-18 |
20120261777 | Magnetoresistive Element and Method of Manufacturing the Same - A magnetoresistive element (and method of fabricating the magnetoresistive element) that includes a free ferromagnetic layer comprising a first reversible magnetization direction directed substantially perpendicular to a film surface, a pinned ferromagnetic layer comprising a second fixed magnetization direction directed substantially perpendicular to the film surface, and a nonmagnetic insulating tunnel barrier layer disposed between the free ferromagnetic layer and the pinned ferromagnetic layer, wherein the free ferromagnetic layer, the tunnel barrier layer, and the pinned ferromagnetic layer have a coherent body-centered cubic (bcc) structure with a (001) plane oriented, and a bidirectional spin-polarized current passing through the coherent structure in a direction perpendicular to the film surface reverses the magnetization direction of the free ferromagnetic layer. | 2012-10-18 |
20120261778 | SPIN-TORQUE MEMORY WITH UNIDIRECTIONAL WRITE SCHEME - Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme. | 2012-10-18 |
20120261779 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni. | 2012-10-18 |
20120261780 | BACKSIDE-ILLUMINATED IMAGE SENSOR AND FABRICATING METHOD THEREOF - A backside-illuminated image sensor and a fabricating method thereof are provided. The fabricating method includes the following steps. Firstly, a first substrate having a first side and a second side is provided, wherein a sensing structure is formed on the first side of the first substrate, and the sensing structure includes an alignment mark. Then, a second substrate is provided and bonded to the first side of the first substrate. Then, a light-transmissible structure is formed on the second side of the first substrate at a location corresponding to the alignment mark. Afterwards, an optical structure is positioned on the second side of the first substrate by referring to the light-transmissible structure and the alignment mark. | 2012-10-18 |
20120261781 | SIDEWALL FOR BACKSIDE ILLUMINATED IMAGE SENSOR METAL GRID AND METHOD OF MANUFACTURING SAME - The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature. | 2012-10-18 |
20120261782 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD OF PRODUCING THE SAME - The present invention provides a solid-state image pickup device that includes a plurality of photoelectric conversion units disposed in a semiconductor substrate, a first planarizing layer disposed at a first principal surface side of the semiconductor substrate where light enters, a color filter layer disposed on the first planarizing layer and including color filters each of which is provided for a corresponding photoelectric conversion unit, and a second planarizing layer disposed on the color filter layer for reducing a level difference between the color filters. In the solid-state image pickup device, a gap is disposed in a position corresponding to a boundary between the neighboring color filters in the color filter layer, the gap extending to the second planarizing layer, and a sealing layer for sealing the gap is disposed on the gap and the second planarizing layer. | 2012-10-18 |
20120261783 | BACK-SIDE ILLUMINATED IMAGE SENSOR PROVIDED WITH A TRANSPARENT ELECTRODE - A back-side illuminated image sensor formed from a thinned semiconductor substrate, wherein: a transparent conductive electrode, insulated from the substrate by an insulating layer, extends over the entire rear surface of the substrate; and conductive regions, insulated from the substrate by an insulating coating, extend perpendicularly from the front surface of the substrate to the electrode. | 2012-10-18 |
20120261784 | METHOD FOR FORMING A BACK-SIDE ILLUMINATED IMAGE SENSOR - A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) forming, from the front surface of the substrate, areas of same conductivity type as the substrate but of higher doping level, extending deep under the front surface, these areas being bordered with insulating regions orthogonal to the front surface; b) thinning the substrate from the rear surface to the vicinity of these areas and all the way to the insulating regions; c) partially hollowing out the insulating regions on the rear to surface side; and d) performing a laser surface anneal of the rear surface of the substrate. | 2012-10-18 |
20120261785 | SHARED MEMBRANE THERMOPILE SENSOR ARRAY - A thermopile sensor array is provided. The thermopile sensor array may include multiple pixels formed by multiple thermopiles arranged on a single common shared support membrane. A separation between the edge of the shared support membrane and the outermost thermopile(s) may be included to provide additional thermal isolation between the thermopile and an underlying silicon substrate. | 2012-10-18 |
20120261786 | SEMICONDUCTOR DEVICE, INK CARTRIDGE, AND ELECTRONIC DEVICE - A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit. | 2012-10-18 |
20120261787 | PASSIVE DEVICES FABRICATED ON GLASS SUBSTRATES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Passive devices fabricated on glass substrates, methods of manufacture and design structures are provided. The method includes forming an opaque or semi-opaque layer on at least a first side of a glass substrate. The method further includes forming one or more passive devices on the opaque or semi-opaque layer on a second side of the glass substrate. | 2012-10-18 |
20120261788 | SELF-ALIGNED AIRGAP INTERCONNECT STRUCTURES AND METHODS OF FABRICATION - Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer. | 2012-10-18 |