42nd week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130270578 | SEMICONDUCTOR DEVICE WITH HEAT REMOVAL STRUCTURE AND RELATED PRODUCTION METHOD - According to the invention, a semiconductor device composite structure is provided which comprises an initial substrate with discreet, integrated devices and a heat removal structure. The heat removal structure comprises: a bond layer which is attached to the initial substrate or the devices, a heat removal structure which is attached on the bond layer and which consists of a material with a specific thermal conductivity which is at least double the level of the average specific heat conductivity of the initial substrate or the devices, and one or more metallic thermal bridges which thermally connect the devices with the heat removal structure via the bond layer. The thermal bridges are designed as vertical through connections (vias) through the bond and heat removal structure. The invention furthermore relates to an associated production method. | 2013-10-17 |
20130270579 | Epitaxy Silicon on Insulator (ESOI) - Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region. | 2013-10-17 |
20130270580 | Flat Panel Display Device and Method of Manufacturing the Same - A flat panel display device and method of manufacturing the display device. The display device comprises a first substrate and a connection pad located along a side of the first substrate. A second substrate overlaps with the first substrate, wherein the second substrate does not overlap with an exposed portion of the first substrate. A first contact pad electrically couples the second substrate and the first substrate. A first distance from the side of the first substrate to a boundary between the exposed portion of the first substrate and the second substrate is greater than a second distance from the side of the first substrate to the first contact pad. The display device may be, for example, a touch capable display device that uses the first contact pad to transfer touch sensing signals from the second substrate to the first substrate. | 2013-10-17 |
20130270581 | MULTI-CHIP LIGHT EMITTER PACKAGES AND RELATED METHODS - Light emitter packages having multiple light emitter chips, such as light emitting diode (LED) chips, and related methods are provided. In one aspect, a light emitter package can include a submount, an array of light emitter chips disposed on a portion of the submount, and a lens provided over the submount and covering at least portions of the array. In some aspects, at least some of the light emitter chips can be adapted to emit light of a first dominant wavelength. In further aspects, at least some other light emitter chips are adapted to emit light of a second dominant wavelength that is different than the first dominant wavelength. In some aspects, the lens can be asymmetric. In some aspects, a collective center of the chips, or a center of an array of chips can be offset from a center of the asymmetric lens. | 2013-10-17 |
20130270582 | Display Device - Disclosed are a TFT array substrate for decreasing a bezel width and a display device including the same. The display device includes a first substrate including a display area (including a pixel formed in a pixel area defined by a gate line and a data line which intersect) and a non-display area that includes a built-in shift register connected to the gate line and a gate link part connected to the built-in shift register, a second substrate facing the first substrate, and a seal pattern formed in the non-display area of the first substrate in correspondence with an edge portion of the second substrate to facing-couple the first and second substrates. The seal pattern includes a first hardening area hardened by a first hardening process, and a second hardening area hardened by a second hardening process. | 2013-10-17 |
20130270583 | METHOD OF FORMING COPPER WIRING AND METHOD OF MANUFACTURING DISPLAY DEVICE - A method of forming a copper wiring includes forming a copper film on a substrate; forming a resist on the copper film in accordance with a predetermined pattern; forming an oxide film on the copper film on which the resist is formed; etching the copper film on which the oxide film is formed; and removing the resist after the etching of the copper film. | 2013-10-17 |
20130270584 | OPTOELECTRONIC PACKAGE AND METHOD FOR MAKING SAME - An optoelectronic package includes a substrate and a cover element bonded onto the substrate. The cover element defines a cavity for accommodating semiconductor chips and optoelectronic components. The cover element includes a first adhesive bonding area configured for receiving a first adhesive and being bonded with a predetermined region of the substrate by the first adhesive. The engagement of the cover element and the substrate defines a second adhesive bonding area. The second adhesive bonding area is configured for receiving a second adhesive and confining the second adhesive within a localized area. A method for making an optoelectronic package is also provided. | 2013-10-17 |
20130270585 | SYSTEM AND METHODS FOR WARM WHITE LED LIGHT SOURCE - An LED light emitter includes a single emitter structure having a substrate with a plurality of light emitting diodes (LEDs) arranged thereon, wherein the plurality of LEDs includes at least one first LED die that produces a first color light, and at least one second LED die that produces a second color light. The LED light emitter also includes a total internal reflection (TIR) lens positioned to collect light emitted from the single emitter structure and adapted to mix the light from the plurality of LEDs to produce a uniform light. The plurality of LEDs are selected such that the light output by the LED light emitter has a desired color temperature when an equal current is supplied to all of the plurality of LEDs. | 2013-10-17 |
20130270586 | Light Emitting Diode Package and Method of Manufacturing the Same - A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes. | 2013-10-17 |
20130270587 | REMOTE PHOSPHOR LED CONSTRUCTIONS - A white light source includes a short wavelength LED and a phosphor layer that emits light at longer visible wavelengths. A dichroic reflector transmits the longer wavelength light, and reflects some LED light onto the phosphor such that as light travels from the LED to the dichroic reflector it does not pass through the phosphor. The LED may emit blue light, and the dichroic reflector may transmit a second portion of the LED light, such that the light source output light includes both the second portion of the LED light and the longer wavelength phosphor light. The LED may be mounted on a flexible substrate having a cavity region and neighboring region, the LED being mounted in the cavity region. A dielectric layer may be thinner in the cavity region than in the neighboring region, or a hole may extend completely through the dielectric layer in the cavity region. | 2013-10-17 |
20130270588 | LEAD FRAME ASSEMBLY, LED PACKAGE AND LED LIGHT BAR - A lead frame assembly includes a surrounding frame and a plurality of lead frame sets arranged in a matrix. Each lead frame set includes spaced-apart first and second lead frames and a connecting structure interconnecting one of the lead frame sets to an adjacent lead frame set. Each lead frame set is further connected to the surrounding frame through the connecting structure thereof. A plurality of insulated bars are spacedly formed on a lead frame panel. Each insulated bar covers a corresponding row of the lead frame sets and exposes bottom surfaces of the first and second lead frames. Each insulated bar further covers portions of the surrounding frame that are adjacent to two opposite outermost ones of the lead frame sets. | 2013-10-17 |
20130270589 | OPTOELECTRONIC DEVICE WITH NON-CONTINUOUS BACK CONTACTS - An optoelectronic device is disclosed. The optoelectronic device comprises a semiconductor structure; a plurality of contacts on the front side of the semiconductor structure; and a plurality of non-continuous metal contacts on a back side of the semiconductor structure. In an embodiment, a plurality of non-continuous back contacts on an optoelectronic device improve the reflectivity and reduce the losses associated with the back surface of the device. | 2013-10-17 |
20130270590 | LED MODULE - An LED module comprises an LED and a lens matching with the LED. The lens comprises a light-guiding portion and a plurality of retaining portions protruded from the light-guiding portion. The LED includes a substrate, a first electrode and a second electrode mounted on the substrate. A plurality of through holes is defined in the first electrode and a second electrode, respectively. Each retaining portion includes a rugged portion. The retaining portions are inserted into the through holes correspondingly, and the rugged portion abuts the substrate. Glue is applied between the rugged portion and the substrate. | 2013-10-17 |
20130270591 | POLYCARBONATE COMPOSITIONS CONTAINING CONVERIONS MATERIAL CHEMISTRY AND HAVING ENHANCED OPTICAL PROPERTIES, METHODS OF MAKING AND ARTICLES COMPRISING THE SAME - In some embodiments, a composition comprises a bisphenol-A polycarbonate, wherein a molded article of the bisphenol-A polycarbonate has transmission level greater than or equal to 90.0% at 2.5 mm thickness as measured by ASTM D1003-00 and a yellow index (YI) less than or equal to 1.5 as measured by ASTM D1925. In some embodiments, light emitting device comprises: a lighting element located in a housing. The housing is formed from a plastic composition comprising: the polycarbonate composition and a conversion material. After the conversion material has been exposed to an excitation source, the conversion material has a luminescence lifetime of less than 10 | 2013-10-17 |
20130270592 | SUBMOUNT BASED SURFACE MOUNT DEVICE (SMD) LIGHT EMITTER COMPONENTS AND METHODS - Submount based surface mount design (SMD) light emitter components and related methods are disclosed. In one aspect, a method of providing a submount based light emitter component can include providing a ceramic based submount, providing at least one light emitter chip on the submount, providing at least one electrical contact on a portion of the submount, and providing a non-ceramic based reflector cavity on a portion of the submount. | 2013-10-17 |
20130270593 | SAPPHIRE SUBSTRATE AND SEMICONDUCTOR LIGHT EMITTING DEVICE - A sapphire substrate having a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device comprises a plurality of projections on the principal surface. Each of the projections has a bottom that has a substantially polygonal shape. Each side of the bottom of the projections has a depression in its center. Vertexes of the bottoms of the respective projections extend in a direction that is within a range of ±10 degrees of a direction that is rotated clockwise by 30 degrees from a crystal axis “a” of the sapphire substrate. | 2013-10-17 |
20130270594 | LIGHT-EMITTING DIODE PACKAGE - A light-emitting diode (LED) package comprising a carrier, an LED chip and a phosphor glue is provided. The carrier has a recess, an upper surface, and a ring-shape rough surface connected to a top edge of the recess. The LED chip is disposed within the recess. The phosphor glue fills up the recess and over the upper surface of the carrier. An edge of the phosphor glue contacts the ring-shape rough surface. | 2013-10-17 |
20130270595 | LIGHT EMITTING DIODE DIE AND LIGHT EMITTING DIODE PACKAGE INCORPORATING THE SAME - An LED die comprises a substrate and an epitaxial layer formed thereon. The epitaxial layer comprises a first n-type semiconductor layer, an active layer and a p-type semiconductor layer grown on the substrate in sequence. The LED die defines a receiving recess formed in a center of a top face of the p-type semiconductor layer. The receiving recess extends through the p-type semiconductor layer, the active layer and into the n-type semiconductor layer along a top-to-bottom direction of the epitaxial layer. A pair of p-pads are located at two opposite sides of the p-type semiconductor layer, respectively. A first n-pad is received in the receiving recess and located on the n-type layer. | 2013-10-17 |
20130270596 | LIGHT SENSORS AND SOURCES COMPRISING AT LEAST ONE MICROCAVITY WITH A LOCALIZED TAMM PLASMON MODE - A light source or sensor including: a stack of dielectric or semiconductive layers includes an alternation in a vertical direction of layers of high refractive index and of low refractive index forming an interference mirror, and presenting a top layer of high refractive index; at least one first metal pellet deposited or transferred on the top layer of the stack of layers to form a structure supporting a first Tamm plasmon mode that is spatially localized in at least one lateral direction perpendicular to the vertical direction; and at least one light emitter or detector arranged inside the stack of layers under the metal pellet and at a depth corresponding to a local maximum of the electric field of the Tamm plasmon mode to emit or detect radiation at the resonant wavelength thereof. | 2013-10-17 |
20130270597 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM WITH THE SAME - A light emitting device including a light emitting structure having a first conduction type semiconductor layer, an active layer, and a second conduction type semiconductor layer, a metal filter having an irregular pattern disposed on the light emitting structure, a transparent conductive layer disposed between the light emitting structure and the metal filter, and openings disposed between the irregular patterns in the metal filter. | 2013-10-17 |
20130270598 | LIGHT EMITTING DEVICE HAVING AUTO-CLONING PHOTONIC CRYSTAL STRUCTURES - A light emitting device having auto-cloning photonic crystal structures comprises a substrate, a first semiconductor layer, an active emitting layer, a second semiconductor layer and a saw-toothed multilayer film comprising auto-cloning photonic crystal structures. The saw-toothed multilayer film provides a high reflection interface and a diffraction mechanism to prevent total internal reflection and enhance light extraction efficiency. | 2013-10-17 |
20130270599 | LIGHT-EMITTING DEVICE - The present application is related to a light-emitting device. The present application illustrates a vertical light-emitting device in one embodiment, comprising: a conductive substrate includes a through-hole, a patterned semiconductor structure disposed on a first surface of the substrate, a first bonding pad and a second bonding pad disposed on a second surface of the substrate, a conductive line passing through the through-hole connecting electrically the semiconductor structure layer, and an insulation layer on at least one sidewall of the through-hole insulates the conductive line form the substrate. | 2013-10-17 |
20130270600 | Functionalization of a Substrate - A method of increasing a work function of an electrode is provided. The method comprises obtaining an electronegative species from a precursor using electromagnetic radiation and reacting a surface of the electrode with the electronegative species. An electrode comprising a functionalized substrate is also provided. | 2013-10-17 |
20130270601 | PACKAGE STRUCTURE OF SEMICONDUCTOR LIGHT EMITTING DEVICE - A package structure of a semiconductor light emitting device is provided. The packaging structure comprises a substrate, a circuit board, a semiconductor light emitting device and a coating layer is provided. The circuit board has an opening portion disposed on the substrate for exposing a surface of the substrate. The semiconductor light emitting device is disposed on the surface of the substrate exposed by the opening portion. The coating layer covers the sidewalls of the opening portion and the circuit board. | 2013-10-17 |
20130270602 | LIGHT-EMITTING DIODE PACKAGE - The present invention provides an LED packaging structure comprising a leadframe, including: a first electrode including a first functional area and a first extension area extending from the first functional area: a second electrode including a second functional area and a second extension area extending from the second functional area, a cup-shaped insulator, wrapping the first and second electrodes, including an emitting concave formed at the inner side of the cup-shaped insulator and exposing the upper surfaces of the first and second functional areas, wherein portions of the first and second extension areas are exposed from the bottom of the outer side of the cup-shaped insulator; an interposed spacer physically separating the first and second electrodes; and an electroplating layer partially covering the surfaces of the first and second electrodes. | 2013-10-17 |
20130270603 | LIGHT EMITTING DIODE - A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are orderly stacked on the substrate. The second semiconductor layer is covered with stepped three-dimensional nano-structures in a particular shape, which act to reabsorb wide-angle incident light and re-emit the light at narrower angles of incidence, to increase the light-giving properties of the light emitting diode | 2013-10-17 |
20130270604 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A light emitting device includes a light emitting layer made of semiconductor; an upper electrode including a bonding electrode capable of connecting a wire thereto and a thin-wire electrode surrounding the bonding electrode with a spacing and including a junction with the bonding electrode, and a current diffusion layer provided between the light emitting layer and the upper electrode and made of semiconductor, the current diffusion layer including a recess that is formed in a non-forming region of the upper electrode and capable of emitting light emitted from the light emitting layer. | 2013-10-17 |
20130270605 | APPARATUS AND METHOD FOR TRANSIENT ELECTRICAL OVERSTRESS PROTECTION - An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation. The holes- or electrons-enhanced conduction protection circuit includes a bi-directional bipolar device having an emitter/collector, a base, and a collector/emitter; a first bipolar transistor having an emitter electrically coupled to the first node, a base electrically coupled to the emitter/collector of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor; and a second bipolar transistor having an emitter electrically coupled to the second node, a base electrically coupled to the collector/emitter of the bipolar device, and a collector electrically coupled to the base of the bipolar transistor. | 2013-10-17 |
20130270606 | Semiconductor Device with Integrated Breakdown Protection - A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path. | 2013-10-17 |
20130270607 | Semiconductor Device Channel System and Method - A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not. | 2013-10-17 |
20130270608 | HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS - Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed. | 2013-10-17 |
20130270609 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device is provided with a plurality of photoelectric converting portions each having a photosensitive region and an electric potential gradient forming region, and which are juxtaposed so as to be along a direction intersecting with a predetermined direction, a plurality of buffer gate portions each arranged corresponding to a photoelectric converting portion and on the side of the other short side forming a planar shape of the photosensitive region, and accumulates a charge generated in the photosensitive region of the corresponding photoelectric converting portion, and a shift register which acquires charges respectively transferred from the plurality of buffer gate portions, and transfers the charges in the direction intersecting with the predetermined direction, to output the charges. The buffer gate portion has at least two gate electrodes to which predetermined electric potentials are respectively applied so as to increase potential toward the predetermined direction. | 2013-10-17 |
20130270610 | SEMICONDUCTOR STRUCTURE, METHOD OF OPERATING SAME, AND PRODUCTION METHOD - A semiconductor structure includes a semiconductor layer of a first conductivity type, a photosensitive zone configured such that photogenerated charges may be accumulated in a first potential well, a region of the first conductivity type, formed in the semiconductor layer, for temporarily storing the photogenerated charges in a second potential well, a transfer gate between the region of the second conductivity type and the photosensitive zone for defining a potential barrier between the first and second potential wells during a non-transfer phase, and for eliminating the potential barrier between the first and second potential wells during a transfer phase, and a readout structure for reading out the temporarily stored photogenerated charges, which includes a JFET, the gate of which is formed by the region of the second conductivity type. | 2013-10-17 |
20130270611 | SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS - A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron. | 2013-10-17 |
20130270612 | Non-Planar FET and Manufacturing Method Thereof - The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET. | 2013-10-17 |
20130270613 | METHOD OF TRIMMING SPACERS AND SEMICONDUCTOR STRUCTURE THEREOF - A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode. | 2013-10-17 |
20130270614 | FORMATION OF A TRENCH SILICIDE - Systems and methods are presented for controlling formation of a silicide region. A selective etch layer is utilized to control formation of a trench opening, and further can be utilized to open up a trench to facilitate correct exposure of an active Si region to subsequently form a silicide. Issues regarding over-dimension, under-dimension, and misalignment of a trench are addressed. The selective etch material is chosen to facilitate control of the trench formation and also to enable removal of the selective etch layer without affecting any adjacent structures/material. The selective etch layer can be an oxide, for example aluminum oxide, Al | 2013-10-17 |
20130270615 | METHOD FOR MAKING TRANSISTORS - A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth. | 2013-10-17 |
20130270616 | SEMICONDUCTOR DEVICE - A semiconductor device preventing a defect in manufacturing process, such as disconnection of a film to be formed. Further, a semiconductor device with favorable electric characteristics and high performance can be provided. In a top-gate semiconductor device in which a source electrode and a drain electrode are provided in contact with an oxide semiconductor film, a sidewall insulating film is provided to fill a recessed portion between the source electrode and a gate electrode and a recessed portion between the drain electrode and the gate electrode, which cause disconnection of a film to be formed on and in contact with the gate electrode. Further, the sidewall insulating film is provided so that a recessed portion is not formed between the sidewall insulating film and another film included in the semiconductor device. | 2013-10-17 |
20130270617 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer. | 2013-10-17 |
20130270618 | TOUCH PANEL AND FABRICATING METHOD THEREOF - A touch panel and fabricating method thereof are provided. The patterned transparent conductive layer, disposed on the substrate, includes first electrodes. The photo-sensing layers are disposed on the first electrodes. The first patterned conductive layer includes gate electrodes, scan lines and second electrodes. The gate electrodes and the scan lines are disposed on the substrate. The second electrodes are disposed on the photo-sensing layers. The first electrodes, the photo-sensing layers and the second electrodes constitute photo-sensors. The second patterned conductive layer includes source electrodes and drain electrodes, wherein the gate electrodes, the channel layers, the source electrodes and the drain electrodes constitute read-out transistors and each of the read-out transistors is electrically connected to the corresponding photo-sensor respectively. | 2013-10-17 |
20130270619 | SEMICONDUCTOR DEVICE COMPRISING FERROELECTRIC ELEMENTS AND FAST HIGH-K METAL GATE TRANSISTORS - Ferroelectric circuit elements, such as field effect transistors or capacitors, may be formed on the basis of hafnium oxide, which may also be used during the fabrication of sophisticated high-k metal gate electrode structures of fast transistors. To this end, the hafnium-based oxide having appropriate thickness and material composition may be patterned at any appropriate manufacturing stage, without unduly affecting the overall process flow for fabricating a sophisticated high-k metal gate electrode structure. | 2013-10-17 |
20130270620 | STRUCTURE AND METHOD FOR FINFET INTEGRATED WITH CAPACITOR - The present disclosure provides one embodiment of a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T | 2013-10-17 |
20130270621 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND FABRICATION METHOD THEREOF - A nonvolatile semiconductor storage device has a plurality of memory strings in which electrically rewritable memory cells are connected in series. The memory strings have word-line electroconductive layers laminated at a prescribed interval to sandwich an interlayer insulating film onto a semiconductor substrate and through holes that penetrate through the word-line electroconductive layers and the interlayer insulating films. The gate insulating film is formed along an inner wall of the through holes and includes a charge-accumulating film. The columnar semiconductor layer is formed inside the through holes to sandwich the gate insulating film along with the word-line electroconductive layer. The columnar semiconductor layer contains carbon, oxygen, or nitrogen. | 2013-10-17 |
20130270622 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE - Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion. | 2013-10-17 |
20130270623 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device has plural memory cells arranged on a semiconductor substrate, plural select transistors for selecting the memory cell for carrying out record or read, and an insulating film arranged between adjacent memory cells and between adjacent select transistors. The memory cell and select cell transistors include gates extending the same distance from the substrate, and an insulator between adjacent select cell transistors, between the select cell transistors and the memory transistors, and between adjacent memory transistors, the height of the insulator between the select cell transistors is higher than between the select cell transistors and the memory transistors, and between adjacent memory transistors. An insulating layer deposited thereover is deposited having an in situ flatness, without further planarization. | 2013-10-17 |
20130270624 | GATE STRUCTURE IN NON-VOLATILE MEMORY DEVICE - A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced. | 2013-10-17 |
20130270625 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A three-dimensional (3D) semiconductor memory device includes a stack structure, a channel structure, and a vertical insulator. The stack structure includes gate patterns and insulating patterns which are alternately and repeatedly stacked on a substrate. A channel structure penetrates the stack structure and is connected to the substrate. A vertical insulator includes a high-k dielectric layer. The vertical insulator is covered by the channel structure and the high-k dielectric pattern of the vertical insulator is in contact with the gate patterns. | 2013-10-17 |
20130270626 | INTEGRATED CIRCUIT SELF ALIGNED 3D MEMORY ARRAY AND MANUFACTURING METHOD - A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers. | 2013-10-17 |
20130270627 | FinFET NON-VOLATILE MEMORY AND METHOD OF FABRICATION - A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer. | 2013-10-17 |
20130270628 | Replacement Channels - The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure. | 2013-10-17 |
20130270629 | SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR - Disclosed herein is a device that includes: a semiconductor substrate; a first semiconductor pillar having a side surface that is substantially perpendicular to a main surface of the semiconductor substrate; an insulator pillar having a side surface that is substantially perpendicular to the main surface of the semiconductor substrate and a top surface that is substantially parallel to the main surface of the semiconductor substrate; a first gate electrode covering the side surface of the first semiconductor pillar with intervention of a first gate insulation film; an extended gate electrode covering the side surface of the insulator pillar, the extended gate electrode being configured integrally with the first gate electrode; and a conductive film formed on the top surface of the insulator pillar, the conductive film being in contact with the extended gate electrode in a position above the top surface of the insulator pillar. | 2013-10-17 |
20130270630 | METHOD FOR MANUFACTURING A POWER DEVICE BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE, IN PARTICULAR HAVING A FIELD PLATE VERTICAL STRUCTURE AND CORRESPONDING DEVICE - An embodiment of a method for manufacturing a power device integrated on a semiconductor substrate comprising the steps of: growth on said substrate of an epitaxial layer; photo-lithography and etching of said epitaxial layer for the formation of at least one deep trench; deposition of a dielectric layer with partial filling of the at least one trench; complete filling of the at least one trench with a layer of sacrificial material; selective etching of the dielectric layer with consequent retrocession below the layer of sacrificial material; selective etching of the layer of sacrificial material with consequent formation of an empty region within the at least one trench; growth of a layer of gate oxide; formation of at least one gate region, of at least one buried source region, of at least one body region and of at least one source region; deposition of a dielectric layer; simultaneous formation of at least one gate contact, at least one body/source contact and at least one buried source contact; formation of a source contact region and of a gate contact region through deposition, masking and etching of a metallisation layer. An embodiment of the method also comprises the step of formation of the at least one gate region and of the at least one buried source region, electrically insulated, through a single deposition of a conductive filling material on the epitaxial layer, on the vertical walls of the trench and within the empty region; and through etching of the conductive filling material forming a first spacer and a second spacer, suitable for serving as a gate electrode and forming a buried source electrode within the empty region. | 2013-10-17 |
20130270631 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer. | 2013-10-17 |
20130270632 | SEMICONDUCTOR DEVICE HAVING A FLOATING SEMICONDUCTOR ZONE - A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region. | 2013-10-17 |
20130270633 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view. With respect to a column formed by the body contact regions aligned in a predetermined column direction, the trenches are disposed at both sides in a row direction orthogonal to the column direction in a plan view, extend in the column direction, and form meandering lines each connecting a plurality of curved portions so that a predetermined gap in the row direction is formed respectively between adjacent trenches extending in the column direction and between the trenches and the body contact regions. | 2013-10-17 |
20130270634 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate. A low voltage device is also formed in the substrate. The high voltage device includes a drift region, a gate, a source, a drain, and a mitigation region. The mitigation region has a second conductive type, and is formed in the drift region between the gate and drain. The mitigation region is formed by a process step which also forms a lightly doped drain (LDD) region in the low voltage device. | 2013-10-17 |
20130270635 | Semiconductor Device with False Drain - An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic. | 2013-10-17 |
20130270636 | Transistor Having An Isolated Body For High Voltage Operation - The present application discloses various implementations of a transistor having an isolated body for high voltage operation. In one exemplary implementation, such a transistor comprises a deep well implant having a first conductivity type disposed in a substrate having a second conductivity type opposite the first conductivity type. The transistor includes a source-side well and a drain-side well of the first conductivity type. The source-side well and the drain-side well are electrically coupled to the deep well implant. The deep well implant, the source-side well, and the drain-side well electrically isolate a body of the transistor from the substrate. | 2013-10-17 |
20130270637 | SEMICONDUCTOR DEVICE - A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region. | 2013-10-17 |
20130270638 | STRAINED SOI FINFET ON EPITAXIALLY GROWN BOX - A semiconductor structure includes an epitaxial insulator layer located on a substrate. A fin structure is located on the epitaxial insulator layer, where at least one epitaxial source-drain region having an embedded stressor is located on the epitaxial insulator layer and abuts at least one sidewall associated with the fin structure. The epitaxial source-drain region having the embedded stressor provides stress along the fin structure such that the provided stress is based on a lattice mismatch between the epitaxial source-drain region, and both the epitaxial insulator layer and the one side-wall associated with the fin structure. | 2013-10-17 |
20130270639 | FinFET Design with Reduced Current Crowding - An integrated circuit structure includes an integrated circuit structure includes a substrate, insulation regions over the substrate, and a fin field-effect transistor (FinFET). The FinFET includes a plurality of fins over the substrate, wherein each of the plurality of fins comprises a first fin portion and a second fin portion, a gate stack on a top surface and sidewalls of the first fin portion of each of the plurality of fins, an epitaxial semiconductor layer comprising a portion directly over the second fin portion of each of the plurality of fins, and sidewall portions directly over the insulation regions, and a silicide layer on, and having an interface with, the epitaxial layer, wherein a peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of peripherals of the plurality of fins is greater than 1. | 2013-10-17 |
20130270640 | SEMICONDUCTOR DEVICE - A semiconductor device includes a SOI substrate including a silicon substrate, an oxide layer on the silicon substrate, and a silicon layer on the oxide layer; a source region and a drain region formed in the silicon layer; and an acceptor-doped layer formed between the oxide layer and the silicon substrate, the acceptor-doped layer being doped with acceptors. | 2013-10-17 |
20130270641 | METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES SO AS TO TUNE THE THRESHOLD VOLTAGE OF SUCH DEVICES - Disclosed herein are various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate to define at least one fin (or fins) for the device, prior to forming a gate structure above the fin (or fins), performing a first epitaxial growth process to grow a first semiconductor material on exposed portions of the fin (or fins) and forming the gate structure above the first semiconductor material on the fin (or fins). | 2013-10-17 |
20130270642 | Pseudo Butted Junction Structure for Back Plane Connection - Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate. | 2013-10-17 |
20130270643 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer. | 2013-10-17 |
20130270644 | REPLACEMENT GATE STRUCTURES AND METHODS OF MANUFACTURING - Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further includes segmenting the continuous replacement gate structure into separate replacement gate structures. The method further includes forming insulator material between the separate replacement gate structures. | 2013-10-17 |
20130270645 | WORKFUNCTION METAL STACKS FOR A FINAL METAL GATE - Transistor devices are formed with a pMOS and an nMOS workfunction stack of substantially equal thickness after gate patterning. Embodiments include forming n-type and p-type areas in a substrate, forming a pMOS workfunction metal stack layer on both areas, forming a hardmask layer on the pMOS workfunction metal stack layer on the n-type area, removing the pMOS workfunction metal stack layer from the p-type area, forming an nMOS workfunction metal stack layer on the p-type area and on the hardmask layer, and removing the nMOS workfunction metal stack layer from the hardmask layer. | 2013-10-17 |
20130270646 | INTEGRATED CIRCUITS HAVING IMPROVED METAL GATE STRUCTURES AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a PFET trench in a PFET region and an NFET trench in an NFET region of an interlayer dielectric material on a semiconductor surface. The NFET trench is partially filled with an N-type work function metal layer to define an inner cavity. The PFET trench and the inner cavity in the NFET trench are partially filled with a P-type work function metal layer to define a central void in each trench. In the method, the central voids are filled with a metal fill to form metal gate structures. A single recessing process is then performed to recess portions of each metal gate structure within each trench to form a recess in each trench above the respective metal gate structure. | 2013-10-17 |
20130270647 | STRUCTURE AND METHOD FOR NFET WITH HIGH K METAL GATE - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal. | 2013-10-17 |
20130270648 | SEMICONDUCTOR DEVICES WITH SELF-ALIGNED SOURCE DRAIN CONTACTS AND METHODS FOR MAKING THE SAME - Replacement metal gates well suited for self-aligned contact formation are made by replacing the dummy gate with a recessed polysilicon layer and then effecting an aluminum-polysilicon substitution. The resulting upper polysilicon layer is easily removed from the recessed aluminum layer, which can then be protected with a protective dielectric layer for subsequent formation of a source or drain contact hole. | 2013-10-17 |
20130270649 | BIPOLAR TRANSISTOR MANUFACTURING METHOD - A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench. | 2013-10-17 |
20130270650 | RESISTOR AND MANUFACTURING METHOD THEREOF - A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously. | 2013-10-17 |
20130270651 | Sidewall-Free CESL for Enlarging ILD Gap-Fill Window - An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon. | 2013-10-17 |
20130270652 | Apparatus for FinFETs - A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin. | 2013-10-17 |
20130270653 | Non-Uniform Semiconductor Device Active Area Pattern Formation - In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc. | 2013-10-17 |
20130270654 | SEMICONDUCTOR DEVICE WITH REDUCED CONTACT RESISTANCE AND METHOD OF MANUFACTURING THEREOF - A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface. | 2013-10-17 |
20130270655 | SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES - A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures. | 2013-10-17 |
20130270656 | REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES - The present disclosure is generally directed to various replacement gate structures for semiconductor devices. One illustrative gate structure disclosed herein includes, among other things, a gate insulation layer and a layer of gate electrode material with a substantially horizontal portion having a first thickness and a substantially vertical portion having a second thickness that is less than the first thickness. Furthermore, the substantially horizontal portion of the layer of gate electrode material is positioned adjacent to a bottom of the replacement gate structure and above at least a portion of the gate insulation layer, and the substantially vertical portion is positioned adjacent to sidewalls of the replacement gate structure. | 2013-10-17 |
20130270657 | MICROMACHINED MONOLITHIC 6-AXIS INERTIAL SENSOR - The device layer of a 6-degrees-of-freedom (6-DOF) inertial measurement system can include a single proof-mass 6-axis inertial sensor formed in an x-y plane, the inertial sensor including a main proof-mass section suspended about a single, central anchor, the main proof-mass section including a radial portion extending outward towards the edge of the inertial sensor, a central suspension system configured to suspend the 6-axis inertial sensor from the single, central anchor, and a drive electrode including a moving portion and a stationary portion, the moving portion coupled to the radial portion, wherein the drive electrode and the central suspension system are configured to oscillate the 6-axis inertial sensor about a z-axis normal to the x-y plane. | 2013-10-17 |
20130270658 | METHODS FOR PRODUCING A CAVITY WITHIN A SEMICONDUCTOR SUBSTRATE - A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed. | 2013-10-17 |
20130270659 | ANGULAR VELOCITY SENSOR - An angular velocity sensor for detecting an angular velocity includes a substrate having the stationary portion, two pair of driver weights, two detector weights, and a detector electrode. The angular velocity is detected by using a differential signal output indicating a variation in capacitances. When the absolute value of a de-coupling ratio (=(fanti−fin)/fanti) is greater than or equal to 0.07, the occurrence of the anti-phase mode movement can be prevented so as to prevent the occurrence of the output error of the gyro sensor and detect the angular velocity more precisely. | 2013-10-17 |
20130270660 | SEALED PACKAGING FOR MICROELECTROMECHANICAL SYSTEMS - One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit, wherein the microelectromechanical layer includes a cap comprising a membrane that extends to the integrated circuit. | 2013-10-17 |
20130270661 | Magnetoresistive random access memory cell design - A new magnetic memory cell comprises a perpendicular-anisotropy tunneling magnetic junction (TMJ) and a fixed in-plane spin-polarizing layer, which is separated from the perpendicular-anisotropy data storage layer of tunneling magnetic junction by a non-magnetic layer. The non-magnetic layer can be made of metallic or dielectric materials. | 2013-10-17 |
20130270662 | IMAGE SENSOR OF CURVED SURFACE - A method for manufacturing an image sensor, including the steps of: forming elementary structures of an image sensor on the first surface of a semiconductor substrate; installing a handle on the first surface; defining trenches in the handle, the trenches forming a pattern in the handle; and installing, on a hollow curved substrate, the obtained device on the free surface side of the handle, the pattern being selected according to the shape of the support surface. | 2013-10-17 |
20130270663 | ANTI-REFLECTIVE LAYER FOR BACKSIDE ILLUMINATED CMOS IMAGE SENSORS - A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method includes depositing a metal oxide anti-reflection laminate on the first surface of the substrate. The metal oxide anti-reflection laminate includes one or more composite layers of thin metal oxides stacked over the photodiode. Each composite layer includes two or more metal oxide layers: one metal oxide is a high energy band gap metal oxide and another metal oxide is a high refractive index metal oxide. | 2013-10-17 |
20130270664 | FREE-STANDING TWO-SIDED DEVICES - Devices having features deposited on two sides of a device substrate and methods for making the same. The devices are useful, for example, as the components in a macroelectronic system. In a preferred embodiment, the devices are photosensors having a plurality of electrodes patterned on a first side of the device and an electromagnetic interference filter patterned on a second side of the device. The method facilitates the fabrication of two-sided devices through the use of an immobilizing layer deposited on top of devices patterned on a first side of a device substrate; flipping the device substrate; processing the second side of the device substrate to produce patterned features on the second side of the device substrate; and releasing the devices having patterned elements on two sides of each device. | 2013-10-17 |
20130270665 | IMAGE SENSOR AND IMAGE CAPTURE APPARATUS - In an image sensor in which each microlens of a microlens array is disposed at a position corresponding to each pixel on a side to which light flux is incident, a layer formed of a member different from a member constituting the microlens array is disposed on the side of the microlens array to which light flux is incident, and a surface of the layer formed of the different member has a phase structure optically -opposite to that of the microlens array. | 2013-10-17 |
20130270666 | PHOTODIODE ARRAY - This photodiode array | 2013-10-17 |
20130270667 | Metal Grid in Backside Illumination Image Sensor Chips and Methods for Forming the Same - A method includes forming a plurality of image sensors on a front side of a semiconductor substrate, and forming a dielectric layer on a backside of the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The dielectric layer is patterned into a plurality of grid-filling regions, wherein each of the plurality of grid-filling regions overlaps one of the plurality of image sensors. A metal layer is formed on top surfaces and sidewalls of the plurality of grid-filling regions. The metal layer is etched to remove horizontal portions of the metal layer, wherein vertical portions of the metal layer remain after the step of etching to form a metal grid. A transparent material is filled into grid openings of the metal grid. | 2013-10-17 |
20130270668 | TRENCHED SEMICONDUCTOR STRUCTURE - A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate. A plurality of active region trenches and a termination region trench are formed in the epitaxial layer. The ion implantation layer is formed in the active region trenches by doping impurities of a second conductive type. The termination region dielectric layer covers the termination region trench. The active region dielectric layer covers the ion implantation region. The first polysilicon layer covers the active region dielectric layer and fills the active region trenches. The depth of the termination region trench is greater than that of the active region trenches and close to that of the depletion region under reverse breakdown. | 2013-10-17 |
20130270669 | SEMICONDUCTOR STRUCTURE WITH DISPERSEDLY ARRANGED ACTIVE REGION TRENCHES - A semiconductor structure with dispersedly arranged active region trenches is provided. The semiconductor structure comprises a semiconductor substrate, an epitaxial layer, and an active region dielectric layer. The semiconductor substrate is doped with impurities of a first conductive type having a first impurity concentration. The epitaxial layer is doped with impurities of the first conductive type having a second impurity concentration and is formed on the semiconductor substrate. The epitaxial layer has a plurality of active region trenches formed therein being arranged in a dispersed manner. The active region dielectric layer covers a bottom and a sidewall of the active region trenches. Wherein, the active region trench has an opening in a tetragonal shape on a surface of the epitaxial layer, and the first impurity concentration is greater than the second impurity concentration. | 2013-10-17 |
20130270670 | SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIA INTERCONNECT - The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure. | 2013-10-17 |
20130270671 | Capacitor Array Layout Arrangement for High Matching Methodology - Some embodiments relate a capacitor array arranged on a semiconductor substrate. The capacitor array includes an array of unit capacitors arranged in a series of rows and columns. An interconnect structure couples unit capacitors of the array to establish a plurality of capacitor elements. The respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances. In establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate. Other methods and devices are also disclosed. | 2013-10-17 |
20130270672 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes first and second storage electrodes formed to be spaced apart from each other on a substrate, an insulating continuous support pattern connected to top surfaces of the first and second storage electrodes, a storage dielectric layer formed to cover the first and second storage electrodes and the continuous support pattern, and a plate electrode formed on the storage dielectric layer. The continuous support pattern includes a first contact part connected to the top surface of the first storage electrode, a second contact part connected to the top surface of the second storage electrode, and a connection part connecting the first and second contact parts with each other. | 2013-10-17 |
20130270673 | DOPED ELECTRODES FOR DRAM APPLICATIONS - A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode layers are conductive molybdenum oxide. | 2013-10-17 |
20130270674 | ON-CHIP CAPACITOR STRUCTURE - At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit. | 2013-10-17 |
20130270675 | ON-CHIP CAPACITORS AND METHODS OF ASSEMBLING SAME - An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes. | 2013-10-17 |
20130270676 | METAL-INSULATOR-METAL (MIM) CAPACITOR WITH INSULATOR STACK HAVING A PLURALITY OF METAL OXIDE LAYERS - Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack. | 2013-10-17 |
20130270677 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having a principal surface, a first conductor formed on the semiconductor substrate and including a conductive film having a first side wall portion and a first bottom surface portion both of which are continuously formed on a first trench having a first width in a direction parallel to the principal surface, and a second conductor formed on the semiconductor substrate and including a conductive film having a second side wall portion and a second bottom surface portion both of which are continuously formed on a second trench having a second width in a direction parallel to the principal surface, the second width being larger than the first width. | 2013-10-17 |