42nd week of 2008 patent applcation highlights part 59 |
Patent application number | Title | Published |
20080256346 | CENTRAL PROCESSING UNIT HAVING BRANCH INSTRUCTION VERIFICATION UNIT FOR SECURE PROGRAM EXECUTION - Provided are a central processing unit (CPU) and method for executing a branch instruction of a CPU, which can protect user's data by preventing an error due to a computer virus and a hacker is provided. The CPU includes: a branch instruction verification unit which verifies whether a branch instruction is valid; and a branch instruction execution unit which executes the branch instruction when the branch instruction is valid. The method includes: verifying whether the branch instruction is valid; and not executing the branch instruction when the branch instruction is invalid. | 2008-10-16 |
20080256347 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PATH-CORRELATED INDIRECT ADDRESS PREDICTIONS - A method, system, and computer program product are provided, for maintaining a path history register of register indirect branches. A set of bits is generated based on a set of target address bits using a hit selection and/or a hash function operation, and the generated set of bits is inserted into a path history register by shifting bits in the path history register and/or applying a hash operation, information corresponding to prior history is removed from the path history register, using a shift out operation and/or a hash operation. The path, history register is used to maintain a recent target, table and generate register-indirect branch target address predictions based on path history correlation between register-indirect branches captured by the path history register. | 2008-10-16 |
20080256348 | METHOD FOR CONFIGURATION OF A PROCESSING UNIT - A method for configuration of an Auxiliary Processing Unit (APU) of multiprocessor system is presented. The multiprocessor system has at least a Main Processing Unit (MPU) coupled to the APU via a communication link. The APU has at least a first memory and a second memory. The method includes a plurality of steps. At step the first memory is divided into an application sector, a boot sector and a common sector. At another step interrupts of the APU except interrupt/s that is/are being received via the communication link are disabled. At a further step interrupt vector/s pertaining to the communication link is/are mapped to the boot sector of the first memory. At another step a configuration code is received selectively into the application sector of the first memory and into the second memory. At a further step the interrupt/s that is/are being received via the communication link are disabled. At a further step the common sector of the first memory is updated from the second memory. | 2008-10-16 |
20080256349 | SYSTEM AND METHOD OF ENABLING USE OF SOFTWARE APPLICATIONS USING STORED SOFTWARE LICENSING INFORMATION - A system and method of enabling use of software applications using stored software licensing information is disclosed. In one form, a method of enabling use of a software application is disclosed. The method can include accessing a first software licensing information of a first software application within a non-volatile memory of an information handling system. The first licensing information can be stored in association with an order fulfillment process. The method can also include executing an initialization routine in association with a BIOS of the information handling system. In one form, the initialization routine can be operable to initiate accessing the software licensing information from the non-volatile memory to enable use of the first software application. | 2008-10-16 |
20080256350 | MOTHERBOARD, INFORMATION PROCESSOR, SETTING METHOD AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH SETTING PROGRAM IS STORED - A motherboard can be installed commonly in each of a plurality of electronic devices of various types different in configuration without modifying the BIOS setting by comprising a setting information retaining section retaining setting information for a setting process for each electronic device; a specification information obtaining section obtaining specification information for specifying the type of each electronic device; a modifying information retaining section retaining modification information for modifying the setting information according to the type of each electronic device; a setting information modifying section modifying, on the basis of the specification information and the modification information retained, the setting information according to the type of the device in which the motherboard is installed; and a setting process performing section for performing the setting process for the device on the basis of the modified setting information. | 2008-10-16 |
20080256351 | BIOS configuration and management - The present invention provides a system and method for a modular and enhanced kernel device manager (KDM). KDM is passed control during POST after Enhanced Device Initialization Manager (eDIM) has performed device initialization. KDM configures and manages all the devices enumerated by the eDIM. KDM groups these devices into Input Device, Output Device and/or Storage Device classifications and links them with proper class specific kernel (Input Kernel, Output Kernel, and Storage Kernel) through an Input Pipe, Output Pipe, and/or Storage Pipe. | 2008-10-16 |
20080256352 | Methods and systems of booting of an intelligent non-volatile memory microcontroller from various sources - Methods and systems of booting an intelligent non-volatile memory (NVM) microcontroller from various sources are described. According to one aspect of the present invention, a NVM microcontroller comprises multiple memory interfaces. Each of the memory interfaces may connect to one of the various sources for booting. The sources may include random access memory (RAM), read-only memory (ROM), Electrically Erasable Programmable ROM (EEPROM) (e.g., NOR flash memory, NAND flash memory). RAM may include static RAM (SRAM), dynamic RAM (DRAM), and synchronous dynamic RAM (SDRAM). Other sources include Secure Digital (SD) card and intelligent non-volatile memory devices. The NAND flash memory may include single-level cell (SLC) flash or multi-level cell (MLC) flash. SLC flash uses a single level per cell or two states per cell, while MLC flash stores four, eight or more states per cell. | 2008-10-16 |
20080256353 | Method and Apparatus for Hiding Information in Communication protocol - A method and apparatus for hiding information in a communication protocol signal are disclosed. The apparatus comprises a bit selection unit, an information encoding unit and an information decoding unit, wherein the bit selection unit selects suitable bits in the signal for hiding information, the information encoding unit encodes the information into the suitable bits selected by the bit selection unit, and the information decoding unit decodes the information encoded in the suitable bits. | 2008-10-16 |
20080256354 | Systems and methods for exception handling - Systems and methods for managing digital assets in a distributed computing environment are described. Meta-data for the digital assets is stored separately from the digital assets. Meta-data for some of the digital assets is copied and stored at a central location. Meta-data for the digital assets is generated by clients of the system. A method for overriding a policy associated with a digital asset on a client computer after determining a centralized policy database is inaccessible includes: selecting, by a management computing device, a first digital asset likely to exist on a client; digitally signing, by the management computing device information corresponding to the first digital asset and information identifying a second digital asset and a policy corresponding to the second digital asset; receiving, by the client, the digitally signed information; and implementing, by the client, the policy corresponding to the second digital asset. | 2008-10-16 |
20080256355 | Communication Apparatus, Control Method For A Communication Apparatus, Computer Program Product, And Computer Readable Storage Medium - A communication apparatus for outputting e-mail to a network including a storing part configured to store e-mail addresses and related encryption information signifying whether e-mail directed to the addresses should be encrypted or in plain text; a displaying part configured to display the e-mail addresses stored in the storing unit as selectable destinations by a user; a receiving part configured to receive an instruction to encrypt e-mail or keep the e-mail in plain text for addresses selected as destinations via the displaying part; an e-mail control part configured to control creation of the e-mail based on the instruction received by the receiving part and the encryption information related to the selected e-mail addresses; and an output part configured to output the created e-mail through the e-mail control part to the network. | 2008-10-16 |
20080256356 | SECURE MEDIA BROADCASTING USING TEMPORAL ACCESS CONTROL - Improved key management techniques are disclosed for temporal access control of one or more services in a computer network. For example, a method for providing access control in a client-server system includes the following steps. A client obtains an authorization key for a time interval. A server derives an encryption key corresponding to a given time and uses the encryption key to encrypt a message. The client derives a decryption key corresponding to the given time and decrypts the message. | 2008-10-16 |
20080256357 | METHODS AND APPARATUS FOR ACCESS CONTROL IN SERVICE-ORIENTED COMPUTING ENVIRONMENTS - Improved access control techniques for use in a service-oriented computing environment are disclosed. For example, one method for authenticating a client in a service-oriented environment, wherein the service-oriented environment includes a plurality of services, includes the following steps. At least one service of the plurality of services is invoked. State information is associated with the at least one service invoked. The state information is used to authenticate a client with at least one service. Further, a method for access control in a service-oriented environment, wherein the service-oriented environment includes a plurality of services, includes the following steps. A rule specification language is provided. At least one rule is specified using the rule specification language. A verification is performed to determine whether or not the client satisfies the at least one rule. The client is granted access to a service when the client satisfies the at least one rule. | 2008-10-16 |
20080256358 | System and method for managing digital certificates on a remote device - A system and method for managing a digital certificate associated with a remote device is provided. The method includes providing a Web Service Application Programming Interface (API) and communicating digitally between the Web Service API and a remote device, including one of requesting the remote device to perform a task associated with managing digital certificates, and responding to a request from the remote device for performing a task associated with managing digital certificates. | 2008-10-16 |
20080256359 | Method and apparatus for file sharing between a group of user devices with encryption-decryption information sent via satellite and the content sent separately - A communication system | 2008-10-16 |
20080256360 | Method and apparatus for authenticating a code image upon starting a device - A device such as a mobile receiving unit ( | 2008-10-16 |
20080256361 | Watermarking of a Processing Module - The present invention relates to a method, for watermarking a processing module ( | 2008-10-16 |
20080256362 | Method and apparatus for digital signature authentication, and computer product - An apparatus for digital signature authentication includes a dividing unit that divides streaming data into plural pieces of partial data in a predetermined unit; a first creating unit that creates a hash value string including plural hash values corresponding to the pieces of partial data; a second creating unit that creates a first binary tree using the hash value string; and a third creating unit that creates a digital signature of a signer using a root value of the first binary tree. | 2008-10-16 |
20080256363 | Trusted component update system and method - A trusted component update system comprises verify logic configured to validate integrity of an update to a trusted component of a computing device, and logic disposed in the trusted component and configured to validate integrity of the verify logic. | 2008-10-16 |
20080256364 | DYNAMIC NEGOTIATION OF SECURITY ARRANGEMENTS BETWEEN WEB SERVICES - The present invention relates to computer-based devices and methods negotiate and implement security arrangements between two or more web services. More particularly, it relates to devices and methods that specify input and output interfaces, computation and generation of a security contract consistent with inputs, and implementation of security in accordance with negotiated security arrangements. Particular aspects of the present invention are described in the claims, specification and drawings. | 2008-10-16 |
20080256365 | APPARATUS FOR WRITING INFORMATION ON A DATA CONTENT ON A STORAGE MEDIUM - An apparatus for writing checksum information on a data content on a storage medium. The apparatus has a provider for providing checksum information based on the data content and a writer for writing the data content and the checksum information on the storage medium such that a baseline reader and an enhanced reader can read the data content, the enhanced reader can read and process the checksum information, and the baseline reader ignores, skips or does not read the checksum information. | 2008-10-16 |
20080256366 | System and Method for Booting a Multiprocessor Device Based on Selection of Encryption Keys to be Provided to Processors - A system and method for booting a multiprocessor device based on selection of encryption keys to be provided to the processors are provided. With the system and method, a security key and one or more randomly generated key values are provided to a selector mechanism of each processor of the multiprocessor device. A random selection mechanism is provided in pervasive logic that randomly selects one of the processors to be a boot processor and thereby, provides a select signal to the selector of the boot processor such that the boot processor selects the security key. All other processors select one of the one or more randomly generated key values. As a result, only the randomly selected boot processor is able to use the proper security key to decrypt the boot code for execution. | 2008-10-16 |
20080256367 | Duo Codes for Product Authentication - Systems and methods are provided that employ two or more cryptographically linked codes. The codes, when encrypted, become cipher texts that appear unrelated. The codes described herein are characterized by a series of bits including one or more switch bits. The cipher text of a code having a switch bit in one state will appear to be unrelated to the cipher text of another code differing only in that the switch bit is in the opposite state. The cryptographically linked codes can be used in various combinations, such as on a product and its packaging, on a product and a component of the product, on a certificate packaged with the product and on the packaging, or on outer and inner packagings of the product. | 2008-10-16 |
20080256368 | Method and Device For Protecting Digital Content in Mobile Applications - The present invention provides methods and devices allowing a secure way of sharing protected content. A content holder may share the content under certain restrictions. The invention offers a secure sharing method preventing copyright violations and preserving the copyright owners control over the content use, while also offering new marketing possibilities to him. A method for protecting digital content is provided which comprises receiving said digital content, encrypting said digital content using a encryption algorithm resulting in encrypted content, generating license information associated to said encrypted content, wherein said license information is provided as one or more executable code sections, which are executable on a processor-based entity. | 2008-10-16 |
20080256369 | DISC DRIVE COUNTERFEITING COUNTERMEASURE - Counterfeiting of optical disc drives used with game systems is prevented by storing an obfuscated authentication key in firmware of the disc drive. Each disc drive can implement a different obfuscation scheme. The authentication key is parsed into components and the components are stored in various locations in firmware of the disc drive. Drive specific software also is stored in the firmware. Remaining locations of the firmware are randomly populated with binary values. | 2008-10-16 |
20080256370 | Intrusion Protection For A Client Blade - Receiving, by a blade management module from a client blade, notification of a loss of communications between a remote desktop apparatus and the client blade; responsive to the notification, accepting, by the blade management module from the remote desktop apparatus, an instruction to alter a power setting of the client blade; and; responsive to the instruction, altering, by the blade management module, the power setting of the client blade. | 2008-10-16 |
20080256371 | SYSTEM AND METHOD FOR POWER MANAGEMENT IN A COMPUTING DEVICE FOR POWER OVER ETHERNET - A system and method for operating system power management in a computing device for power over Ethernet (PoE). Computing devices such as portable computers or embedded devices having an operating system (OS) can leverage power management features in an OS. Power management state information such as user parameters, computing device parameters, application parameters, IT parameters, network parameters, etc. can be used to generate power requests that are acted upon by power sourcing equipment. | 2008-10-16 |
20080256372 | Inline Power Controller - An inline power controller includes at least one analog interface circuit module (AICM) having a first analog input node for receiving an inline power port voltage, a second analog input node for receiving an inline power port current, a first analog output for effecting an inline power port voltage, a second analog output for effecting an inline power port current, and a digital interface converting the received inline power port voltage to a digital value, the inline power port current to a digital value, a first digital value to the first analog output and a second digital value to the second analog output. A digital serial bus (DSB) couples the AICM to a digital controller via digital serial bus interfaces (DSBIs). | 2008-10-16 |
20080256373 | SYSTEM AND METHOD FOR COLLECTING POWER MANAGEMENT PARAMETERS IN A COMPUTING DEVICE FOR POWER OVER ETHERNET - A system and method for collecting power management parameters in a computing device for power over Ethernet (PoE). Computing devices such as portable computers can include a collection component that is responsible for gathering power management information from various parts of the computing device. The collected power management information can then be sent to a LAN on motherboard device for use in a PoE allocation scheme. | 2008-10-16 |
20080256374 | Sharing Non-Sharable Devices Between an Embedded Controller and A Processor in a Computer System - System and method for sharing a device, e.g., non-volatile memory, between a host processor and a microcontroller. In response to system state change to a first state wherein the microcontroller is assured safe access to the non-volatile memory (e.g., in response to power-on reset, system reset, sleep state, etc.), the microcontroller holds the system in the first state (e.g., system reset), and switches access to the non-volatile memory from the processor to the microcontroller. While the system is held in the first state, the microcontroller accesses the device (e.g., non-volatile memory), e.g., fetches program instructions/data from the non-volatile memory and loads the program instructions/data into a memory of the microcontroller. After the access, the microcontroller changes or allows change of the system state, e.g., switches access to the device, e.g., the non-volatile memory, from the microcontroller to the processor, and releases the system from the first state. | 2008-10-16 |
20080256375 | SYSTEM OF INTEGRATED ENVIRONMENATLLY HARDENED ARCHITECTURE FOR SPACE APPLICATION - An environmentally hardened architecture comprises a hybrid processor, a high speed bus having environmentally-sensitive interfaces, an environmentally hardened bus having environmentally-hardened interfaces, and an environmentally-hardened processor communicatively coupled to an environmentally-sensitive interface of the high speed bus and communicatively coupled to an environmentally-hardened interface of the environmentally hardened bus. The hybrid processor includes an environmentally-hardened processing section and an environmentally-sensitive processing section. At least one environmentally-sensitive interface is configured to pass data to and from the environmentally-sensitive processing section and another environmentally-sensitive interface is configured to pass data to and from the environmentally-hardened processing section of the hybrid processor. An environmentally-hardened interface is configured to pass data to and from the environmentally-hardened processing section of the hybrid processor. The environmentally-hardened processor processes critical applications in the environmentally-hardened processing section of the at least one hybrid processor during an environmental event. | 2008-10-16 |
20080256376 | MULTI-THREAD POWER-GATING CONTROL DESIGN - The invention relates to a multi-thread power gating control design, setting idle components into a sleep mode to reduce power consumption due to current leakage. Based on compiler techniques, the invention arranges predicted-power-gating instructions into every thread of a may-happen-in-parallel region. A predicted-power-on instruction determines whether the corresponding component has been powered on, and powers on the component when it has not been powered on yet. A predicted-power-off instruction determines whether the component is required in the rest of the may-happen-in-parallel region, and powers off the component when it is required later. | 2008-10-16 |
20080256377 | Power Management for Buses in Cmos Circuits - The invention relates to a controlled shut-down of an electronic circuit or circuits such that the electrical power consumption of that circuit or circuits is minimized and that each said circuit is at a status which is a pre-determined state ( | 2008-10-16 |
20080256378 | Audio/Video Content Synchronization Through Playlists - A method is disclosed for performing bi-directional synchronization between a host device having a large capacity, e.g., a personal computer ( | 2008-10-16 |
20080256379 | Clock architecture for multi-processor systems - In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal. | 2008-10-16 |
20080256380 | SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD FOR THE SAME - A functional block is divided into a plurality of regions. In each region, a clock main line extending along a first direction, a clock branch line group including a plurality of clock branch lines extending along a second direction perpendicular to the first direction and electrically connected to the clock main line, a clock driving cell electrically connected to the clock main line and a clock synchronous cell group including a plurality of clock synchronous cells electrically connected to the clock main line or the clock branch line group are provided. The clock branch line groups of the respective regions are electrically separated from each other, and the clock driving cell singly drives the clock main line connected thereto and the clock branch line group connected to the clock main line. | 2008-10-16 |
20080256381 | METHOD AND SYSTEM FOR ANALOG FREQUENCY CLOCKING IN PROCESSOR CORES - A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequency. Digital frequency control data and an analog signal are both transmitted to that at least one processor core; and that processor core uses the received analog signal and digital frequency control data to set the frequency of the output clock signal of the clocking subsystem. In a preferred implementation, multiple cores are asynchronously clocked and the core frequencies are independently set. | 2008-10-16 |
20080256382 | METHOD AND SYSTEM FOR DIGITAL FREQUENCY CLOCKING IN PROCESSOR CORES - Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an output clock signal, which may be an analog signal at a variable frequency. Digital frequency control data are transmitted or distributed to the processor core; and that one processor core receives the digital frequency control data transmitted to the core, and uses that received digital frequency control data to set the frequency of the output clock signal of the clocking subsystem of the processor core. Preferably, multiple cores are asynchronously clocked and the core frequencies are independently set, and, there is no phase relationship between the core clocks. | 2008-10-16 |
20080256383 | METHOD AND SYSTEM OF PREDICTING MICROPROCESSOR LIFETIME - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 2008-10-16 |
20080256384 | Mechanism for Recovery from Site Failure in a Stream Processing System - A failure recovery framework to be used in cooperative data stream processing is provided that can be used in a large-scale stream data analysis environment. Failure recovery supports a plurality of independent distributed sites, each having its own local administration and goals. The distributed sites cooperate in an inter-site back-up mechanism to provide for system recovery from a variety of failures within the system. Failure recovery is both automatic and timely through cooperation among sites. Back-up sites associated with a given primary site are identified. These sites are used to identify failures within the primary site including failures of applications running on the nodes of the primary site. The failed applications are reinstated on one or more nodes within the back-up sites using job management instances local to the back-up sites in combination with previously stored state information and data values for the failed applications. In additions to inter-site mechanisms, each one of the plurality of sites employs an intra-site back-up mechanism to handle failure recoveries within the site. | 2008-10-16 |
20080256385 | OPTIMIZATION OF PORT LINK RECOVERY - Provided are techniques for determining a link speed. When a link between two computing devices is operational, a link speed for use in communicating across the link is stored and a remembered indicator is set to TRUE. After any event occurs that causes the link to become inoperational, in response to determining that the remembered indicator is TRUE, the stored link speed is used when attempting to make the link become operational. | 2008-10-16 |
20080256386 | Raid configuration indication in network attached storage - In one embodiment a network attached storage device comprises at least one storage media, a storage controller to manage input/output requests directed to the at least one storage media, and a RAID interrogation module to receive a RAID configuration query, wherein the RAID configuration query includes a volume identifier that identifies a storage volume, accesses a RAID configuration table in a memory module coupled to the network attached storage device, and presents RAID configuration data obtained from the RAID configuration table. | 2008-10-16 |
20080256387 | AUTOMATED ERROR RECOVERY OF A LICENSED INTERNAL CODE UPDATE ON A STORAGE CONTROLLER - A system, method and article of manufacture are provided for the automatic recovery from errors encountered during an automated Licensed Internal Code (LIC) update on a storage controller. The present invention functions with a concurrent or nonconcurrent automated LIC update. The automated recovery from many error conditions is transparent to the attached host system and on-site service personnel, resulting in an improvement in the LIC update process. | 2008-10-16 |
20080256388 | Method for Fast System Recovery via Degraded Reboot - A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process. | 2008-10-16 |
20080256389 | Strategies for Performing Testing in a Multi-User Environment - A strategy is described in which multiple testing agents perform multiple respective tests in a multi-user environment. One such multi-user environment allows multiple clients to interact with remote applications that are executed on a server. According to one exemplary case, a central test management module coordinates the execution of the multiple tests by the testing agents. For instance, the test management module can prevent testing agents that make demands on a global state of the multi-user environment from interfering with other testing agents. | 2008-10-16 |
20080256390 | Project Induction in a Software Factory - A computer-implemented method, system, and computer-readable medium for inducting a software project into a software factory is presented, wherein an induction process identifies what processes and sub-processes are needed to create the software factory, and wherein the induction process identifies potential risks to the software factory. In a preferred embodiment, the computer-implemented method comprises the steps of: submitting a factory project proposal to a service definition process; creating a service definition template from a compilation of selected checklists; scoring and classifying the service definition template to determine if the candidate project may be executed in the software factory; in response to the service definition template scoring above a pre-determined acceptable score, transmitting the factory project proposal to a service induction process; and in response to the candidate project passing a final review process, transmitting the candidate project to the software factory for execution. | 2008-10-16 |
20080256391 | Apparatus to Use Fabric Initialization to Test Functionality of all Inter-Chip Paths Between Processors in System - A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved. | 2008-10-16 |
20080256392 | Techniques for prioritizing test dependencies - Techniques for prioritizing test dependencies are described. A computer system employing such techniques may present a test structure for a set of test cases. The test structure may comprise prioritized test cases and dependencies between test cases. The dependencies may be based on predicted test case failure given failure of another test case. Other embodiments are described and claimed. | 2008-10-16 |
20080256393 | DETECTING UNEXPECTED IMPACT OF SOFTWARE CHANGES USING COVERAGE ANALYSIS - A computer-implemented method for evaluating software code includes measuring a first coverage of a test applied to the software code and then making a modification in a first section of the software code. A second coverage of the test applied to the software code is measured after making the modification. A difference is identified between the first coverage and the second coverage in a second section of the software code, which is separate from the first section and was not modified since the first coverage was measured, and an indication of the difference is output. | 2008-10-16 |
20080256394 | Method and apparatus for testing media player software applications - A method, system and program application is provided for automatically testing the operation of a media player with media files (e.g., video files) that are embodied in various formats. In one illustrative example visually encoded metrics are embedded in a media file that is to serve as a test file. These metrics can be detected and decoded when the test file is rendered by the media player. A testing program automatically executes various playback commands to simulate the way a user would operate the media player when viewing a media file. The testing program captures the media player's display buffer after the execution of each command. The display buffer includes the frame or frames that are played by the media player as a result of the commands. The metric or metrics embedded in the captured frames are detected and decoded and compared to a database that includes the metric or metrics that would be expected if the media player is correctly playing the test file. | 2008-10-16 |
20080256395 | DETERMINING AND ANALYZING A ROOT CAUSE INCIDENT IN A BUSINESS SOLUTION - A method, system and computer program product for analyzing a state changing event are disclosed. According to an embodiment, a method for analyzing a state changing event comprises: detecting a state changing event of a first resource; tracing a dependence link beginning at the first resource to a resource that the first resource depends on until finding a second resource having a state changing event that is not dependent on any resource with a state changing event; and identifying the state changing event of the second resource as a root cause incident for analysis. | 2008-10-16 |
20080256396 | INTER-THREAD TRACE ALIGNMENT METHOD AND SYSTEM FOR A MULTI-THREADED PROCESSOR - Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Inter-thread trace alignment with execution trace processing includes recording timing data relating to a common predetermined event. Such an event may be the number of cycles since a last thread initiated execution tracing or the number of cycles since all threads terminated execution tracing. The number of cycles at which a thread initiates execution tracing is referenced to the common predetermined event for maintaining the timing of execution tracing. The data relating to the common predetermined event is then updated to associate with the time at which the thread initiated execution tracing. The result is to permit aligning the timing data associated with all threads. Interrelated records permit reconstructing interdependent execution tracing information for threads operating in the multi-threaded processor, as well as synchronizing timing data for all operating threads. | 2008-10-16 |
20080256397 | System and Method for Network Performance Monitoring and Predictive Failure Analysis - A method and system for detecting performance degradation of a plurality of monitored components in a networked storage system. Performance data is collected from the plurality of monitored components. Component statistics are generated from the collected performance data. Heuristics are applied to the generated component statistics to determine the likelihood of failure or degradation of each of the plurality of monitored components. | 2008-10-16 |
20080256398 | Using EMI signals to facilitate proactive fault monitoring in computer systems - A system that monitors electromagnetic interference (EMI) signals to facilitate proactive fault monitoring in a computer system is presented. During operation, the system receives EMI signals from one or more antennas located in close proximity to the computer system. The system then analyzes the received signals to proactively detect anomalies during operation of the computer system. | 2008-10-16 |
20080256399 | SOFTWARE EVENT RECORDING AND ANALYSIS SYSTEM AND METHOD OF USE THEREOF - A software service running in the background of an operating system and used by a user to record metadata and screen shots of the user interface screens in an operating system whenever errors occur in the operating system or in any application running on the operating system. The software service also manages the recorded data to ensure resources are used efficiently to minimize the use of storage space in the recording location or buffer. The software running in the background monitors, filters and logs programs and user actions, and if a problem occurs within the monitored software, a problem report can be created for a support team to analyze and include corresponding recorded data. The suggested selection of recorded data can be displayed and edited by the user. | 2008-10-16 |
20080256400 | System and Method for Information Handling System Error Handling - Non-fatal errors at an information handling system link are managed by firmware of the information handling system. For example, a PCI Express link controller initiates an SMI interrupt upon detection of a non-fatal error associated with the PCI Express link. A non-fatal error monitor associated with an SMI handler in the BIOS of the information handling system receives the interrupt, determines the component of the information handling system associated with non-fatal error and issues an error message if the non-fatal error meets a predetermined condition, such as a predetermined number of errors associated with the component. | 2008-10-16 |
20080256401 | Information Processing Apparatus, Information Processing System, Information Processing Method and Computer Program - The present invention is directed to an information processing system composed of plural information processing units adapted for mutually executing data communication, and for executing data processing in which communication data has been applied. The first entity A transmits error notification data on the basis of error detection to execute initial state return processing on the condition that data reception after error notification data has been transmitted is made, and the second entity B transmits error notification data on the basis of error detection to execute initial state return processing on the condition that transmit processing of error notification data is executed. Thus, the both entities A and B can return to the initial state in a manner synchronous with each other. As a result, it becomes possible to perform reliable error recovery and data processing restart. | 2008-10-16 |
20080256402 | METHOD AND CIRCUIT FOR REDUCING SATA TRANSMISSION DATA ERRORS BY ADJUSTING THE PERIOD OF SENDING ALIGN PRIMITIVES - A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced. | 2008-10-16 |
20080256403 | Soft error rate calculation method and program, integrated circuit design method and apparatus, and integrated circuit - A first mathematical expression indicating a dependence of SER on an information storage node diffusion layer area at the same information storage node voltage Vn is derived with a use of a result of measuring a relationship between SER and the information storage node diffusion layer area of a storage circuit or an information holding circuit composed of MISFET using a plurality of information storage node voltages Vn as a parameter. Then, a second mathematical expression is derived from the measurement result by substituting a relationship indicating a dependence of SER on an information storage node voltage at the same information storage node diffusion layer area Sc into the first mathematical expression. SER can be calculated by substituting a desired information storage node diffusion layer area and a desired information storage node voltage of a storage circuit or an information holding circuit into the second mathematical expression. | 2008-10-16 |
20080256404 | FAULT LOCATION ESTIMATION SYSTEM, FAULT LOCATION ESTIMATION METHOD, AND FAULT LOCATION ESTIMATION PROGRAM FOR MULTIPLE FAULTS IN LOGIC CIRCUIT - A fault location estimation system comprises single-fault-assumed diagnostic means that assumes a single fault and stores fault candidates, fault types, and detected error-observation nodes at which an error arrives from the fault candidates; error-observation node basis candidate classification means that classifies error propagating fault candidates into groups according to error-observation nodes using the fault candidates and the error-observation nodes and stores the groups as fault candidate groups; inclusion fault candidate group selection means that acquires a relation between each fault candidate group and a fault output, calculates an inclusion relation among the fault candidate groups, and, if path information on one fault candidate group includes path information on another fault candidate group, deletes the inclusion fault candidate group; inter-pattern overlapping means that calculates combinations of fault candidate groups that can reproduce a test result in all test patterns by referencing the fault candidates and the fault candidate classification result and extracts fault candidates that are common to fault candidate groups, calculated in multiple patterns, to create a new fault candidate group; and multiple-fault simulation checking means that selects fault candidates from the combinations of fault candidate groups, one from each fault candidate group, performs multiple-fault simulation, compares the simulation result with the test result, and outputs a combination of fault candidate groups which matches relatively well with the test result and has a relatively high fault possibility. | 2008-10-16 |
20080256405 | COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS - A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip. | 2008-10-16 |
20080256406 | Testing System - There is provided an improved testing system. More specifically, in one embodiment, there is provided a method including accessing machine overall equipment effectiveness or efficiency (OEE) data including machine generated operational event states of an automated testing (ATE) system and times the machine generated operational event states occurred, receiving operator OEE data including operator entered operational event states of the ATE and times the operator observed operational event states, and combining the machine OEE data and the operator OEE data to generate merge OEE data. | 2008-10-16 |
20080256407 | PROCESS AND SYSTEM FOR THE VERIFICATION OF CORRECT FUNCTIONING OF AN ON-CHIP MEMORY - A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM. Moreover, the method includes defining, in the logic self-test circuit, a logic self-test core to process the ROM code and to generate a flag based upon a control signature and defining, in the logic self-test circuit, a nonvolatile storage block, coupled to the logic self-test core, to store the control signature. Furthermore, the method includes writing the ROM code to the at least one nonvolatile ROM and writing the control signature to the nonvolatile storage block, during a same fabrication step. | 2008-10-16 |
20080256408 | TEST APPARATUS AND PERFORMANCE BOARD FOR DIAGNOSIS - A test apparatus being capable of replacing a test module with the other kind of test module that tests device under tests by using the test module is provided. The test apparatus includes a plurality of test modules that transmit/receive signals to/from the device under tests to test the device under test; and a performance board for diagnosis that diagnose the plurality of test modules. The performance board for diagnosis including: a motherboard provided common to the plurality of test, modules; a circuit for diagnosis that transmits/receives a signal to/from each test module to diagnose the test module; a plurality of inter-board to module connectors that connect between the corresponding test module and the circuit for diagnosis; and
| 2008-10-16 |
20080256409 | HYBRID CORRECTIVE SCHEME FOR DROPPED PACKETS - In one embodiment, a hybrid packet repair scheme adaptively switches among unicast retransmission, multicast retransmission, and Forward Error Correction (FEC) depending on the receiver population and the nature of the error prompting the repair operation. The NACK patterns are used to heuristically determine the degree of correlation among packet losses. In an additional embodiment, wasting bandwidth and processing on retransmissions of FEC that will fail to correct the errors is avoided by evaluating the nature of the error and the bandwidth needed to optimally repair it. Unicast retransmission, multicast retransmission, or FEC repair is then dynamically performed according to the loss patterns derived from the NACK arrivals and other network conditions. | 2008-10-16 |
20080256410 | Mimo System Performing Hybrid Arq and Retransmission Method Thereof - The present invention relates to a multiple antenna transmitting/receiving apparatus that performs a hybrid automatic repeat request, and a retransmission method thereof. An initial transmission signal is encoded into the form of an initial transmission matrix and transmitted to the receiving apparatus, the initial transmission matrix corresponding to a linear dispersion code, with a result of error checking performed on the initial transmission signal by the receiving apparatus. When an error is detected in the initial transmission signal, a first retransmission signal is generated by encoding the initial transmission signal in the form of a retransmission matrix and transmitted to the receiving apparatus. The retransmission matrix is formed of constituent elements of the initial transmission matrix but different from the initial transmission matrix, and corresponds to a linear dispersion code having the same capacity and diversity gain as those of the initial transmission matrix. | 2008-10-16 |
20080256411 | Retransmission in a Cellular Communication System - A base station ( | 2008-10-16 |
20080256412 | TRANSPORT STREAM GENERATING APPARATUS, TURBO PACKET DEMULTIPLEXING APPARATUS, AND METHODS THEREOF - A transport stream generating apparatus, a turbo packet demultiplexing apparatus, and methods thereof, the transport stream generating apparatus including: a Reed Solomon (RS) encoder to RS-encode turbo data, an interleaver to interleave the RS-encoded turbo data, a duplicator to add a parity insertion area to the interleaved turbo data, and a multiplexer to multiplex normal data and the turbo data processed by the duplicator to generate a transport stream. Accordingly, reception performance can be improved in an advanced vestigial sideband (AVSB) system. | 2008-10-16 |
20080256413 | Redundancy in Signal Distribution Trees - A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees ( | 2008-10-16 |
20080256414 | SYSTEM AND DEVICE WITH ERROR DETECTION/CORRECTION PROCESS AND METHOD OUTPUTTING DATA - A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane. | 2008-10-16 |
20080256415 | Error Detection/Correction Circuit as Well as Corresponding Method - In order to provide an error detection/correction circuit ( | 2008-10-16 |
20080256416 | Apparatus and method for initializing memory - An apparatus includes a memory including a controller for initializing the memory, the controller storing a first data including a first code for correcting a first error of the first data, to the memory when initializing, and a memory controller controlling a data transmission to the memory, the memory controller being connected to the memory. The memory controller includes a code generation circuit storing a second data including a second code, to the memory after the initializing, the second code including an address parity for detecting an address causing a second error of the second data in said memory. | 2008-10-16 |
20080256417 | SDRAM convolutional interleaver with two paths - An SDRAM convolutional interleaver with two paths. Symbols are assigned to a given one of the two paths, then are sorted to minimize (to one) a number of breaks in a sequential Interleaver write address. After sorting, the symbols are stored staggered in SRAM and burst written to SDRAM. Before writing to SDRAM, data is accumulated for four symbols at a time, and the data is written four symbols wide to optimize SDRAM access time. 8 bit symbols are written 32 bits at a time to SDRAM. | 2008-10-16 |
20080256418 | DYNAMIC STREAM INTERLEAVING AND SUB-STREAM BASED DELIVERY - A communications system can provide methods of dynamically interleaving streams, including methods for dynamically introducing greater amounts of interleaving as a stream is transmitted independently of any source block structure to spread out losses or errors in the channel over a much larger period of time within the original stream than if interleaving were not introduced, provide superior protection against packet loss or packet corruption when used with FEC coding, provide superior protection against network jitter, and allow content zapping time and the content transition time to be reduced to a minimum and minimal content transition times. Streams may be partitioned into sub-streams, delivering the sub-streams to receivers along different paths through a network and receiving concurrently different sub-streams at a receiver sent from potentially different servers. When used in conjunction with FEC encoding, the methods include delivering portions of an encoding of each source block from potentially different servers. | 2008-10-16 |
20080256419 | Configurable Split Storage of Error Detecting and Correcting Codes - Memory space of a digital device may be configured for both instructions/data (op-code) and ECC or parity when required, otherwise the entire memory space may be configured for just the program instructions/data. A standard word width memory may be configured for ECC or non-ECC functionality, or parity or non-parity functionality, based upon a desired application. The last portion of the memory may be allocated for ECC or parity data rather then application code when an ECC or parity implementation is required. When an ECC or parity implementation is not required, the entire memory may be used for the application code. This allows a digital device and memory to be used in applications having different robustness (e.g., application code integrity) requirements without have to fabricate different digital devices. | 2008-10-16 |
20080256420 | ERROR CHECKING ADDRESSABLE BLOCKS IN STORAGE - Provided are a method, system, and article of manufacture for error checking addressable blocks in storage. Addressable blocks of data are stored in a storage in stripes, wherein each stripe includes a plurality of data blocks for one of the addressable blocks and at least one checksum block including checksum data derived from the data blocks for the addressable block. A write request is received to modify data in one of the addressable blocks. The write and updating the checksum are performed in the stripe having the modified addressable block. An indication is made to perform an error checking operation on the stripe for the modified addressable block in response to the write request, wherein the error checking operation reads the data blocks and the checksum in the stripe to determine if the checksum data is accurate. An error handling operation is initiated in response to determining that the checksum data is not accurate. | 2008-10-16 |
20080256421 | Variable forward error correction for optical communication links - A method and system for setting a variable forward error correction overhead in an optical transport network frame for an optical link at a node are disclosed. In one embodiment, a method includes selecting a forward error correction overhead, signaling an optical node the selected forward error correction overhead, and setting the forward error correction overhead in the optical network transport frame for use in transmission of data over the optical link. In one embodiment, the forward error correction overhead is complementary to the data payload to maintain total transmission rate. | 2008-10-16 |
20080256422 | Apparatus for Providing Error Correction Capability to Longitudinal Position Data - A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits for each of the LPOS words. A determination is then made as to whether or not there is an error within one of the LPOS words based on its corresponding syndrome bits. | 2008-10-16 |
20080256423 | Apparatus for Providing Error Correction Capability to Longitudinal Position Data - A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits for each of the LPOS words. A determination is then made as to whether or not there is an error within one of the LPOS words based on its corresponding syndrome bits. | 2008-10-16 |
20080256424 | INFORMATION BIT PUNCTURING FOR TURBO CODING WITH PARAMETER SELECTABLE RATE MATCHING TAILORED TO LOWER EB/NO WITHOUT DEGRADING BLER (BLOCK ERROR RATE) PERFORMANCE - Information bit puncturing for turbo coding with parameter selectable rate matching tailored to lower Eb/No without degrading BLER (Block Error Rate) performance. A means is presented herein by which puncturing is performed to each of three bit sequences from a turbo encoder (i.e., the systematic bits or information bits within an block to be turbo encoded, the parity bits output from a first constituent encoder, and the parity bits output from a second constituent encoder). The number of bit punctured from each of the parity bits output from the first constituent encoder and the parity bits output from the second constituent encoder need not be the same number of bits. The manner in which puncturing may be performed can be adaptive and/or changeable, in that, first puncturing parameters may be employed at a first time and second puncturing parameters may be employed at a second time, etc. | 2008-10-16 |
20080256425 | Method of Encoding and Decoding Adaptive to Variable Code Rate Using Ldpc Code - A variable code rate adaptive encoding/decoding method using LDDC code is disclosed, in which an input source data is encoded using the LDPC (low density parity check) code defined by a first parity check matrix configured with a plurality of submatrices. The present invention includes the steps of generating a second parity check matrix corresponding to a code rate by reducing a portion of a plurality of submatrices configuring a first parity check matrix according to the code rate to be applied to encoding an input source data and encoding the input source data using the second parity check matrix. | 2008-10-16 |
20080256426 | Low Density Parity Check Codes For Mimo Systems - A low density parity check code is generated by defining first a framework combining symbol detection and low density parity check decoding. Probabilistic information describing multiple-input-multiple-output channels is defined, and a low density parity check code is generated based on said framework and said probabilistic information describing multiple-input-multiple-output channels. | 2008-10-16 |
20080256427 | SYSTEM, METHOD, AND SERVICE FOR PROVIDING A GENERIC RAID ENGINE AND OPTIMIZER - A generic RAID engine system accepts an access request, accepts a metadata input comprising a layout description and, optionally, a plurality of resource optimization objectives, accepts a dynamic input comprising a dynamic state of an I/O stack comprising the generic RAID engine and a fault configuration of a plurality of storage devices in the I/O stack, and accepts RAID code input comprising information about the RAID code used by the I/O stack. The metadata input, the dynamic input, and the RAID code input are utilized to transform the access request into individual device reads and individual device writes such that RAID code relationships for the storage devices are maintained at all times. An optional optimizer module selects strategies that meet the resource optimization objectives. | 2008-10-16 |
20080256428 | System for facilitating the preparation of a patent application with an automatically variable omnibus form paragraph - A method of preparing a patent application in conjunction with a word processing program. Key explanations/disclaimers are inserted into an omnibus form paragraph in response to keys being found in the claims. This increases efficiency in the drafting of the patent application and prevents mistakes by ensuring that the omnibus form paragraph contains the necessary disclaimers/explanations for the style of claims in the patent application. | 2008-10-16 |
20080256429 | APPARATUS AND METHOD FOR CREATING PUBLICATIONS FROM STATIC AND DYNAMIC CONTENT - A computer readable storage medium comprises a publication definition module to create and define properties for a publication object. The publication definition module includes executable instructions to associate a set of static documents and a set of report templates with the publication object. Executable instructions define a conditional delivery rule for the publication object. The conditional delivery rule specifies a condition for the inclusion of a report template from the set of report templates to be merged with a static document from the set of static documents. | 2008-10-16 |
20080256430 | AUTOMATED IMPLEMENTATION OF CHARACTERISTICS OF A NARRATIVE EVENT DEPICTION BASED ON HIGH LEVEL RULES - Systems and methods providing automated implementation of production characteristics for a narrative event, where a presentation criterion encoding the production characteristics is interpreted and selects a set of algorithms to use to implement those production characteristics, and where those algorithms implement the production characteristics for the event content representing the narrative event as a presentation criterion production collection and a presentation criterion integration specification, such that for an event depiction from the event content integrated with the presentation criterion production collection according to the presentation criterion integration specification, that event depiction reflects the production characteristics. | 2008-10-16 |
20080256431 | Apparatus and Method for Generating a Data File or for Reading a Data File - An apparatus for generating a data file has a navigation information generator and a file constructor. The file constructor constructs a file having a metadata container and a media data container. The metadata container comprises information indicating presentation times for a plurality of media samples, and the media data container includes these media samples. Additionally, the file constructor inserts redundant navigation information records into the media data container. A reader calculates presentation times of media samples based on these navigation information records in the media data container. | 2008-10-16 |
20080256432 | System and Method of Defining a Hierarchical Datamodel and Related Computation and Instruction Rules Using Spreadsheet Like User Interface - The present invention relates to the field of information processing involving digital computers, embedded devices and more particularly, to a method and system for defining hierarchical data model and related computation and instructions rules using electronic spreadsheet like interface. The system and method of the invention arc directed to user friendly, fast, development of multi-user, workflow enabled applications using spreadsheet as a tool for application modeling. | 2008-10-16 |
20080256433 | COPY AND PASTE OF CELLS IN A MULTI-DIMENSIONAL SPREADSHEET - A system and method for copying and pasting cells in a multi-dimensional spreadsheet. The method is implemented by execution of program code by a processor of a computer system. A source range of cells is copied and pasted in a multi-dimensional spreadsheet onto a destination range of cells in the spreadsheet by performance of a comprehensive paste of the source range of cells onto the destination range of cells. A graphical object in the source range of cells has an associated fastened range of cells, and an associated working range of cells identified by a first relative offset. The copying and pasting results in: the graphical object being within the destination range of cells; and the fastened range of cells and the working range of cells being respectively pasted into an associated fastened range of cells and an associated working range of cells in the destination range of cells. | 2008-10-16 |
20080256434 | Methods, Systems, And Computer Program Products For Associating User-Provided Annotation Data With Markup Content Of A Resource - Methods and systems are described for associating user-provided annotation data with markup content of a resource. In one aspect, an annotation element is detected through processing a resource for presentation by a client. The annotation element is defined in a markup-language for accepting annotation and is associated with a tag defining a boundary of markup content for the resource. Based on the annotation element, a form for receiving user-provided annotation data is presented. The received annotation data is associated with the markup content bounded by the tag. In another aspect, a resource including the annotation element is provided. The provided resource including the annotation element is provided to a network entity, such as a client or a server. | 2008-10-16 |
20080256435 | Interconnection of Document Preparation, Document Viewing, and Alert Processing in Structured Documents - A method and system for notifying a user to review a document stored on a computer. The method scans the document to identify and locate a citation in the document, where the citation is a link to a target document. The method stores the citation in a citations database. The method periodically compares the citations database to a changed documents database. When the comparison determines that the target document is a changed document, the method stores an entry in a hits database, where the entry identifies the document, the citation, and the target document. The method sends an alert message to the user to request that the user review the entry in the hits database. | 2008-10-16 |
20080256436 | Method and Apparatus for Transmitting Accessibility Requirements to a Server - A method, apparatus, and computer instructions for transmitting accessibility requirements. Content is received from a computer at a data processing system. The content is parsed for a selected indicator. The data processing system is queried to identify accessibility requirements in response to the selected indicator being present. The identified accessibility requirements are sent to the computer. These accessibility requirements are use by the computer to generate content for the data processing system. | 2008-10-16 |
20080256437 | Document Processing Apparatus and Document Processing Method - The present invention enables a document described in multiple markup languages to be appropriately processed. | 2008-10-16 |
20080256438 | APPLICATION ISOLATION SYSTEM - A facility for managing a document conversion environment is described. In various embodiments, the facility includes a native application associated with a native document type and an isolation service. The isolation service determines whether a native application associated with the native document type has started and when it has not started, starts the native application and causes the started native application to load and convert a native document to a common document format, wherein the isolation service starts a single instance of the native application and monitors the single instance of the native application so that it complies with specified a parameter, condition, or setting of operation. | 2008-10-16 |
20080256439 | LAYING OUT GRAPHICAL ELEMENTS ON A PAGE - Disclosed are methods for laying out objects on a page which may be operative at a pre-layout calculation stage ( | 2008-10-16 |
20080256440 | GLUING LAYOUT CONTAINERS - A method is disclosed for laying out a plurality of containers on a page to generate a document upon insertion of content in the containers. The containers each have edges whose position upon layout is independent of the dimensions of the content inserted in each container. An association is created between an edge of a first container and an edge of a second container that is parallel and opposed to the first edge which constrains the second edge to a relation to the first edge. The page may then be laid out using the containers such that the edge of the first container moves dependent on the dimensions of content inserted in the first and second containers. | 2008-10-16 |
20080256441 | Flash rich textfields - Techniques are described for providing full support of inline images within online instant messaging applications such as those developed for Flash. When a message contains both a text component and an image component, the image component is separated from the text component. The location of the text is measured dynamically either using an XML ruler component or a bitmap ruler component. Based upon the locations of the text, the images are placed on an invisible image layer. The text is placed on a textfield to be displayed to the user. The image or textfield layer is then placed on top of the other of the image or textfield layer so that both the text component and the image component of the message are visible to the user. | 2008-10-16 |
20080256442 | DATA VISUALIZATION DEVICE AND METHOD - A data visualization device comprises a focal attribute calculator for calculating a focal value of each of a plurality of data input items, and for categorizing each of the plurality of data input items as either non-cluster blobs or second blobs. The device further comprises a clustering attribute calculator for clustering data input items categorized as second blobs into one or more cluster blobs, and a visualization shaper for arranging the one or more cluster blobs and the non-cluster blobs, relative to each other in accordance with the focal values of the data input items of respective blobs. | 2008-10-16 |
20080256443 | SYSTEM FOR AGGREGATING AND DISPLAYING SYNDICATED NEWS FEEDS - The invention relates to a system for aggregating and displaying syndicated news feeds, said system comprising a graphical user interface comprising at least a first and a second user spaces, a tag generator engine to generate relevant tags from the incoming content of each syndicated news feed, a processor operatively coupled to the graphical user interface and the tag generator engine for displaying on the first user space representations of the relevant tags as a function of said tags occurrences, said representations adapted to be dragged and dropped onto the second user space, said processor being further arranged to display in the second user space the content associated to a tag when its representation is dropped into said second user space. | 2008-10-16 |
20080256444 | Internet Visualization System and Related User Interfaces - Systems and methods are described for an Internet visualization system and related user interfaces. In one implementation, the system analyzes Internet search logs to determine most popular search queries across the world at a current time. A user interface displays a keyword of each of the most popular queries in a single visual display that relates each query to a geographical location of greatest popularity. The system can also filter queries according to demographics. In one implementation the user interface provides a 3-dimensional Internet visualization that adopts an ocean or seascape theme. The ocean floor displays a map of the world, and query bubbles rise from geographical locations on the map. The size and duration of each query bubble denotes the relative popularity of a given query. | 2008-10-16 |
20080256445 | SYSTEM AND METHOD FOR AUTOMATED AIDS FOR ACTIVITIES OF DAILY LIVING - Systems and methods for aiding individuals to complete tasks of daily living are provided. The situationally aware system comprises a controller, sensors, and effectors. The controller may include a program that describes a sequence of steps the user should perform to accomplish the task. In response to the information from the sensors and the user's compliance with the steps of the sequence, the controller instructs the effector(s) to relay at least one instructional cue to the user to aid in the performance of the task. The instructional cue may range from a simple blinking light, to detailed audio and/or visual instructions, to relaying a reward for the completion of the task. The instructional cue may also instruct the user to refrain from performing a task. The system is programmable, configurable, and may interface to the Internet. | 2008-10-16 |