42nd week of 2008 patent applcation highlights part 41 |
Patent application number | Title | Published |
20080254544 | ERROR DETECTION AND REJECTION FOR A DIAGNOSTIC TESTING SYSTEM - A system for measuring a property of a sample is provided. The system comprises a diagnostic measuring device having a memory and a diagnostic test strip for collecting the sample. The strip has embedded thereon a pattern representative of at least first data and second data, the first data being data representing at least one of parameters related to measuring the property, codes usable for calibration of the diagnostic measuring device, or parameters indicating proper connection between the measuring device and the test strip and the second data usable for detecting and rejecting potential errors affecting the proper measurement of the property. | 2008-10-16 |
20080254545 | APPARATUS AND METHOD FOR BIOCHEMICAL ANALYSIS - An apparatus for analyzing that performs a plurality of treatment operations includes a plurality of treatment units arranged in a vertical direction of the apparatus. The apparatus for analyzing also includes a conveying mechanism configured to convey a sample between the treatment units. The sample is delivered above or in the treatment units. A pipette chip is also delivered above or in the treatment units. | 2008-10-16 |
20080254546 | A Cyanine-based probe\tag-peptide pair for fluorescence protein imaging and fluorescence protein imaging methods - A molecular probe comprises two arsenic atoms and at least one cyanine based moiety. A method of producing a molecular probe includes providing a molecule having a first formula, treating the molecule with HgOAc, and subsequently transmetallizing with AsCl | 2008-10-16 |
20080254547 | SUPRACOLONIC AERODIGESTIVE NEOPLASM DETECTION - The invention provides methods and materials for detecting supracolonic aerodigestive premalignant and malignant neoplasms. Specifically, the invention provides methods and materials for determining whether a stool sample from a mammal contains a neoplasm-specific marker from a neoplasm located in the supracolonic aerodigestive tissue of a mammal. | 2008-10-16 |
20080254548 | Detection of target analytes using particles and electrodes - The invention relates to the use of particles comprising binding ligands and electron transfer moieties (ETMs). Upon binding of a target analyte, a particle and a reporter composition are associated and transported to an electrode surface. The ETMs are then detected, allowing the presence or absence of the target analyte to be determined. | 2008-10-16 |
20080254549 | SYSTEMS AND METHODS FOR DETECTING AND ANALYZING POLYMERS - A detection system and methods for improving the ability of the detection system to recognize labels that are disposed on a polymer. Embodiments of the invention include schemes for selecting emitters and labels used within the system in a manner that allows an increase in the number of distinct labels that can be used together in a system. In other embodiments, the detection system and methods are directed to identifying portions of a detection signal that may be associated with extra labels residing within a detection zone. In other embodiments, the detection system and methods relate to using wide field imaging detectors while reducing out of focus noise contributions to detection signals of the system. Still, other embodiments relate to the use of linear array detectors to detect labels | 2008-10-16 |
20080254550 | DRUG DETECTION KIT AND METHOD - This invention relates to a kit and to a method of using the kit for the in situ detection of trace quantities of drugs on any surface. The method involves using a sampling means that is purposefully designed to sample trace elements of a drug to sample an unknown drug, chemically reacting the sampled drug with a buffer or digesting solution to produce a composition which is detectable, by immunological techniques. To test the reacted sample it is placed in a well in a detection tablet that has been impregnated with a detecting chemical and produce a visible indication of the presence of absence of a particular drug. | 2008-10-16 |
20080254551 | Immunoprecipitaion-Based Method to Purify and Characterise Biological Macromolecular Complexes - This invention concerns an artificial adapter protein that combines an antibody-binding activity with two affinity tags and its use in isolation of antibody-antigen complexes. Using this adapter protein, complexes can be obtained at good yield and in the high purity necessary for the identification of all biological macromolecules that are associated with the antigen. | 2008-10-16 |
20080254552 | Methods and devices for analyte detection - Methods for detecting one or more analytes, such as a protein, in a fluid path are provided. The methods include resolving, immobilizing and detecting one or more analytes in a fluid path, such as a capillary. Also included are devices and kits for performing such assays. | 2008-10-16 |
20080254553 | In Situ, Ex Situ and Inline Process Monitoring, Optimization and Fabrication - Methods and systems for in situ process control, monitoring, optimization and fabrication of devices and components on semiconductor and related material substrates includes a light illumination system and electrical probe circuitry. The light illumination system may include a light source and detectors to measure optical properties of the in situ substrate while the electrical probe circuitry causes one or more process steps due to applied levels of voltage or current signals. The electrical probe circuitry may measure changes in electrical properties of the substrate due to the light illumination, the applied voltages and/or currents or other processes. The in situ process may be controlled on the basis of the optical and electrical measurements. | 2008-10-16 |
20080254554 | METHOD FOR PRODUCING OPTICAL COUPLING ELEMENT - A method for producing an optical coupling element of the present invention includes the steps of: determining the mounting position of a light-emitting element and a light-receiving element on the front surface of the header portion of each lead frame based on the current amplification factor of the light-receiving element to be mounted; determining the bending angle of each header portion and a distance between the two elements after being bent by calculation such that a predetermined current transfer ratio and an internal insulation distance required by the optical coupling element to be produced are obtained; detecting the determined mounting position by detecting intersections of V-shaped grooves in a grid pattern formed on the front surface of each header portion; mounting each element onto the detected position of the front surface of each header portion while detecting the concave-convex shape; and bending each header portion after mounting each element at the bending angle determined by calculation. | 2008-10-16 |
20080254555 | PATTERNING METHOD FOR LIGHT-EMITTING DEVICES - A method of patterning a substrate that includes: | 2008-10-16 |
20080254556 | Semiconductor Light Emitting Device and Method of Manufacture - A light-emitting diode (“LED”) device has an LED chip attached to a substrate. The terminals of the LED chip are electrically coupled to leads of the LED device. Elastomeric encapsulant within a receptacle of the LED device surrounds the LED chip. A second encapsulant is disposed within an aperture of the receptacle on the elastomeric encapsulant. | 2008-10-16 |
20080254557 | Method for manufacturing lens for led package - A method for manufacturing a lens for a light emitting diode (LED) package is disclosed. The method for manufacturing a lens for an LED package includes: forming a dome lens on each of a plurality of LED packages placed on a fixing plate, the dome lens made of silicon; forming a concave groove in the dome lens by using a jig for pressing the dome lens; curing the dome lens; and removing the LED packages from the fixing plate. | 2008-10-16 |
20080254558 | Side-emitting LED package and method of manufacturing the same - The invention relates to a side-emitting LED package and a manufacturing method thereof. The side-emitting LED package includes a substrate with an electrode formed thereon, and a light source disposed on the substrate and electrically connected to the electrode. The side-emitting LED package also includes a molded part having an upper surface with a center thereof depressed concavely, covering and protecting the substrate and the light source, and a reflection layer covering an entire upper surface of the molded part to reflect light sideward from the molded part which forms a light transmitting surface. The package is not restricted in the shape of the molded part and is not affected by the LED chip size, enabling a compact structure. The invention can also process a substrate by a PCB process, enabling mass-production. | 2008-10-16 |
20080254559 | Method of Fabricating Liquid Crystal Display Device - Provided is a method of fabricating a liquid crystal display device. The method includes fabricating a liquid crystal panel divided into transmission and non-transmission regions, and including an upper substrate and a lower substrate, which are spaced apart from and opposite to each other, and a liquid crystal layer filled between the substrates, wherein the lower substrate has a plurality of thin film transistors; depositing a transparent conductive layer having a certain thickness on the upper substrate exposed to the exterior of the liquid crystal panel; and performing an etching process for removing the entire transparent conductive layer and a portion of the upper substrate to form irregular prominences and depressions on a surface of the upper substrate exposed to the exterior. Therefore, it is possible to improve readability and contrast ratio by diffusely reflecting external light and scattering internal light. | 2008-10-16 |
20080254560 | Display device, method for manufacturing display device, and SOI substrate - A manufacturing method is provided which achieves an SOI substrate with a large area and can improve productivity of manufacture of a display device using the SOI substrate. A plurality of single-crystalline semiconductor layers are bonded to a substrate having an insulating surface, and a circuit including a transistor is formed using the single-crystalline semiconductor layers, so that a display device is manufactured. Single-crystalline semiconductor layers separated from a single-crystalline semiconductor substrate are applied to the plurality of single-crystalline semiconductor layers. Each of the single-crystalline semiconductor layers has a size corresponding to one display panel (panel size). | 2008-10-16 |
20080254561 | METHOD OF FABRICATING VERTICAL STRUCTURE COMPOUND SEMICONDUCTOR DEVICES - A method of fabricating a vertical structure opto-electronic device includes fabricating a plurality of vertical structure opto-electronic devices on a crystal substrate, and then removing the substrate using a laser lift-off process. The method then fabricates a metal support structure in place of the substrate. In one aspects the step of fabricating a metal support structure in place of the substrate includes the step of plating the metal support structure using at least one of electroplating and electro-less plating. In one aspect, the vertical structure is a GaN-based vertical structure, the crystal substrate includes sapphire and the metal support structure includes copper. Advantages of the invention include fabricating vertical structure LEDs suitable for mass production with high reliability and high yield. | 2008-10-16 |
20080254562 | Method of making a light emitting element - A method of making a light emitting element, the light emitting element with a semiconductor layer represented by: Al | 2008-10-16 |
20080254563 | METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE - A method for manufacturing a semiconductor optical device includes: forming a p-type cladding layer; forming a capping layer on the p-type cladding layer the capping layer being selectively etchable relative to the p-type cladding layer; forming a through film on the capping layer; forming a window structure by in implantation; removing the through film after the ion implantation; and selectively removing the capping layer using a chemical solution. | 2008-10-16 |
20080254564 | METHOD FOR MANUFACTURING SOLID-STATE IMAGE SENSOR AND SOLID-STATE IMAGE SENSOR - There is provide a divided exposure technology capable of restraining deterioration in the performance of a solid-state image sensor. A photoresist is formed over a semiconductor substrate and subjected to divided exposure. A dividing line for divided exposure is located at least over a region of a semiconductor substrate in which an active region in which a pixel is to be formed is defined. The photoresist is then developed and patterned. By utilizing the patterned photoresist, an element isolation structure for defining the active region in the semiconductor substrate is formed in the semiconductor substrate. | 2008-10-16 |
20080254565 | METHOD FOR FABRICATING SEMICONDUCTOR IMAGE SENSOR - A semiconductor image sensor and a method for fabricating the same are described. The semiconductor image sensor includes a substrate having at least a photoactive region therein and an IR cutting layer over the photoactive region. | 2008-10-16 |
20080254566 | SURFACE-EMISSION SEMICONDUCTOR LASER DEVICE - A surface-emitting semiconductor laser device includes a semi-insulating substrate, a layer structure with a bottom multilayer reflector, an n-type cladding layer, an active layer structure for emitting laser, a p-type cladding layer and a top multilayer reflector with a dielectric material, consecutively formed on the semi-insulating substrate, the active layer structure, the p-type cladding layer and the top multilayer reflector, configuring a mesa post formed on a portion of the n-type cladding layer, the p-type cladding layer or the p-type multilayer reflector. The surface-emitting semiconductor laser includes a p-side electrode formed on another portion of the p-type cladding layer, and an n-side electrode formed on another portion of the n-type cladding layer. The n-side electrode includes a substantially uniform Au film and AuGeNi film or AuGe film consecutively formed on the n-type cladding layer, and an alloy is formed between said Au film and said AuGeNi film or AuGe film. | 2008-10-16 |
20080254567 | Thick film conductive composition and processe for use in the manufacture of semiconductor device - The present invention is directed to a thick film conductive composition comprising: a) electrically conductive silver powder; b) ZnO powder; c) lead-free glass frits wherein based on total glass frits: Bi | 2008-10-16 |
20080254568 | Composition and Method of Forming a Device - The present invention provides a method of forming a semiconducting device comprising an organic semiconducting material, which method comprises: heating a composition comprising the organic semiconducting material to a temperature at or above the melting point or glass transition temperature of the composition to form a melt; cooling the melt to a temperature below the melting point or glass transition temperature of the composition; and wherein a first substance or object capable of inhibiting and/or preventing dewetting is adjacent the composition before or during heating, or the composition further comprises an agent capable of inhibiting and/or preventing dewetting. | 2008-10-16 |
20080254569 | Semiconductor Device - One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more of a metal oxide including zinc-gallium, cadmium-gallium, cadmium-indium. | 2008-10-16 |
20080254570 | ANGLE CONTROL OF MULTI-CAVITY MOLDED COMPONENTS FOR MEMS AND NEMS GROUP ASSEMBLY - A method of making a mold includes forming spaced mold cavities in a mold body. The mold cavities include geometrically similar portions, but have respective depths below an initial reference surface that vary as a function of position along a particular direction. The mold cavities can be formed using anisotropic etching of preferred crystal directions in single crystal materials such as silicon. A portion of the mold material adjacent the initial reference surface is removed to expose a new reference surface at a tilt angle with respect to the initial reference surface. The modified mold cavities have their respective axes at a new desired tilt angle relative to the new reference surface. | 2008-10-16 |
20080254571 | System in package (SIP) with dual laminate interposers - There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer. There is also provided a method of manufacturing comprising forming a first subassembly by coupling a substrate and a semiconductor die, and forming second subassembly by attaching a controller to an interposer, and coupling the first subassembly to the second subassembly. | 2008-10-16 |
20080254572 | Vertical system integration - The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs. | 2008-10-16 |
20080254573 | INTEGRATED CIRCUIT THERMAL MANAGEMENT METHOD AND APPARATUS - An apparatus, method, and system for providing thermal management for an integrated circuit includes a first metallic layer directly placed on a back surface of the integrated circuit. An integrated heat spreader with a substantially cap-like shape is placed over the integrated circuit, with an aperture of a ceiling wall of the integrated heat spreader exposing a back surface of the integrated circuit at least in part. The first metallic layer is directly placed on top of an exterior surface of the ceiling wall of the integrated heat spreader as well as the back surface of the integrated circuit. | 2008-10-16 |
20080254574 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - By preparing a package substrate which has a plurality of lands of NSMD structure, and the output wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is achieved. | 2008-10-16 |
20080254575 | ENCAPSULATION METHOD AND APPARATUS - A method and apparatus for encapsulating items such as electronic devices. A mold material is dispensed onto the electronic device and the device is situated between first and second molds. One mold is moved towards the other so as to vary the size of a cavity defined by the first and second molds. A vacuum is applied to the cavity and the vacuum is varied in response to the size of the cavity. The vacuum can be varied in response to a predetermined vacuum profile. For example, in certain embodiments the vacuum is varied in response to the position of the first mold relative to the second mold, wherein the vacuum is increased as the cavity height is reduced. | 2008-10-16 |
20080254576 | Method of fabricating a self-aligning damascene memory structure - A method of forming a three-dimensional, non-volatile memory array utilizing damascene fabrication techniques is disclosed. A bottom set of conductors is formed and a set of first pillar shaped elements of heavily doped semiconductor material as formed thereon. A mold is formed of insulating material having pillar shaped openings self-aligned with the first pillar shaped elements and a second semiconductor is deposited over the mold to form second pillar shaped elements aligned with the first pillar shaped elements. The pillar elements formed may be further processed by forming another mold of insulating material having trench openings aligned with the pillar shaped elements and then filling the trenches with conductive material to form conductors coupled to the pillar shaped elements. | 2008-10-16 |
20080254577 | Sectional Field Effect Devices and Method of Fabrication - A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors. | 2008-10-16 |
20080254578 | Method for fabricating thin film transistors - A method for fabricating thin film transistors is disclosed. An amorphous silicon film is formed on a substrated and selectively irradiated with a laser beam for lateral growth to form a plurality of polysilicon regions. The whole surface of the substrate is then oxidized and irradiated with exicer laser annealing. | 2008-10-16 |
20080254579 | Semiconductor device and fabrication thereof - A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap. | 2008-10-16 |
20080254580 | Realization of Self-Positioned Contacts by Epitaxy - Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region of the substrate surface (for example, through epitaxial growth). The growth material is surrounded by an insulating material. The grown material is then removed to form a void in the insulating material which coincides with the desired location of the metal contact. This removal of the grown material exposes the region on the substrate surface. Conductive material is then deposited to fill the void and thus form the metal contact directly with the region of the substrate surface. | 2008-10-16 |
20080254581 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer. | 2008-10-16 |
20080254582 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING SINGLE-ELEMENT TYPE NON-VOLATILE MEMORY ELEMENTS - A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits. | 2008-10-16 |
20080254583 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device includes steps of forming a gate electrode on the surface of a region of a semiconductor substrate provided with a first element, forming an insulating film to cover the surface of the gate electrode and another region of the semiconductor substrate provided with a second element and forming a sidewall insulating film covering the side surface of the gate electrode while leaving the insulating film on the region of the semiconductor substrate provided with the second element by a prescribed thickness by etching the insulating film up to an intermediate portion from the surface thereof. | 2008-10-16 |
20080254584 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method for manufacturing a flash memory device including providing a semiconductor substrate having a cell region and a periphery region; and then adjusting a threshold voltage of the cell region; and then forming a memory device on the cell region and forming a transistor on the periphery region; and then forming an interlayer dielectric layer on the memory device and the transistor, wherein the height of a first portion of the interlayer dielectric layer at the cell region is greater the height of a second portion of the interlayer dielectric layer at the periphery region; and then removing the height difference between the first portion of the interlayer dielectric layer and the second portion of the interlayer dielectric layer. | 2008-10-16 |
20080254585 | Method for fabricating semiconductor memory - A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation region; forming a gate electrode by forming a mask on a surface of the layer of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer of the gate electrode material; forming a charge storing layer at least one of side surfaces of the gate electrode in contact with the convex portion; and forming a sidewall on a part of the charge storing layer. | 2008-10-16 |
20080254586 | SOI SEMICONDUCTOR DEVICE WITH BODY CONTACT AND METHOD THEREOF - A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source. | 2008-10-16 |
20080254587 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES USING SELF-ALIGNED PROCESS TO INCREASE DEVICE PACKING DENSITY - A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure. | 2008-10-16 |
20080254588 | METHODS FOR FORMING TRANSISTORS WITH HIGH-K DIELECTRIC LAYERS AND TRANSISTORS FORMED THEREFROM - A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %. | 2008-10-16 |
20080254589 | METHOD FOR MANUFACTURING COLLARS OF DEEP TRENCH CAPACITORS - A method for manufacturing collars of deep trench capacitors includes providing a substrate with a deep trench in which there is a trench capacitor in the bottom; forming an inner wall layer completely covering the deep trench and the substrate; forming a hard mask layer on the surface of the inner wall layer; performing a selective implanting but not on the hard mask layer on the wall of the deep trench; performing a selective wet etching to remove the not implanted hard mask layer; and performing an anisotropic dry etching to substantially remove the inner wall layer on the bottom of the deep trench so as to partially expose the trench capacitor and to substantially retain the collars of the deep trench capacitors intact. | 2008-10-16 |
20080254590 | Fabrication process for silicon-on-insulator field effect transistors using high temperature nitrogen annealing - Disclosed is a method of fabricating a silicon-on-insulator (SOI) device that enables high device densities and mitigates variances in carrier mobility and saturation drain current (Id | 2008-10-16 |
20080254591 | Method for Making a Thin-Film Element - A method for making a thin-film element includes epitaxially growing a first crystalline layer on a second crystalline layer of a support where the second crystalline layer is a material different from the first crystalline layer, the first crystalline layer having a thickness less than a critical thickness. A dielectric layer is formed on a side of the first crystalline layer opposite to the support to form a donor structure. The donor structure is assembled with a receiver layer and the support is removed. | 2008-10-16 |
20080254592 | Method of forming isolation structure for semiconductor integrated circuit substrate - Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths. | 2008-10-16 |
20080254593 | Method for Fabricating Isolation Layer in Semiconductor Device - A method of fabricating an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, depositing a high-density plasma (HDP) oxide layer partially filling the trench by supplying an HDP deposition source, etching an overhang generated while the HDP oxide layer is deposited using a fluorine-containing etching gas, depositing a liner HDP oxide layer on the HDP oxide layer by supplying an inert gas and an HDP deposition source such that fluorine (F) is trapped in the liner HDP oxide layer, performing an isotropic etching on an overhang portion of a side surface of the HDP oxide layer using the fluorine (F) trapped in the liner HDP oxide layer, and forming an HDP capping layer on the liner HDP oxide layer to fill a remaining portion of the trench. | 2008-10-16 |
20080254594 | STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS - Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si. | 2008-10-16 |
20080254595 | Method for manufacturing SOI substrate - An SOI substrate having no worry about a fluctuation in electrical characteristics due to generation of oxygen donors is provided. | 2008-10-16 |
20080254596 | Method for Transferring Wafers - The invention concerns a method for preparing a thin layer ( | 2008-10-16 |
20080254597 | Method for manufacturing SOI substrate - A method for manufacturing an SOI substrate superior in film thickness uniformity and resistivity uniformity in a substrate surface of a silicon layer having a film thickness reduced by an etch-back method is provided. After B ions is implanted into a front surface of a single-crystal Si substrate | 2008-10-16 |
20080254598 | Laser Irradiation Method, Laser Irradiation Apparatus, And Semiconductor Device - An object of the present invention is obtaining a semiconductor film with uniform characteristics by improving irradiation variations of the semiconductor film. The irradiation variations are generated due to scanning while irradiating with a linear laser beam of the pulse emission. At a laser crystallization step of irradiating a semiconductor film with a laser light, a continuous light emission excimer laser emission device is used as a laser light source. For example, in a method of fabricating an active matrix type liquid crystal display device, a continuous light emission excimer laser beam is irradiated to a semiconductor film, which is processed to be a linear shape, while scanning in a vertical direction to the linear direction. Therefore, more uniform crystallization can be performed because irradiation marks can be avoided by a conventional pulse laser. | 2008-10-16 |
20080254599 | Thermal Processing of Silicon Wafers - Apparatus and methods that minimize surface defect development in silicon wafers during thermal processing at relatively high temperatures at which silicon wafers are annealed and at less extreme temperature, or for other purposes. The apparatus and methods have utility to horizontally-disposed furnaces for silicon wafers and to vertically-oriented furnaces in which larger wafers can be thermally processed. A selectively-sealable process tube encloses silicon wafers during heating of the silicon wafers to a predetermined temperature, and a heating atmosphere supply system induces through the process tube a positive flow of a process gas, such as hydrogen or argon, that is non-reactive with solid silicon at the predetermined temperature. A process tube outlet vents gas from the process tube, and an impurity sensor in the process tube outlet detects oxygen and moisture in the vented gas to verify the purity of the atmosphere surrounding the wafers during thermal processing. | 2008-10-16 |
20080254600 | METHODS FOR FORMING INTERCONNECT STRUCTURES - A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening. | 2008-10-16 |
20080254601 | METHODS FOR OPTIMIZING THIN FILM FORMATION WITH REACTIVE GASES - A method for producing a Group IV semiconductor thin film in a chamber is disclosed. The method includes positioning a substrate in the chamber, wherein the chamber further has a chamber pressure. The method further includes depositing a nanoparticle ink on the substrate, the nanoparticle ink including set of Group IV semiconductor nanoparticles and a solvent, wherein each nanoparticle of the set of Group IV semiconductor nanoparticles includes a nanoparticle surface, wherein a layer of Group IV semiconductor nanoparticles is formed. The method also includes striking a hydrogen plasma; and heating the layer of Group IV semiconductor nanoparticles to a fabrication temperature of between about 300° C. and about 1350° C., and between about 1 nanosecond and about 10 minutes; wherein the Group IV semiconductor thin film is formed. | 2008-10-16 |
20080254602 | METHOD OF IMPURITY INTRODUCTION AND - A method of introducing an impurity into a wafer surface is provided. The method comprises the steps of: low energy implantation of impurity into a surface of the wafer to generate an implanted dopant layer; and simultaneously removing an implanted surface of the implanted dopant layer to generate a doping profile with controlled areal impurity dosage. | 2008-10-16 |
20080254603 | Method of fabricating semiconductor device - There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO | 2008-10-16 |
20080254604 | METHOD FOR FABRICATING A HYBRID ORIENTATION SUBSTRATE - A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer. | 2008-10-16 |
20080254605 | METHOD OF REDUCING THE INTERFACIAL OXIDE THICKNESS - One inventive aspect is related to a method of minimizing the final thickness of an interfacial oxide layer between a semiconductor material and a high dielectric constant material. The method comprises depositing a covering layer on the high dielectric constant material. The method further comprises removing adsorbed/absorbed water from the high dielectric constant material prior to depositing the covering layer. The removal of adsorbed/absorbed water is preferably done by a degas treatment. The covering layer may be a gate electrode or a spacer dielectric. | 2008-10-16 |
20080254606 | Method of Manufacturing Semiconductor Device - Provided is a method of manufacturing a semiconductor device in which properties of photoresist through a lithography process are changed to form a dummy structure, and the structure is applied to a process of forming a gate electrode. The method includes the steps of: forming a buffer layer on the top of a semiconductor substrate; applying an inorganic photoresist on the buffer layer, and forming a photoresist pattern using a lithography process; thermally treating the photoresist pattern using a predetermined gas; uniformly depositing an insulating layer on the thermally treated structure, and etching the deposited layer by the deposited thickness in order to expose the thermally treated photoresist pattern; depositing an insulating layer on the etched structure, and etching the deposited insulating layer to expose the thermally treated photoresist pattern; removing the exposed photoresist pattern using an etching process; forming a gate oxide layer in the portion in which the photoresist pattern is removed; and forming a gate electrode on the gate oxide layer. Accordingly, in forming a structure for manufacturing a nano-sized device, the properties of the layer formed by a lithography process are improved through thermal treatment, and thus the structure used to manufacture various devices can be easily formed. | 2008-10-16 |
20080254607 | INTEGRATION APPROACH TO FORM THE CORE FLOATING GATE FOR FLASH MEMORY USING AN AMORPHOUS CARBON HARD MASK AND ARF LITHOGRAPHY - Systems and methods are described that facilitate integrating ArF core patterning of floating gate structures in a flash memory device followed by KrF periphery gate patterning using a hard mask comprising a material such as amorphous carbon to facilitate core gate construction. The amorphous carbon hard mask can facilitate preparing such core gate structures while protecting periphery gate stacks such that the periphery stacks are ready for immediate KrF lithography upon completion of core gate formation without requiring additional resist deposition between core and periphery etches. | 2008-10-16 |
20080254608 | METHOD OF FORMING CONTACT STRUCTURE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a contact structure includes forming an isolation region defining active regions in a semiconductor substrate. Gate patterns extending to the isolation region while crossing the active regions are formed. A sacrificial layer is formed on the semiconductor substrate having the gate patterns. Sacrificial patterns remaining on the active regions are formed by patterning the sacrificial layer. Molding patterns are formed on the isolation region. Contact holes exposing the active regions at both sides of the gate patterns are formed by etching the sacrificial patterns using the molding patterns and the gate patterns as an etching mask. Contact patterns respectively filling the contact holes are formed. The disclosed method of forming a contact structure may be used in fabricating a semiconductor device. | 2008-10-16 |
20080254609 | APPARATUS AND METHOD FOR ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE - Method of making an electronic fuse blow resistor structure. In one embodiment, the method includes forming an insulator film, depositing a conductor on the insulator film, and after the depositing, etching the conductor to form a plurality of spaced apart non-conductive regions and a plurality of spaced-apart conductive regions. In another embodiment, the method includes forming the insulator film, forming a conductive sheet, and sub-dividing the conductive sheet into the plurality of conductive regions. | 2008-10-16 |
20080254610 | Semiconductor device and process for manufacturing the same - The present invention relates to a semiconductor device in which electrodes formed on a semiconductor chip and electrodes formed on a wiring board are electrically connected via projecting elastic electrodes, and further relates to a mounting method of reducing a pressure applied to electrodes formed on a substrate or underlying wirings when a semiconductor chip and a wiring board are bonded. | 2008-10-16 |
20080254611 | INTERCONNECTION DESIGNS AND MATERIALS HAVING IMPROVED STRENGTH AND FATIGUE LIFE - Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter. | 2008-10-16 |
20080254612 | POLYCARBOSILANE BURIED ETCH STOPS IN INTERCONNECT STRUCTURES - Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition Si | 2008-10-16 |
20080254613 | METHODS FOR FORMING METAL INTERCONNECT STRUCTURE FOR THIN FILM TRANSISTOR APPLICATIONS - Methods for forming a metal interconnection structure in thin-film transistor applications are provided in the present invention. In one embodiment, the method may include providing a substrate into a processing chamber, supplying a first gas mixture into the chamber to deposit a metal layer on the substrate, and supplying a second gas mixture into the chamber to deposit a barrier layer on the metal layer. In another embodiment, a metal interconnection structure may include a substrate, a first barrier layer disposed on the substrate, a metal layer disposed on the substrate in a processing chamber, a second barrier layer disposed on the metal layer formed in the processing chamber a second barrier layer disposed on the metal layer formed in the processing chamber, wherein the first barrier layer, the metal layer and the second barrier layer are configured to form a metal interconnection structure for TFT devices. | 2008-10-16 |
20080254614 | MULTILAYERED CAP BARRIER IN MICROELECTRONIC INTERCONNECT STRUCTURES - Structures having low-k multilayered dielectric diffusion barrier layer having at least one low-k sublayer and at least one air barrier sublayer are described herein. The multilayered dielectric diffusion barrier layer are diffusion barriers to metal and barriers to air permeation. Methods and compositions relating to the generation of the structures are also described. The advantages of utilizing these low-k multilayered dielectric diffusion barrier layer is a gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability as the multilayered dielectric diffusion barrier layer are impermeable to air and prevent metal diffusion. | 2008-10-16 |
20080254615 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface - A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features. | 2008-10-16 |
20080254616 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed. | 2008-10-16 |
20080254617 | Void-free contact plug - A semiconductor device manufacturing process for forming a contact plug includes sequentially depositing a titanium or tantalum contact layer ( | 2008-10-16 |
20080254618 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The invention is directed to improvement of reliability of a semiconductor device having penetrating electrodes by preventing a protection film and an insulation film peeling. A peeling prevention layer for preventing an insulation film and a protection layer peeling is formed in corner portions of the semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method. | 2008-10-16 |
20080254619 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. First, a semiconductor substrate and a dielectric layer positioned on the semiconductor substrate are prepared. Subsequently, the dielectric layer is etched to form a hole structure in the dielectric layer. Afterward, a degas process is performed. An ultraviolet (UV) treatment is carried out to the semiconductor substrate in the degas process so as to expel at least a gas contained in the dielectric layer. Next, a barrier layer is formed on the sidewall and on the bottom of the hole structure. Furthermore, the hole structure is filled with a conductive material. Since the UV treatment can degas the dielectric layer efficiently, the formed semiconductor device can have a fine and stable structure. | 2008-10-16 |
20080254620 | METHOD FOR FABRICATING LANDING PLUG OF SEMICONDUCTOR DEVICE - A method of fabricating a landing plug of a semiconductor device includes performing a double patterning process to separately form a landing plug contact hole for a storage node and a landing plug contact hole for a bit line, thereby facilitating forming a device having a half pitch of 30 nm. | 2008-10-16 |
20080254621 | Wafer Electroless Plating System and Associated Methods - A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM). | 2008-10-16 |
20080254622 | CMOS SILICIDE METAL GATE INTEGRATION - The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure. | 2008-10-16 |
20080254623 | METHODS FOR GROWING LOW-RESISTIVITY TUNGSTEN FOR HIGH ASPECT RATIO AND SMALL FEATURES - The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 μΩ-cm for a 500 Angstrom film may be obtained. | 2008-10-16 |
20080254624 | METAL CAP FOR INTERCONNECT STRUCTURES - A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap. | 2008-10-16 |
20080254625 | Method for Cleaning a Semiconductor Structure and Chemistry Thereof - A method for removing a etch residue (e.g., polymer or particle) from a semiconductor structure and using a cleaning chemistry and the composition of the chemistry is described. By providing a semiconductor structure with etch residue on it, the semiconductor substrate is then placed in a chemistry to remove the particle, wherein the chemistry comprises dilute hydrofluoric acid and a carboxylic acid. In one embodiment the carboxylic acid is selected from tartaric acid, acetic acid, citric acid, glycolic acid, oxalic acid, salicyclic acid, or phthalic acid, and the dilute hydrofluoric acid is approximately 0.1 weight % of hydrofluoric acid. | 2008-10-16 |
20080254626 | PROCESSING APPARATUS - A processing apparatus for transferring a relief pattern on a mold to a resist on a substrate through a compression of the mold against the resist, includes a supplier for supplying the resist between the substrate and the mold, and a recovery unit for recovering the resist. | 2008-10-16 |
20080254627 | METHOD FOR ADJUSTING FEATURE SIZE AND POSITION - Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sidewalls. The critical dimension of the spacers is selected based upon the sidewall positions, so that the spacers are centered at desired positions. The mandrels are removed and the spacers are used as mandrels for a subsequent spacer formation. A second material is then deposited on the first set of spacers, with the critical dimensions of the second set of spacers chosen so that these spacers are also centered at their desired positions. The first set of spacers is removed and the second set is used as a mask for etching a substrate. By selecting the critical dimensions of spacers based partly on the measured position of mandrels, the pitch of the spacers can be finely controlled. | 2008-10-16 |
20080254628 | HIGH THROUGHPUT CHEMICAL MECHANICAL POLISHING COMPOSITION FOR METAL FILM PLANARIZATION - A chemical mechanical polishing process including a single copper removal CMP slurry formulation for planarization of a microelectronic device structure preferably having copper deposited thereon. The process includes the bulk removal of a copper layer using a first CMP slurry formulation having oxidizing agent, passivating agent, abrasive and solvent, and the soft polishing and over-polishing of the microelectronic device structure using a formulation including the first CMP slurry formulation and at least one additional additive. The CMP process described herein provides a high copper removal rate, a comparatively low barrier material removal rate, appropriate material selectivity ranges to minimize copper dishing at the onset of barrier material exposure, and good planarization efficiency. | 2008-10-16 |
20080254629 | Composition and method used for chemical mechanical planarization of metals - Compositions for use in CMP processing and methods of CMP processing. The composition utilizes low levels of particulate material, in combination with at least one amino acid, at least one oxidizer, and water to remove a metal layer such as one containing copper to a stop layer with high selectivity. | 2008-10-16 |
20080254630 | DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES - Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect. | 2008-10-16 |
20080254631 | METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film. | 2008-10-16 |
20080254632 | Method for forming a semiconductor structure having nanometer line-width - A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the Γ-shaped metal gate with nano scale line-width can be formed. | 2008-10-16 |
20080254633 | MULTIPLE EXPOSURE LITHOGRAPHY METHOD INCORPORATING INTERMEDIATE LAYER PATTERNING - A method of patterning a semiconductor substrate includes creating a first set of patterned features in a first inorganic layer; creating a second set of patterned features in one of the first inorganic layer and a second inorganic layer; and transferring, into an organic underlayer, both the first and second sets of patterned features, wherein the first and second sets of patterned features are combined into a composite set of patterned features that are transferable into the substrate by using the organic underlayer as a mask. | 2008-10-16 |
20080254634 | Photoresist composition and method of manufacturing a thin-film transistor substrate using the same - In one example, a photoresist composition includes about 1 to about 70 parts by weight of a first binder resin including a repeat unit represented by the following Chemical Formula 1, about 1 to about 70 parts by weight of a second binder resin including a repeat unit represented by the following Chemical Formula 2, about 0.5 to about 10 parts by weight of a photo-acid generator, about 1 to about 20 parts by weight of a cross-linker and about 10 to about 200 parts by weight of a solvent. The photoresist composition may improve the heat resistance and adhesion ability of a photoresist pattern. | 2008-10-16 |
20080254635 | Method for Accelerated Etching of Silicon - A method for the plasma-free etching of silicon using the etching gas ClF | 2008-10-16 |
20080254636 | Etching of silicon oxide film - An etching method includes preparing a target object such that a first oxide film made of silicon oxide containing at least one of B and P is formed on a substrate, a second oxide film made of silicon oxide containing neither of B and P is formed on the first oxide film, and a contact portion is present below an interface between the first oxide film and the second oxide film. The etching method further includes etching the second oxide film and the first oxide film, thereby forming a hole reaching the contact portion, and etching the first oxide film by a dry process using a gas containing HF, thereby expanding a portion of the hole adjacent to an upper side of the contact portion and inside the first oxide film. | 2008-10-16 |
20080254637 | Methods for removing photoresist defects and a source gas for same - A method for removing at least one photoresist defect is disclosed. The photoresist defect is exposed to a plasma produced from a source gas including oxygen and a non-oxidizing gas in a plasma reactor, wherein the oxygen is present in the source gas at from 1% by volume to about 89% by volume. The non-oxidizing gas includes a mixture of hydrogen and nitrogen, ammonia or combinations thereof. A method for processing a semiconductor device structure is also disclosed, as are embodiments of the source gas. | 2008-10-16 |
20080254638 | ETCH PROCESS WITH CONTROLLED CRITICAL DIMENSION SHRINK - Methods to etch an opening in a substrate layer with reduced critical dimensions are described. A multi-layered mask including a lithographically patterned photoresist and an unpatterned organic antireflective coating (BARC) is formed over a substrate layer to be etched. The BARC layer is etched with a significant negative etch bias to reduce the critical dimension of the opening in the multi-layer mask below the lithographically define dimension in the photoresist. The significant negative etch bias of the BARC etch is then utilized to etch an opening having a reduced critical dimension into the substrate layer. To plasma etch an opening in the BARC with a significant negative etch bias, a polymerizing chemistry, such as CHF | 2008-10-16 |
20080254639 | METHOD FOR ETCHING ORGANIC HARDMASKS - A method of etching or removing an amorphous carbon organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an amorphous carbon organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the amorphous carbon organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the amorphous carbon organic hardmask with the plasma, with the amorphous carbon organic hardmask being at a temperature in excess of 200° C., to remove the amorphous carbon organic hardmask without substantially harming the underlying substrate. | 2008-10-16 |
20080254640 | METHOD OF REMOVING MATERIAL LAYER AND REMNANT METAL - A method of removing material layer is disclosed. First, a semiconductor substrate is fixed on a rotating platform, where a remnant material layer is included on the surface of the semiconductor substrate. Afterward, an etching process is carried out. In the etching process, the rotating platform is rotated, and an etching solution is sprayed from a center region and a side region of the rotating platform toward the semiconductor substrate until the material layer is removed. Since the semiconductor substrate is etched by the etching solution sprayed from both the center region and the side region of the rotating platform, the etching uniformity of the semiconductor substrate is improved. | 2008-10-16 |
20080254641 | Manufacturing Method Of Semiconductor Device And Film Deposition System - A dielectric film ( | 2008-10-16 |
20080254642 | METHOD OF FABRICATING GATE DIELECTRIC LAYER - A method for fabricating gate dielectric layer is provided. First, a sacrificial layer is formed on a substrate. Next, fluorine ions are implanted into the substrate. Then, the sacrificial layer is then removed. Finally, a dielectric layer is formed on the substrate. | 2008-10-16 |
20080254643 | STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND DIELECTRIC CAPPING LAYER - An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO | 2008-10-16 |