42nd week of 2009 patent applcation highlights part 49 |
Patent application number | Title | Published |
20090259827 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CREATING DEPENDENCIES AMONGST INSTRUCTIONS USING TAGS - A system, method, and computer program product are provided for creating dependencies amongst instructions using tags. In operation, tags are associated with a first instruction and a second instruction. Additionally, a dependency is created between the first instruction and the second instruction, utilizing the tags. Furthermore, the first instruction and the second instruction are executed in accordance with the dependency. | 2009-10-15 |
20090259828 | EXECUTION OF RETARGETTED GRAPHICS PROCESSOR ACCELERATED CODE BY A GENERAL PURPOSE PROCESSOR - One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU. | 2009-10-15 |
20090259829 | THREAD-LOCAL MEMORY REFERENCE PROMOTION FOR TRANSLATING CUDA CODE FOR EXECUTION BY A GENERAL PURPOSE PROCESSOR - One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU. | 2009-10-15 |
20090259830 | Quantifying Completion Stalls Using Instruction Sampling - A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath, is marked (tagged) for monitoring by a performance monitoring unit. The progress of marked instructions is monitored by the performance monitoring unit, and various stall counters are triggered by the progress of the marked instructions and the instruction groups they form a part of. The stall counters count cycles to give an indication of when certain delays associated with particular instructions occur and how serious the delays are. | 2009-10-15 |
20090259831 | DEFINING MEMORY INDIFFERENT TRACE HANDLES - A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace. | 2009-10-15 |
20090259832 | RETARGETTING AN APPLICATION PROGRAM FOR EXECUTION BY A GENERAL PURPOSE PROCESSOR - One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU. | 2009-10-15 |
20090259833 | SYSTEM AND METHOD OF ENABLING A FUNCTION WITHIN A MODULE CONFIGURED TO BE USED WITHIN AN INFORMATION HANDLING SYSTEM - A system and method of enabling a function within a module configured to be used with an information handling system is disclosed. In one form, the method of enabling functions includes detecting whether to install a custom install routine within a module configured to enable access to a hash function, and accessing a lock bit configured to lock access to the hash function. The method can further include detecting whether to set the lock bit to lock access to the hash function. | 2009-10-15 |
20090259834 | Manufacturing Information Handling Systems - Manufacturing a virtual information handling system (IHS) includes creating a virtual IHS including a component identifier. A boot process is then begun for the virtual IHS. A manufacturing operating system is then retrieved for the virtual IHS using the component identifier. The manufacturing operating system is then installed on the virtual IHS. Manufacturing a virtual IHS may also include determining a common operating system and a common software subset among a plurality of to-be-manufactured virtual IHSs. A first virtual IHS may then be created and the common operating system may be configured on the first virtual IHS. At least a portion of a first virtual IHS software may also be configured on the first virtual IHS. The configuration of the first virtual IHS software on the first virtual IHS is stopped when the common software subset is configured on the first virtual IHS. The first virtual IHS may then be cloned to create a cloned virtual IHS. | 2009-10-15 |
20090259835 | SYSTEM AND METHOD FOR TRACKING AND RECORDING SYSTEM CONFIGURATIONS OF ELECTRONIC DEVICES - A system for tracking and recording system configurations of an electronic device includes: a storage device; and a microprocessor, for checking whether a current system configuration of the electronic device is different from a first reference configuration of the electronic device, and storing the current system configuration into the storage device if the current system configuration is different from the first reference configuration. | 2009-10-15 |
20090259836 | RUNNING OPERATING SYSTEM ON DYNAMIC VIRTUAL MEMORY - A method making possible booting up and running a system image of an operating system together with diskspace or drivespace, either free or stored with data or application files, for use on the type of storage medium, such as but not limited to internal physical memory or internal RAM, that virtual memory allocated out of the system memory pool upon boot-up can be and is used for mapping for access of such type of storage medium by the operating system under concern in device(s), including computer system(s) or computer-controlled device(s) or operating-system-controlled device(s) capable of running the operating system under concern. | 2009-10-15 |
20090259837 | COMPUTER SYSTEM - A computer system including a first memory unit, a second memory unit and a switch unit is provided. The first memory unit stores a first BIOS. The second memory unit stores a second BIOS. The switch unit has a first configuration and a second configuration. Upon the computer system being started, the switch unit receives an enable signal. When the switch unit is in the first configuration, the enable signal is provided to the first memory unit to start the first basic input/output system. When the switch unit is in the second configuration, the enable signal is provided to the second memory unit to start the second basic input/output system. | 2009-10-15 |
20090259838 | Hardware-Bonded Credential Manager Method and System - An internet data exchange authentication method that can provide much of the user authentication assurance and capability of dedicated computer security cryptographic hardware, without requiring that the user actually have such hardware. This method allows users with computerized devices to communicate securely with secure servers by creating customized challenge-response authentication objects (pockets) where both the challenge and the response is based partially on the hardware identity of the user's computerized device, and partially on a secret (such as a random number) known only by the secure server. The secure server receives the device's hardware identity, generates the secret, creates the pocket, encrypts the pocket, and sends the encrypted pocket back to the user's device. The secure server, or a third trusted credential server, then sends the decryption key for the encrypted pocket back to the user using a different, “out of band” communications modality, thus reducing the chances of interception. | 2009-10-15 |
20090259839 | SECURITY AUTHENTICATION SYSTEM AND METHOD - Authentication system and method are provided. The authentication system includes: a server configured to provide at least two security levels and configured to transmit one of at least two security modules corresponding to the security level of a user terminal, via communications network, to the user terminal based, at least in part, upon an environment of the user terminal; and an authentication server communicatively linked with the server and configured to perform a user authentication in response to a user authentication request from the user terminal. Accordingly, various hackings can be prevented and the user authentication can be accomplished with user's convenience and security. | 2009-10-15 |
20090259840 | Systems and methods for authenticating an electronic message - Systems and methods are disclosed for authenticating electronic messages. A data structure is generated by a computer server which allows for the authentication of the contents and computer server identity of a received electronic message and provides a trusted stamp to authenticate when the message was sent. Data which can authenticate the message, the computer server identity, and the time the message was sent is included into a data structure which is called an Electronic PostMark (EPM). | 2009-10-15 |
20090259841 | Method for allocating multiple authentication certificates to vehicles in a vehicle-to-vehicle communication network - In a vehicle-to-vehicle communication network utilizing PKI security methods to protect communications and in which the PKI encryption utilizes a Certificate Authority having both a private key and a publicly distributed key, a method for allocating multiple certificates for each vehicle which are assigned to each vehicle in the communication network. The method includes the step of assigning a unique secret key k to each vehicle in the communication network. The Certificate Authority then creates a plurality of public key and private key encryption pairs for each vehicle and each encryption pair is associated with an index i. A plurality of certificates are then created with one certificate for each value of the index. A revocation list comprising the secret keys is maintained by the Certificate Authority so that all encryption pairs assigned to a particular vehicle may be revoked by the secret key k corresponding to that vehicle. | 2009-10-15 |
20090259842 | METHOD, PRODUCT AND APPARATUS FOR ACCELERATING PUBLIC-KEY CERTIFICATE VALIDATION - A validation authority for certificates searches for and verifies paths and certificate revocation lists periodically, and classifies the paths into valid paths and invalid paths in accordance with the results of the validations, so as to register the paths in databases beforehand. Besides, in a case where a request for authenticating the validity of a certificate has been received from an end entity, the validation authority judges the validity of the public key certificate by checking in which of the valid-path database and the invalid-path database a path corresponding to the request is registered. On the other hand, in a case where the path corresponding to the validity authentication request is not registered in either of the databases, the validity of the public key certificate is authenticated by performing path search and validation anew. | 2009-10-15 |
20090259843 | REVOCATION OF CRYPTOGRAPHIC DIGITAL CERTIFICATES - Different targets (c | 2009-10-15 |
20090259844 | CONTENT PROVIDING SYSTEM, USER SYSTEM, TRACING SYSTEM, APPARATUS, METHOD, AND PROGRAM - With each embodiment of the present invention, a content providing system comprises a content encrypting section which encrypts content by use of a session key and a header generating section which encrypts the session key by use of an encryption key in such a manner that the session key can be obtained by use of a decryption key assigned to a user system and generates header information including the encrypted session key and one or more values based on user identification information of each of the user systems that are permitted to obtain the session key. The content providing system transmits the encrypted content and the header information to each user system. Since the header information does not explicitly include user identification information of the user systems, information about whose decryption keys have been revoked is not leaked out in the block box tracing. | 2009-10-15 |
20090259845 | System and method for execution of a secured environment initialization instruction - A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations. | 2009-10-15 |
20090259846 | Exception types within a secure processing system - An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain. | 2009-10-15 |
20090259847 | Security protocols for hybrid peer-to-peer file sharing networks - In a hybrid peer-to-peer file sharing network including a receiver peer and a provider peer, the receiver sends the provider a ticket [ | 2009-10-15 |
20090259848 | OUT OF BAND SYSTEM AND METHOD FOR AUTHENTICATION - A method and system for out of band authentication for ensuring a user is in possession of a device. | 2009-10-15 |
20090259849 | Methods and Apparatus for Authenticated User-Access to Kerberos-Enabled Applications Based on an Authentication and Key Agreement (AKA) Mechanism - Methods and apparatus are provided for authenticated user-access to Kerberos-enabled applications based on an Authentication and Key Agreement mechanism. A user is first authenticated using an Authentication and Key Agreement mechanism based on a bootstrapping protocol that mutually authenticates the user and one or more servers; and, once the user is authenticated, the user is enabled to derive a session key and is provided with a first ticket to a Ticket Granting Server. The first ticket can establish an identity of the user and include the session key. The bootstrapping protocol can be based on a Generic Bootstrapping Architecture | 2009-10-15 |
20090259850 | Information Processing Device and Method, Recording Medium, Program and Information Processing System - An information processing device regarding which access to data held by the information processing device itself, in multiple regions, is requested from another information processing device, includes: an authenticating unit to perform authenticating processing of the other information processing device; a receiving unit to receive an access license ticket including an access code and a check digit; an access license ticket generating key generating unit to generate an access license ticket generating key, which is key information for computing a check digit using data held beforehand, a root key, an access control key, and other key information which is key information to manage data of a region other than the predetermined region, corresponding to an access code; check digit computing unit to compute a check digit corresponding to the access code described in the access license ticket; and access license ticket validating unit to validate the access license ticket. | 2009-10-15 |
20090259851 | Methods and Apparatus for Authentication and Identity Management Using a Public Key Infrastructure (PKI) in an IP-Based Telephony Environment - Methods and apparatus arc provided for user authentication using a Public Key Infrastructure (PKI) in an IP-based telephony environment, such as an IMS network. A user of a user device attempting to access an IP-based telephony network can be authenticated by obtaining one or more private keys of the user from a secure memory associated with the user device; generating an integrity key and a ciphering key; encrypting the integrity key and the ciphering key using a session key; encrypting the session key with a public key of the IP-based telephony network; and providing the encrypted session key, encrypted integrity key and encrypted ciphering key to the IP-based telephony network for authentication. A network-based method is also provided for authenticating a user in an IP-based telephony network. | 2009-10-15 |
20090259852 | RELIABLE STORAGE MEDIUM ACCESS CONTROL METHOD AND DEVICE - A method of and device for granting access to content on a storage medium, including obtaining cryptographic data from a property, such as a wobble, of the storage medium, reading helper data from the storage medium, and granting the access based on an application of a delta-contracting function to the cryptographic data and the helper data. The delta-contracting function allows the choice of an appropriate value of the helper data, such that any value of the cryptographic data which sufficiently resembles the original primary input value leads to the same output value. Substantially different values of the cryptographic data lead to different values of the output. | 2009-10-15 |
20090259853 | DYNAMIC MULTIMEDIA FINGERPRINTING SYSTEM - A dynamic multimedia fingerprinting system is provided. A user requests multimedia content from a Web cache server that verifies that the user is authorized to download the content. A custom fingerprint specific to the user is generated and dynamically inserted into the content as the content is delivered to the user. The custom fingerprint can be generated on the Web cache server or at the content provider's server. The system allows a content provider to specify where the custom fingerprint is inserted into the content or where the fingerprint is to replace a placeholder within the content. | 2009-10-15 |
20090259854 | METHOD AND SYSTEM FOR IMPLEMENTING A SECURE CHAIN OF TRUST - A method, an integrated circuit and a system for implementing a secure chain of trust is disclosed. While executing secure boot code in a secure boot mode, less-secure boot code may be authenticated using a secret key. A secure key may also be calculated or generated during the secure boot mode. After control is turned over to the authenticated less-secure boot code, at least one application may be authenticated using the secure key. Once authenticated in the less-secure boot mode, the application may be executed by the programmable integrated circuit. In this manner, a secure chain of trust may be implemented for the programmable integrated circuit. | 2009-10-15 |
20090259855 | Code Image Personalization For A Computing Device - A method and apparatus for personalizing a software component to be executed in particular environment are described herein. According to an aspect of the invention, in response to an executable code image representing a software component to be installed in an electronic device, the executable code image is encrypted using an encryption key. The encryption key is then wrapped with a UID that uniquely identifies the electronic device, where the UID is embedded within a secure ROM of the electronic device. The wrapped encryption key and the encrypted executable code image are then encapsulated into a data object to be stored in a storage of the electronic device, such that when the electronic device is subsequently initialized for operation, the executable code image can only be recovered using the UID of the electronic device to retrieve a decryption key in order to decrypt the executable code image. | 2009-10-15 |
20090259856 | DATA PROCESSING APPARATUS - A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal. | 2009-10-15 |
20090259857 | System and Method for Efficient Security Domain Translation and Data Transfer - A mobile UE includes a CPU, a secure DMA module, a secure cryptographic module, secure memory, and non-secure memory. The secure cryptographic module and secure memory allow access only by secure processes, including the secure DMA module. The CPU manages cryptographic keys and initializes DMA transfers in secure mode. The CPU executes the DMA transfers in non-secure mode. A first DMA transfer moves data encrypted in a first security domain to the secure cryptographic module, and moves clear text data to the secure memory. A second DMA transfer moves the clear text data to the secure cryptographic module, and data encrypted in a second security domain out of the secure cryptographic module. The data encrypted in the second security domain are transmitted to an external device. The secure memory protects the clear text data from being copied; only encrypted data is accessible by non-secure processes. | 2009-10-15 |
20090259858 | METHOD AND APPARATUS FOR THE SECURE STORAGE OF AUDIO SIGNALS - In one embodiment, a method, system and apparatus for recording audio is provided so that the recording can be authenticated. The system may be implemented as a central server that is accessed via one or more lines for audio communication, or as a stand-alone unit. The system operates by encrypting communicated data (e.g., audio signals), storing the encrypted information, and providing at least one user with a key that can be used to decrypt the stored information. | 2009-10-15 |
20090259859 | POWER SUPPLY SYSTEM FOR MOTHERBOARD - An exemplary power supply system and method for a motherboard includes a power circuit providing power for a south bridge, and a controller having first and second transistors. An input terminal of the power circuit is connected to a power supply. An output terminal of the power circuit is connected to a reset pin of the south bridge. A first terminal of the first transistor is configured for receiving a control signal from the south bridge. A second terminal of the first transistor is connected to a first terminal of the second transistor. A second terminal of the second transistor is connected to the reset pin of the south bridge. Each of the first and second transistors has a third terminal grounded. | 2009-10-15 |
20090259860 | POWER SUPPLY CIRCUIT FOR MOTHERBOARD - A power supply circuit for a motherboard includes an input/output (I/O) controller, a power circuit providing a working voltage for the I/O controller, and a first resistor. The I/O controller includes an I/O controller voltage pin and an I/O controller case open detection (COPEN) pin. The power circuit includes an input, a first output, a second output, and a GND pin. The input of the power circuit is connected to a standby power supply; and the first output of the power circuit is connected to the I/O controller voltage pin. The second output of the power circuit is connected to the I/O controller COPEN pin via the first resistor; and the GND pin of the power circuit is grounded. | 2009-10-15 |
20090259861 | POWER MANAGEMENT IN A DATA PROCESSING DEVICE HAVING MASTERS AND SLAVES | 2009-10-15 |
20090259862 | CLOCK-GATED SERIES-COUPLED DATA PROCESSING MODULES - A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data. | 2009-10-15 |
20090259863 | RESPONDING TO INTERRUPTS WHILE IN A REDUCED POWER STATE - To reduce power consumption, a processor can be placed into a reduced power state. Before doing so, interrupt events can be designated as wakeup events. While the processor is in the reduced power state, if an event designated as a wakeup event occurs, then a signal is directed to a wakeup event handler instead of to an interrupt handler. In response to the signal, the wakeup event handler causes power to be restored to the processor, so that the event can be subsequently serviced. | 2009-10-15 |
20090259864 | SYSTEM AND METHOD FOR INPUT/OUTPUT CONTROL DURING POWER DOWN MODE - A system and method for maintaining values on output pads of an integrated circuit during entry, exit, and while a portion of the integrated circuit is in a power conservation or deep power down mode. The method for entering a power conservation mode includes determining a power conservation mode value which will be maintained at an output pad while a portion of an integrated circuit is in a power conservation mode. The power conservation mode value may then be selected for output and the power conservation mode value is held at the output pad. The portion of the integrated circuit to enter the power conservation mode is then electrically decoupled from the output pad. The portion of the integrated circuit may then be placed in the power conservation mode without output signal slighting while maintaining the output value. | 2009-10-15 |
20090259865 | Power Management Using At Least One Of A Special Purpose Processor And Motion Sensing - A power management device useable in a mobile station includes a main processor configured to execute applications including signal processing applications and further configured to enter a sleep mode in response to predetermined criteria. The device further includes a circuit configured to operate when the main processor is in the sleep mode comprising at least one of a low power processor and a sensor to monitor at least one of signals, commands, inputs, and changes in environment, the circuit waking up the main processor responsive to one of the low power processor and the sensor. The device may operate a method and may execute instructions based on a machine readable medium. | 2009-10-15 |
20090259866 | ELECTRONIC DEVICE AND POWER SUPPLY UNIT - An electronic device has: an operation unit; a power supply unit; an input changeover switch; and a controller. The power supply unit is supplied commercial power and supplies the operating power to the operation unit. The input changeover switch switches between supplying or not supplying the commercial power to the power supply unit. The controller controls the input changeover switch. The controller includes: a power input portion; a control signal input portion; and a switching signal output portion. When the device power is being supplied from a master electronic device to the power input portion and the control signal from the master electronic device is received by the control signal input portion, the switching signal output portion outputs to the input changeover switch a signal instructing to switch and supply the commercial power to the power supply unit. | 2009-10-15 |
20090259867 | Power Supply Capable of Receiving Digital Communications from Electronic Devices - A power supply capable of receiving digital communications from an electrical device is described. The power supply includes a microprocessor and instructions, configured for execution by the microprocessor, to receive a digital communication from a device to be powered by the power supply. A method of supplying power is also described. The method includes receiving a digital communication from a device and supplying power to the device based on the digital communication. | 2009-10-15 |
20090259868 | INFORMATION PROCESSING APPARATUS, POWER MODE CONTROL METHOD, AND POWER MODE CONTROL PROGRAM PRODUCT - An information processing apparatus switches from a regular power mode to a power saving mode in the event that a first control unit does not process packets for a certain period of time. The information processing apparatus includes a packet table in which packets to be processed by the first control unit are registered, and a determining unit for determining whether the system of the information processing apparatus can switch to the power saving mode. In the event that the determining unit determines that the system can switch to the power saving mode, a network controller processes the packets based on the packet table. | 2009-10-15 |
20090259869 | SAMPLING CHIP ACTIVITY FOR REAL TIME POWER ESTIMATION - A system and method for real-time power estimation. A core may be divided into units. Each unit is simulated to achieve a real power consumption characterization. The power consumption is sampled. Statistical analysis is performed that assumes the core has node capacitance switching behavior that is approximated by a stationary random process with a Poisson distribution. The statistical analysis determines the number of samples to take during a sample interval. The operational frequency, sample interval, and number of samples are used to determine the number of signals to sample. Signals are chosen that have a high correlation with the node capacitance switching behavior, such as clock enable signals on the last stage of a clock distribution system. Weights with tuned values are assigned to each sampled signal. Sampling occurs during every predetermined number of clock cycles. The weights of asserted sampled signals are summed in order to determine a repeatable power estimation value. | 2009-10-15 |
20090259870 | MANAGING TIMERS IN A MULTIPROCESSOR ENVIRONMENT - Timers are managed in a multiprocessing environment. Some timers are local to a given logical processor; such a local timer is inserted on and will be canceled only from that logical processor. Other timers are global to a logical processor. A global timer which was inserted on a given logical processor may be canceled from that logical processor or from another logical processor. Global timers are serviced in response to expiration of an associated local timer. | 2009-10-15 |
20090259871 | SYNCHRONIZING SIGNALS RELATED TO THE OPERATION OF A COMPUTER SYSTEM - Some embodiments of the present invention provide a system that synchronizes signals related to the operation of a computer system. During operation, a set of correlation coefficients between a first signal and a second signal is generated, wherein each correlation coefficient is associated with a different phase shift between the first signal and the second signal. Then, a synchronizing phase shift associated with the highest correlation coefficient in the set of correlation coefficients is determined in order to synchronize the first signal and the second signal. | 2009-10-15 |
20090259872 | PROGRAMMABLE DATA SAMPLING RECEIVER FOR DIGITAL DATA SIGNALS - Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes a linear receiver portion having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver portion is configured to compare the DQ signal to the reference voltage, and to generate the differential output signal in response to the comparison. A sense amplifier portion is coupled to the linear receiver portion. The sense amplifier portion has input nodes connected to the output nodes of the linear receiver portion, and an output node for a binary output signal having voltage characteristics compatible with the computer processor. The sense amplifier portion is configured to transform the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver portion, the programming architecture being configured to set operating characteristics of the linear receiver portion. | 2009-10-15 |
20090259873 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER SAVING FEATURE - A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state. | 2009-10-15 |
20090259874 | DATA TRANSFER DEVICE AND METHOD THEREOF - A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate. | 2009-10-15 |
20090259875 | Store Clock and Store Clock Fast Instruction Execution - Two forms of TOD Clock instructions are provided, Store Clock and Store Clock Fast. Execution of the Store Clock Fast instruction may produce a time of day (TOD) result that is exactly the same as a previous TOD result, however execution of Store Clock Fast instructions while the clock is running always produce unique TOD results. | 2009-10-15 |
20090259876 | COMPUTER SYSTEM AND METHOD FOR AUTOMATICALLY OVERCLOCKING - A computer system for automatically overclocking includes an overclocking element, a detecting circuit and a basic input/output system (BIOS). The overclocking element has a signal standard. The detecting circuit is used for acquiring an I/O signal of the overclocking element. The BIOS is used for comparing the signal standard with the I/O signal to obtain a comparing result. The BIOS is further used for adjusting a reference signal according to the comparing result. The reference signal is an input signal of the overclocking element. | 2009-10-15 |
20090259877 | Method to Implement a Monotonic Counter with Reduced Flash Part Wear - A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicating a first increment field of the plurality of increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter. | 2009-10-15 |
20090259878 | Multirate transmission system and method for parallel input data - A multirate transmission system for transmitting parallel input data from a first location to a second location includes a transmitter portion and a receiver portion. The transmitter portion receives the parallel data, including the information related to a parallel data clock and stores the data in a buffer where it is subsequently read and serialized for transmission on a serial data link to the receiver portion where it is deserialized, including recovery of the parallel data clock in the serialized data stream. The receiver portion stores the parallel data in a buffer where it is read at a data rate corresponding to the parallel data clock of the incoming parallel data. The parallel data at the transmitter portion is associated with generated control characters when parallel data is not read from the buffer associated with the transmitter portion. | 2009-10-15 |
20090259879 | DETERMINING CORRECTIVE ACTIONS USING A GEOMETRICALLY-BASED DETERMINATION OF SUFFICIENT CONFIDENCE - A method, system, and apparatus for determining a corrective action for a diagnosable system are provided. A failure mode reasoning engine (FMRE) receives an evidence notification. The FMRE determines a plurality of evidentiary-failure-mode-probability rectangles (EFMPRs) based on the evidence notification. A candidate EFMPR in the plurality of EFMPRs is determined. The candidate EFMPR may be determined based on a distance from an origin of an evidentiary-failure-mode-probability graph. An overlap area is determined between the candidate EFMPR and the other EFMPRs in the plurality of EFMPRs. The overlap area is compared to an overlap threshold. If the overlap area is less than the overlap threshold, a reasoned failure mode (i.e., correct diagnosis) and/or a reasoned corrective action for the diagnosable system is determined, based on the candidate EFMPR. The FMRE may report and/or take the reasoned corrective action. | 2009-10-15 |
20090259880 | PROCESS FLOW EXECUTION APPARATUS, CONTROL METHOD THEREOF, AND STORAGE MEDIUM STORING CONTROL PROGRAM THEREFOR - A process flow execution apparatus capable of notifying a user of a task or a setting that is not supported in an application of a version lower than a version set in a process flow that describes process contents of a plurality of tasks. A process flow application handling the process flow is installed in the apparatus that can communicate with another apparatus capable of handling the process flow application, via a network. An acceptance unit accepts an instruction to execute the plurality of tasks based on the process flow. A control unit controls to display a warning screen on a display unit if a version of a process flow application that generates the process flow for which the acceptance unit has accepted the execution instruction is higher than a version of the process flow application installed in the process flow execution apparatus. | 2009-10-15 |
20090259881 | FAILSAFE RECOVERY FACILITY IN A COORDINATED TIMING NETWORK - A failsafe recovery capability for a Coordinated Timing Network. The recovery capability facilitates recovery when communication is lost between two servers of the coordinated timing network. The capability includes checking another system's status in order to determine what action is to be taken. The status includes the stratum level of the servers and a version number indicating the code level of the servers. | 2009-10-15 |
20090259882 | APPARATUS AND METHOD FOR IDENTIFYING DISK DRIVES WITH UNREPORTED DATA CORRUPTION - A RAID controller uses a method to identify a storage device of a redundant array of storage devices that is returning corrupt data to the RAID controller. The method includes reading data from a location of each storage device in the redundant array a first time, and detecting that at least one storage device returned corrupt data. In response to detecting corrupt data, steps are performed for each storage device in the redundant array. The steps include reading data from the location of the storage device a second time without writing to the location in between the first and second reads, comparing the data read the first and second times, and identifying the storage device as a failing storage device if the compared data has a miscompare. Finally, the method includes updating the location of each storage device to a new location and repeating the steps for the new location. | 2009-10-15 |
20090259883 | ROBUST SYNCHRONIZATION OF DIAGNOSTIC INFORMATION AMONG POWERTRAIN CONTROL MODULES - An automotive system has a primary control module, such as an engine control module (ECM) configured for connection to a malfunction indicator lamp (MIL), and a secondary control module, such as a transmission control module (TCM), each in communication with each other over a bus. Each control module includes a respective diagnostic data status record. Each record includes a pending fault field, a confirmed fault field and an MIL control status field. An improved method for synchronizing the diagnostic data contained in the respective status records includes an extended status signal set that is used to communicate over the bus. The set includes a diagnostic testing complete signal, a fault present signal and a MIL request signal indicative of a request to illuminate the MIL. Logic in the receiving control module (ECM) interprets the extended status signal set to properly synchronize its diagnostic data status record with the TCM's, including both pending and confirmed faults. | 2009-10-15 |
20090259884 | COST-REDUCED REDUNDANT SERVICE PROCESSOR CONFIGURATION - A redundant service processor configuration is provided. A first processor in a first node operates elements in the first node. A first control line connects the first processor to a first multiplexer in the first node. A second processor in a second node operates elements in the second node. A second control line connects the second processor to a second multiplexer in the second node. The first control line from the first processor connects to the second multiplexer. The second control line from the second processor connects to the first multiplexer. In response to a failure of the second processor, the first processor operates the first multiplexer to initialize the elements of the first node, the second processor is switched off, and the first processor operates the second multiplexer to initialize the elements of the second node. Analogous operations occur in response to a failure of the first processor. | 2009-10-15 |
20090259885 | Systems and methods for redundancy management in fault tolerant computing - Systems and methods for redundancy management in fault tolerant computing are provided. The systems and methods generally relate to enabling the use of non-custom, off-the-shelf components and tools to provide redundant fault tolerant computing. The various embodiments described herein, generally speaking, use a decrementer register in a general purpose processor for synchronizing identical operations across redundant general purpose processors, execute redundancy management services in the kernels of commercial off-the-shelf real-time operating systems (RTOS) running on the general purpose processors, and use soft coded tables to schedule operations and assign redundancy management parameters across the general purpose processors. | 2009-10-15 |
20090259886 | APPARATUS AND METHODS FOR RESTORING SYSTEM OPERATION STATES - A process for restoring an operational state of a portable handheld device is provided. The device may include multiple computing units and persistent storage. The operational state may be generated by a sequence of events. The operational state may receive signals corresponding to a plurality of event types. The process may include selecting an event type for storage, storing in the persistent storage events corresponding to the selected event type, receiving a signal indicating an interruption of operation, and transmitting the stored events to restore the device to the operational state. | 2009-10-15 |
20090259887 | SELF-SERVICE TERMINAL EQUIPMENT AND GUIDANCE SCREEN PROCESSING METHOD - A self-service terminal equipment includes at least one input/output device, a display device, a storage unit, and a control unit, wherein the storage unit includes a guidance information storage unit that stores recovery information in association with guidance information, the control unit includes a user program executing unit, and an input/output interface control unit, and the input/output interface control unit includes a command information control unit that outputs command information to the input/output device such that the input/output device is controlled, a recovery information control unit that inputs the recovery information output from the input/output device controlled, and a guidance screen control unit that obtains the guidance information stored in the guidance information storage unit corresponding to the recovery information input by control of the recovery information control unit and displays a guidance screen that displays the guidance information on the display device. | 2009-10-15 |
20090259888 | APPARATUS FOR DISPLAYING BIOS POST CODE AND METHOD THEREOF - An apparatus for displaying a basic input output system (BIOS) power-on self-test (POST) code and a method thereof are provided. The apparatus includes a BIOS, a conversion module, and an output module. The BIOS is used for generating a POST code. The POST code is transmitted via a low pin count (LPC) interface. The conversion module receives the POST code and converts the POST code into a system management bus (SMBus) format. The output module is used for receiving and outputting the POST code transmitted by the conversion module. The output module is an SMBus interface. | 2009-10-15 |
20090259889 | TEST DEVICE AND METHOD FOR HIERARCHICAL TEST ARCHITECTURE - A test device for a hierarchical test architecture is disclosed. The architecture includes cores for plural test layers, a top-level data register, and a top-level test controller. Cores for each test layer are hierarchical test circuits. The top-level test controller retrieves plural control signals, controls the top-level data register based on first type control signals in the control signals, and controls each core based on second type control signals in the control signals. | 2009-10-15 |
20090259890 | Method & apparatus for hardware fault management - A hardware health evaluation module is associated with a hardware module or device and employs a linked list of error records to continually evaluate the state of the hardware module to determine whether or not it is currently operating with or without errors. In the event that the health evaluation module determines that the hardware module is not operating in an error free manner, it detects and stores, for a specified period of time, an indication of the error and associates this detected error or errors with one or more of the error records. The error records are designed to provide assistance in diagnosing the cause of a hardware error. | 2009-10-15 |
20090259891 | DEFECT DETECTION APPARATUS FOR OPTICAL DISC AND METHOD THEREOF - Disclosed is a defect detection apparatus of an optical disk drive. The optical disc drive records a set of first data onto at least one data unit of an optical disc. The defect detection apparatus comprises an error detector and a defect verification unit. The error detector receives the set of first data, being recorded and the set of second data derived from the data unit of the optical disc, and then compares the set of first data with that of second data to generate error information of the set of second data. The defect verification unit determines whether the data unit is defective according to the error information. The object that the defect detection apparatus of the invention performs verification for can be a sector, an ECC Block or a cluster. The error detector can be a channel bit error detector, a byte error detector or a frame error detector. | 2009-10-15 |
20090259892 | Method and Apparatus for Producing a Metastable Flip Flop - The method includes predetermining an output enable time period by measuring the maximum settling time when a signal is read during a transition from 0 to 1 or vice versa, and multiplying the maximum settling time by a safety factor 2.5, to set an output enable time period; reading and latching an input value; and transmitting the latched value onward after the predetermined output enable time period. An embodiment of the apparatus | 2009-10-15 |
20090259893 | 10GBase-T training algorithm - A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied. | 2009-10-15 |
20090259894 | ERROR CORRECTION FOR DISK STORAGE MEDIA - Embodiments of the invention provide methods and systems for improving the reliability of data stored on disk media. Logical redundancy is introduced into the data, and the data within a logical storage unit is divided into sectors that are spatially separated by interleaving them with sectors of other logical storage units. The logical redundancy and spatial separation reduce or minimize the effects of localized damage to the storage disk, such as the damage caused by a scratch or fingerprint. Thus, the data is stored on the disk in a layout that improves the likelihood that the data can be recovered despite the presence of an error that prevents one sector from being read correctly. | 2009-10-15 |
20090259895 | SEMICONDUCTOR MEMORY DEVICE PARALLEL BIT TEST CIRCUITS - Parallel bit test circuits for use in a semiconductor memory devices are provided which include a first bus that has N bus lines that are configured to transfer a first group of N bits of test result data and a second bus that has N bus lines that are configured to transfer a second group of N bits of test result data. These parallel bit test circuits further include a switching unit that has a plurality of unit switches, where each switch is configured to connect a bus line of the first bus and a respective bus line of the second bus in response to a switching control signal that is applied after the second group of N bits of test result data are output from the second bus, to transfer the first group of N bits of test result data from the first bus to the second bus so as to output a total of 2N bits of test result data through the second bus. | 2009-10-15 |
20090259896 | BAD BLOCK IDENTIFYING METHOD FOR FLASH MEMORY, STORAGE SYSTEM, AND CONTROLLER THEREOF - A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged. | 2009-10-15 |
20090259897 | Logic circuit protected against transient disturbances - The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit ( | 2009-10-15 |
20090259898 | Test vector generating method and test vector generating program of semiconductor logic circuit device - The X-type of each bit permutation is determined (step | 2009-10-15 |
20090259899 | METHOD AND APPARATUS FOR AUTOMATIC SCAN COMPLETION IN THE EVENT OF A SYSTEM CHECKSTOP - A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred. | 2009-10-15 |
20090259900 | TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT - A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern. | 2009-10-15 |
20090259901 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 2009-10-15 |
20090259902 | Semiconductor device - Provided is a semiconductor device that can be reduced in size while variation in shape among circuit patterns is reduced. The semiconductor device includes multiple circuit patterns and first dummy patterns. The multiple circuit patterns are disposed at regular intervals, and are used as part of the circuit. The multiple circuit patterns consist of two outermost circuit patterns and the other inner circuit patterns. The first dummy patterns are disposed on outer sides of the two outermost circuit patterns, respectively. The distance between each of the outermost circuit patterns and the corresponding first dummy pattern is equal to a distance between any adjacent two of the circuit patterns. A width of each of the first dummy patterns is smaller than a width of any of the circuit patterns, and is equal to a minimum design rule width, for example. | 2009-10-15 |
20090259903 | WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE - Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals. | 2009-10-15 |
20090259904 | Testing Mobile Wireless Devices During Device Production - A system and method of testing a wireless communication device during device production comprises designating as a data log buffer when the device is being produced, at least part of random access memory (RAM) of the device that is allocated for virtual machine and/or application usage when the device is operational; and testing the device and storing test log data in the buffer. After testing, the data can be obtained from the buffer and processed using a debugging and log analysis tool. | 2009-10-15 |
20090259905 | SYSTEM AND METHOD FOR QUANTUM COMPUTER CALIBRATION AND PERFORMANCE ESTIMATION - A system and method for characterizing noise in a quantum system includes determining pulse sequences for unitary twirling operations. Twirling processes are applied to a quantum system to calibrate errors and to determine channel parameters. Noise characteristics are determined from calibration data collected to calibrate the errors and to determine the channel parameters. The noise characteristics are characterized to determine if the noise is independent relaxation of qubits or collective relaxation of qubits. | 2009-10-15 |
20090259906 | DATA SUBSTITUTION SCHEME FOR OVERSAMPLED DATA - Low latency and computationally efficient techniques may be employed to account for errors in data such as low bit-width, oversampled data. In some aspects these techniques may be employed to mitigate audio artifacts associated with sigma-delta modulated audio data. In some aspects an error may be detected in a set of encoded data based on an outcome of a channel decoding process. Upon determining that a set of data may contain at least one error, the set of data may be replaced with another set of data that is based on one or more neighboring data sets. For example, in some aspects a set of data including at least one bit in error may be replaced with data that is generated by applying a cross-fading operation to neighboring data sets. In some aspects a given data bit may be flipped as a result of a linear prediction operation that is applied to PCM equivalent data that is associated with the given data bit and its neighboring data bits. In some aspects a set of data including at least one bit in error may be replaced with data that is generated by performing linear interpolation operations on PCM equivalent data that is associated with neighboring data sets. | 2009-10-15 |
20090259907 | Inter-packet selective symbol mapping in a joint incremental redundancy and symbol mapping diversity system - An integrated incremental redundancy symbol mapping diversity system for a communication device. The integrated incremental redundancy symbol mapping diversity system includes a transmitter. The transmitter packetizes a retransmission packet according to a modulation scheme in response to a retransmission request from the receiver. The transmitter includes an output packet processor and an inter-packet selective symbol mapper. The output packet processor determines a transmission iteration of a bit segment of the retransmission packet. The inter-packet selective symbol mapper applies a first symbol map pattern to the bit segment based on the transmission iteration of the bit segment and applies a second symbol map pattern to another bit segment of the retransmission packet based on the transmission iteration of the other bit segment. The first symbol map pattern is different from the second symbol map pattern. | 2009-10-15 |
20090259908 | ARQ AND HARQ PROTOCOL DATA UNITS AND METHOD OF FORMATION - The present invention provides for a method of forming at least one ARQ PDU from an ARQ service data unit (SDU), the ARQ PDU comprising a header portion and a data portion, and the method including selective addition of a Length Indicator field to the said header portion responsive to the determination of the presence in the PDU of the last bit of an ARQ SDU and if a HARQ PDU is formed of a plurality of ARQ PDUs wherein the last of the ARQ PDUs is arranged not to include an LI within its header if it is found not to be carrying the last bit of the ARQ SDU and LI will be added to all other ARQ PDUs though they are not carrying last bit of ARQ SDU. | 2009-10-15 |
20090259909 | PHYSICAL HARQ INDICATOR CHANNEL (PHICH) RESOURCE ASSIGNMENT SIGNALING IN A WIRELESS COMMUNICATION ENVIRONMENT - Systems and methodologies are described that facilitate signaling Physical Hybrid Automatic Repeat Request (HARQ) Indicator Channel (PHICH) resource assignments in a wireless communication environment. At least a portion of a current PHICH resource assignment for a current Transmission Time Interval (TTI) and at least a portion of a subsequent PHICH resource assignment for a subsequent TTI can be encoded within a common encoded signal. Further, the common encoded signal can be sent to an access terminal during the current TTI. For instance, the common encoded signal can be transmitted via a Physical Broadcast Channel (PBCH). Alternatively, the common encoded signal can be sent through dedicated Radio Resource Control (RRC) signaling during handover. The access terminal can decode the common encoded signal received from the base station to identify the current PHICH resource assignment (or portion thereof) and the subsequent PHICH resource assignment (or portion thereof). | 2009-10-15 |
20090259910 | METHOD AND APPARATUS FOR PERFORMING RANDOM ACCESS PROCEDURES - A mobile terminal and a method of performing a random access procedure by the terminal is achieved by transmitting a random access preamble to a base station, receiving a random access response from the base station, and performing an uplink transmission using an uplink grant from the base station. The uplink transmission is performed by using a maximum number of HARQ (Hybrid Automatic Repeat reQuest) transmissions parameter, which is included in a System Information Block (SIB) received from the base station. | 2009-10-15 |
20090259911 | Method and Apparatus for Improving Transmission Time Interval Bundling - A method for improving transmission time interval bundling transmission in a wireless communication system includes transmitting a first bundle at a first time point, and transmitting a second bundle at a second time point behind the first time point, wherein the second time point is located in a bundle round trip time of the first bundle, and the bundle round trip time is a specific multiple of a Hybrid Automatic Repeat Request Round Trip Time. | 2009-10-15 |
20090259912 | LDPC CODES AND STOCHASTIC DECODING FOR OPTICAL TRANSMISSION - A method for error correction and a decoder using low density parity check (LDPC) codes includes initializing extrinsic probability information between variable nodes and check nodes in a bipartite graph including generating a Bernoulli sequence according to a probability of a bit having a value one. Parity checking is performed in accordance with a parity check equation. If the parity check equation is not satisfied, then extrinsic information is updated in check nodes from variable nodes using a parity node update logic circuit in a first half iteration, extrinsic information is updated in variable nodes from check nodes using a variable node update logic circuit in a second half iteration, and the variable nodes are updated with a probability based upon the extrinsic information passed between check nodes and variable nodes wherein the probability represents a likelihood that an ith bit is a one. Information bits are passed when the parity check equation is satisfied or a predetermined number of iterations has been reached. | 2009-10-15 |
20090259913 | METHOD FOR ENCODING CONTROL INFORMATION IN A WIRELESS COMMUNICATION SYSTEM USING LOW DENSITY PARITY CHECK CODE, AND METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING THE CONTROL INFORMATION - A method and apparatus for transmitting control information in a wireless communication system using a Low Density Parity Check (LDPC) code is provided. The number of LDPC blocks, through which L1 post-signaling information is to be transmitted, is determined according to the total number of bits of the L1 post-signaling information. The number of input information bits of each LDPC block is calculated when the determined number of LDPC blocks is plural. The number of puncturing bits among parity bits of each LDPC block is determined considering a modulation order. A frame including one or multiple LDPC blocks generated through the preceding steps is transmitted. | 2009-10-15 |
20090259914 | DIGITAL CONTENT PROTECTION SYSTEMS AND METHODS - What is disclosed is a method of operating an integrated circuit which includes an input module, an output module, and a processing module coupled to the input module and the output module. The method includes, in the input module, receiving a first data segment; in the processing module, reading a hard coded identifier from an identifier module coupled to the processing module, processing the first data segment with the hard coded identifier to generate a first encoded data segment; and in the output module, transferring the first encoded data segment for storage on a storage system. | 2009-10-15 |
20090259915 | Structured low-density parity-check (ldpc) code - The invention introduces an apparatus, method and system that allow coding matrices to be expanded to accommodate various information packet sizes and support for various code rates; additionally the invention defines a number of coding matrices particularly suited to the methodology. The invention enables high throughput implementations, allows achieving low latency, and offers other numerous implementation benefits. At the same time, the new parity part of the matrix preserves the simple (recursive) encoding feature. | 2009-10-15 |
20090259916 | DATA ACCESSING METHOD, CONTROLLER AND STORAGE SYSTEM USING THE SAME - Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command. | 2009-10-15 |
20090259917 | METHOD OF CORRECTING MESSAGE ERRORS USING CYCLE REDUNDANCY CHECKS - A method of correcting errors in a message transmitted over a digital communication channel, where the message was encoded using a CRC for purposes of error detection. A parity-check matrix representation of the CRC is computed for any fixed-length message, and that parity-check matrix is combined with the parity-check matrix for any error correcting code that used in conjunction with the CRC. The combined parity-check matrix is extended using sparsification algorithms to allow it to work well under a message passing decoder (MPD). Received messages are decoded using the message passing decoder, making it possible to correct more errors than if the CRC were decoded in a conventional manner. | 2009-10-15 |
20090259918 | POSITION DETECTION ERROR CORRECTING METHOD - A position detection error correcting method that corrects position detection errors using a limited storage capacity, by calculating position detection error correction values by four simple arithmetic operations at startup to reduce a startup time delay and consumption of a storage capacity even when a portion containing steep error variations exists. Detection error correction values of a position detector are expressed by a correction function using a periodic function, and correction parameters of the correction values are stored in advance in a non-volatile memory. At startup, these correction parameters are read out, and a position detection error correction value corresponding to each detected position is calculated and stored in a random access memory. The output position detection error correction value detector corresponding to each detected position is read out from the random access memory and a corrected detected position value corrected for the detected position value error is calculated. | 2009-10-15 |
20090259919 | FLASH MANAGEMENT USING SEPARATE MEDTADATA STORAGE - Disclosed are techniques for flash memory management, including storing metadata and/or error correcting information separately from payload data. In various embodiments, metadata and/or error correcting information are stored in a random access memory within a solid state drive. | 2009-10-15 |
20090259920 | APPARATUS AND METHOD FOR ERROR CORRECTION IN MOBILE WIRELESS APPLICATIONS INCORPORATING MULTI-LEVEL AND ADAPTIVE ERASURE DATA - A receiver ( | 2009-10-15 |
20090259921 | METHOD AND APPARATUS FOR DECODING SHORTENED BCH CODES OR REED-SOLOMON CODES - The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied. | 2009-10-15 |
20090259922 | CHANNEL DECODING-BASED ERROR DETECTION - Low latency and computationally efficient techniques may be employed to account for errors in data such as low bit-width, oversampled data. In some aspects these techniques may be employed to mitigate audio artifacts associated with sigma-delta modulated audio data. In some aspects an error may be detected in a set of encoded data based on an outcome of a channel decoding process. Upon determining that a set of data may contain at least one error, the set of data may be replaced with another set of data that is based on one or more neighboring data sets. For example, in some aspects a set of data including at least one bit in error may be replaced with data that is generated by applying a cross-fading operation to neighboring data sets. In some aspects a given data bit may be flipped as a result of a linear prediction operation that is applied to PCM equivalent data that is associated with the given data bit and its neighboring data bits. In some aspects a set of data including at least one bit in error may be replaced with data that is generated by performing linear interpolation operations on PCM equivalent data that is associated with neighboring data sets. | 2009-10-15 |
20090259923 | Method for fail-safe transmission, safety switching device and control unit - A method for fail-safe transmission of information between a transmitter and a receiver is disclosed. At least two telegrams relating to the information are transmitted as a first telegram via a first channel and a second telegram via a second channel from the transmitter to the receiver. To identify an error affecting the information during transmission, a first identifier is generated from a first subset of the first telegram being used at the receiver to identify the information contained in the first telegram. This method is used for communication from a safety switching device to a control unit. | 2009-10-15 |
20090259924 | Data Protection Method for Variable Length Records by Utilizing High Performance Block Storage Metadata - An enhanced mechanism for providing data protection for variable length records utilizes high performance block storage metadata. In an embodiment, an emulated record that emulates a variable length record, such as a Count-Key-Data (CKD) record or an Extended-Count-Key-Data (ECKD) record, is generated by a Host Bus Adapter (HBA) of a mainframe system. The emulated record comprises a sequence of extended fixed-length blocks, each of which includes a data block and a footer. A confluence of the footers defines a high performance block storage metadata unit associated with the emulated record and includes a checksum that covers all data blocks and all footers of the entire emulated record. In one embodiment, the checksum is checked during transit of the emulated record between a HBA and a storage subsystem (e.g., by the HBA when the emulated record is received from the storage subsystem, and/or by a switch in the data transfer path), during a hardening step when writing the emulated record to a disk, and/or during a verification step when reading the emulated record from the disk. | 2009-10-15 |
20090259925 | Broadcast Equipment Communication Protocol - A method for transmitting data between components of a digital broadcasting system includes: receiving payload data, adding a content layer header to the payload data to form a content layer data frame, adding a transmission and authentication layer header and a cyclic redundancy check field to the content layer data frame to form a transmission and authentication layer data frame, adding an application framing layer header to the transmission and authentication layer data frame to form an application framing layer data frame, and transmitting the application framing layer data frame to a destination component. | 2009-10-15 |
20090259926 | METHODS AND APPARATUS TO PLAY AND CONTROL PLAYING OF MEDIA CONTENT IN A WEB PAGE - Methods and apparatus to play and control playing of media content in a web page are disclosed. In one example, a method of monitoring media content in a web page loads a web page containing a media player and media content, processes an image of the web page to determine a control associated with the media player, and monitors the media content based on the control. | 2009-10-15 |