42nd week of 2009 patent applcation highlights part 23 |
Patent application number | Title | Published |
20090257225 | Method and device for lamp having multiple light illuminating angles - This invention provides a method and a device for lamp having multiple illuminating angles. The inner surface of the lamp shade have a plurality of locating faces arranged with different angle all round the inner surface of the lamp shade, the light emitting diodes or other illuminating elements being installed respectively on the locating faces. Each light emitting diode can emit light perpendicularly with its locating face so as to control the illuminating angle and scope of lamp. | 2009-10-15 |
20090257226 | LED LAMP HAVING A SEALED STRUCTURE - An LED lamp includes a lamp holder, a heat sink, a plurality of LED modules, a cover, an envelope and a sealing cushion. The lamp holder has a connecting portion at a bottom thereof adapted for engaging with a lamp socket to fix the LED lamp in position. The heat sink is disposed on the lamp holder. The LED modules are attached to a circumference of the heat sink. The cover is coupled to a top of the heat sink. The envelope encloses the heat sink and the LED modules therein and has a lower end engaging with the lamp holder and an upper end engaging with the cover. The sealing cushion is provided between at least one of the combinations of the lamp holder and the envelope, and of the cover and the envelope to prevent an entry of foreign matter. | 2009-10-15 |
20090257227 | BALLOON LAMP - A balloon lamp includes a holder base, a balloon shade affixed to the holder base at the top, a balloon connector mounted in the balloon shade to secure a balloon, a power supply unit mounted in the holder base, and one or more LEDs installed in the balloon shade or the holder base and electrically connected to the power supply unit to emit light toward the balloon, thus producing a lighting effect. | 2009-10-15 |
20090257228 | Portable Computer and Keyboard Illuminating Device Thereof - A keyboard illuminating device for a portable computer includes a battery module and an illuminating module. The battery module can supply power to the portable computer and includes a housing. The illuminating module is disposed on the battery module and is powered by the battery module to illuminate a keyboard of the portable computer. The illuminating module hides in the battery module when the keyboard illuminating device is in a first status, and the illuminating module protrudes from a surface of the battery module when the keyboard illuminating device is in a second status. | 2009-10-15 |
20090257229 | LIGHT GUIDING POLE AND ILLUMINATION ASSEMBLY USING SAME - A light guiding pole ( | 2009-10-15 |
20090257230 | CASSEGRAIN OPTICAL CONFIGURATION TO EXPAND HIGH INTENSITY LED FLASHLIGHT TO LARGER DIAMETER LOWER INTENSITY BEAM - A flashlight in accordance with an embodiment of the present application includes an LED light source, a lens positioned opposite the LED light source, a convex mirror positioned substantially in a center of the inner surface of the lens, wherein light from the LED light source is reflected off the convex mirror back toward the LED light source and a concave mirror positioned opposite the convex mirror to reflect the light from the convex mirror as a wide diameter beam of light out of the flashlight through the lens. The convex mirror maybe replaced by a substantially flat, mirrored section of the lens if desired. | 2009-10-15 |
20090257231 | Electronic apparatus - An electronic apparatus includes: a cover having an optically-transparent base and a shielding film for making an inside invisible; and a substrate disposed inside and covered by the cover, the substrate being mounted with a light emitting element for emitting light toward the cover and a touch sensor disposed at a position surrounding the light emitting element to detect a touch of an outer surface of the cover by a finger. The electronic apparatus further includes an icon board disposed at a position between the substrate and the cover and having a light transmitting section formed to define an outline of light emitted by the light emitting element toward the cover. The shielding film shows light emitted by the light emitting element and passing through the icon board. | 2009-10-15 |
20090257232 | DISPLAY HOUSING FOR COMPUTING DEVICE - An improved housing for a computing device is disclosed. The improved housing can have one or more of the following aspects. A first aspect of the invention pertains to a computer housing having a logo or other symbol that can be illuminated using light from the backside of a display panel. A second aspect of the invention pertains to a suspended frame is able to support a display panel within a display housing. A third aspect of the invention pertains to a computing device provided with an internal antenna. A fourth aspect of the invention pertains to a stiffener for a computer housing so as to increase the rigidity and strength of the computer housing. A fifth aspect of the invention pertains to a housing having a logo, symbol or other device that can be illuminated using light from the backside of a display panel. A sixth aspect of the invention pertains to a lid for a computing device, such as a portable computer, that is provided with a translucent housing. | 2009-10-15 |
20090257233 | Adjustable Reflector Luminaire - The disclosure provides a luminaire having an adjustable light reflector affording a selection of flood pattern lighting. | 2009-10-15 |
20090257234 | LED LAMP - An LED lamp includes a first heat sink, a plurality of LED modules and a connecting member. The first heat sink has base plate and a plurality of first fins arranged on the base plate. The LED modules are attached to a bottom surface of the base plate. Outer ends of the LED modules are located at a level higher than that of inner ends of the LED modules. The mounting base is alternatively fixed to one of a top and a bottom of the first heat sink so that the LED lamp can be selectively used as a floor lamp or a pedant lamp. | 2009-10-15 |
20090257235 | Shade support for a spiral shaped compact fluorescent light - The shade supporting device of this invention attaches a shade of various styles to the glass tube portion of a spiral shaped compact fluorescent light. | 2009-10-15 |
20090257236 | LAMP BASE AND LAMP - The invention relates to a lamp base comprising a plastic base part ( | 2009-10-15 |
20090257237 | SAFETY SYSTEM UTILIZING LIGHTING INCORPORATED INTO APPAREL - A safety system and apparatus which incorporates an illumination member into an article of apparel where the illumination member is capable of being activated so that it simultaneously corresponds to the illumination of a lighting system of a motor vehicle. A safety device kit includes an illumination member capable of being illuminated that can be contained within, or attached to, a wearable article that can be worn by a user and a separate activation device capable of activating an illumination member. | 2009-10-15 |
20090257238 | AUTOMATIC ILLUMINATING APPARATUS AND METHOD FOR MOTOR VEHICLES - The present invention relates to an automatic illuminating apparatus for motor vehicles. The apparatus includes an illumination device for emitting light beams, comprising a first light emitting member for emitting light beams in daytime and a controlling device electrically connected with the illumination device. The controlling device includes a sensor for sensing whether the vehicle is in motion, a time recording module for recording current time, a memory for storing an illumination period of the first light emitting member, a processor for analyzing whether the current time is in the illumination period which is electrically connected with the time recording module, the memory and the processor, and a controlling module for controlling the first light emitting member emitting light beams based on an analyzed result from the processor. | 2009-10-15 |
20090257239 | PUSH-IN SOCKET ASSEMBLY - A ball socket for connection with a ball stud provides for easy manufacturing and assembly using a flat-stamped flexible retainer clip. The retainer clip is inserted into the socket and flexes to snap-fit within in the socket. The flex of the clip also flexes wings of the clip which engage with a receiving boss or socket. The flexion of the clip allows for easy push-in of the socket and sufficient resistance to accidental pull-out. The push-in socket design eliminates the need for screw-mounting of the socket. The socket assembly may be manufactured for use in connection with disengageable or conventional ball studs. | 2009-10-15 |
20090257240 | VEHICLE LAMP - A vehicle lamp including a projector headlight using an LED light source for a low beam can include a shade, an LED light source, an ellipsoidal reflector and a projector lens. Both a focus of the projector lens and a top edge of the shade can be located near a second focus of the reflector. The LED light source can be located near a first focus located below the second focus of the reflector. Therefore, light emitted from the LED light source can be effectively gathered near the focus of the projector lens via the reflector and can be projected via the projector lens with high light use-efficiency. The projector lens can include light dispersing portions or structures on an upside and downside thereof for reducing chromatic aberration. Thus, the lamp can project a favorable light distribution that can conform to light distribution standards for vehicle headlights and the like. | 2009-10-15 |
20090257241 | TRIM COMPONENT WITH CONCEALED INDICIUM - A component of an actuatable apparatus includes a substrate having an external surface defining a selected area, an illumination source actuatable between an illuminated state and a non-illuminated state, and an opaque indicia coating applied over the selected area. The illumination source is positioned behind the selected area. A portion of the opaque indicia coating defines a pattern having a greater light transmissivity than the portion of the opaque indicia coating not comprising the pattern. The pattern is invisible when the illumination source is in the non-illuminated state, and visible when the illumination source is in the illuminated state and transmits light through the pattern. | 2009-10-15 |
20090257242 | LIGHT-EMITTING DEVICES AND RELATED METHODS - Light-emitting devices and related methods are described that involve spatially distributing the light emission from a primary light source such as a laser or LED before it is incident on the photoluminescent material. The photoluminescent material emits a secondary emission that may comprise visible light. Some variations of the light-emitting devices may utilize an optical waveguide to couple-in light from the primary light source and spatially distribute the coupled-in light in a controlled manner to pump the photoluminescent material. A variety of configurations for high efficiency light fixtures may be possible using the light-emitting devices and methods described herein. | 2009-10-15 |
20090257243 | Fiber optic display systems and related methods - Fiber optic display systems and related methods are disclosed. According to one embodiment, a fiber optic display system can include a plurality of fiber optics. Output ends of the fiber optics can be spaced from one another and can be arranged in predetermined positions such that at least a portion of the output ends are positioned in a first plane and another portion of the output ends are positioned in a second plane. A light-transmissive material can contain the output ends. The output ends can terminate within the light-transmissive material and can be angled with respect to the light-transmissive material such that light transmitted within the fiber optics emits into the light-transmissive material. A light source can generate a plurality of light beams and selectively control input of the light beams into the input ends for transmission of light in the fiber optics such that an image is formed. | 2009-10-15 |
20090257244 | LIGHT EMITTING PANEL ASSEMBLIES - Light emitting panel assembly includes a panel member, at least one light source and a light transition member located between the light source and the light input surface of the panel member. On or in the light transition member are elements that effect a desired colored or white light output distribution from a light output area of the panel member. The light transition member may comprise a coating or surface treatment on the light input surface that effects the color of light emitted by the light output area. Alternatively a transparent sheet, plate or film attached to or positioned against the light input surface may have a coating, surface treatment or deformities that effect the color of light passing through the sheet, plate or film to obtain a desired colored or white light output distribution from the light output area. | 2009-10-15 |
20090257245 | LIGHT GUIDES AND BACKLIGHT SYSTEMS INCORPORATING PRISMATIC STRUCTURES AND LIGHT REDIRECTORS - Improved apparatus and method for collecting and directing light from a source via a light guide and modulated display assembly in an efficient manner through the design and use of prismatic optical structures, diffusers and/or light redirectors. | 2009-10-15 |
20090257246 | BACK LIGHT MODULE AND DISPLAY APPARATUS USING THE SAME - A back light module including a frame, a light-guide plate and a light source is provided. The frame has a opening and a first surface and a second surface opposite to the first surface. The opening is extended from the first surface to the second surface of the frame, so that an inner surface of the opening is connected to the first surface and the second surface. At least a portion of the inner surface is slanted toward the inner of the opening. The light-guide plate is integrated with the frame and at least a portion of the opening is filled with the light-guide plate. The light-guide plate is tightly attached to the inner surface of the frame. The light source is adjacent to the light-guide plate. | 2009-10-15 |
20090257247 | Switching Power Supply Circuit and Surge Absobring Circuit - Provided is a switching power supply device capable of effectively improving power supply efficiency with a small number of parts. The switching power supply device includes: a switching circuits (S | 2009-10-15 |
20090257248 | DIRECT CURRENT/DIRECT CURRENT CONVERTER WITH MULTIPLE OUTPUTS - In a DC/DC converter comprising a transformer ( | 2009-10-15 |
20090257249 | SEMICONDUCTOR DEVICE, AND ENERGY TRANSMISSION DEVICE USING THE SAME - An energy transmission device includes: a semiconductor device formed on a first semiconductor substrate; a semiconductor integrated circuit including a reverse current preventing diode and a control circuit; a DC voltage source; and a transformer. The reverse current preventing diode includes a reverse current preventing layer of a second conductivity type formed at a surface of a second semiconductor substrate, and a well layer of a first conductivity type formed in the second semiconductor substrate and covering the reverse current preventing layer. The transformer includes a primary winding connected in series with the semiconductor device and the DC voltage source, and a first secondary winding connected to a load. The energy transmission device is configured so that electric power is supplied from the first secondary winding of the transformer to the load. A second drain electrode of the semiconductor device is electrically connected to the reverse current preventing layer. | 2009-10-15 |
20090257250 | SYNCHRONOUS RECTIFIER DC/DC CONVERTERS USING A CONTROLLED-COUPLING SENSE WINDING - A synchronous rectifier DC/DC converter is provided. The synchronous rectifier DC/DC converter includes a power transformer, a first diode, a first MOSFET, and a first controller. The power transformer includes a core, a primary winding, a secondary winding, and a sense winding. The primary winding is wrapped around the core and receives an input voltage of the synchronous rectifier DC/DC converter. The secondary winding is wrapped around the core and provides the energy of an output current of the synchronous rectifier DC/DC converter. The sense winding is wrapped around the core and provides a sense signal. The first diode is coupled to the secondary winding for rectifying the output current. The first MOSFET is coupled in parallel with the first diode. The first controller is coupled to the sense winding and the first MOSFET for turning on and turning off the first MOSFET according to the sense signal. | 2009-10-15 |
20090257251 | Switching control circuit for a switching power converter - A switching control circuit is coupled to a switching device and an auxiliary winding of a transformer, wherein a primary winding of the transformer is coupled to the switching device. The switching control circuit includes a voltage receiver, a comparing unit and a propagation delay circuit, wherein the voltage receiver is coupled to the auxiliary winding of the transformer for receiving a reflected voltage signal and transforming the reflected voltage signal into a peak voltage signal, while the switching device is turned off. The comparing unit is coupled to the voltage receiver for receiving the peak voltage signal and a first threshold voltage, and outputting a comparison result. The propagation delay circuit is coupled to the comparing unit for receiving the comparison result, and outputting a PWM signal to turn on the switching device after a delay time. | 2009-10-15 |
20090257252 | Power supply device for an electric circuit - In the case of a power supply device ( | 2009-10-15 |
20090257253 | METHOD FOR OPERATING A CONVERTER CIRCUIT AND APPARATUS FOR IMPLEMENTING THE METHOD - The disclosure specifies a method for operating a converter circuit, the converter circuit having a converter unit with a large number of drivable power semiconductor switches and with a three-phase electrical AC voltage system, in which the drivable power semiconductor switches are driven by means of a drive signal (S | 2009-10-15 |
20090257254 | VOLTAGE-CLAMP POWER CONVERTERS - Several inversion circuits used to convert a DC input to an AC output comprise two series circuits, at least one clamp capacitor, and at least one transformer. Each of the series circuits is in parallel with the DC input. The first series circuit includes one switch network and at least one transformer primary. The second series circuit includes one voltage-clamp network and at least one transformer primary. At least one clamp capacitor couples the first and the second series circuits, and is attached to each series circuit at a node between the respective transformer primary winding. The voltage-clamp network may be implemented with two of the three sub-circuits connected in series: a diode, a resister-capacitor-diode, and a MOSFET-capacitor. | 2009-10-15 |
20090257255 | ACTIVE SNUBBER FOR TRANSITION MODE POWER CONVERTER - A transition mode power converter having an active snubber the operation of which is controlled using an auxiliary winding on the transformer of the power converter. In one embodiment, the power converter includes a transformer having a primary winding connected to a voltage source, a primary switch, an auxiliary switch, a capacitor, and an auxiliary winding on the transformer. The primary switch includes a first terminal connected to the primary winding of the transformer and a second terminal connected to a common node. The auxiliary switch includes a first terminal connected to the voltage source and to the primary winding. The capacitor is connected between a second terminal of the auxiliary switch and the first terminal of the primary switch. The auxiliary winding of the transformer is connected to a third terminal of the auxiliary switch and controls operation of the auxiliary switch via the third terminal. | 2009-10-15 |
20090257256 | HIGH EFFICIENT INPUT CURRENT SHAPING FOR AC TO DC CONVERTERS WITH POWER FACTOR CORRECTION REQUIREMENT - A high efficient input current shaping AC to DC converter with PFC front end that reduces input current harmonics is provided. In one embodiment, an AC to DC converter connectable with an alternating current source and operable to output a direct current comprises a PFC front end followed by a DC/DC converter. The PFC front end reduces harmonic components present in an input current waveform received by the PFC front end from the alternating current source and includes current steering circuitry and, optionally, valley filling circuitry. The DC/DC converter comprises one that presents pure resistive input impedance to the PFC front end. The DC/DC converter outputs the direct current to a load connected thereto. | 2009-10-15 |
20090257257 | CONTROL DEVICE FOR INTERLEAVED CONVERTERS, A SYSTEM OF INTERLEAVED CONVERTERS AND RELATED CONTROL METHOD - Control device for a switching converter structure comprising at least a first and a second interleaved converter, wherein the control device is configured to designate one converter as master and at least the other converter as slave, to set a time delay of the operating cycle of the slave converter and to synchronize the master and the at the least one slave converter. | 2009-10-15 |
20090257258 | POWER SUPPLY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The present invention is directed to largely improve the efficiency at the time of light load of a power supply apparatus using a PFC controller. A PFC controller is provided with a voltage-current converter. The voltage-current converter converts voltage of a signal output from an error amplifier for detecting voltage level of output voltage to an arbitrary current value and outputs the current value as a correction current. The voltage-current converter outputs a correction current of a large current value when the error amplifier detects that the load is light, and the PFC controller performs control to decrease the output voltage. | 2009-10-15 |
20090257259 | BRIDGE SYNCHRONOUS RECTIFIER - A current-triggered synchro-rectifier comprising an electronic switch configured to be in its ON setting when the current flowing through its cathode exceeds a predetermined threshold. The electronic switch may include a half-wave rectifier wired to the source terminal and the drain terminal of a MOSFET device, and a current monitor configured to monitor the drain-current flowing through the drain terminal. The current monitor sends a gate signal to the gate terminal such that the MOSFET is switched to its ON state when the drain-current exceeds a first threshold current and the MOSFET is switched to its OFF state when the drain-current falls below a second threshold current. Usefully, the synchro-rectifier may be incorporated into a full-wave rectifier. | 2009-10-15 |
20090257260 | ANALOG INPUT DEVICE - An analog input device according to the present invention includes a scanning circuit ( | 2009-10-15 |
20090257261 | CONTROL METHOD FOR THE MATRIX CONVERTER - An output voltage command signal for outputting a specified three-phase ac output voltage is generated by a line voltage control command signal generating section, and a signal representing a current flow ratio is generated by a current flow ratio generating section based on a specified input current command signal. The output voltage command signal is corrected by a command signal computing section based on the output voltage command signal generated by the line voltage control command signal generating section and the signal representing the current flow ratio generated by the current flow ratio generating section. A PWM conversion signal is generated by a PWM conversion signal generating section based on the corrected output voltage command signal and a carrier signal. Based on the generated PWM conversion signal, a three-phase ac input voltage is converted into a specified three-phase ac input voltage by a conversion section. | 2009-10-15 |
20090257262 | DRAM AND MEMORY ARRAY - A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction, and the word lines are disposed on the bit lines in a second direction. Each recess channel is in the substrate between two bit lines below the word line, and each conductive plug connects each recess channel and the word lines. Each trench capacitor is disposed in the substrate between two bit lines where the recess channels are not formed. Because the word lines can be electrically connected with the recess channels directly without using an additional chip area, the WL access time can be accelerated without an increase of the chip size. | 2009-10-15 |
20090257263 | Method and Apparatus for Computer Memory - A method and apparatus for forming computer memory | 2009-10-15 |
20090257264 | MEMORY AND METHOD OF EVALUATING A MEMORY STATE OF A RESISTIVE MEMORY CELL - An integrated circuit comprises a first signal line, a second signal line and a resistive memory cell. The resistive memory cell is actively connectable to the first signal line. The integrated circuit further comprises a coupling device configured to generate a difference of potential between the first and second signal line when the resistive memory cell is actively connected to the first signal line. | 2009-10-15 |
20090257265 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same - A nonvolatile memory cell includes a steering element located in series with a storage element. The storage element includes a carbon material and the memory cell includes a rewritable cell having multiple memory levels. | 2009-10-15 |
20090257266 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same - A method of programming a nonvolatile memory cell includes applying at least one initialization pulse having a duration of at least 1 ms, followed by applying plural programming pulses having a duration of less than 1 ms. The cell includes a steering element located in series with a storage element, and the storage element includes a carbon material. | 2009-10-15 |
20090257267 | NON-VOLATILE MULTI-LEVEL RE-WRITABLE MEMORY CELL INCORPORATING A DIODE IN SERIES WITH MULTIPLE RESISTORS AND METHOD FOR WRITING SAME - A very dense cross-point memory array of multi-level read/write two-terminal memory cells, and methods for its programming, are described. Multiple states are achieved using two or more films that each have bi-stable resistivity states, rather than “tuning” the resistance of a single resistive element. An exemplary memory cell includes a vertical pillar diode in series with two different bi-stable resistance films. Each bi-stable resistance film has both a high resistance and low resistance state that can be switched with appropriate application of a suitable bias voltage and current. Such a cross-point array is adaptable for two-dimensional rewritable memory arrays, and also particularly well-suited for three-dimensional rewritable (3D R/W) memory arrays. | 2009-10-15 |
20090257268 | Semiconductor device having single-ended sensing amplifier - A sense amplifier in a semiconductor storage device includes a memory cell for storing information on the basis of the size of the resistance value between a signal input/output terminal and a power supply terminal, the semiconductor storage device having a structure in which the bit line capacitance during signal reading from the memory cell is reduced, wherein the amplifier amplifies a signal outputted from an input/output terminal through the use of a single MOS transistor that has a single-ended structure. | 2009-10-15 |
20090257269 | Low-Complexity Electronic Circuits and Methods of Forming the Same - An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit. | 2009-10-15 |
20090257270 | DAMASCENE INTEGRATION METHODS FOR GRAPHITIC FILMS IN THREE-DIMENSIONAL MEMORIES AND MEMORIES FORMED THEREFROM - In some aspects, a microelectronic structure is provided that includes (1) a first conducting layer; (2) a first dielectric layer formed above the first conducting layer and having a feature that exposes a portion of the first conducting layer; (3) a graphitic carbon film disposed on a sidewall of the feature defined by the first dielectric layer and in contact with the first conducting layer at a bottom of the feature; and (4) a second conducting layer disposed above and in contact with the graphitic carbon film. Numerous other aspects are provided. | 2009-10-15 |
20090257271 | RESISTANCE CHANGE ELEMENT AND METHOD OF MANUFACTURING THE SAME - In a resistance change memory (ReRAM) storing data by utilizing change in resistance of a resistance change element, a lower electrode (ground-side electrode) of the resistance change element is formed of a transition metal such as Ni, and an upper electrode (positive polarity-side electrode) is configured of a noble metal such as Pt. In addition, a transition metal oxide film between the lower electrode and the upper electrode is formed of an oxide film (NiOx film) of a transition metal that is of the same kind as the transition metal constituting the lower electrode, for example. | 2009-10-15 |
20090257272 | REDUCED SIZE CHARGE PUMP FOR DRAM SYSTEM - A memory system includes: a memory array, comprising a plurality of memory banks, respectively enabled by a plurality of bank enable signals; a bank selector circuit, for generating the plurality of bank enable signals; a plurality of charge pump components, coupled between the plurality of memory banks and the bank selector circuit, and respectively enabled by the plurality of bank enable signals; and a charge pump circuit, coupled to the plurality of charge pump components, for regulating a supply voltage required by the memory system. | 2009-10-15 |
20090257273 | 2T SRAM CELL STRUCTURE - A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch. | 2009-10-15 |
20090257274 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I | 2009-10-15 |
20090257275 | Seasoning phase change memories - A seasoned phase change memory has been subjected to a longer pulse to adjust resistance levels prior to use of the phase change memory. | 2009-10-15 |
20090257276 | NONVOLATILE ANALOG MEMORY - A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a first current source, a second current source, and a current adjuster. The first current source generates a first current, and the second current source generates a second current. The current adjuster turns on or turns off a current path of the second current according to a reference current and the first current. Furthermore, when the current path of the second current is turned on, the first current is adjusted according to the second current, such that the first current is equal to the reference current. | 2009-10-15 |
20090257277 | Flash memory including reduced swing amplifiers - For realizing low power and high speed flash memory, reduced swing amplifiers are used for reading, such that a first reduced swing amplifier serves as a local sense amp for reading a memory cell through a short local bit line, a second reduced swing amplifier serves as a segment sense amp for reading the local sense amp, and a third reduced swing amplifier serves as a global sense amp for reading the segment sense amp through a global bit line. When reading data, a voltage difference in the local bit line is converted to a time difference by the sense amps for differentiating low data and high data, which realizes low power consumption with the reduced swing amplifiers. And, short local bit line is quickly discharged when reading, which realizes fast operation. Additionally, alternative circuits and memory cell structures for implementing the memory are described. | 2009-10-15 |
20090257278 | FLASH MEMORY DEVICE HAVING SHARED ROW DECODER - A flash memory device includes at least two mats and a row decoder shared by the mats. Each mat includes multiple word lines, bit lines, and blocks that share the bit lines. The row decoder includes a block decoder that generates a block selection signal for selecting a block, a block word line boosting circuit that generates a high voltage block word line signal in response to the block selection signal, a word line driver that drives word line drive signals driving the word lines of the selected block using drive voltages according to an operation mode and the word lines of an unselected block using a first bias voltage, and a string selection line driver that drives a string selection signal of the selected block using a drive voltage according to the operation mode and the string selection signal of the unselected block using a second bias voltage. | 2009-10-15 |
20090257279 | MEMORY DEVICE OPERATION - Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device or by using one bit line as a ground node for sensing current flow through the strings. The use of bit lines for virtual grounding is further suitable to other array architectures. | 2009-10-15 |
20090257280 | NAND FLASH MEMORY DEVICE AND METHOD OF OPERATING SAME - An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL, a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch | 2009-10-15 |
20090257281 | METHOD OF PROGRAMMING A FLASH MEMORY DEVICE USING SELF BOOSTING - A method of programming a flash memory device controls a channel boosting level to ensure device properties. The flash memory device is programmed in an Incremental Step Pulse Program (ISPP) manner by applying a program voltage to a selected memory cell and a pass voltage to unselected memory cells. The programming is performed by varying the pass voltage so that a gap of a predetermined range is maintained between a channel voltage and a word line voltage of the unselected memory cell. | 2009-10-15 |
20090257282 | NON-VOLATILE STORAGE SYSTEM WITH INITIAL PROGRAMMING VOLTAGE BASED ON TRIAL - A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a second set of non-volatile storage elements (which may or may not include the first set). | 2009-10-15 |
20090257283 | METHOD FOR DELETING DATA FROM NAND TYPE NONVOLATILE MEMORY - To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element. | 2009-10-15 |
20090257284 | METHOD AND APPARATUS FOR IMPROVING STORAGE PERFORMANCE USING A BACKGROUND ERASE - Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included is the act of asserting a background-process-busy flag after receiving the at least one erase command and the at least one erasable block address. At least one block in the memory associated with the at least one erasable block address is erased, wherein the erasing occurs at a time delay after receiving the at least one erase command if a background enable flag is asserted. Finally, the background-process-busy flag is negated after the erasing is complete. | 2009-10-15 |
20090257285 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes an input buffering block configured to buffer an input signal transmitted from an input pin, a latch block configured to latch the input signal buffered by the input buffering block, a defect discriminating block configured to discriminate whether or not the input signal latched by the latch block is defective signal in response to a test mode signal, and a data output buffer configured to buffer an output signal of the defect discriminating block to transmit it to a data output pin, wherein the input signal is one of an input command signal and an input address signal. | 2009-10-15 |
20090257286 | APPARATUS AND METHOD FOR OUTPUTTING DATA IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for outputting data in a semiconductor integrated circuit includes a clock generation block configured to activate a first clock signal for outputting a data signal and a second clock signal for outputting a data strobe signal based on a predetermined timing, and a data output block configured to latch a pre-data signal and a pre-data strobe signal in response to the first clock signal and the second clock signal, respectively. | 2009-10-15 |
20090257287 | PROGRAMMABLE BIAS CIRCUIT ARCHITECTURE FOR A DIGITAL DATA/CLOCK RECEIVER - Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to generate a first differential output signal in response to a comparison between the first input and the second input. The first differential output signal has a specified programmable voltage swing that is influenced by the first bias voltage. The receiver architecture also includes a first programmable bias circuit coupled to the first linear receiver stage. The first programmable bias circuit is configured to generate the first bias voltage. | 2009-10-15 |
20090257288 | APPARATUS AND METHOD FOR INCREASING DATA LINE NOISE TOLERANCE - Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current source. | 2009-10-15 |
20090257289 | INTERNAL VOLTAGE GENERATOR AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage. | 2009-10-15 |
20090257290 | LOW POWER SHIFT REGISTER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register. | 2009-10-15 |
20090257291 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING PIPE-IN SIGNAL THEREOF - A semiconductor memory device includes a preliminary signal generator configured to output a preliminary pipe-in signal enabled when a read command is applied. A delay unit is configured to delay the preliminary pipe-in signal and output the delayed preliminary pipe-in signal to match the timing of output data. A pipe-in signal generator generates a pipe-in signals that are enabled between a predetermined enable point and a next enable point of the delayed preliminary pipe-in signal output. | 2009-10-15 |
20090257292 | Semiconductor device having resistance based memory array, method of reading, and writing, and systems associated therewith - One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array. | 2009-10-15 |
20090257293 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a selector line selection circuit for selecting, in a read operation, a selector line for connecting a first main bit line connected to the sense amplifier with a sub-bit line to which the memory cell being read is connected, a selector line for connecting the first main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs, a selector line for connecting a second main bit line connected to the sense amplifier with a sub-bit line to which the reference cell is connected, and a selector line for connecting the second main bit line with a sub-bit line of at least one sector different from the sector to which the memory cell being read belongs. | 2009-10-15 |
20090257294 | PROGRAMMABLE LINEAR RECEIVER FOR DIGITAL DATA CLOCK SIGNALS - Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has a first programmable swing voltage associated therewith. The second stage has a programmable shift voltage associated therewith, and the third stage has a second programmable swing voltage associated therewith. The receiver architecture also includes a programming architecture coupled to the first stage, the second stage, and the third stage. The programming architecture is configured to set the first programmable swing voltage, the programmable shift voltage, and the second programmable swing voltage. | 2009-10-15 |
20090257295 | Randomizing Current Consumption in Memory Devices - In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory cells, output a plurality of data bits corresponding to the identified specific memory cell; and a delay controller that is configured to delay the outputting to the input/output interface of at least one of the plurality of data bits based on a randomly selected or pseudo-randomly selected delay value. The memory device can further include a delay block having a plurality delay paths having varying delays, and randomly selecting or pseudo-randomly selecting the delay value can include randomly selecting or pseudo-randomly selecting one of the plurality of delay paths through which to transmit a control signal. | 2009-10-15 |
20090257296 | Programmable memory repair scheme - The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element. | 2009-10-15 |
20090257297 | MULTI-CHIP SEMICONDUCTOR DEVICE PROVIDING ENHANCED REDUNDANCY CAPABILITIES - A semiconductor device including a plurality of semiconductor chips is provided. A semiconductor device includes a storing unit in which redundancy information portions are stored, and a comparing unit comparing a current address to the redundancy information portions and enabling or disabling operation of a semiconductor device based on the comparison result. | 2009-10-15 |
20090257298 | Semiconductor device having single-ended sensing amplifier - A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first MOS transistor to a global bit line, and a global bit line voltage determination circuit; and at least the ON/OFF timing of the second MOS transistor or the read timing of a global sense amplifier that includes the global bit line voltage determination circuit is controlled by the output signal of a delay circuit that includes a replica of the first MOS transistor and a replica of the global bit line voltage determination circuit. | 2009-10-15 |
20090257299 | SOFTWARE REFRESHED MEMORY DEVICE AND METHOD - A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory refresh operations in a conventional volatile memory device, such as a DRAM. A processor can perform periodic memory refresh operations by executing a set of memory refresh instructions implemented in software, rather than in hardware. Accordingly, the memory device can advantageously be simplified, because the need for memory refresh circuitry and for a unique refresh control signal are advantageously eliminated. Moreover, the processor executing the memory refresh instructions can typically perform more sophisticated algorithms, as compared to memory refresh circuitry implemented in hardware, for determining when to perform a memory refresh operation. For example, the processor can determine whether each individual memory cell needs to be refreshed, thereby advantageously avoiding performing unnecessary refresh operations on memory cells that do not need to be refreshed. | 2009-10-15 |
20090257300 | FUSE INFORMATION CONTROL DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME, AND CONTROL METHOD THEREOF - A fuse information control device having a delay circuit to delay an active signal, includes a fuse circuit that outputs fuse information in response to a fuse information control signal, and a fuse information control signal generating unit that generates the fuse information control signal in response to one of the active signal and internal delay signals of the delay circuit. | 2009-10-15 |
20090257301 | Voltage Level Comparison Circuit of Semiconductor Memory Apparatus, Voltage Adjustment Circuit Using Voltage Level Comparison Circuit, and Semiconductor Memory Apparatus Using the Same - A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage. | 2009-10-15 |
20090257302 | Semiconductor memory apparatus capable of reducing ground noise - An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level. | 2009-10-15 |
20090257303 | Container System - A method and system for providing a homogenized slurry output comprises a container body defining an interior portion, a discharge for supplying the slurry from the container body to a downstream source and at least one inlet in fluid communication with a pressurized supply of slurry for introducing the slurry into the interior portion of the container body in a circulation pattern that creates a homogenized mixture of slurry in the interior portion of the body. | 2009-10-15 |
20090257304 | Electronic manager for bread dough mixers and operating method - The invention relates to an electronic manager for bread dough mixers and to an operating method. The invention consists of an integral module ( | 2009-10-15 |
20090257305 | APPARATUS FOR SEPARATING SPRINGS - An apparatus for separating springs includes a hollow casing, first and second tubes, and a plate. The casing defines an entrance hole allowing springs to enter, and an exit hole allowing springs to exit. The first tube has one end connected to a bottom of the casing, allowing gas to be introduced into the casing. The second tube has one end connected to a middle of the casing opposite to the hole, allowing gas to be introduced into the casing. The plate is fixed to the bottom of the casing for supporting the springs. The plate is ventilated, and is located above the end of the first tube. | 2009-10-15 |
20090257306 | BONE CEMENT MIXING AND DELIVERY SYSTEM WITH AUTOMATED BONE CEMENT TRANSFER BETWEEN MIXER AND DELIVERY DEVICE AND METHOD OF MIXING AND AUTOMATED TRANSFER OF BONE CEMENT BETWEEN MIXER AND DELIVERY DEVICE AND METHOD OF MIXING AND AUTOMATED TRANSFER OF BONE CEMENT BETWEEN MIXER AND DELIVERY DEVICE - A bone cement mixing and delivery system is provided in which separate components of bone cement are mixed together in a mixer to form a bone cement mixture. The mixer includes a mixing paddle and a mixing shaft connected to the mixing paddle. A motor operatively engages the mixing shaft to rotate the mixing shaft and the mixing paddle to mix the components in a mixing chamber. The motor also operatively engages a transfer mechanism. After a predetermined mixing period has elapsed, the motor automatically actuates the transfer mechanism to transfer the mixture to a delivery device. The mixture is then delivered to a target site, such as a vertebral body of a patient or other anatomical site. | 2009-10-15 |
20090257307 | AUTOMATED MUD SLOWNESS ESTIMATION - An integrated framework is described for automating some or all of mud slowness estimation for both fast and slow formations. An estimation of fluid slowness based on monopole radial profiling is calculated if conditions permit. Alternatively, an estimation of fluid slowness based on Scholte wave slowness is estimated if conditions do not permit calculation based on monopole radial profiling. Tool standoff may also be estimated based on monopole radial profiling. | 2009-10-15 |
20090257308 | Migration velocity analysis methods - A method of performing migration velocity analysis may include: obtaining seismic data and an initial velocity model; determining reflection points; deriving a wavepath backprojection operator based on the initial velocity model and the reflection points by constructing wavepaths from each reflection point of the reflection points; and performing a traveltime inversion using the wavepath backprojection operator. The initial velocity model may be updated based on the traveltime inversion. Determining reflection points may be automated by calculating reflection points based on results from a depth migration algorithm performed on the initial velocity model. Selection of residual moveout values may be automated by selecting based on a dip field for each prestack gather obtained from a depth migration algorithm performed on the initial velocity model. Residual traveltimes may be calculated using the selected residual moveout values. The residual traveltimes may be used in the traveltime inversion. | 2009-10-15 |
20090257309 | METHODS AND SYSTEMS FOR SEISMIC EVENT DETECTION - The invention is directed to a system for detecting seismic waves. The system has one or more sensor modules. Each sensor module has a detection unit, a positioning module, a digitizer, a radio transmitter, and a power supply. The system also includes a communications interface including a receiver, a data storage device, and a data relay module, and a data processor. The system may be used to detect seismic events by positioning sensor modules in an area, positioning a communications interface module in an area, establishing communication, polling the sensor modules for data, and relaying the data. The polling and relaying may be repeated at predetermined time intervals. Then, analysis may be performed on the data, and the seismic event may be identified as a precursor. | 2009-10-15 |
20090257310 | Method of processing echo profile, and pulse-echo system for use with the method - An echo profile in a pulse-echo ranging system is processed by determining the relative slope at points on the profile, determining the relative area of each region of positive slope on the profile, identifying within the region having the largest relative area a point of greatest relative slope as a leading edge reference point, and using either said leading edge reference point or a peak within the echo profile as an echo timing measurement point. | 2009-10-15 |
20090257311 | Method of processing echo pulses, and pulse-echo ranging system using the method - Error correction in an echo pulse is performed by periodically (for example, every 100th pulse) generating a parabola derived from a selected part of the pulse leading edge. An error value is generated from the distance from a leading edge reference point to the peak of the generated parabola or to the echo peak, whichever is less. In this way an error correction is dynamically re-learned. | 2009-10-15 |
20090257312 | Autonomous Sonar System and Method - An autonomous sonar system and method provide an arrangement capable of beamforming in three dimensions, detecting loud targets, adaptively beamforming in three dimensions to avoid the loud targets, detecting quiet targets, localizing the loud or quiet targets in range, bearing, and depth, detecting modulation of noise associated with propellers of the loud or quiet targets, generating three dimensional tracks of the loud or quiet targets in bearing, range and depth, making classification of the loud or quiet targets, assigning probabilities to the classifications, and generating classification reports according to the classifications for communication to a receiving station, all without human assistance. | 2009-10-15 |
20090257313 | AIRBORNE ACOUSTIC SENSOR ARRAY - Embodiments for determining the bearings to targets from a remote location are disclosed. The apparatus consists of an array of acoustic sensors that is capable of autonomous flight. The array may be large in diameter, approximately one meter or greater. The apparatus is capable of navigating its flight to arrive at a predetermined location, measuring acoustic sound waves emitted by targets both during flight and after landing. The apparatus may then calculate the bearings to the targets and transmit this information to a remote location. | 2009-10-15 |
20090257314 | ACOUSTIC WIDE AREA AIR SURVEILLANCE SYSTEM - A method and apparatus for detecting an aircraft. The method is provided for wide area tracking of aircraft. An acoustic emission of the aircraft is detected from a plurality of locations. A position of the aircraft at a set of times is estimated by comparing a set of harmonically related Doppler shifted frequencies for the acoustic emission to an expected zero Doppler shifted frequency of the aircraft to form an estimated position. The position of the aircraft and a heading of the aircraft are tracked using the estimated position. The aircraft type is classified based on the corresponding set of zero Doppler frequencies at each acoustic sensor. | 2009-10-15 |
20090257315 | POSITION TRACING SIGNAL GENERATOR UNIT AND INPUT SYSTEM HAVING THE SAME - Disclosed are a position tracing signal generator unit and an input system using the same. The position tracing signal generator unit of the present invention generates ultrasonic signals with a constant time interval to allow ultrasonic signals generated from a plurality of ultrasonic signal generator to be overlapped and amplified. It is possible to increase the intensity of the ultrasonic signal and lengthen the range. Due to the structural advantages of the present invention as described above, it is possible to solve a problem of the prior art, i.e., a large thickness of the position tracing signal generator unit caused by a large size of the ultrasonic sensor for increasing the intensity of the ultrasonic signal. | 2009-10-15 |
20090257316 | System for communicating location of survivors in mine emergencies - The disclosed system uses seismic signaling to locate survivors in a mine collapse. A separate transmitter with a specific pre-selected frequency or frequencies is placed in pre-positioned safety zones of a mine. The system generates frequency-locked, unmodulated seismic energy, which allows rescuers to identify the safety zone where a transmitter is activated. The transmitter comprises an oscillator that generates the signal. The oscillator drives the transducer. The transducer causes the inertial mass to move. The movement of the inertial mass generates the seismic waves, which are conducted through the pressure plate to the earth. The seismic signal is detected then amplified, filtered, converted and then processed. The use of a continuous signal enables the processing unit to identify the frequency of the signal with a very low error rate, using frequency content identification. The disclosure also describes a method for transmitting seismic waves through the earth using the above described system. | 2009-10-15 |
20090257317 | Macrosonic Generator for the Air-Based Industrial Defoaming of Liquids - This invention refers to a sonic and/or ultrasonic generator for emission in air with a power capacity and certain radiation characteristics which permit the necessary acoustic levels (>170 dB ref. 2·10 | 2009-10-15 |
20090257318 | TIMEPIECE WITH A CALENDAR MECHANISM - A timepiece with calendar function including a dial having a tens digit display aperture for displaying the tens digit of the date and a ones digit display aperture for displaying the ones digit of the date, and a calendar mechanism that displays the date by presenting specific numerals through the dial. The calendar mechanism includes a ones display wheel having ones markers whereby the ones digit is displayed through the ones digit display aperture, a tens display wheel having tens markers whereby the tens digit is displayed through the tens digit display aperture, a ones drive mechanism that drives the ones display wheel, and a tens drive mechanism that drives the tens display wheel. The tens markers include normal tens markers that display only the tens digit in the tens digit display aperture, and a two-digit display marker that displays a tens digit in the tens digit display aperture and a ones digit in the ones digit display aperture. | 2009-10-15 |
20090257319 | Method and Device for Measuring Time Intervals - A device is dislosed for measuring a plurality of time intervals. | 2009-10-15 |
20090257320 | RESONATOR, UNIT HAVING RESONATOR, OSCILLATOR HAVING UNIT AND ELECTRONIC APPARATUS HAVING OSCILLATOR - An electronic apparatus comprises a display portion and at least one oscillating circuit comprising an amplifier, at least one resistor, a plurality of capacitors, and a unit having a case and a resonator. The resonator is vibratable in a flexural mode and has first and second vibrational arms, and at least one groove is formed in at least one of opposite main surfaces of each of the first and second vibrational arms, and at least one mounting arm protrudes from the base portion and extends in a common direction with at least one of the first and second vibrational arms. An output signal of the at least one oscillating circuit comprising the resonator is a clock signal for use in operation of the electronic apparatus to display time information at the display portion. | 2009-10-15 |
20090257321 | Dithering control of oscillator frequency to reduce cumulative timing error in a clock - A method for correcting time error in an oscillator operated clock according to one aspect of the invention includes at selected times determining at least one of a time error in the clock and a frequency difference between the oscillator and a reference oscillator by detecting a time reference signal. A change in the at least one of the time error and the frequency difference between a first one and a second one of the detecting the time reference signals is determined. A frequency of the oscillator is adjusted so as to substantially cancel a cumulative time error between the second one of the detecting the time reference signal and a selected detecting the time reference signal. | 2009-10-15 |
20090257322 | SHOCK ABSORBER FOR THE OSCILLATING WEIGHT OF A TIMEPIECE - The oscillating weight ( | 2009-10-15 |
20090257323 | Watch with rotatable case - A rotatable wrist watch is provided. The rotatable wrist watch includes a watch case, a dial, a crown, an outer periphery, a wrist strap and a spindle. The watch case has an exterior and an interior. The exterior includes two opposing faces and a side portion. A dial is located on each opposing face with a plurality of dials located on at least one of the opposing faces. Each dial indicates a time. A crown is provided for each dial. Each crown is located on the side portion and is movable to adjust the time indicated by the respective dial. The outer periphery is located a distance from and circumscribing the watch case. The wrist strap is coupled to the outer periphery. The spindle extends between the watch case and the outer periphery and is configured to permit the watch case to pivot about an axis between a first position where one of the watch faces is visible and a second position where the other watch face is visible. | 2009-10-15 |
20090257324 | Flexible Waveguide With Adjustable Index Of Refraction - A flexible waveguide with an adjustable index of refraction. The core layer and/or the cladding layer of a flexible waveguide may include a plurality of nanoparticles having a different index of refraction than the core layer and/or cladding layer. The plurality of nanoparticles may have an index of refraction that is greater than or less than an index of refraction of either the core layer or the cladding layer in order that the overall effective index of refraction of either the core layer or the cladding layer can be adjusted. | 2009-10-15 |