41st week of 2010 patent applcation highlights part 52 |
Patent application number | Title | Published |
20100262767 | DATA STORAGE DEVICE - A data storage device may include a command bus, a status bus, multiple memory devices that are operably coupled to the command bus and to the status bus, and a controller including multiple channel controllers, where the channel controllers are operably coupled to the command bus and to the status bus and each of the channel controllers is arranged and configured to control one or more of the memory devices. The data storage device may include multiple programmable logic devices that are operably coupled to the status bus, where each of the programmable logic devices is configured to retrieve a ready/busy signal from each of the memory devices under control of one of the channel controllers using the status bus, serialize the ready/busy signals and communicate the serialized ready/busy signals to the channel controllers. | 2010-10-14 |
20100262768 | CONFIGURABLE FLASH MEMORY CONTROLLER AND METHOD OF USE - A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least one FLASH memory chip. The FLASH control logic including mapping logic for configuring the FLASH data bus based upon the type of FLASH memory chip coupled thereto. A method and system in accordance with the present invention provides the following advantages: Configurable data bus on the FLASH memory controller through software to simplify routing complexity. Configurable chip select and control bus for flexibility of FLASH memory placement. Elimination of external resistor network for layout simplicity. A scalable architecture for higher data bus bandwidth support. Auto-detection of FLASH memory type and capacity configuration. | 2010-10-14 |
20100262769 | METHOD AND CIRCUIT FOR ADJUSTING A SELF-REFRESH RATE TO MAINTAIN DYNAMIC DATA AT LOW SUPPLY VOLTAGES - A method and circuit for refreshing dynamic data stored in an integrated circuit are disclosed. The integrated circuit receives a supply voltage and operates in a self-refresh mode of operation to refresh the dynamic data at a refresh time that defines how often the dynamic data is refreshed during the self-refresh mode. The method includes monitoring a magnitude of the supply voltage and adjusting the refresh time as a function of the monitored magnitude of the supply voltage. The integrated circuit may be any type of integrated circuit that stores dynamic data, such as a memory device like a dynamic random access memory, DDR DRAM, SLDRAM, or RDRAM, or other type of integrated circuit such as a microprocessor. | 2010-10-14 |
20100262770 | Method for Enhancing Information Security in a Computer System - A method for enhancing information security in a computer system includes receiving a service serial number, encoding the service serial number according to an encoding rule, to generate a first hard-disk code, storing the first hard-disk code into a hard disk of the computer system to make the hard disk to be accessed by only the computer system. | 2010-10-14 |
20100262771 | DATA STORAGE SYSTEM AND CACHE DATA-CONSISTENCY ASSURANCE METHOD - According to one embodiment, a data storage system includes a controller which accesses a first storage device using a first module on startup and accesses the first storage device using a second module after the startup. The first module records, when the write-target data is written to the first storage device, trace information indicating the write command in a second storage device. The second module determines, when taking over a reception of a command instructing writing/reading of data from the first module, whether or not unupdated data to be updated as a result of a writing of the first module is cached in the second storage device based on the trace information, and invalidates a data block including the unupdated data when the unupdated data is cached. | 2010-10-14 |
20100262772 | TRANSFER CONTROL OF A STORAGE VOLUME BETWEEN STORAGE CONTROLLERS IN A CLUSTER - A first storage controller that is part of a cluster of storage controllers includes an interface to communicate with at least one storage subsystem having a storage volume, where the first storage controller is initially assigned to process requests for the storage volume. The first storage controller further includes a processor to receive requests to access the storage volume, where the requests include client requests from one or more client computers and proxy requests from one or more other storage controllers in the cluster. Based on monitoring the client requests and the proxy requests, it is determined that a second of the storage controllers in the cluster is to be assigned to process requests for the storage volume. In response to the determining, control of the storage volume is transferred from the first storage controller to the second storage controller. | 2010-10-14 |
20100262773 | DATA STRIPING IN A FLASH MEMORY DATA STORAGE DEVICE - A method is disclosed for striping data from a host to a data storage device that includes a plurality of memory chips and a plurality of physical channels for communication of data between the host and the plurality of memory chips, where each channel is operably connected to a different plurality of the memory chips. The method includes determining a number of physical channels in the plurality of channels, determining a first channel chunk size with which to write data to memory chips connected to separate channels, segmenting, via the host, logically sequential data into first channel chunk size segments, and striping data to different channels of the data storage device in first channel chunk size units. | 2010-10-14 |
20100262774 | STORAGE CONTROL APPARATUS AND STORAGE SYSTEM - A storage control apparatus is provided. The storage control apparatus reads from and writes to a plurality of storages of a storage system including a plurality of servers and a control server that sets storage areas available to one of the plurality of servers from among the storage areas of the plurality of storages sharable among the plurality of servers. The apparatus includes a first acquisition unit that acquires, for each of the storages, an index about the distance between the control server and the storage, a second acquisition unit that acquires, for each of the storage areas in the storages, an index about a writing speed to the storage area, and a calculation unit that calculates, for each of the storage areas, a general index indicating the quality of the storage area based on the indexes acquired by the first acquisition unit and second acquisition unit. | 2010-10-14 |
20100262775 | RAID CONTROL APPARATUS AND RAID SYSTEM - A RAID system performs host I/O processing during RAID formatting of a plurality of physical disk drives. The controller executes sequential format processing and one-point format processing. A RAID format writing size (SFS) for sequential format processing is set larger than a RAID format writing size (OFS) for one-point format processing. Delay of host I/O processing is reduced, so that the time required for RAID formatting can be shortened. | 2010-10-14 |
20100262776 | DATA DRIVE - A data drive for interfacing with an electronic device through a memory card reader is described. The memory card reader accepts a memory card, which stores data having a first format. The data drive includes a storage device for storing data having a second format, a connector that emulates the memory card's connections, an interface unit between the storage device and the connector, and a controller for controlling data transfers between the storage device and the interface unit. The interface unit converts data between the first and second formats. The data drive attaches to the memory card reader through the connector and transfers data between the storage device and the external device through the memory card reader. The storage device can be a hard disk drive, permitting a relatively inexpensive and large capacity storage area to be used to transfer data through the memory card reader. | 2010-10-14 |
20100262777 | STORAGE APPARATUS AND METHOD FOR ELIMINATING REDUNDANT DATA STORAGE USING STORAGE APPARATUS - A storage apparatus | 2010-10-14 |
20100262778 | Empirically Based Dynamic Control of Transmission of Victim Cache Lateral Castouts - In response to a data request, a victim cache line is selected for castout from a lower level cache, and a target lower level cache of one of the plurality of processing units is selected. A determination is made whether the selected target lower level cache has provided more than a threshold number of retry responses to lateral castout (LCO) commands of the first lower level cache, and if so, a different target lower level cache is selected. The first processing unit thereafter issues a LCO command on the interconnect fabric. The LCO command identifies the victim cache line to be castout and indicates that the target lower level cache is an intended destination of the victim cache line. In response to a successful coherence response to the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache. | 2010-10-14 |
20100262779 | Program And Data Annotation For Hardware Customization And Energy Optimization - Technologies are generally described herein for supporting program and data annotation for hardware customization and energy optimization. A code block to be annotated may be examined and a hardware customization may be determined to support a specified quality of service level for executing the code block with reduced energy expenditure. Annotations may be determined as associated with the determined hardware customization. An annotation may be provided to indicate using the hardware customization while executing the code block. Examining the code block may include one or more of performing a symbolic analysis, performing an empirical observation of an execution of the code block, performing a statistical analysis, or any combination thereof. A data block to be annotated may also be examined. One or more additional annotations to be associated with the data block may be determined. | 2010-10-14 |
20100262780 | APPARATUS AND METHODS FOR RENDERING A PAGE - Aspects relate to apparatus and methods for rending a page on a computing device, such as a web page. The apparatus and methods include receiving a request for a requested instance of a page and determining if the requested instance of the page corresponds to a document object model (DOM) for the page stored in a memory. Further, the apparatus and methods include retrieving a dynamic portion of the DOM corresponding to the requested instance if the requested instance of the page corresponds to the DOM stored in the memory. The dynamic portion may be unique to the requested instance of the page. Moreover, the apparatus and methods include storing the dynamic portion of the DOM corresponding to the requested instance of the page in a relationship with the static portion of the DOM. | 2010-10-14 |
20100262781 | Loading Data to Vector Renamed Register From Across Multiple Cache Lines - A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences. | 2010-10-14 |
20100262782 | Lateral Castout Target Selection - In response to a data request of a first processing unit among a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and selects the lower level cache of a second of the plurality of processing units as an intended destination of a lateral castout (LCO) command by randomized round-robin selection. The first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and the intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held in the lower level cache of one of the plurality of processing units other than the first processing unit. | 2010-10-14 |
20100262783 | Mode-Based Castout Destination Selection - In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing. | 2010-10-14 |
20100262784 | Empirically Based Dynamic Control of Acceptance of Victim Cache Lateral Castouts - A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line. | 2010-10-14 |
20100262785 | Method and System for an Extensible Caching Framework - Systems and methods which provide an extensible caching framework are disclosed. These systems and methods may provide a caching framework which can evaluate individual parameters of a request for a particular piece of content. Modules capable of evaluating individual parameters of an incoming request may be added and removed from this framework. When a request for content is received, parameters of the request can be evaluated by the framework and a cache searched for responsive content based upon this evaluation. If responsive content is not found in the cache, responsive content can be generated and stored in the cache along with associated metadata and a signature formed by the caching framework. This signature may aid in locating this content when a request for similar content is next received. | 2010-10-14 |
20100262786 | Barriers Processing in a Multiprocessor System Having a Weakly Ordered Storage Architecture Without Broadcast of a Synchronizing Operation - A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories. In response to a request to perform an update to a portion of a first image of memory contained in the level three cache memory of a first processing unit while at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after the at least one kill-type command is complete. | 2010-10-14 |
20100262787 | TECHNIQUES FOR CACHE INJECTION IN A PROCESSOR SYSTEM BASED ON A SHARED STATE - A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state. | 2010-10-14 |
20100262788 | PRE-COHERENCE CHANNEL - A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the invention include multiple cache agents that each communication with the same protocol agent. In one embodiment, a pre-coherence channel couples the cache agents to the protocol agent to enable the protocol agent to receive events corresponding to cache operations from the cache agents to maintain ordering with respect to the cache operation events. | 2010-10-14 |
20100262789 | Methods and Devices for Accessing a Memory and a Central Processing Unit Using the Same - A memory accessing method including the following steps is provided. Firstly, two instructions are fetched. Next, the two instructions are respectively decoded to obtain two operation fields and two address fields. The two operation fields indicate the type of operation in accessing the memory. One of the address fields includes a first upper address corresponding to the first memory block and a first lower address corresponding to a first memory unit of the first memory block. The other one of the two address fields includes a second upper address corresponding to the second memory block and a second lower address corresponding to a second memory unit of the second memory block. Then, whether two instructions are performing the same type of operation on the same memory block is determined. If yes, the type of operation indicated by the two operation fields is performed on the corresponding memory block parallelly. | 2010-10-14 |
20100262790 | Memory Controllers, Methods, and Systems Supporting Multiple Memory Modes - A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices. | 2010-10-14 |
20100262791 | SOFTWARE REFRESHED MEMORY DEVICE AND METHOD - A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory refresh operations in a conventional volatile memory device, such as a DRAM. A processor can perform periodic memory refresh operations by executing a set of memory refresh instructions implemented in software, rather than in hardware. Accordingly, the memory device can advantageously be simplified, because the need for memory refresh circuitry and for a unique refresh control signal are advantageously eliminated. Moreover, the processor executing the memory refresh instructions can typically perform more sophisticated algorithms, as compared to memory refresh circuitry implemented in hardware, for determining when to perform a memory refresh operation. For example, the processor can determine whether each individual memory cell needs to be refreshed, thereby advantageously avoiding performing unnecessary refresh operations on memory cells that do not need to be refreshed. | 2010-10-14 |
20100262792 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ESTIMATING WHEN A RELIABLE LIFE OF A MEMORY DEVICE HAVING FINITE ENDURANCE AND/OR RETENTION, OR PORTION THEREOF, WILL BE EXPENDED - A method according to one embodiment includes gathering monitor data information from a memory device having finite endurance and/or retention, the monitor data being data of known content stored in dedicated memory cells of known write cycle count; analyzing the monitor data information; estimating a reliable life of the memory device or portion thereof based on the analysis; tracking a rate of change of at least a highest cycle count of user data; estimating when the reliable life of the memory device or portion thereof will be expended based on the tracking and the estimating; and taking an action prior to the reliable life of the memory device or portion thereof being expended. Additional systems, methods, and computer program products are also disclosed. | 2010-10-14 |
20100262793 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SKEWING EXPECTED WEAROUT TIMES OF MEMORY DEVICES - A method in one embodiment includes writing first data to a first memory device of a memory array at a first number of writes per unit time; writing second data to a second memory device of the memory array at a second number of writes per unit time; and skewing expected wearout times of the memory devices by making the second number of writes per unit time less than the first number of writes per unit time. A method in another embodiment includes writing first data to a first memory device of a memory array; writing second data to a second memory device of the memory array; and skewing expected wearout times of the memory devices by making a number of available storage units cm the second memory device less than a number of available storage units on the first memory device. | 2010-10-14 |
20100262794 | Data backup for virtual machines - Methods and apparatus involve computing backup for virtual representations on a physical hardware platform. The platform has a processor, memory and available storage upon which a plurality of virtual machines are configured. Also, each virtual machine has a type of operating system that may be the same or different as another virtual machine. A plurality of virtual machine proxies exists as complements to the virtual machines in order to actually conduct the backup. Upon indication of a present need for conducting a backup operation, the proxy with an operating system most closely approximating or matching the operating system of the virtual machine needing backup is selected for undertaking the operation. In this manner, backup is no longer conducted with ill-fitting physical backup proxies with incompatible operating systems. In other embodiments, nuances of conducting backup are described as are templates and cloning. Computer program products are further described. | 2010-10-14 |
20100262795 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ANALYZING MONITOR DATA INFORMATION FROM A PLURALITY OF MEMORY DEVICES HAVING FINITE ENDURANCE AND/OR RETENTION - A method according to one embodiment includes gathering monitor data information from a plurality of memory devices having finite endurance and/or retention, the monitor data being data of known content stored in dedicated memory cells of known write cycle count; analyzing the monitor data information; and taking an action relating to at least one of the devices based on the analyzing. Additional systems, methods, and computer program products are also disclosed. | 2010-10-14 |
20100262796 | METHOD FOR AUTOMATICALLY BACKING UP DIGITAL DATA PRESERVED IN MEMORY IN A COMPUTER INSTALLATION AND DATA MEDIUM READABLE BY A COMPUTER HAVING THE ASSOCIATED INSTRUCTIONS STORED IN THE MEMORY THEREOF - The invention relates in particular to a method for automatically backing up digital data preserved in memory in a computer installation to a remote backup system accessible through the computer installation via a data transmission network. This method comprises the steps consisting in: extracting and analysing ( | 2010-10-14 |
20100262797 | VIRTUAL MACHINE DATA BACKUP - Disclosed is a method and system for efficiently backing up a virtual machine file. A virtual machine file is logically divided into a plurality of fixed-size blocks of similar size, for example, a number of 1 MB data blocks. An MD5 hash value is generated from the contents of each block. Each block is written to a file having a filename that includes a filesystem-compliant form (e.g., hexadecimal form) of the computed MD5 hash value. A backup device includes a directory hierarchy having a plurality of first-level directories corresponding to the first two bytes of the hash value, and a plurality of second-level directories corresponding to the next two bytes of the hash value. The blocks are uniquely stored in the directory corresponding to the byte value pairs of the hash. The present disclosure provides data integrity checking and reduces storage requirements for duplicative, redundant, or null data. | 2010-10-14 |
20100262798 | STORAGE CONTROLLER AND DATA MANAGEMENT METHOD - Upon receiving a primary/secondary switching command from a secondary host system, a secondary storage control device interrogates a primary storage control device as to whether or not yet to be transferred data that has not been remote copied from the primary storage control device to the secondary storage control device is present. In the event that yet to be transferred data is present, the secondary storage control device receives yet to be transferred data from the primary storage control device and updates a secondary volume. The primary storage control device then manages positions of updates to the primary volume due to host accesses to the primary volume occurring at the time of the secondary storage control device receiving the primary/secondary switching command onwards using a differential bitmap table. | 2010-10-14 |
20100262799 | METHOD AND APPARATUS FOR FACILITATING FAST WAKE-UP OF A NON-VOLATILE MEMORY SYSTEM - A method includes storing at a non-volatile memory in a data storage device a first copy of a memory management table. The method further includes storing, at the non-volatile memory, a list of data entries that identify unused blocks of the non-volatile memory, where the list defines an order of allocating the unused blocks. The method further includes, in response to detecting a power event, accessing an entry of the ordered list to identify a block, and selectively updating the first copy of the memory management table based on a status of the identified block. | 2010-10-14 |
20100262800 | INFORMATION PROCESSING DEVICE - An information processing device in which memory bands can be significantly cut. In the present device, an access determining/managing portion ( | 2010-10-14 |
20100262801 | TYPE SYSTEM SUPPORT FOR MEMORY ISOLATION PERMISSIONS - An object reference is tagged with an isolation permission modifier. At least two permissions can be included, and in an example three permissions are included. In implementing the permissions, type modifiers for controlling access to type members through references pointing at an object are defined. One of the type modifiers is associated with each occurrence of a type name. Each of the of type modifiers defines a different access permission to restrict operations on the object to which the reference points. | 2010-10-14 |
20100262802 | Reclamation of Thin Provisioned Disk Storage - A thin provisioned storage system may have a file system manager that presents a logical storage system to a user and a storage management system that manages physical storage devices. When a block of data is freed at the logical layer, the file system manager may identify the freed block and send a command to the physical layer. The physical layer may identify the corresponding physical block or blocks and free those blocks on the physical layer. The storage management system may use a table to manage the location of blocks of data across multiple physical storage devices. | 2010-10-14 |
20100262803 | STORAGE SYSTEM AND STORAGE CONTROL METHOD - A storage method and system where the storage system includes a plurality of servers and a control server configured to select a storage area available to be used by each of the servers from among storage areas of a group of storage devices sharable among the plurality of servers. The system includes, a detecting unit configured to detect an available capacity of a specified storage device other than the storage group, where the specified storage device is designated for use only by a specified server selected from among the servers, a specifying unit configured to specify an available area corresponding to the available capacity detected from the specified storage device through the detecting unit, and a setting unit configured to set the specified available area to a shared storage area that is available to be shared among the server. | 2010-10-14 |
20100262804 | Effective Memory Clustering to Minimize Page Fault and Optimize Memory Utilization - An embodiment of the invention provides a method for effective memory clustering to minimize page faults and optimize memory utilization. More specifically, the method monitors data access requests to secondary storage and identifies data addresses in secondary storage having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein a cross-sectional partition is created (sliced) from the multi-dimensional cluster. The method receives a request for a data object in secondary storage and identifies a data address corresponding to the requested data object. The data address is mapped to the multi-dimensional cluster and/or the memory page; and, the memory page is transferred to a data cache in primary storage. | 2010-10-14 |
20100262805 | PROCESSOR WITH ASSIGNABLE GENERAL PURPOSE REGISTER SET - A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the second CPU register set with the CPU, and control logic for controlling the multiplexer logic to switch from the first CPU register set to the second CPU register set upon receipt of at least one of a plurality of interrupt signals, wherein the at least one of a plurality of interrupt signals must meet a condition that is programmable within the control logic. | 2010-10-14 |
20100262806 | Tracking Effective Addresses in an Out-of-Order Processor - Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag. | 2010-10-14 |
20100262807 | Partial Flush Handling with Multiple Branches Per Group - Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group. | 2010-10-14 |
20100262808 | MANAGING INSTRUCTIONS FOR MORE EFFICIENT LOAD/STORE UNIT USAGE - The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit. | 2010-10-14 |
20100262809 | System and Method for Conflict Resolution During the Consolidation of Information Relating to a Data Service - A context aware mechanism including a system configured to receive presence data relating to at least one of a presentity and a watcher, and to resolve a conflict that arises during processing of the presence data according to a criteria. A method is also provided. | 2010-10-14 |
20100262810 | CONCURRENT INSTRUCTION OPERATION METHOD AND DEVICE - A concurrent instruction operation method and device are provided. The method includes: establishing a concurrent queue, and setting a queue base address and a queue maximum length of the concurrent queue; generating concurrent operation instructions according to a length of data that needs to be written or read as well as the queue base address and queue maximum length of the concurrent queue; and executing the concurrent operation instructions in the concurrent queue, and completing a data operation to the concurrent queue. | 2010-10-14 |
20100262811 | DEBUG SIGNALING IN A MULTIPLE PROCESSOR DATA PROCESSING SYSTEM - A system includes a first processor, a second processor, a first clock coupled to the first processor, and a third clock coupled to the first processor and to the second processor. The first processor includes debug circuitry coupled to receive the third clock, synchronization circuitry coupled to receive the first clock, wherein the synchronization circuitry receives a first request to enter a debug mode and provides a first synced debug entry request signal and wherein the first synced debug entry request signal is synchronized with respect to the first clock, and an input for receiving a second synced debug entry request signal from the second processor wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted. | 2010-10-14 |
20100262812 | REGISTER CHECKPOINTING MECHANISM FOR MULTITHREADING - Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. Threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume. | 2010-10-14 |
20100262813 | Detecting and Handling Short Forward Branch Conversion Candidates - Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions. | 2010-10-14 |
20100262814 | HANDLING EXCEPTIONS RELATED TO CORRUPT APPLICATION STATE - An exception handling system is described herein that provides one or more distinguished classes of software exceptions that are handled differently than other exceptions. The system treats a distinguished exception as a “hard to catch” exception that is not passed to the catch block of program code unless a developer performs extra steps to acknowledge the distinguished nature of the exception and confirm that the program code is prepared to properly handle the exception. Exceptions that fall into this class are typically those that represent conditions from which normal exception handling practices cannot successfully recover, namely exceptions that corrupt application state. Accordingly, the system prevents the developer from catching these classes of exceptions by default unless the developer explicitly requests to have these exceptions delivered to the program code. Thus, the exception handling system encourages correct programming practices by preventing developer error by default. | 2010-10-14 |
20100262815 | Detection Mechanism for System Image Class - A method, apparatus and program product for automatically detecting the configuration of a hardware platform, generating the communications necessary to request the correct OS for the platform, authenticating the request at a remote server, detecting the image class based on a class node policy, and downloading the correct OS to the requesting platform while avoiding any necessity of inventorying or entering node-specific information such as a MAC (Media Access Control) address or UUID (Universally Unique Identifier). | 2010-10-14 |
20100262816 | METHOD AND SYSTEM FOR POST-BUILD MODIFICATION OF FIRMWARE BINARIES TO SUPPORT DIFFERENT HARDWARE CONFIGURATIONS - A firmware data processing system may be operable to allocate a configuration area in the firmware binary image file for customizable settings. During the firmware build process for the firmware binary image file, default configuration information may be inserted into this configuration area. This default configuration information may be either actual default setting values or indicator to use the default setting values. During post-build modification process, a separately created utility application may be operable to read in the original firmware binary image file, select new settings, and insert new configuration information into the configuration area. The utility application may also be operable to create a new firmware binary image file with reproduced checksums or other error detection mechanisms required for the original firmware binary image file, based on the new configuration information in the configuration area. | 2010-10-14 |
20100262817 | USER SELECTABLE DATA WIPE - A data storage device includes a computer-readable medium encoded with a computer program that, when executed communicates with a basic input/output system (BIOS), receives a user selection from the BIOS to wipe the data storage device and performs a wipe of the data storage device. In an embodiment, the wipe of the data storage device includes writing a series of | 2010-10-14 |
20100262818 | Computer system and method of booting the same - A computer system and a method of booting a computer system using a solid state drive (SSD) as a main storage device is provided. The method includes mapping an address of a memory included in the SSD to an address used by a central processing unit (CPU) to select a boot code, uploading the boot code of an operating system (OS) stored in a non-volatile memory block included in the SSD to the memory included in the SSD, generating an interrupt signal based on a progress rate of the boot code upload, and performing a boot operation based on the boot code uploaded to the memory included in the SSD in response to the interrupt signal. | 2010-10-14 |
20100262819 | METHOD AND APPARATUS FOR IMPLEMENTING MULTIPLE SERVICE PROCESSING FUNCTIONS - A multi-service processing method, including: configuring different cores of a multi-core processor to process different services; and sending received packets to the cores in the pre-defined service processing sequence. The multi-core processor apparatus, includes the configuration management unit, the packet distributing unit, and the multi-core processor. The method and apparatus can save investments in devices while implementing multiple service processing functions. | 2010-10-14 |
20100262820 | METHOD OF CONTROLLING A PDA PHONE AND PDA PHONE USING THE SAME - A method for controlling a PDA (personal digital assistant) phone is provided. A first interface configuration file and a second interface configuration file are provided. An interface selection command is received, designating the first or second interface configuration file. A first boot procedure is performed. The first or second interface configuration file is loaded and displayed as an operation interface of the PDA phone. | 2010-10-14 |
20100262821 | SECURE IDENTIFICATION SYSTEM - Methods and apparatus are described which provide secure interactive communication of text and image information between a central server computer and one or more client computers located at remote sites for the purpose of storing and retrieving files describing and identifying unique products, services, or individuals. Textual information and image data from one or more of the remote sites are stored separately at the location of the central server computer, with the image data being in compressed form, and with the textual information being included in a relational database with identifiers associated with any related image data. Means are provided at the central computer for management of all textural information and image data received to ensure that all information may be independently retrieved. Requests are entered from remote terminals specifying particular subject matter, and the system is capable of responding to multiple simultaneous requests. Textural information is recalled and downloaded for review, along with any subsequently requested image data, to be displayed at a remote site. Various modes of data and image formatting are also disclosed, including encryption techniques to fortify data integrity. The server computers may be interfaced with other computers to effect financial transactions, and images representing the subjects of transactions may be uploaded to the server computer to create temporary or permanent records of financial or legal transactions. A further feature of the system is the ability to associate an identification image with a plurality of accounts, transactions, or records. | 2010-10-14 |
20100262822 | CONTENT TRANSMITTING APPARATUS, CONTENT TRANSMITTING METHOD, AND CONTENT TRANSMITTING PROGRAM - A content transmitting apparatus, includes: an acquisition device configured to acquire content data distributed in streaming mode; a temporary storage device configured to store temporarily the content data acquired by the acquisition device; a data control device configured to read the content data from the temporary storage device on a first-in first-out basis; an encryption device configured to encrypt in units of a predetermined amount the content data read out by the data control device; and a transmission device configured to transmit the content data encrypted by the encryption device to a predetermined receiving apparatus via a network. If the remaining capacity of the temporary storage device becomes smaller than a predetermined threshold value depending on status of the network, then the data control device discards the content data read from the temporary storage device. | 2010-10-14 |
20100262823 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 2010-10-14 |
20100262824 | System and Method for Software Protection and Secure Software Distribution - The various embodiments of the present invention provide a secure software distribution and execution method. According to the method, a server receives software from service provider for downloading to a client and identifies the sections for encoding. APIs are inserted in the identified sections. A unique ID is created based on the identity of the each client to generate an encryption algorithm, decryption key and decryption algorithm. The identified sections are encrypted with the generated encryption algorithm. The encrypted application along with encryption algorithm, decryption key and decryption algorithm are downloaded to the driver of the client machine. The API makes call to the driver by sending the encrypted segment when the encrypted portion is reached during the execution of software in the client machine so that the driver decrypts the encoded portion using the received key and the decryption algorithm to enable the continuous execution of the downloaded software. | 2010-10-14 |
20100262825 | SECURITY METHOD OF MOBILE INTERNET PROTOCOL BASED SERVER - A security method in a server-based mobile IP system is provided. Specifically, in the security method, general data is securely exchanged in addition to a control message that is exchanged between a mobile node and a server or between mobile nodes. Specifically, provided is a method of securely exchanging data by using a mobile node including an mPAK execution module generating necessary keys by exchanging key information with the server while performing a mutual authentication process and negotiating the security policy; and a security module setting a security policy that is negotiated with the corresponding node and applying the security policy to data according to the set security policy when transmitting the data. | 2010-10-14 |
20100262826 | SYSTEM AND METHOD FOR ACQUIRING TERMINAL BINDING KEY - A first terminal subscribes to at least one service using a service guide in which information necessary for reception of each service is stored, and sends the service guide and an identifier (ID) of the subscribed service to a smartcard. The smartcard stores the service guide and the ID of the subscribed service, and sends the service guide and the ID of the subscribed service to a second terminal through a response message to a request message used for acquiring TBK information, received from the second terminal. The second terminal receives the response message by sending the request message to the smartcard, acquires TBK information corresponding to a service that the second terminal intends to play back, from the service guide depending on the subscribed service's ID included in the response message, and acquires the TBK by performing an authentication process using the TBK information. | 2010-10-14 |
20100262827 | Secure Storage Device For Transfer Of Data - Described herein are methods and devices of securing data. For example, a method of securing data comprises receiving, by a secure storage device, unsecure data from a source. The secure storage device is removably attached to the source. The method further comprises securing the unsecure data within the secure storage device by performing digital processing related to the unsecure data to create secure data. The secure storage device is responsive to the same protocol as an unsecure storage device and as a result the secure storage device is transparent to the source. The source responds to the secure storage device as if it were an unsecure storage device. | 2010-10-14 |
20100262828 | SYSTEMS, DEVICES, AND METHODS FOR SECURELY TRANSMITTING A SECURITY PARAMETER TO A COMPUTING DEVICE - Embodiments of the systems, devices, and methods described herein generally facilitate the secure transmittal of security parameters. In accordance with at least one embodiment, a representation of first data comprising a password is generated at the first computing device as an image or audio signal. The image or audio signal is transmitted from the first computing device to the second computing device. The password is determined from the image or audio signal at the second computing device. A key exchange is performed between the first computing device and the second computing device wherein a key is derived at each of the first and second computing devices. In at least one embodiment, one or more security parameters (e.g. one or more public keys) are exchanged between the first and second computing devices, and techniques for securing the exchange of security parameters or authenticating exchanged security parameters are generally disclosed herein. | 2010-10-14 |
20100262829 | SYSTEMS, DEVICES, AND METHODS FOR SECURELY TRANSMITTING A SECURITY PARAMETER TO A COMPUTING DEVICE - Embodiments of the systems, devices, and methods described herein generally facilitate the secure transmittal of security parameters. In accordance with at least one embodiment, a representation of first data comprising a password is generated at the first computing device as an image or audio signal. The image or audio signal is transmitted from the first computing device to the second computing device. The password is determined from the image or audio signal at the second computing device. A key exchange is performed between the first computing device and the second computing device wherein a key is derived at each of the first and second computing devices. In at least one embodiment, one or more security parameters (e.g. one or more public keys) are exchanged between the first and second computing devices, and techniques for securing the exchange of security parameters or authenticating exchanged security parameters are generally disclosed herein. | 2010-10-14 |
20100262830 | AUTHENTICATION DEVICE, AUTHENTICATION METHOD, AND PROGRAM BACKGROUND OF THE INVENTION - Provided is an authentication device which includes a register in which a first-bit or a second-bit different from the first-bit is stored, m first determination units for determining whether input information and authentication information match, and for storing the first-bit in the register if a result of the determination is TRUE and for storing the second-bit in the register if FALSE, (N−m) second determination units for determining whether input information and authentication information do not match, and for storing the first-bit in the register if a result of the determination is TRUE and for storing the second-bit in the register if FALSE, and an authentication determination unit for determining that an authentication is established, in case the first-bit is stored in the register by a determination process by every first determination unit and the second-bit is stored in the register by a determination process by every second determination unit. | 2010-10-14 |
20100262831 | Method and Apparatus for Providing Secure Linking to a User Identity in a Digital Rights Management System - Disclosed is a DRM device and method for providing secure linking to a user identity. A first request is sent to a subscriber identity module. A message is received from the subscriber identity module via a secure authenticated channel. The message comprises at least a a master key identifier, a random number, and a derived key. In response to the message, a second request is sent to a DRM server. The second request comprises at least a master key identifier, the device identifier, and a random number. Also disclosed is a DRM server and method for providing secure linking to a user identity. A first request is received from a DRM device. The first request comprises at least master key identifier, a device identifier, and a random number. The DRM device is authenticated. A second request for an application specific key is sent to a trusted key management server. The second request comprises at least a master key identifier. At least a key is received from the trusted key management server. A derived key is determined from the key received from the trusted key management server based at least on the device identifier and the random number. A challenge/response scheme is used to determine whether the derived key of the DRM server matches a derived key of the DRM device. | 2010-10-14 |
20100262832 | ENTITY BIDIRECTIONAL AUTHENTICATION METHOD AND SYSTEM - An entity bidirectional authentication method and system, the method involves: the first entity sends the first message; the second entity sends the second message to the credible third party after receiving the said first message; the said credible third party returns the third message after receiving the second message; the said second entity sends the fourth message after receiving the third message and verifying it; the said first entity receives the said fourth message and verifies it, completes the authentication. Compared with the conventional authentication mechanism, the invention defines an on-line retrieval and authentication mechanism of a public key, realizes the centralized management for it, simplifies the operating condition of the protocol, and facilitates the application and implement. | 2010-10-14 |
20100262833 | ACTIVATING STREAMING VIDEO IN A BLU-RAY DISC PLAYER - Techniques are described herein for using cryptographic elements of the Advanced Access Content System (AACS) in a client-server environment to cryptographically authenticate client applications that are executing on non-revoked AACS-compliant playback devices. The techniques described herein may be used to protect a server application from providing information to client applications executing in non-AACS-compliant or revoked environments. In one embodiment, the techniques are used to authenticate a Blu-ray Disc Java Application executing on a non-revoked AACS-compliant Blu-ray Disc Player. | 2010-10-14 |
20100262834 | ONE TIME PASSWORD KEY RING FOR MOBILE COMPUTING DEVICE - Single-use character combinations are a secure mechanism for user authentication. Such “one-time passwords” (OTPs) can be generated by a mobile device to which the user otherwise maintains easy access. A key exchange, such as in accordance with the Diffie-Hellman algorithm, can provide both the mobile device and a server with a shared secret from which the OTPs can be generated. The shared secret can be derived from parameters posted on the server and updated periodically, and the mobile device can obtain such parameters from the server before generating an OTP. Such parameters can also specify the type of OTP mechanism to be utilized. A second site can, independently, establish an OTP mechanism with the mobile device. For efficiency, the first server can provide an identity token which provides the mobile device's public key in a trusted manner, enabling more efficient generation of the shared secret with the second server. | 2010-10-14 |
20100262835 | METHOD AND SYSTEM FOR OBTAINING A PIN VALIDATION SIGNAL IN A DATA PROCESSING UNIT - The present invention relates to a method for obtaining a PIN validation signal in a data processing unit, the method including the steps of receiving a PIN in the data processing unit, submitting it to a first portable object for verifying it and obtaining a validation signal. The method further includes the steps of catching or receiving an entered PIN directly in said first portable object for verifying it; transmitting a fake PIN to the data processing unit, the fake PIN being seen by the data processing unit as a PIN to submit to the first portable object for verifying it, and returning a validation signal in case the entered PIN is verified successfully in the first portable object. The invention relates also to corresponding system and secure portable object. | 2010-10-14 |
20100262836 | PRIVACY AND CONFIDENTIALITY PRESERVING MAPPING REPOSITORY FOR MAPPING REUSE - Described herein are systems and methods for importing and retrieving schema mappings while preserving privacy and confidentiality so that existing mappings can be reused across different customers without allowing reverse engineering of the original schemas. The disclosed embodiments provide different levels of mapping anonymity and correspondingly, available structural information in the retrieved mappings, in accordance with the security and privacy requirements. | 2010-10-14 |
20100262837 | Systems And Methods For Personal Digital Data Ownership And Vaulting - Systems and methods are provided for aggregating user-generated digital information. As an example, a system and method can be configured to collect, throughout a current day, a plurality of digital data receipts from different classes of information representing the user activities of a single user; encrypt each data receipt using an encryption method under the control of the user; rout each encrypted data receipt to a first storage facility; and aggregate the encrypted data receipts associated with the user at a second storage facility. | 2010-10-14 |
20100262838 | DIGITAL DATA FILE ENCRYPTION APPARATUS AND METHOD - According to an embodiment, the invention provides a method for decrypting content, the comprising: receiving the content without a source encryption key from a source device connected to the electric reproducing device, the content having been encrypted with the source encryption key in the source device; performing a first addition operation by using a first device internal key and an ID, the first device internal key being associated with the electric reproducing device; generating a device encryption key based on an output of the first addition operation and a second device internal key by using a predetermined encryption algorithm, wherein the second device internal key is associated with the electric reproducing device; decrypting the content using the device encryption key; decoding the decrypted content; and outputting the decoded content. | 2010-10-14 |
20100262839 | Obfuscating Execution Traces of Computer Program Code - A computer-implemented method of generating tamper-protected computer program code. The method comprises obtaining a representation of the computer program code, the computer program being adapted to cause a data processing system to perform a plurality of computational tasks in a first order of execution, each computational task being represented in the representation of the computer program code by at least one program statement; obtaining a plurality of alternative orders of execution of the computational tasks; generating an executable representation of the program code adapted to cause a data processing system to select a randomized order of execution from the plurality of alternative orders of execution and to execute the computational tasks in the selected randomized order of execution. | 2010-10-14 |
20100262840 | METHOD AND DEVICES FOR PROTECTING A MICROCIRCUIT FROM ATTACKS FOR OBTAINING SECRET DATA - A method of protecting a microcircuit against attacks aimed at discovering secret data used on the execution, by the microcircuit, of an encryption algorithm includes generating at least one protection parameter for the secret data and modifying the execution of the encryption algorithm through that protection parameter. Generation of the at least one protection parameter includes defining a function generating, by successively applying to at least one secret parameter which is stored in memory, a sequence of values which can only be determined from that secret parameter and that function, and to generate the protection parameter in a reproducible way from at least one value in that sequence. | 2010-10-14 |
20100262841 | METHOD FOR SECURE PROGRAM CODE EXECUTION IN AN ELECTRONIC DEVICE - The invention relates to a method for secure piecemeal execution of a program code. In the method, the program code is split to a number of pieces in a first electronic device. The pieces are provided one after another to a second electronic device, which computes a message authentication code from the pieces and returns the authenticated pieces back to the first electronic device. In order to execute the program, the authenticated pieces are provided for execution to the second electronic device, which verifies the message authentication codes in the pieces to allow the execution of the pieces in the second electronic device. | 2010-10-14 |
20100262842 | Computational Energy Measurement Without Hardware Support - Techniques and technologies are disclosed herein for measuring and managing energy consumption of the individual hardware components and software modules of various systems and devices. Such techniques and technologies do not require the addition of hardware to the systems (or devices), the modification of software modules hosted by the systems, or other modifications to the systems. Moreover, some of the techniques and technologies measure the energy consumed by the individual software modules as a result of the hardware operations which they call. | 2010-10-14 |
20100262843 | Energy Controlled Data Transmission of a Field Device - A field device acquires measured values and transferring data in an energy-controlled manner. A control device monitors the quantity of energy collected in the field device and triggers data transfer only when the quantity of energy collected has exceeded a predetermined threshold value. In particular, data transfer can take place at irregular intervals. | 2010-10-14 |
20100262844 | METHOD AND SYSTEM FOR ENERGY EFFICIENT NETWORKING OVER A SERIAL COMMUNICATION CHANNEL - Aspects of a method and system for energy efficient networking over a serial communication channel are provided. In this regard, one or more circuits in an Ethernet PHY that communicates over one or more serial communication channels may transmit and/or receive physical layer signals to maintain and/or refresh synchronization and/or training parameters while operating in an energy saving mode. The Ethernet PHY may transition out of the energy saving mode upon transmitting and/or receiving a wake sequence via the serial communication channel(s), where the wake sequence comprises one or more deterministic forward error correction (FEC) block in instances that FEC is utilized for communications via the serial communication channel(s). The one or more circuits in the Ethernet PHY may be operable to perform forward error correction (FEC) functions and one or more of the FEC functions may be disabled while remaining ones of the FEC functions are enabled. | 2010-10-14 |
20100262845 | CABLE WITH MEMORY - A cable for providing electric power from a power source to a mobile device, the cable having a first connector at a first end of the cable for connecting the cable to a mobile device and with a second connector at a second end for connecting the cable to the power source, wherein the cable comprises a memory module for backup and bidirectional transfer of data to and from the mobile device. | 2010-10-14 |
20100262846 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM - An information processing device includes: a setting means for setting a standby time independently from another information processing device as an authentication target in a case where an authentication request is made from an authentication request-side device; and a transmission means for waiting for the standby time set by the setting means and transmitting unique identification information to the authentication request-side device. | 2010-10-14 |
20100262847 | APPARATUS AND METHODS OF CONTROLLING A POWER MANAGEMENT MODE OF A DIGITAL PROCESING DEVICE - An apparatus and method of controlling power consumption of a digital processing device. The apparatus and method determine whether a power management mode of the digital processing device is enabled. When a power management mode is enabled, the power is reduced to at least one portion of the digital processing device to fully power one or more memory devices of the digital processing device to a normal operation ready state. When the power management mode is disabled, power is provided to the one or more memory devices of the digital processing device to the normal operation ready state. | 2010-10-14 |
20100262848 | POWER CONSUMPTION MANAGEMENT IN A NETWORK DEVICE - A method includes buffering an initial amount of data of a data set transmitted from a MAC. When an amount of time for data associated with the data set to fill a PHY buffer approaches an amount of time for the far-end PHY to transition from the second far-end PHY power state to the first far-end PHY power state, buffering a remaining amount of data of the data set transmitted from the MAC and transmitting the data to a far-end PHY after the far-end PHY transitions between a second and first far-end PHY power state. When the amount of time for data associated with the data set to fill the buffer exceeds the amount of time for the far-end PHY to transition from the second to the first far-end PHY power state, transmitting a data delay indicator to the MAC to preempt the MAC from transmitting the remaining amount of data. | 2010-10-14 |
20100262849 | ELECTRONIC DEVICE FOR REDUCING POWER CONSUMPTION DURING SLEEP MODE OF COMPUTER MOTHERBOARD AND MOTHERBOARD THEREOF - A power-saving electronic device for use with a computer motherboard in a “suspend to memory” state is disclosed. The power-saving electronic device enables compulsory interruption of power supply to a south bridge chip and a super input output (SIO) chip of the computer motherboard in the “suspend to memory” state, such as an S3 state of Advanced Configuration and Power Interface (ACPI), so as to save power. After a user presses a power switch, the power-saving electronic device enables the south bridge chip and SIO chip to be powered on by a standby power supplied thereto and enables the computer motherboard to remain capable of awakening and resuming from the S3 state. | 2010-10-14 |
20100262850 | Power Budget Controller and Related Method for Ethernet Device - A power budget controller for an Ethernet device is disclosed. The Ethernet device is connected with another Ethernet device through a cable. The power budget controller includes a length estimation unit, a power selection unit and a link monitoring unit. The length estimation unit is utilized for generating a detection signal to the cable and for estimating length of the cable according to a refection waveform of the detection signal. The power selection unit is coupled to the length estimation unit, and utilized for adjusting a transmission power of the Ethernet device according to an estimation result of the cable length. The link monitoring unit is coupled to the power selection unit, and utilized for monitoring a link status of the Ethernet device to determine whether the transmission power is selected correctly. | 2010-10-14 |
20100262851 | NETWORK APPARATUS WITH POWER SAVING CAPABILITY AND POWER SAVING METHOD APPLIED TO NETWORK MODULE - A network apparatus with power saving capability includes a network block, a cable-connection status detection circuit and a control circuit. The network block is used for providing a network communication function. The cable-connection status detection circuit is used for detecting the cable-connection status between the network block and the link partner to generate a detecting result. The control circuit is coupled between the network block and the cable-connection status detection circuit, and implemented for controlling the network block to switch between a first operation mode and a second operation mode according to the detecting result. The power consumption of the network block operating in the first operation mode is higher than the power consumption of the network block operating in the second operation mode. | 2010-10-14 |
20100262852 | AUTOMATIC SUSPENDING APPARATUS FOR COMPUTER - An automatic suspending apparatus is electrically connected to a computer, to allow the computer to enter into a sleep state. The suspending apparatus includes an image identifying module and a control module. The image identifying module includes an image capturing device to get image information in front of the computer, and an image identifying unit to determine whether body information of a user of the computer exists in the image information. The control module includes a timing module to record time and output an enable signal, and a signal simulation module to output a sleep signal to the computer for controlling the computer to enter into the sleep state. | 2010-10-14 |
20100262853 | INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS, AND RECORDING MEDIUM - An information processing apparatus that shortens the waiting time that a user feels when restoration from a hibernation state is performed, a method for controlling the same, and a recording medium are provided. To accomplish this, when restoration from a power saving state (hibernation state) is performed, the information processing apparatus of the present invention restores only an operating system (OS) to a state of an execution in a main storage memory (RAM), and thereafter restores processes in the OS to a state of an execution. Further, the OS sequentially transfers images of the processes to the RAM from a non-volatile storage apparatus, and resumes execution of the processes from a process for which transfer is complete. | 2010-10-14 |
20100262854 | MANAGEMENT OF POWER STATES IN A PORTABLE COMPUTING DEVICE - Embodiments of the present invention provide a method and apparatus for managing power states in a personal computing device, while maintaining a perception by the user of “instant on” functionality. In various embodiments of the invention, the power states are presented to the user as a simple on/off option and the power management protocol is not visible within the user interface of the personal computing device thereby providing the user with the impression that the system is operating with a simple binary on/off protocol. In one embodiment of the invention, the personal computing device is operable to transition between a set of power states that include: 1) an “on” power state wherein the display is on and the customer can use all input devices; 2) a “ready” state wherein the display is turned off, but some modules, such as a radio module, remain on; 3) an “off” state wherein the personal computing device turns off after a slight pause, but a “booted kernel” is held in SDRAM; and 4) a “dead” state wherein none of the modules of the personal computing device are powered and the device must be cold booted to restart. | 2010-10-14 |
20100262855 | Uncore Thermal Management - A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value. | 2010-10-14 |
20100262856 | Operating Mode For Extreme Power Savings When No Network Presence Is Detected - Drivers which control hardware devices in a network adapter chip are disabled prior to reducing power to a first portion of circuits in the network adapter chip. Power is received by a second portion of circuits which are utilized for detecting network activity and communicating the activity to processors. Upon network activity detection, the first portion of circuits receives power. Drivers are enabled subsequent to detection. Drivers are enabled after receiving power by the first portion of circuits. Processors control hardware devices, disable devices before power reduction, enable devices after network activity detection and enable devices after receiving power. The network adapter chip is reset for power reception. A power reduction mode is selected where drivers are disabled after reducing power. Drivers are enabled after hardware devices are enabled. A first state is characterized by no signal before disabling drivers. A second state is characterized by signal detection before receiving power. | 2010-10-14 |
20100262857 | DATA STORAGE DEVICE INCLUDING A FAILURE DIAGNOSTIC LOG - In a particular embodiment, a data storage device is disclosed that can include a data storage medium having a device failure partition including a device failure log to store operational state information. The operational state information can include commands, data, performance data, and environmental data associated with the data storage device. The data storage device can further include a controller adapted to selectively store the operational state information to the device failure log in a first-in first-out (FIFO) order representing recent states of the data storage device. | 2010-10-14 |
20100262858 | Invariants-Based Learning Method and System for Failure Diagnosis in Large Scale Computing Systems - A method system for diagnosing a detected failure in a computer system, compares a failure signature of the detected failure to an archived failure signature contained in a database to determine if the archived failure signature matches the failure signature of the detected failure. If the archived failure signature matches the failure signature of the detected failure, an archived solution is applied to the computer system that resolves the detected failure, the archived solution corresponding to a solution used to resolve a previously detected computer system failure corresponding to the archived failure signature in the database that matches the detected failure. | 2010-10-14 |
20100262859 | SYSTEM AND METHOD FOR FAULT TOLERANT TCP OFFLOAD - Systems and methods that provide fault tolerant transmission control protocol (TCP) offloading are provided. In one example, a method that provides fault tolerant TCP offloading is provided. The method may include one or more of the following steps: receiving TCP segment via a TCP offload engine (TOE); calculating a TCP sequence number; writing a receive sequence record based upon at least the calculated TCP sequence number to a TCP sequence update queue in a host; and updating a first host variable with a value from the written receive sequence record. | 2010-10-14 |
20100262860 | LOAD BALANCING AND HIGH AVAILABILITY OF COMPUTE RESOURCES - Compute resources of multiple resource cards are assigned to compute resource pools. Each compute resource pool is typically associated with a specific service (e.g., VoIP, video service, deep packet inspection, etc). Compute resource groups are created in each compute resource pool and are allocated one or more compute resources of that compute resource pool. Those compute resources in a given resource pool that are not allocated to a compute resource group are set as backup compute resources. Upon a failure of a compute resource in a compute resource pool that includes backup compute resources, a backup compute resource is selected and takes over the function of the failed compute resource. Upon a failure of a compute resource in a compute resource group of a compute resource pool that does not include a backup compute resource, the traffic is load balanced across the remaining compute resources of that compute resource group. | 2010-10-14 |
20100262861 | PRESERVING STATE INFORMATION OF A STORAGE SUBSYSTEM IN RESPONSE TO COMMUNICATION LOSS TO THE STORAGE SUBSYSTEM - A storage subsystem has a plurality of storage devices. An indication of failure of at least one of the plurality of storage devices is detected. In response to detecting the indication of failure, monitoring is performed for a further condition. According to the monitored further condition, it is determined whether the at least one storage device has failed or whether communication has been lost to the storage subsystem. In response to determining that communication has been lost, state information of the storage subsystem is preserved to enable restoration of the storage subsystem after communication to the storage subsystem is recovered. | 2010-10-14 |
20100262862 | DATA PROCESSING SYSTEM, DATA PROCESSING METHOD, AND COMPUTER - A computer for the stream data processing system includes a query recovery point management table. A recovery point management section determines a recovery point for the stream data processing system by identifying the oldest one of input tuples used for generating output tuples, which are managed, or an earlier tuple through the use of a query recovery point stored in the query recovery point management table, and transmits the determined recovery point for the stream data processing system to an additional computer. The additional computer stores the last-received recovery point for the stream data processing system in a checkpoint file. When the computer for the stream data processing system recovers from a fault, the additional computer transmits data succeeding the stored recovery point to the computer for the stream data processing system. | 2010-10-14 |
20100262863 | METHOD AND DEVICE FOR THE ADMINISTRATION OF COMPUTERS - The invention relates to a method and a device ( | 2010-10-14 |
20100262864 | AUTOMATIC REPRODUCTION TEST DEVICE AND AUTOMATIC REPRODUCTION TEST METHOD IN EMBEDDED SYSTEM - An automatic reproduction test device in an embedded system to which external equipment ( | 2010-10-14 |
20100262865 | SYSTEM AND METHOD FOR DIAGNOSING HOME APPLIANCE - A system and method for diagnosing a home appliance are disclosed. The home appliance outputs product information as a predetermined sound signal, and transmits the sound signal to a service center of a remote site over a communication network, such that a service technician of the service center can easily check a current status of the home appliance. The diagnostic system effectively detects data using multiple synchronous signals having a time difference, quickly diagnoses a current status or fault of the home appliance, provides a service for more correctly diagnosing a faulty operation of the home appliance, and increases user satisfaction and reliability. | 2010-10-14 |
20100262866 | CROSS-CONCERN CODE COVERAGE ASSESSMENT - A method for software processing includes extracting from software code under test respective items of meta-information pertaining to elements of the software code and receiving respective quality data regarding the elements of software code. The quality data and meta-information are processed in a computer so as to assign respective metrics to the items of the meta-information responsively to the quality data regarding the elements of the software code to which the items pertain. At least some of the meta-information is presented to a user in accordance with the assigned metrics. | 2010-10-14 |