41st week of 2010 patent applcation highlights part 24 |
Patent application number | Title | Published |
20100259958 | ZERO VOLTAGE SWITCHING HIGH-FREQUENCY INVERTER - There is provided a zero-voltage switching high-frequency inverter capable of supplying a current of a large amplitude operation to a load, while suppressing a main switch current. The zero-voltage switching high-frequency inverter according to the present invention comprises: a first switch S | 2010-10-14 |
20100259959 | ZERO VOLTAGE SWITCHING HIGH-FREQUENCY INVERTER - There is provided a zero-voltage switching high-frequency inverter capable of supplying a current of a large amplitude operation to a load, while suppressing a main switch current. The zero-voltage switching high-frequency inverter according to the present invention comprises: a first switch S | 2010-10-14 |
20100259960 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. | 2010-10-14 |
20100259961 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Double-Global-Bit-Line Architecture - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A double-global-bit-line architecture provides a pair of global bit lines for each bit lines for accessing a row of memory elements in parallel. A first one of each pair allows the local bit lines of the row to be sensed while a second one of each pair allows local bit lines in an adjacent row to be set to a definite voltage so as to eliminate leakage currents between adjacent rows of local bit lines. | 2010-10-14 |
20100259962 | Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture - A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line. | 2010-10-14 |
20100259963 | Data line layouts - A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads. | 2010-10-14 |
20100259964 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells. | 2010-10-14 |
20100259965 | HIGH SPEED OTP SENSING SCHEME - A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline. | 2010-10-14 |
20100259966 | NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY APPARATUS, AND NONVOLATILE SEMICONDUCTOR APPARATUS - A nonvolatile memory element comprises a first electrode ( | 2010-10-14 |
20100259967 | MEMORY CELL - A memory cell is provided, in which a resistance value is appropriately controlled, thereby a variable resistance element may be applied with a voltage necessary for changing the element into a high or low resistance state. A storage element | 2010-10-14 |
20100259968 | STORAGE DEVICE AND INFORMATION RERECORDING METHOD - A storage device that improves ability of adjusting a resistance value level in recording and enables stable verification control is provided. VWL supplied from a second power source to a control terminal of a transistor is increased (increase portion: ΔVWL) for every rerecording by verification control by a WL adjustment circuit. In the case where a variable resistive element is able to record multiple values, ΔVWL is a value variable for every resistance value level of multiple value information. That is, ΔVWL is a value variable according to magnitude relation of a variation range of recording resistance of the variable resistive element due to a current. In the region where the variation range of the recording resistance is large (source-gate voltage VGS of the transistor is small), ΔVWL is small, while in the region where the variation range of the recording resistance is small (VGS is large), ΔVWL is large. | 2010-10-14 |
20100259969 | Preservation circuit and methods to maintain values representing data in one or more layers of memory - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 2010-10-14 |
20100259970 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including a substrate, first and second wiring lines formed above the substrate to be insulated from each other, and memory cells disposed between the first and second wiring lines, wherein the memory cell includes: a variable resistance element for storing as information a resistance value; and a Schottky diode connected in series to the variable resistance element. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of which serves as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein. | 2010-10-14 |
20100259971 | Two-Port 8T SRAM Design - An integrated circuit includes a two-port static random access memory (SRAM) cell, which includes a first half write-port, a second half write-port, and a read-port. The first half write-port includes a first pull-up transistor, a first pull-down transistor, and a first pass-gate transistor interconnected to each other. The second half write-port includes a second pull-up transistor, a second pull-down transistor, and a second pass-gate transistor interconnected to each other and to the first half write-port. Channel lengths of the first pass-gate transistor and the second pass-gate transistor are less than channel lengths of the first pull-down transistor and the second pull-down transistor. The read-port includes a read-port pull-down transistor connected to the first half write-port, and a read-port pass-gate transistor connected to the read-port pull-down transistor. | 2010-10-14 |
20100259972 | SEMICONDUCTOR MEMORY AND SYSTEM - A semiconductor memory has a short transistor coupling complementary storage nodes of a latch circuit of a memory cell. A transfer transistor and the short transistor have a diffusion layer in common coupled to one of the storage nodes. The short transistor and a driver transistor have a diffusion layer in common coupled to the other storage node. The transfer transistor, the short transistor, and the driver transistor are continuously disposed via the diffusion layers in common, and thereby, variation of characteristics of the transfer transistor can be prevented. Accordingly, it may be possible to prevent that current supplying ability of the transfer transistor changes depending on a layout in the memory cell, and that an operation margin of the memory cell deteriorates. | 2010-10-14 |
20100259973 | 8T SRAM CELL WITH HIGHER VOLTAGE ON THE READ WL - The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor. | 2010-10-14 |
20100259974 | NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT - Disclosed is a non-volatile semiconductor memory circuit. The non-volatile semiconductor memory circuit a memory cell array, and a verification sense amplifier controller configured to control switching devices, which receive external input data, depending on a level of the input data such that distribution voltage is changed when controlling a write operation by comparing the input data with cell data written in the memory cell array so as to provide cell data. | 2010-10-14 |
20100259975 | PHASE CHANGE MONEY DEVICE - A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit. | 2010-10-14 |
20100259976 | Shared Transistor in a Spin-Torque Transfer Magnetic Random Access Memory (STTMRAM) Cell - A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ. | 2010-10-14 |
20100259977 | VCC CONTROL INSIDE DATA REGISTER OF MEMORY DEVICE - A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device. | 2010-10-14 |
20100259978 | METHODS AND APPARATUS UTILIZING EXPECTED COUPLING EFFECT IN THE PROGRAMMING OF MEMORY CELLS - Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized to tighten the distribution of threshold voltages for a given bit pattern by compensating for anticipated threshold voltage shift due to capacitive coupling, which can facilitate more discernable Vt ranges, and thus a higher number of bits of data per memory cell. Tightening the distribution of threshold voltages can further facilitate wider margins between Vt ranges, and thus an increased reliability in reading the correct data value of a memory cell. | 2010-10-14 |
20100259979 | Self Limiting Method For Programming A Non-volatile Memory Cell To One Of A Plurality Of MLC Levels - A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end, a floating gate insulated from a first portion of the channel region and adjacent to the second region, a first control gate adjacent to the floating gate and insulated therefrom, and insulated from a second portion of the channel region, and adjacent to the first region, a second control gate capacitively coupled to the floating gate, and positioned over the floating gate. A method programming the cell to one of a plurality of MLC states comprises applying a current source to the first region. A first voltage is applied to the first control gate sufficient to turn on the second portion of the channel region. A second voltage is applied to the second region, sufficient to cause electrons to flow from the first region towards the second region. A third voltage is applied to the second control gate sufficient to cause electrons in the channel region to be injected onto the floating gate. The third voltage is applied uninterrupted until the floating gate is programmed to the one state. | 2010-10-14 |
20100259980 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. | 2010-10-14 |
20100259981 | Trap-charge non-volatile switch connector for programmable logic - A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion. | 2010-10-14 |
20100259982 | FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE - A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address. | 2010-10-14 |
20100259983 | NONVOLATILE MEMORY DEVICE AND DATA RANDOMIZING METHOD THEREOF - A method is for operating a nonvolatile memory device, where the memory device includes a memory cell array and a page buffer block. The method includes loading program data into the page buffer block, loading random sequence data into the page buffer block, generating randomized data by executing a logic operation, such as a bit-wise XOR operation, in the page buffer circuit on the program data and the first random sequence data, and programming the randomized data into the memory cell array. | 2010-10-14 |
20100259984 | ERASE METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - An erase method of a nonvolatile semiconductor memory device including a semiconductor substrate with diffusion regions spaced from each other, a first insulating layer formed on the semiconductor substrate, a first gate electrode formed in a first area on the first insulating layer, a charge accumulation layer formed in a second area on the first insulating layer, a second insulating layer formed on the charge accumulation layer and a second gate electrode formed on the second insulating layer includes a step of injecting hot holes into the charge accumulation layer from the diffusion region and a step of injecting channel hot electrons into a part of the charge accumulation layer close to the first gate electrode side. | 2010-10-14 |
20100259985 | Trap-charge non-volatile switch connector for programmable logic - A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion. | 2010-10-14 |
20100259986 | Trap-charge non-volatile switch connector for programmable logic - A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion. | 2010-10-14 |
20100259987 | Two Pass Erase For Non-Volatile Storage - Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells' threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing. | 2010-10-14 |
20100259988 | OFFSET NON-VOLATILE STORAGE - A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements. | 2010-10-14 |
20100259989 | OFFSET NON-VOLATILE STORAGE - A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements. | 2010-10-14 |
20100259990 | MEMORY ARRAYS, MEMORY DEVICES AND METHODS OF READING MEMORY CELLS - Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional memory array architectures. Reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device. | 2010-10-14 |
20100259991 | Nonvolatile memory cell and method for producing the same - A nonvolatile memory cell comprising a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate with a gate insulation film interposed between them, a pair of impurity diffusion layers formed in a surface layer of the semiconductor substrate on both sides of the gate electrode, a channel region positioned in the surface layer of the semiconductor substrate between the pair of impurity diffusion layers, a charge storage layer formed on a surface of at least one impurity diffusion layer and along a side wall of the gate electrode, and a charge storage layer electrode laminated on the charge storage layer. | 2010-10-14 |
20100259992 | METHODS AND APPARATUS FOR PROGRAMMING A MEMORY CELL USING ONE OR MORE BLOCKING MEMORY CELLS - Methods and apparatus for programming a memory cell using one or more blocking memory cells facilitate mitigation of capacitive voltage coupling. The methods include applying a program voltage to a selected memory cell of a string of memory cells, and applying a cutoff voltage to a set of one or more memory cells of the string between the selected memory cell and a select gate. The methods further include applying a pass voltage to one or more other memory cells of the string between the selected memory cell and the select gate. Other methods further include applying other pass voltages, other cutoff voltages and/or intermediate voltages to still other memory cells of the string. | 2010-10-14 |
20100259993 | SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges. | 2010-10-14 |
20100259994 | FLASH MEMORY AND DATA ERASING METHOD OF THE SAME - When data erasure of a flash memory is interrupted and restarted from the interrupted point, time required for the data erasure is shortened. A flash memory includes a memory cell(s), a verification circuit, and a power supply circuit. The verification circuit measures a threshold voltage of the memory cell(s) by verifying an erasure state of the memory cell(s). The power supply circuit applies, to the memory cell(s), one or more pulse voltages whose initial pulse voltage has a strength that corresponds to the measured threshold voltage. | 2010-10-14 |
20100259995 | METHOD OF PERFORMING READ OPERATION OF NONVOLATILE MEMORY DEVICE - In a method of performing a read operation of a nonvolatile memory device, a selected bit line is precharged. A pass voltage is sequentially applied to all word lines. The pass voltage applied to a word line, selected from among all the word lines, is changed for a read voltage. The read voltage is applied to the selected word line. Data of a memory cell coupled to the selected word line is read. | 2010-10-14 |
20100259996 | System and method for providing low cost high endurance low voltage electrically erasable programmable read only memory - A system and method are disclosed for increasing the reliability of a channel erase procedure in an electrically erasable programmable read only memory (EEPROM) memory cell. A memory cell of the present invention comprises a program gate, a control gate, and a floating gate that erase data using a channel erase procedure. An erase capacitor is coupled to the floating gate to provide a low voltage bias that decreases the voltage that is required to perform a Fowler-Nordheim erase process in the memory cell. The erase capacitor of the present invention is formed without adding a step in the manufacturing process of the memory cell. Memory cells of the present invention are low cost, high endurance, low voltage memory cells. | 2010-10-14 |
20100259997 | Storage circuit and storage method - A storage circuit includes a first switching unit that receives data and is controlled to switch between an electrically connecting state and an electrically disconnecting state according to a clock signal input to a gate terminal of the first switching unit, an inverting unit that inverts the data and outputs the inverted data, a second switching unit that receives the inverted data and is controlled simultaneously with the first switching unit to switch between the electrically connecting state and the electrically disconnecting state according to the clock signal input to a gate terminal of the second switching unit and a latching unit that is connected to an output terminal of the first switching unit and an output terminal of the second switching unit, latches the data and the inverted data, and outputs the data and the inverted data simultaneously. | 2010-10-14 |
20100259998 | Non-volatile RAM, and solid state drive and computer system including the same - The non-volatile random access memory (RAM) includes a non-volatile RAM array, a buffer configured to buffer data to be programmed in the non-volatile RAM array and configured to buffer data read from the non-volatile RAM array, and a control block configured to read data from at least one of the non-volatile RAM array and the buffer based on whether the data to be read has been stored in the buffer, a temperature when the data was programmed, and a time lapse since the programming of the data. | 2010-10-14 |
20100259999 | KEEPERS, INTEGRATED CIRCUITS, AND SYSTEMS THEREOF - A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter. | 2010-10-14 |
20100260000 | Low-Power Operation of Static Memory in a Read-Only Mode - A static random access memory (SRAM) operable that is biased at lower power supply voltages in a read-only mode than in a read/write mode. The SRAM can be embedded within a large-scale integrated circuit, for example in combination with a microprocessor and associated circuitry. Upon system control circuitry determining that an SRAM array can be operated in a read-only mode, for example that a large number of read operations are likely to be performed prior to writing to the SRAM array, the power supply voltages applied to the SRAM array are reduced. The array power supply voltage and periphery power supply voltage can be at separate voltages and separately reduced from the read/write mode to the read-only mode. The read-only mode can be readily used for instruction cache memories, and for local instruction memories associated with an embedded microcontroller. | 2010-10-14 |
20100260001 | MEMORY DEVICE AND METHODS THEREOF - A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor. | 2010-10-14 |
20100260002 | Circuit and Method for Small Swing Memory Signals - Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines that extend across the memory. A small signal write driver circuit is coupled to the global bit lines and configured to output a small signal differential voltage on the global bit lines during write cycles. A global sense amplifier is coupled to the global bit line pairs and configured to output a full swing voltage on a data line during a read cycle. Methods for providing small swing global bit line signals to memory cells are disclosed. The use of small swing differential voltage signals across the memory reduces power consumption and shortens memory cycle time. | 2010-10-14 |
20100260003 | SEMICONDUCTOR MEMORY APPARATUS AND REFRESH CONTROL METHOD OF THE SAME - A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. FBC transistor pairs are formed by sharing the source lines in the plurality of the floating body cell transistors. When a refresh signal is enabled, the semiconductor memory apparatus is configured to read data stored in the memory cell block by enabling a refresh read signal and then configured to rewrite the read data in the memory cell block by enabling a refresh write signal. | 2010-10-14 |
20100260004 | DEVICE AND SYSTEM FOR MIXING AND DISPENSING COMPONENTS STORED SEPARATELY FROM ONE ANOTHER - Mixing devices and systems are disclosed for storing separate components and for mixing and dispensing those components on demand. A mixing device includes a syringe having a generally tubular housing formed with a mixing chamber. A plunger is fitted to the tubular housing to form a first syringe. A dispensing syringe is releasably connected to the mixing chamber. At this point each syringe holds a desired amount of a mixture component. The contents of one syringe are passed through the mixing chamber to the other syringe, forming a usually incomplete mixture. The mixture is then passed through the mixing chamber to the other syringe. Multiple passes through the mixing chamber are continued until the desired mixing result is achieved, and the mixture material is contained in the second syringe that is used to thereafter dispense desired amounts of the mixture. | 2010-10-14 |
20100260005 | MILK FROTHING APPARATUS HAVING IMPROVED FROTHING EFFECT - An apparatus for frothing a liquid food product is disclosed. It comprises a drive unit ( | 2010-10-14 |
20100260006 | COOLING DEVICE FOR HIGH PRESSURE HOMOGENIZING APPARATUS - A suspension contains a base material including a fine solid matter. The base material may be in the form of a semifluid matter. The base material is compressed with a high pressure. The compressed base material is passed through an orifice at a high speed. The orifice includes a small clearance defined between (a) the end of the movable valve provided slidably and rotatably in the length direction inside of the cylinder case and (b) the opposing wall surface of the cylinder case. For dispersion, to emulsification, crushing, and subdivision of the base material, there is provided a heat exchange unit including continuous conduits through which a cooling medium can flow, the conduits extending over a desired length in the length direction about the orifice as a source of heat. | 2010-10-14 |
20100260007 | Preparation of therapeutic foam - Closed pouch comprising a wall defining an enclosed space containing carbon dioxide, and a pair of syringes contained within the enclosed space. The syringes are connected together by a syringe connector, and of the syringes contains a gas or gas mixture other than air, while the other contains a foamable liquid. Breakage of the syringe, connector and pumping of the syringes produces a foam useful in the treatment of varicose veins. | 2010-10-14 |
20100260008 | ROTOR-STATOR-DEVICE FOR DISPERSING OR HOMOGENIZING | 2010-10-14 |
20100260009 | COMPACT STATIC MIXER AND RELATED MIXING METHOD - A static mixing device that uniquely utilizes fluid shear, turbulence and impingement in a compact package to mix fluids, in particular liquids, entering the inlet of the device. The static mixing device enables a reduction in dead volume and/or pressure drop when compared to prior art static mixers. | 2010-10-14 |
20100260010 | CONTAINER WITH FLEXIBLE WALLS - A container with a flexible container wall, in particular a disposable bioreactor, with a container interior in which a a mixer is arranged at one end of a mixer shaft which is passed through the container wall and is drivable from the outside, wherein the mixer shaft and/or mixer is/are designed such that it/they are foldable and such that it/they can be stabilized from the outside. | 2010-10-14 |
20100260011 | CADENCE ANALYSIS OF TEMPORAL GAIT PATTERNS FOR SEISMIC DISCRIMINATION - Systems, methods, and apparatus are described that provide for analysis of seismic data. Features of temporal gait patterns can be extracted from seismic/vibration data. A mean temporal gait pattern can be determined. A statistical classifier can be used to model features of the data. The model can be used to classify the data. As a result, discrimination of seismic sources can be performed. Systems for discrimination of seismic data are also described. A system can include a vibration sensor system configured and arranged to detect vibrations. A system can also include a processor system configured and arranged to receive data from the vibration sensor, recognize the seismic data as belonging to a particular class of seismic data, and produce an output signal corresponding to the recognized particular class of seismic data. | 2010-10-14 |
20100260012 | SYSTEM AND METHOD FOR CONTROLLING AN ACOUSTIC TRANSDUCER - A system and method for controlling operation of a transducer circuit, e.g., including an acoustic transducer arranged to cause mixing, cavitation or other movement in a liquid contained in a vessel located remote from the transducer. A load current of a transformer used to generate a drive signal for the transducer may be controlled to vary sinusoidally, to vary between negative and positive values and such that the load current flows in a closed loop when a zero voltage bias is applied across the primary transformer winding, to have a reduced or eliminated 3 | 2010-10-14 |
20100260013 | Mechanically Filtered Hydrophone - A hydrophone ( | 2010-10-14 |
20100260014 | Watch Casing - The present invention provides a watch casing ( | 2010-10-14 |
20100260015 | Heat-assisted magnetic recording head with near-field light generating element - A heat-assisted magnetic recording head includes a magnetic pole, a waveguide, a near-field light generating element, and a substrate on which they are stacked. The near-field light generating element and the waveguide are disposed farther from the top surface of the substrate than is the magnetic pole. The near-field light generating element has an outer surface including: a first end face located in the medium facing surface; a second end face farther from the medium facing surface; and a coupling portion coupling the first and second end faces to each other. The first end face includes a near-field light generating part. The waveguide has an outer surface including an opposed portion opposed to a part of the coupling portion. The head further includes a mirror that reflects light emitted from a light source disposed above the waveguide, so as to let the light travel through the waveguide toward the medium facing surface. | 2010-10-14 |
20100260016 | RECORDING MEDIUM, PLAYBACK APPARATUS, PROGRAM, AND PLAYBACK METHOD - A BD-ROM contains plurality of Titles which can be branched among and a Java application executable upon reproduction of each Title. Each Title has an AV Clip and an application management table. The application is a program described in a virtual-machine oriented programming language. The application management table correlates an application to an application run attribute in the corresponding Title. The run attribute may be a continuation attribute (Persistent) for continuing the application state in the branch origin or an AutoRun attribute for automatically running the application when the application is in a non-run state in the branch origin. | 2010-10-14 |
20100260017 | Method and Apparatus for Capturing Encoded Signals on Label Surface - A method and an apparatus for capturing encoded signals on a label surface. A pick-up head is utilized to detect all or predetermined codes on a control feature zone of a label surface of a Light Scribe disc so as to generate a sub-beam added signal. A calculation unit is used to calculate the average value of the sub-beam added signals. A dynamic slicer, which could dynamically set its standard value at a half of the average value of the sub-beam added signals, slices the sub-beam added signals and captures the encoded signals. A processor decodes the encoded signals and translates those into Light Scribe disc's information. | 2010-10-14 |
20100260018 | Optical Disk Apparatus with an Improved Track Jump Performance - An optical disk device for recording or reproducing an optical disk has: an objective lens for irradiating a laser beam to the optical disk; an actuator for moving the objective lens in the radial direction of the optical disk; and a spindle motor for rotating the optical disk. After the laser beam irradiated to the optical disk passed through a PID portion of the optical disk, the actuator moves the objective lens in the radial direction of the optical disk at a timing corresponding to a rotational speed. Between signals to drive the actuator, an output time of a deceleration signal is set to a predetermined ratio of a time during which an acceleration signal is outputted. While the deceleration signal is outputted, a light spot passes through the PID portion. | 2010-10-14 |
20100260019 | OPTICAL INFORMATION RECORDING APPARATUS AND METHOD - In order to ensure a favorable recording characteristic for a write-once recording medium whose recording layer is made of an organic dye having an absorption spectrum at a wavelength λ=405 nm, this optical information recording apparatus includes a unit to set a write power to form recording marks, a space forming power to form spaces and a pulse width of a cooling pulse, and a unit to record information onto the recording medium according to the setting. The pulse width of the cooling pulse and a ratio of the space recording power to the write power are determined from a favorable region in a plane whose one coordinate axis represents the ratio and whose other coordinate axis represents the pulse width of the cooling pulse. | 2010-10-14 |
20100260020 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus includes a data processing section configured to generate data that is capable of being played back using general playback control information containing clip information defining the number of playback packets. The data processing section generates a data file in which data containing a number of playback packets, the number matching the defined number of playback packets, is contained as playback data associated with the clip information. | 2010-10-14 |
20100260021 | INFORMATION RECORDING APPARATUS, INFORMATION RECORDING METHOD, AND INTEGRATED CIRCUIT - An information recording apparatus includes a recording access setting section that executes an operation for setting parameters to be applied during a period of time that the recording section executes a recording operation, prior to the recording operation, and a successive recording control section that controls the verification section and the recording section such that a verification operation for recorded data and the recording operation for data to be recorded next are executed successively. The successive recording control section controls the recording access setting section such that the recording access setting section simultaneously executes the setting operation for the recording operation to be executed for the data to be recorded next in the period of time that the verification section executes the verification operation. | 2010-10-14 |
20100260022 | LIGHT SPOT POSITION CONTROL APPARATUS AND LIGHT SPOT POSITION CONTROL METHOD - Provided is a light-spot-position control apparatus including: a first-light-source; a second-light-source; a beam-splitter splitting a beam of the second-light-source into m beams; an optical-system allowing a first-beam of the first-light-source and the m beams to irradiate a disk-shaped recording-medium, where grooves and lands are alternately formed with an equal radial width to form the grooves in spiral/concentric shape through common-objective-lens, the optical-system allowing the three beams to irradiate the recording-medium so that an interval of m beam-spots is 1/m of track pitch; a tracking-control-mechanism tracking-controlling the beam by changing a relationship between the optical-axis and the recording-medium; a light-receiving unit individually receiving the m beams; an error-signal generator generating error-signals representing radial-position-errors of the spot-positions of the m beams with respect to the tracks based on received signals; an error-signal selector selecting at least one error-signal; and a servo-controller controlling the tracking-control-mechanism to tracking-servo the beam based on the error-signal. | 2010-10-14 |
20100260023 | VIRTUAL SPOKE SIGNALS FOR CONTROLLING OPTICAL DISC - An optical disc is rotated at no more than 600 revolutions per minute (RPM) using a spindle motor of an optical disc device ( | 2010-10-14 |
20100260024 | DISK-DRIVE SYSTEMS THAT MOVES DATA TO SPARE DRIVES FROM DRIVES ABOUT TO FAIL AND METHOD - A system and method for an improved multiple hard-disk-drive data-storage enclosure. Some embodiments position drives in counter-rotating pairs, each simultaneously accessing half the data, such that seek-caused actuator rotational-acceleration vibration cause simultaneous canceling rotational torque. Some embodiments position the edge of a first drive (or drive pair) at an angle to the actuator midpoint of a nearby second drive (or drive pair), such that rotational-acceleration vibration from a seek-caused actuator rotation in the first drive does not cause a rotational movement into the second drive that affects the tracking or seek operation. Some further embodiments position drives in a herringbone pattern to redirect air flow in addition to reducing rotational-acceleration vibration interaction. Other embodiments include a printed wire circuit board mounted to reduce the rotational-acceleration vibration interaction. | 2010-10-14 |
20100260025 | ADJUSTING METHOD FOR RECORDING CONDITION AND OPTICAL DISC DEVICE - A method for evaluating reproduced signal wherein when Euclidean distance is calculated by judging the coincidence between a binary bit array and a predetermined evaluation bit array in the evaluation of the quality of reproduced signal, in a large capacity optical disc system with constraint length equal to or greater than 5, the assumption is made that the continuous 2T count included in a predetermined evaluation bit array is denoted by i and that each evaluation bit array is composed of a main bit array having a bit length of (5+2i) and auxiliary bit arrays added before and after the main bit array; judgment on whether binary bit arrays include the predetermined evaluation bit array, is concentrated on the coincidence judgment of the main bit arrays; and at the same time, the Euclidean distance between the reproduced signal and the target signal corresponding to the evaluation bit array is calculated with respect to each main bit array and the results of such calculations are separated and counted. | 2010-10-14 |
20100260026 | MULTILAYER OPTICAL DISC - In a multi-layer optical disc, having three ( | 2010-10-14 |
20100260027 | METHOD AND DEVICE FOR WRITING A MULTI-LAYER OPTICAL DISC - A method is described for writing an optical disc ( | 2010-10-14 |
20100260028 | Laser driving device, laser driving method, optical unit, and light device - A laser driving device includes: a first pulse generating section; a second pulse generating section; a light emission waveform generating section; and a light emission level pattern storing section. | 2010-10-14 |
20100260029 | Laser driving device, laser driving method, optical unit, and light device - Disclosed herein is a laser driving device including: a sample-hold section; a first pulse generating section; a second pulse generating section; a light emission waveform generating section; a storing section; and a sampling pulse generating section. | 2010-10-14 |
20100260030 | LIQUID CRYSTAL ELEMENT, OPTICAL HEAD DEVICE, AND VARIABLE OPTICAL MODULATION ELEMENT - A liquid crystal element includes: a transparent substrate; and a liquid crystal layer including: a liquid crystal material; and a concavo-convex portion including periodic concaves and convexes, wherein the concavo-convex portion is aligned so that a longitudinal direction of liquid crystal molecules that are positioned on a side of the transparent substrate and on a concavo-convex surface that is an interface of the concavo-convex portion substantially becomes a vertical direction with respect to a concavo-convex surface on the side of the transparent substrate, or a longitudinal direction of liquid crystal molecules that are positioned on a side, in which a medium is disposed and which is opposite to the transparent substrate, and on the concavo-convex surface that is the interface of the concavo-convex portion substantially becomes the vertical direction with respect to a concavo-convex surface on the side, in which the medium is disposed, to form a diffraction grating. | 2010-10-14 |
20100260031 | Objective Lens for Optical Pickup Apparatus, and Optical Pickup Apparatus - Provided is an objective lens for an optical pickup apparatus. The objective lens collects diffracted light generated by an optical path difference giving structure onto the information recording surface of an optical information recording medium as a spot and suppresses fluctuation of diffraction efficiency due to a change of using wavelength. The optical pickup apparatus using such objective lens is also provided. The total diffraction efficiency can be improved by adjusting a wavelength at which the diffraction efficiencies of a plurality of basic structures forming the optical path difference giving structure in the objective lens are maximum, in accordance with a basic structure. | 2010-10-14 |
20100260032 | RECORDING/REPRODUCTION DEVICE, RECORDING/REPRODUCTION METHOD, AND INFORMATION RECORDING MEDIUM - The present invention contributes to getting a reproduction/recording operation done with stability on an information recording medium by utilizing an absorption edge shifting phenomenon. An apparatus | 2010-10-14 |
20100260033 | DATA RETENTION OF FERROELECTRIC FILMS BY CONTROLLING FILM COMPOSITION AND STRAIN GRADIENT FOR PROBE-BASED DEVICES - For a probe based data storage (PDS) device a ferroelectric film stack may be used as a media to store data bits by polarizing areas of the film as either an up domain or a down domain to represent bits. However a built-in-bias field (BBF) may create domain retention problems. By growing the ferroelectric films with stress and composition gradients this may generate polarization gradients which reduce the bias field. Thus, the retention (or imprint) may be improved with minimized BBF. | 2010-10-14 |
20100260034 | TEST DISC AND DRIVE VERIFICATION METHOD - In a test disc, data (test data) is recorded in such a manner as to fill an entirety of a data region and, next to this test data, border-out data is recorded which contains information indicating that recording is prohibited. By determining whether the data can be played back appropriately from a position in the vicinity of an outer periphery of the disc where playback characteristics are apt to be unstable, whether the data can be played back appropriately from all of the regions is verified. Also, by determining whether it is possible to recognize that test disc is capable of recording, it is verified whether the border-out data can be smoothly acquired from the position in the vicinity of the outer periphery of the disc where playback characteristics are apt to be unstable. | 2010-10-14 |
20100260035 | INFORMATION RECORDING MEDIUM AND MANUFACTURING METHOD THEREOF - An information recording medium ( | 2010-10-14 |
20100260036 | CONTROL CHANNEL FORMULATION IN OFDM SYSTEMS - Control channel information is formulated for transmission in orthogonal frequency division multiplexing (OFDM) systems. In an example embodiment, a method entails formulating control channel information for a transmitting device operating in an OFDM system in which a control channel spans n OFDM symbols, with n being an integer. The method includes acts of allocating, creating, and mapping. Control channel data is allocated to at least one set of resource element groups. At least one order for the set of resource element groups is created in accordance with one or more permutation mechanisms that involve at least one interleaving sequence having a low cross-correlation property. The set of resource element groups is mapped to resource elements of the n OFDM symbols of the control channel responsive to the order that is created using the permutation mechanism(s). The permutation mechanisms may include interleaving sequence(s) and/or cyclic shift(s). | 2010-10-14 |
20100260037 | METHOD AND SYSTEM FOR GUIDING PACKET DATA PROTOCOL ACTIVATION - The invention discloses a method and system for guiding a packet data protocol activation. The method includes determining whether a packet data protocol is activated and if the determination result indicates that the packet data protocol is not activated because of including a wrong service access point name, analyzing service access point name information causing the packet data protocol not activated; introducing in an associating database for associating service access point name reason information causing the packet data protocol not activated and a guide information for properly setting the service access point name; inquiring the associating database based on the service access point name reason information obtained by the analyzing and obtaining the guide information for guiding a user to properly set the service access point name; and transmitting the guide information for guiding the user to properly set the service access point name to the user side. According to the method and system of the invention, the guide information may be generated automatically before the activation of the protocol to thereby reduce the maintenance workload for these functions and to thereby properly guide the user to have the related services provisioned and accessed. | 2010-10-14 |
20100260038 | METHODS AND DEVICES FOR RESTORING SESSION STATE - Methods, systems and devices are provided for restoring a multiple call session. A communication terminal can restore a multiple call session after a fault. A network interface can couple the terminal to a network including multiple access terminals associated with the multiple call session. A request for a state of the multiple call session can be transmitted and received by a server in the network. A response including the state can be received. The multiple call session can be restored based on the state of the multiple call session and other information. | 2010-10-14 |
20100260039 | NETWORK CONNECTOR - A network connector includes an electronically insulative housing having first and second connection ports arranged in the front side thereof, an adapter circuit board mounted in the electrically insulative housing and having first and second conducting terminals respectively connected to the first and second connection ports, a filter module installed in the adapter circuit board and electrically connected to the adapter circuit board, and an automatic diversion device installed in the adapter circuit board and having a signal diversion component electrically connected to the first and second conducting terminals, the filter module and an external power input device in such a manner that when the external power input device fails, the automatic diversion device is turned into a close-circuit status, for enabling inputted WAN signals to be directly transmitted from the first connection port to the second connection port for output to avoid signal interruption. | 2010-10-14 |
20100260040 | ETHERNET RING SYSTEM AND A MASTER NODE AND AN INITIALIZATION METHOD THEREOF - The present invention provides an Ethernet ring system and the master node and the initialization method thereof, comprising the following steps: Step | 2010-10-14 |
20100260041 | LINK FAULT HANDLING METHOD AND DATA FORWARDING APPARATUS - A link fault handling method and a data forwarding apparatus are provided herein. The method includes: A first data forwarding apparatus keeps a neighboring relation with a second data forwarding apparatus after a link between the first data forwarding apparatus and the second data forwarding apparatus fails intermittently. The link between the first data forwarding apparatus and the second data forwarding apparatus fails intermittently in this way: A first fault detecting module in the first data forwarding apparatus receives no fault detection message from the second data forwarding apparatus at a preset time of receiving the message, but receives the fault detection message from the second data forwarding apparatus in an intermittency period after the preset time of receiving the message. The embodiments of the present invention shorten the convergence time of the upper-layer application module, improve the convergence performance, save CPU resources of the data forwarding apparatus, and improve working performance of the data forwarding apparatus. | 2010-10-14 |
20100260042 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN WIRELESS COMMUNICATION SYSTEM - Disclosed are a data transceiver and a method thereof in a wireless communication system, and particularly, is a data transceiver and method thereof using multiple routes in the wireless communication system. The data transmitting/receiving method using the multiple routes in the wireless communication system includes setting a direct route to a corresponding station and a relay route to a relay device, selecting one route from among the direct route and relay route, and transmitting/receiving data through the selected route. | 2010-10-14 |
20100260043 | VIDEO AND DATA NETWORK LOAD BALANCING - A load balancing communications network configured to communicate with multiple data terminals includes: a first data terminal and a second data terminal; a gateway including: a source data receiver module adapted to receive first source data representing video content and second source data representing broadband data content; a pre-coder module adapted to pre-code the first source data using pre-coding schemes to generate sets of representation data; and an ACM module adapted to associate the sets of representation data with coding and modulation schemes; and a transceiver module adapted to generate a first transmission by applying the coding and modulation schemes to the sets of representation data, generate a second transmission from the second source data, and communicate the first transmission to the first data terminal and the second transmission to the second data terminal over a satellite link. | 2010-10-14 |
20100260044 | SYSTEMS AND METHODS FOR HYBRID RATE LIMITING BASED ON DATA BIT COUNT AND DATA PACKET COUNT - A networked computing system employing a hybrid rate-limiting scheme, including one or more service provider device(s) (SPD) and one or more subscriber computing device(s) (SCD), and a data communications network facilitating data communications amongst the networked SPD and SCD devices. A SPD may apply the hybrid rate-limiting scheme to data communications provided to a SCD, based on both data bit count and data packet count information. The rate-limiting scheme may include a dual token bucket algorithm that facilitates rate-limiting PDUs in a data transfer queue utilizing one token bucket for metering data bits and another token bucket for metering data packets. The hybrid rate-limiting scheme may also employ a triple token bucket algorithm that includes one token bucket for metering data bits related to payload only data, a separate token bucket for metering data bits related to total PDU data, and another token bucket for metering data packets. | 2010-10-14 |
20100260045 | VIDEO AND DATA NETWORK LOAD BALANCING WITH VIDEO PLACEHOLDER - A network access unit includes: a source data receiver module to receive multiple first source data representing video content and second source data representing broadband data content; a network control module to generate a master schedule indicating whether each first source data is to be transmitted with one or two layers; a pre-coder module to pre-code each first source data using a first pre-coding scheme to generate a first set of representation data, and if the first source data is to be transmitted with two layers, to pre-code the first source data using a second pre-coding scheme to generate a second set of representation data; and an ACM module to associate each first set of representation data with a first coding and modulation scheme, and associate, for each first source data to be transmitted with two layers, the second set of representation data with a second coding and modulation scheme. | 2010-10-14 |
20100260046 | CONGESTION CONTROL IN A COMMUNICATION NETWORK BASED ON THE CSMA/CA PROTOCOL - The present invention relates to a congestion control method for a communication system supporting layered radio channel structure for communication between at least a first communication device and a second communication device, the layered structure comprising at least a physical layer and a medium access layer. The communication system is arranged to offer a first type of service with a first priority order and a second type of service with a second priority order, in the communication system messages comprising a preamble and a payload can be transmitted between devices, each message being separated by at least a period corresponding to a minimum allowable period between two messages. In the method the first communication device first (a) generates ( | 2010-10-14 |
20100260047 | Optimized Scheduling Method for Delay-Sensitive Traffic on High Speed Shared Packet Data Channels - The present invention supports a scheduling protocol on a wireless communication network to transmit data packets stored in a queue from a user. Two performance metrics are generated and summed to provide a priority. The performance metrics are based on the delay for the data packets stored in the queue and the rate that the data packets can be transmitted on the network. The user with the higher calculated priority for the current time slot has its data packets transmitted. | 2010-10-14 |
20100260048 | APPLICATION-SPECIFIC MANAGEMENT OF HIGH-BANDWIDTH TRANSFERS - Various exemplary embodiments relate to a system and related method for transmission of content over a telecommunications network. The system may include a deep packet inspection (DPI) device configured to perform DPI to identify an application associated with the new flow, determine an amount of bandwidth required for the application, and determine a current amount of bandwidth used by the subscriber. The DPI device may then determine a total amount of bandwidth used by the subscriber. When the total amount of bandwidth exceeds an amount of bandwidth guaranteed to the subscriber, the DPI device may perform a traffic management action on packets belonging to the new flow, such that the total amount of bandwidth used by the subscriber does not exceed the amount of bandwidth guaranteed to the subscriber. | 2010-10-14 |
20100260049 | Limiting RLC Window Size in The HSDPA Flow Control - In one aspect, a method and apparatus are disclosed that can provide an efficient and robust HSDPA flow control solution. The RNC ( | 2010-10-14 |
20100260050 | VIDEO AND DATA NETWORK LOAD BALANCING WITH VIDEO DROP - A network access unit includes: a source data receiver module adapted to receive multiple first source data representing respective video content and second source data representing broadband data content; a network control module adapted to receive link condition data and configuration data, calculate priority data based on the link condition data and the configuration data, and use the priority data to generate a master schedule including program data indicating that some but not all of the multiple first source data are to be transmitted; a pre-coder module adapted to pre-code respective first source data using respective pre-coding schemes to generate respective sets of representation data, if the program data is determined to indicate that the respective first source data is to be transmitted; and an ACM module adapted to associate, for each first source data indicated for transmission, the respective sets of representation data with respective coding and modulation schemes. | 2010-10-14 |
20100260051 | Adaptive Voice Packetization - A method is presented for adapting the packet size for VoIP communications, determined on-the-fly by the total network delay inherent at the time of packet transmission. If network delays are small relative to the maximum permissible latency for VoIP communications, the payload size per packet may be increased to maximize efficiency for the transmitted call. Alternatively, if network delays are large, the payload size per packet may be decreased in order to assure that the perceived quality of the transmitted call is acceptable. | 2010-10-14 |
20100260052 | APPARATUS AND METHOD FOR DETECTING FEMTO BASE STATION IN WIRELESS COMMUNICATION SYSTEM - An apparatus and a method for detecting a femto Base Station (BS) of a Mobile Station (MS) in a wireless communication system including a macro BS and a femto BS are provided. The method includes receiving a request, from the macro BS, to monitor an UpLink (UL) signal of an MS permissible by the femto BS to access, and monitoring the UL signal of the MS permissible to access. | 2010-10-14 |
20100260053 | PROCEDURES, SYSTEMS, APPARATUSES, AND COMPUTER PROGRAMS FOR PERFORMANCE MONITORING OF A PACKET CONNECTION - Procedures, systems, apparatuses, and computer programs are disclosed for performance monitoring of a packet connection. In example embodiments, data is added to a performance monitoring packet at a network element, and the performance monitoring packet is then forwarded to an analysis element. Analysis of the data contained in performance monitoring packet may thereby be conducted at a location other than the receiving interface. | 2010-10-14 |
20100260054 | METHOD AND APPARATUS FOR CONDUCTING MEDIA QUALITY MEASUREMENTS AT A GATEWAY - A system that incorporates teachings of the present disclosure may include, for example, a residential gateway (RG) having a controller to measure media presentation quality in a multicast network inline at the RG and to use Real-time Transport Protocol (RTP) header information from RTP packets to perform the media presentation quality measurements. Other embodiments are disclosed. | 2010-10-14 |
20100260055 | HIGH DATA RATE INTERFACE WITH IMPROVED LINK SYNCHRONIZATION - A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices. | 2010-10-14 |
20100260056 | Mobile Communication System, Common Channel Transmission Control Device, and Common Channel Transmission Control Method Used in the System and Device - A mobile communication system in which a number of common channels are added due to the offering of a new service includes: the assumption that a plurality of common channels can be arranged to transmit the same data, a monitor means that uses the reception path search results of either dedicated channels or random access channels of mobile stations to monitor the communication state of mobile stations within the cell and a control means that, when it is determined that distribution within the cell of mobile stations that receive the new service is unbalanced, effects control to divide and use the communication range permitted by a plurality of common channels. | 2010-10-14 |
20100260057 | METHOD FOR MAPPING CONTROL CHANNELS - A method for mapping control channels is disclosed. This mapping method includes calculating a control channel mapping start time of each cell according to the number of control channel groups allocated to each cell, and performing mapping of repetition of the control channel at intervals of a predetermined distance in order to acquire a diversity gain, wherein the mapping begins from the control channel mapping start time. In this case, control channels of several groups are transmitted in each cell. So, a resource allocation method during transmission of control channels (e.g., PHICH and PCFICH) is improved such that interference between neighboring cells can be reduced, resulting in the improvement of a control channel throughput. | 2010-10-14 |