41st week of 2010 patent applcation highlights part 13 |
Patent application number | Title | Published |
20100258853 | TRENCH SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A trench semiconductor device and a method of making the same are provided. The trench semiconductor device includes a trench MOS device and a trench ESD protection device. The trench ESD protection device is electrically connected between the gate electrode and source electrode of the trench MOS device so as to provide ESD protection. The fabrication of the ESD protection device is integrated into the process of the trench MOS device, and therefore no extra mask is required to define the doped regions of the trench ESD protection device. Consequently, the trench semiconductor device is advantageous for its simplified manufacturing process and low cost. | 2010-10-14 |
20100258854 | SEMICONDUCTOR DEVICE - A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion. | 2010-10-14 |
20100258855 | Field Effect Transistor with Self-aligned Source and Heavy Body Regions and Method of Manufacturing Same - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 2010-10-14 |
20100258856 | MOSFET STRUCTURE WITH GUARD RING - A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure with guard ling, includes: a substrate including an epi layer region on the top thereof a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; and a guard ring wrapping around the trench gates with contact metal plug underneath the gate metal layer. | 2010-10-14 |
20100258857 | Method of Forming a Layer Comprising Epitaxial Silicon, and a Field Effect Transistor - This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated. | 2010-10-14 |
20100258858 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided are a structure for reducing a parasitic capacitance generated between a gate electrode and a bit line in a highly integrated semiconductor memory apparatus, and a fabrication method thereof. The method of fabricating a semiconductor device according to the invention comprises: providing a substrate including an active region and an isolation region; forming a recess over the active region and the isolation region; etching the active region and the isolating region under the recess to form a fin structure; forming a buried gate over the fin structure in a lower portion of the recess; and forming an insulating layer filling in an upper portion of the recess. | 2010-10-14 |
20100258859 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING LOW CONTACT RESISTANCE - Disclosed herein is a method for forming a semiconductor device capable of reducing contact resistance in a highly integrated semiconductor device. The semiconductor device according to an exemplary embodiment of the invention includes an active region defined by an isolation film, the active region having porous regions therein, and gate patterns formed over the active region. | 2010-10-14 |
20100258860 | Semiconductor device including protrusion type isolation layer - A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion. | 2010-10-14 |
20100258861 | SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer. | 2010-10-14 |
20100258862 | TRENCH-GATE FIELD EFFECT TRANSISTOR WITH CHANNEL ENHANCEMENT REGION AND METHODS OF FORMING THE SAME - A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region. | 2010-10-14 |
20100258863 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the present invention having a vertical MOSFET that includes a first trench that is formed in a semiconductor substrate and includes a gate electrode of the vertical MOSFET embedded therein with a gate insulating film interposed therebetween, a second trench that is connected with the first trench and has a trench width wider than the first trench, a gate pad that is connected with the gate electrode and formed to a sidewall of the second trench with the gate insulating film interposed therebetween, and a gate line that is connected with a sidewall of the gate pad and electrically connects with the gate electrode via the gate pad. | 2010-10-14 |
20100258864 | Method of Forming a FET Having Ultra-low On-resistance and Low Gate Charge - In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor. | 2010-10-14 |
20100258865 | TRANSISTOR HAVING RECESS CHANNEL AND FABRICATING METHOD THEREOF - A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer, and a gate electrode filled in the trench. | 2010-10-14 |
20100258866 | Method for Forming Shielded Gate Trench FET with Multiple Channels - A method of forming a field effect transistor (FET) includes the following steps. A pair of trenches extending into a semiconductor region of a first conductivity type is formed. A shield electrode is formed in a lower portion of each trench. A gate electrode is formed in an upper portion of each trench over but insulated from the shield electrode. First and second well regions of a second conductivity type are formed in the semiconductor region between the pair of trenches such that the first and second well regions are vertically spaced from one another and laterally abut sidewalls of the pair of trenches. The gate electrode and the first shield electrode are formed relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state. | 2010-10-14 |
20100258867 | Semiconductor device - A semiconductor device comprises a substrate and a gate which extends on the substrate in a first horizontal direction. A source region is positioned at a first side of the gate and extends in the first direction. A body region of a first conductivity type is under the source region and extends in the first direction. A drain region of a second conductivity type is at a second side of the gate and extends in the first direction. A drift region of the second conductivity type extends between the body region and the drain region in the substrate in a second horizontal direction. A first buried layer is under the drift region in the substrate, the first buried layer extending in the first and second directions. A plurality of second buried layers is between the first buried layer and the drift region in the substrate. The second buried layers extend in the second direction and are spaced apart from each other in the first direction. | 2010-10-14 |
20100258868 | INTEGRATED CIRCUIT SYSTEM WITH A FLOATING DIELECTRIC REGION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer. | 2010-10-14 |
20100258869 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer). | 2010-10-14 |
20100258870 | FINFETS AND METHODS FOR FORMING THE SAME - A Fin field effect transistor includes a fin disposed over a substrate. A gate is disposed over a channel portion of the fin. A source region is disposed at a first end of the fin. A drain region is disposed at a second end of the fin. The source region and the drain region are spaced from the substrate by at least one air gap. | 2010-10-14 |
20100258871 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode. | 2010-10-14 |
20100258872 | SEMICONDUCTOR DEVICE - A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface. | 2010-10-14 |
20100258873 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first contact formed so as to be connected to the first impurity-diffused region, but not to the first gate electrode; and a second contact formed so as to be connected commonly to the second gate electrode and the second impurity-diffused region, wherein each of the first contact and the second contact has a profile such that the taper angle changes at an intermediate position in the depth-wise direction from the surface of an insulating film towards a substrate, and the intermediate position where the taper angle changes resides more closer to the substrate in the second contact, than in the first contact. | 2010-10-14 |
20100258874 | SEMICONDUCTOR DEVICE - A distance “a” from a first gate electrode of a first transistor of a high-frequency circuit to a first contact is greater than a distance “b” from a second electrode of a second transistor of a digital circuit to a second contact. The first contact is connected to a drain or source of the first transistor, and the second contact is connected to a drain or source of the second transistor. | 2010-10-14 |
20100258875 | CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS - A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region. | 2010-10-14 |
20100258876 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n | 2010-10-14 |
20100258877 | INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER - An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer. | 2010-10-14 |
20100258878 | CMOS SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material. | 2010-10-14 |
20100258879 | Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistor Gate Electrode Connections Made Using Linear First Interconnect Level above Gate Electrode Level - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected in part by a first conductor within a first interconnect level. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected in part by a second conductor within the first interconnect level. The first PMOS, second PMOS, first NMOS, and second NMOS transistor devices define a cross-coupled transistor configuration having commonly oriented gate electrodes. | 2010-10-14 |
20100258880 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer. | 2010-10-14 |
20100258881 | DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS - The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region. | 2010-10-14 |
20100258882 | FRONT END MICRO CAVITY - The present invention relates to a method of forming a micro cavity having a micro electrical mechanical system (MEMS) in a process, such as a CMOS process. MEMS resonators are being intensively studied in many research groups and some first products have recently been released. This type of device offers a high Q-factor, small size, high level of integration and potentially low cost. These devices are expected to replace bulky quartz crystals in high-precision oscillators and may also be used as RF filters. The oscillators can be used in time-keeping and frequency reference applications such as RF modules in mobile phones, devices containing blue-tooth modules and other digital and telecommunication devices | 2010-10-14 |
20100258883 | Metal-Ceramic Multilayer Structure - A metal-ceramic multilayer structure is provided. The underlying layers of the metal/ceramic multilayer structure have sloped sidewalls such that cracking of the metal-ceramic multilayer structure may be reduced or eliminated. In an embodiment, a layer immediately underlying the metal-ceramic multilayer has sidewalls sloped less than 75 degrees. Subsequent layers underlying the layer immediately underlying the metal/ceramic layer have sidewalls sloped greater than 75 degrees. In this manner, less stress is applied to the overlying metal/ceramic layer, particularly in the corners, thereby reducing the cracking of the metal-ceramic multilayer. The metal/ceramic multilayer structure includes one or more alternating layers of a metal seed layer and a ceramic layer. | 2010-10-14 |
20100258884 | Method for attaching a first carrier device to a second carrier device and micromechanical components - A method for attaching a first carrier device to a second carrier device includes forming at least one first bond layer and/or solder layer on a first exterior of the first carrier device, a partial surface being framed by the at least one first bond layer and/or solder layer, and placing the first carrier device on the second carrier device and fixedly bonding or soldering the first carrier device to the second carrier device. The at least one first bond layer and/or solder layer includes a first cover area which is larger than a first contact area. | 2010-10-14 |
20100258885 | Mems structure preventing stiction - A MEMS (Micro-Electro-Mechanical-System) structure preventing stiction, comprising: a substrate; and at least two structural layers above the substrate, wherein at least one of the at least two structural layers is a movable part, and anyone or more of the at least two structural layers is provided with at least one bump to prevent the movable part from sticking to another portion of the MEMS structure. | 2010-10-14 |
20100258886 | SPIN TORQUE TRANSFER MAGNETIC TUNNEL JUNCTION STRUCTURE - The present disclosure provides a semiconductor memory device. The device includes a bottom electrode over a semiconductor substrate; an anti-ferromagnetic layer disposed over the bottom electrode; a pinned layer disposed over the anti-ferromagnetic layer; a barrier layer disposed over the pinned layer; a first ferromagnetic layer disposed over the barrier layer; a buffer layer disposed over the first ferromagnetic layer, the buffer layer including tantalum; a second ferromagnetic layer disposed over the buffer layer; and a top electrode disposed over the second ferromagnetic layer. | 2010-10-14 |
20100258887 | Magnetic Tunnel Junction (MTJ) and Methods, and Magnetic Random Access Memory (MRAM) Employing Same - Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided. | 2010-10-14 |
20100258888 | High performance MTJ element for STT-RAM and method for making the same - An STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co | 2010-10-14 |
20100258889 | High performance MTJ elements for STT-RAM and method for making the same - An STT-MTJ MRAM cell utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The cell includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a composite tri-layer free layer that comprises an amorphous layer of Co | 2010-10-14 |
20100258890 | UNIT PIXEL OF IMAGE SENSOR HAVING THREE-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A unit pixel of an image sensor having a three-dimensional structure includes a first chip and a second chip which are stacked, one of the first chip and the second chip having a photodiode, and the other of the first chip and the second chip having a circuit for receiving information from the photodiode and outputting received information. The first chip includes a first pad which is projectedly disposed on an upper surface of the first chip in such a way as to define a concavo-convex structure, and the second chip includes a second pad which is depressedly disposed on an upper surface of the second chip in such a way as to define a concavo-convex structure corresponding to the concavo-convex structure of the first chip. The first chip and the second chip are mated with each other through bonding of the first pad and the second pad. | 2010-10-14 |
20100258891 | FINGERPRINT SENSOR CHIP PACKAGE METHOD AND THE PACKAGE STRUCTURE THEREOF - A fingerprint sensor chip package method and the package structure thereof are disclosed. The invention includes: providing a substrate; arranging a sensor chip on the substrate, with an active surface of the sensor chip facing upward; forming a patterned conductive colloid on the sensor chip, wherein the patterned conductive colloid extends from the periphery of the active surface of the sensor chip along the side wall of the sensor and electrically connects with the circuit layer of the substrate; forming a non-conductive film to cover the sensor chip, the patterned conductive colloid and a portion of the substrate; and forming a conductive film on the non-conductive film. The patterned conductive colloid replaces the conventional bond wires to improve the product yield and to omit the molding process. The conductive film is electrically connected with the grounding point/area on the substrate to dissipate the static charges for protecting the chip. | 2010-10-14 |
20100258892 | Radiation Receiver and Method of Producing a Radiation Receiver - A radiation receiver has a semiconductor body including a first active region and a second active region, which are provided in each case for detecting radiation. The first active region and the second active region are spaced vertically from one another. A tunnel region is arranged between the first active region and the second active region. The tunnel region is connected electrically conductively with a land, which is provided between the first active region and the second active region for external electrical contacting of the semiconductor body. A method of producing a radiation receiver is additionally indicated. | 2010-10-14 |
20100258893 | SOLID-STATE IMAGING DEVICE MANUFACTURING METHOD, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A method of manufacturing a solid-state imaging device includes: a first step of forming a recess portion on a top surface of a semiconductor substrate; a second step of selectively forming an impurity region of a first conductivity type in a lower portion of the recess portion by introducing impurities from a bottom surface of the recess portion; and a third step of forming a semiconductor layer in the recess portion, thus forming a photoelectric conversion portion which includes the impurity region and the semiconductor layer. | 2010-10-14 |
20100258894 | PHOTODIODE ARRAY AND IMAGE PICKUP DEVICE USING THE SAME - A photodiode array with reduced optical crosstalk and an image pickup device using it are provided. The photodiode array | 2010-10-14 |
20100258895 | PHOTODIODE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer ( | 2010-10-14 |
20100258896 | PASSIVATED OPTICAL DETECTORS WITH FULL PROTECTION LAYER - In one example, an optoelectronic transducer includes a first contact, a second contact, a passivation layer, and a protection layer. The passivation layer is formed on top of the first contact and the second contact and is configured to substantially minimize dark current in the optoelectronic transducer. The protection layer is formed on top of the passivation layer and substantially covers the passivation layer. The protection layer is configured to protect the passivation layer from external factors and prevent degradation of the passivation layer. | 2010-10-14 |
20100258897 | Trench junction barrier controlled Schottky - A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region. | 2010-10-14 |
20100258898 | PROCESS FOR FABRICATING AN ELECTRONIC DEVICE - An electronic device made of group III/N materials and a method of fabricating the device. The method includes growing by epitaxy on a substrate layer the following successive layers: a layer adapted to contain an electron gas, a barrier layer, and a surface layer. The method also includes an etching step performed on at least part of the surface layer. After the etching step, an epitaxial regrowth is performed to grow a covering layer on the etched surface layer. The material of the surface layer and the material of the covering layer include at least one Group III element and nitrogen. | 2010-10-14 |
20100258899 | SCHOTTKY DIODE DEVICE WITH AN EXTENDED GUARD RING AND FABRICATION METHOD THEREOF - A Schottky diode device includes a silicon substrate, an epitaxial silicon layer on the silicon substrate, an annular trench in a scribe line region that encompasses the epitaxial silicon layer, an insulation layer on interior sidewall of the annular trench, a silicide layer on the epitaxial silicon layer, a conductive layer on the silicide layer, and a guard ring in the epitaxial silicon layer, wherein the guard ring butts the insulation layer. | 2010-10-14 |
20100258900 | ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING - An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures. | 2010-10-14 |
20100258901 | SEMICONDUCTOR DEVICE, INK CARTRIDGE, AND ELECTRONIC DEVICE - A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit. | 2010-10-14 |
20100258902 | METHOD FOR FORMING FUSE IN SEMICONDUCTOR DEVICE - A method for forming a fuse in a semiconductor device is disclosed. The method for forming the fuse in the semiconductor device forms an interlayer insulating layer when forming a fuse, and forms neighboring metal lines having different thicknesses using a zigzag-opened mask, thus preventing a neighboring fuse of a fuse to be blown from being damaged. A method for manufacturing the semiconductor device deposits a first interlayer insulating layer on a semiconductor substrate, patterns the first interlayer insulating layer using a zigzag-opened pad type mask such that the first interlayer insulating layer has different step heights where the same step height is arranged at every second step height location, deposits a second interlayer insulating layer, patterns the second interlayer insulating layer, and buries a metal on an entire surface, and planarizes the metal until the second interlayer insulating layer is exposed, thus forming a metal pattern. | 2010-10-14 |
20100258903 | STRONTIUM RUTHENIUM OXIDE INTERFACE - Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source. | 2010-10-14 |
20100258904 | BOTTLE-SHAPED TRENCH CAPACITOR WITH ENHANCED CAPACITANCE - In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor. | 2010-10-14 |
20100258905 | SEMICONDUCTOR PACKAGE TO REMOVE POWER NOISE USING GROUND IMPEDANCE - A semiconductor package removes power noise by using a ground impedance. The semiconductor package includes an analog circuit block, a digital circuit block, an analog ground impedance structure, a digital ground impedance structure, and an integrated ground. The integrated ground and the analog circuit block are electrically connected via the analog ground impedance structure, and the integrated ground and the digital circuit block are electrically connected via the digital ground impedance structure, and an inductance of the analog ground impedance structure is greater than an inductance of the digital ground impedance structure. | 2010-10-14 |
20100258906 | CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider than a storage node region. An etch stop film is formed over the conductive pattern and the buffer insulating pattern. An interlayer insulating film is formed over the etch stop film. The interlayer insulating film is etched using the storage node mask to expose the etch stop film. The exposed etch stop film is etched to form the storage node region exposing conductive pattern. A lower storage node is formed over the storage node region. | 2010-10-14 |
20100258907 | Semiconductor device and method of manufacturing the same - An exemplary aspect of the invention provides a novel semiconductor device and a method for manufacturing the same. In an exemplary aspect of the invention, a semiconductor device is manufactured by a method comprising: forming an interlayer film on a semiconductor substrate having a principal surface; forming a first trench having a first opening width and a second trench having a second opening width larger than the first opening width in the interlayer film; forming a conductive film on a top surface of the interlayer film and on a side surface and a bottom surface of each of the first trench and the second trench; and etching the conductive film to remove the conductive film formed on the top surface of the interlayer film, while leaving the conductive film formed on the side surface and the bottom surface of each of the first trench and the second trench, thus forming a first conductor including a conductive film which is continuous over the side surface and the bottom surface of the first trench and a second conductor including a conductive film which is continuous over the side surface and the bottom surface of the second trench. | 2010-10-14 |
20100258908 | ISOLATION OF MIM FIN DRAM CAPACITOR - In one embodiment, a capacitor comprises a substrate, a first electrically insulating layer over the substrate, a fin comprising a semiconducting material over the first electrically insulating layer, a cap formed from a suicide material on the first semiconducting fin, a first electrically conducting layer over the first electrically insulating layer and adjacent to the fin, a second electrically insulating layer adjacent to the first electrically conducting layer and a second electrically conducting layer adjacent to the second electrically insulating | 2010-10-14 |
20100258909 | Longitudinal link trimming and method for increased link resistance and reliability - A resistor ( | 2010-10-14 |
20100258910 | LATERAL JUNCTION VARACTOR WITH LARGE TUNING RANGE - Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (C | 2010-10-14 |
20100258911 | NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate is provided, having a concave or convex warpage on a front surface side, wherein when a rear surface side is placed on a flat surface, an average roughness of the rear surface at a part not in contact with the flat surface and at a part where a height from the flat surface to the rear surface is a prescribed value or more is set to be greater than an average roughness of the rear surface at a part where the height from the flat surface including a part in contact with the flat surface to the rear surface is less than the prescribed value. | 2010-10-14 |
20100258912 | DOPANT DIFFUSION MODULATION IN GaN BUFFER LAYERS - A semi-conductor crystal and method of forming the same. The method includes providing a flow of dopant and column III element containing gases, then stopping flow of dopant and column III element containing gases, reducing the temperature, restarting flow of column III containing gases and then elevating the temperature. | 2010-10-14 |
20100258913 | PATTERNING METHOD AND INTEGRATED CIRCUIT STRUCTURE - A patterning method is provided. First, a mask layer and a plurality of first transfer patterns are sequentially formed on a target layer. Thereafter, a plurality of second patterns is formed in the gaps between the first transfer patterns. Afterwards, a plurality of third transfer patterns is formed, wherein each of the third transfer patterns is in a gap between a first transfer pattern and a second transfer pattern adjacent to the first transfer pattern. A portion of the mask layer is then removed, using the first transfer patterns, the second transfer patterns and third transfer patterns as a mask, so as to form a patterned mask layer. Further, a portion of the target layer is removed using the patterned mask layer as a mask. | 2010-10-14 |
20100258914 | SURFACE MOUNTABLE SEMICONDUCTOR BRIDGE DIE - A semiconductor bridge die may have an “H-design” or “trapezoidal” configuration in which a center bridge segment is flanked by one or more angled walls on each side of the bridge segment. Each wall is plated with a conductive material, thereby providing a continuous conductive path across the top surface of the die. A bottom surface of the die may be connected to a top surface of a header by epoxy in various configurations. The plated angled walls facilitate the solderable connection of the walls to a plated top surface of each of several pins on a top surface of the header, thereby providing a continuous electrical connection between the pins and the die. Also, a method is provided for manufacturing a semiconductor bridge die in accordance with the various embodiments of the die. | 2010-10-14 |
20100258915 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. An epitaxial layer is formed on a semiconductor substrate. A semiconductor element is formed in the epitaxial layer. The semiconductor substrate is removed from the epitaxial layer. | 2010-10-14 |
20100258916 | THERMAL STRESS REDUCTION - The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes within the silicon substrate, which holes create a dotted groove in the saw lanes, and wherein no second layer on an opposing side of the wafer is formed, a patterned wafer obtained by said method. The forming of the holes is preferably combined with other processing steps or another step to avoid additional operations and manipulations prior to, or after standard wafer processing, and it therefore optimizes fabrication quality and costs. Preferably the holes within the silicon substrate having a depth of more than 3 to 50 μm, preferably from 5-40 μm, like 20 μm. | 2010-10-14 |
20100258917 | CONDUCTIVE THROUGH CONNECTION AND FORMING METHOD THEREOF - A conductive through connection having a body layer and a metal layer is disposed on a semiconductor device, which the metal layer is on a top of body layer and includes a conductive body configured to penetrate the body layer and the metal layer. The width/diameter of one end of the conductive body is larger than that of another end thereof. The shape of these two ends of the body layer can be rectangular or circular. | 2010-10-14 |
20100258918 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE EMPLOYING THEREOF - A semiconductor device is provided with a silicon substrate and a structure filled in a through hole that has a rectangular cross section and extends through the silicon substrate. The structure comprises a pipe-shaped through electrode, stripe-shaped through electrodes, silicons, a first insulating film, a second insulating film and a third insulating film. The pipe-shaped through electrode is utilized as a pipe-shaped electric conductor that extends through the silicon substrate. In addition, the stripe-shaped through electrodes are provided in the interior of the pipe-shaped through electrode so that the stripe-shaped through electrodes extend through the silicon substrate and is spaced away from the pipe-shaped through electrode. A plurality of through electrodes are provided in substantially parallel within the inner region of the pipe-shaped through electrode. | 2010-10-14 |
20100258919 | SEMICONDUCTOR PATCH ANTENNA - A semiconductor patch antenna for microwave radiation having a wide pin-junction or pn-junction with the depletion region or embodiments having a separating buried oxide (SiO | 2010-10-14 |
20100258920 | MANUFACTURING METHOD OF ADVANCED QUAD FLAT NON-LEADED PACKAGE - The manufacturing method of advanced quad flat non-leaded packages includes performing a pre-cutting process prior to the backside etching process for defining the contact terminals. The pre-cutting process ensures the isolation of individual contact terminals and improves the package reliability. | 2010-10-14 |
20100258921 | ADVANCED QUAD FLAT-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads electively have a plurality of locking grooves for enhancing the adhesion between the inner leads and the surrounding molding compound. | 2010-10-14 |
20100258922 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened. | 2010-10-14 |
20100258923 | PRE-MOLDED CLIP STRUCTURE - A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed. | 2010-10-14 |
20100258924 | PRE-MOLDED CLIP STRUCTURE - A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed. | 2010-10-14 |
20100258925 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. | 2010-10-14 |
20100258926 | RELAY BOARD AND SEMICONDUCTOR DEVICE HAVING THE RELAY BOARD - A relay board provided in a semiconductor device includes a first terminal, and a plurality of second terminals connecting to the first terminal by a wiring. The wiring connecting to the first terminal is split on the way so that the wiring connects to each of the second terminals. | 2010-10-14 |
20100258927 | Package-on-package interconnect stiffener - Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package. | 2010-10-14 |
20100258928 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a first integrated circuit to the substrate by interconnects only along opposite sides of the first integrated circuit; and attaching a heat spreader to the substrate, the heat spreader extending over the first integrated circuit and between the opposite sides of the first integrated circuit. | 2010-10-14 |
20100258929 | STAIRCASE SHAPED STACKED SEMICONDUCTOR PACKAGE - A staircase shaped stacked semiconductor package is presented which includes a substrate, a multiplicity of semiconductor chip modules, a connection member, and conductive members. The substrate has connection pads along an upper surface edge. Each semiconductor chip module includes a first and a second semiconductor chip that oppose each other. The first and second semiconductor chips have respective first and second bonding pads along exposed surfaces. The connection member is placed on an uppermost semiconductor chip module and has first and second terminals electrically connected to the first and second bonding pads via conductive members. The conductive members are also coupled to the connection pads of the substrate. | 2010-10-14 |
20100258930 | Stacked semiconductor package and method of manufacturing thereof - Provided is a stacked semiconductor package and a method of manufacturing the same. The stacked semiconductor package may include a first semiconductor package, a second semiconductor package, and at least one electrical connection device electrically connecting the first and second semiconductor packages. The first semiconductor package may include a first re-distribution pattern on a first semiconductor chip and a first sealing member on the first substrate, the first sealing member may include at least one first via to expose the first re-distribution pattern. The second semiconductor package may include a second re-distribution pattern on a second semiconductor chip and a second sealing member on a lower side of the second substrate, the second sealing member may include at least one second via to expose the second re-distribution pattern. An electrical connection device may be between the first and second vias to connect the first and the second re-distribution patterns. | 2010-10-14 |
20100258931 | Semiconductor device and method of forming the same - A semiconductor device includes a chip stacked structure. The chip stacked structure may include, but is not limited to, first and second semiconductor chips. The first semiconductor chip has a first thickness. The second semiconductor chip has a second thickness that is thinner than the first thickness. | 2010-10-14 |
20100258932 | Supporting substrate before cutting, semiconductor device, and method of forming semiconductor device - A method of forming a semiconductor device may include, but is not limited to, the following processes. A supporting substrate is prepared. The supporting substrate has a chip mounting area, and a plurality of penetrating slits around the chip mounting area. At least a stack of semiconductor chips is formed over the chip mounting area. A first sealing member is formed, which seals the stack of semiconductor chips without the first sealing member filling the plurality of penetrating slits. | 2010-10-14 |
20100258933 | Semiconductor device, method of forming the same, and electronic device - A semiconductor device includes a substrate, a stack of semiconductor chips, and a first sealing material. The substrate may include, but is not limited to, a chip mounting area and a higher-level portion. The higher level portion surrounds the chip mounting area. The higher-level portion is higher in level than the chip mounting area. The stack of semiconductor chips is disposed over the chip mounting area. A first sealing material seals the stack of semiconductor chips. The first sealing material is confined by the higher-level portion. | 2010-10-14 |
20100258934 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier having a die pad and a plurality of leads, at least a chip, a plurality of wires, and a molding compound. The rough surface of the carrier enhances the adhesion between the carrier and the surrounding molding compound. | 2010-10-14 |
20100258935 | Power Semiconductor Module Comprising A Connection Device With Internal Contact Spring Connection Elements - A power semiconductor module comprises at least one power semiconductor component and a connection device which makes contact with the power semiconductor component. The connection device is composed of a layer assembly having at least one first electrically conductive layer facing the power semiconductor component and forming at least one first conductor track, and an insulating layer following in the layer assembly, and a second layer following further in the layer assembly and forming at least one second conductor track, the second layer being remote from the power semiconductor component. The power semiconductor module has at least one internal connection element, wherein the internal connection element is embodied as a contact spring having a first and a second contact section and a resilient section. The first contact section has a common contact area with a first or a second conductor track of the connection device. | 2010-10-14 |
20100258936 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package is presented which includes multiple semiconductor chips and through-electrodes. Each semiconductor chip has bonding pads formed on a first surface of the semiconductor chip and has a projection which projects from a portion of a second surface of the semiconductor chip. The first and second surfaces of the semiconductor chip face away from each other the first surface. The through-electrodes pass through the first surface and through the projection on the second surface. | 2010-10-14 |
20100258937 | Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer - A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. | 2010-10-14 |
20100258938 | SUBSTRATE AND SEMICONDUCTOR DEVICE - A substrate ( | 2010-10-14 |
20100258939 | STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS - Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device. | 2010-10-14 |
20100258940 | BALL-LIMITING-METALLURGY LAYERS IN SOLDER BALL STRUCTURES - A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer. | 2010-10-14 |
20100258941 | DAMASCENE INTERCONNECTION STRUCTURE AND DUAL DAMASCENE PROCESS THEREOF - A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF | 2010-10-14 |
20100258942 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING USING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a plurality of bit lines having a uniform width on a semiconductor substrate, an active region obliquely arranged to have a predetermined angle with respect to the bit lines, a spacer arranged around the bit lines connected to a center part of the active region. A contact pad is connected to a lower part of the bit lines. The spacer is formed not only at an upper part of sidewalls of the contact pad but also at sidewalls of the bit lines. As a result, a CD of the bit line contact increases, so that a bit line contact patterning margin also increases. A bit line pattern having a uniform width is formed so that a patterning margin increases. A storage electrode contact self-alignment margin increases so that a line-type storage electrode contact margin increases. | 2010-10-14 |
20100258943 | SEMICONDUCTOR DEVICE - A technique for expanding an effective area in which a semiconductor structure required for a semiconductor device to function is desired. With the semiconductor device | 2010-10-14 |
20100258944 | ELECTRONIC APPARATUS AND FABRICATION METHOD OF THE SAME - A first semiconductor component and a second semiconductor component are attached together via an adhesion layer so that the first semiconductor component and the second semiconductor component are electrically connected with each other via a through electrode. The through electrode is formed to fill a through hole formed in the second semiconductor component and a through hole formed in a portion the adhesion layer. The through hole formed in the portion the adhesion layer is positioned between the through hole formed in the second semiconductor component and a second connection surface of a first semiconductor component through electrode. | 2010-10-14 |
20100258945 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a method for manufacturing a semiconductor device involving the step of bonding a metallic ribbon to a pad of a semiconductor chip, breakage of the metallic ribbon is to be prevented while ensuring the bonding strength even when the metallic ribbon becomes thin with reduction in size of the semiconductor chip. In bonding an Al ribbon to a pad of a semiconductor chip by bringing a pressure bonding surface of a wedge tool into pressure contact with the Al ribbon while applying ultrasonic vibration to the ribbon positioned over the pad, recesses | 2010-10-14 |
20100258946 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - A disclosed semiconductor device includes a reinforcing board having first and second faces, an electronic part accommodating portion penetrating the reinforcing board, a through hole, an electronic part having a front face on which an electrode pad is formed and a back face, a through electrode installed inside the through hole, a first sealing resin filling a gap between the through electrode and an inner wall of the through hole, a second sealing resin filled into the electronic part accommodating portion while causing the bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside, and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode. | 2010-10-14 |
20100258947 | Nonvolatile memory devices - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays. | 2010-10-14 |
20100258948 | Semiconductor Wafer and Method of Manufacturing the Same and Method of Manufacturing Semiconductor Device - A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes. | 2010-10-14 |
20100258949 | Reduced Susceptibility To Electrostatic Discharge During 3D Semiconductor Device Bonding and Assembly - A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements. | 2010-10-14 |
20100258950 | PACKAGE WITH SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT MOUNTED THEREIN AND METHOD FOR MANUFACTURING SUCH PACKAGE - A multichip package includes a first chip and a second chip coupled with the first chip. The first chip includes a first base with a semiconductor device mounted on one side of the first base, a first electrical connection unit, a first bonding ring surrounding the semiconductor device, a first insulating layer formed on the other side of the first base and a first external bonding portion formed on the first insulating layer. The first external bonding portion is electrically connected to the first electrical connection unit. The second chip includes an integrated circuit corresponding to the semiconductor device, a second electrical connection unit fusing with the first electrical connection unit, and a second bonding ring fusing with the first bonding ring in order to form a hermetic cavity surrounding the semiconductor device, the integrated circuit, the first electrical connection unit and the second electrical connection unit. | 2010-10-14 |
20100258951 | ASSEMBLING SUBSTRATES THAT CAN FORM 3-D STRUCTURES - A system is described that connects the surface of a first substrate to the edge of a second substrate. The surfaces of additional substrates can be placed on the remaining edges of the second substrate to form a 3-D structure. Rigid support substrates can be connected to the first substrate to provide support for the first and additional substrates. The second substrate can be used to carry heat, fluids, electrical power or signals between first and additional substrates besides providing a mechanical support. | 2010-10-14 |
20100258952 | Interconnection of IC Chips by Flex Circuit Superstructure - Integrated circuit chips have top and bottom surfaces. The bottom surfaces comprise a plurality of IC die terminals in flip-chip assembly with fine-pitch terminals formed on the top surface of corresponding interconnection substrate. Each IC chip includes one or more through-silicon vias and/or edge wrap connectors that extend to the top surface, terminating in IC die terminals. Flexible connectors are coupled between the IC die terminals on the top surfaces of corresponding first and second integrated circuit chips. The flexible connectors are preferably controlled impedance, and may include differential pairs, including twisted pairs, coaxial pairs, and broadside pairs. Conductive vias within the interconnection substrates couple the fine-pitch terminals to corresponding next-level terminals on the bottom surface of the respective interconnection substrates. The next level terminals of the interconnection substrates are interconnected with terminals of a printed circuit board. | 2010-10-14 |