41st week of 2008 patent applcation highlights part 39 |
Patent application number | Title | Published |
20080248602 | LIGHT EMITTING DEVICE PROCESSES - Light-emitting devices, and related components, processes, systems and methods are disclosed. | 2008-10-09 |
20080248603 | Nitride-based semiconductor element and method of preparing nitride-based semiconductor - A method of preparing a nitride semiconductor capable of forming a nitride-based semiconductor layer having a small number of dislocations as well as a small number of crystal defects resulting from desorption with excellent crystallinity on the upper surface of a substrate through a small number of growth steps is proposed. The method of preparing a nitride-based semiconductor comprises steps of forming a mask layer on the upper surface of a substrate to partially expose the upper surface of the substrate, forming a buffer layer on the exposed part of the upper surface of the substrate and the upper surface of the mask layer and thereafter growing a nitride-based semiconductor layer. Thus, the outermost growth surface of the nitride-based semiconductor layer laterally grown on the mask layer does not come into contact with the mask layer. Therefore, desorption hardly takes place from the outermost growth surface of the nitride-based semiconductor layer, whereby a nitride-based semiconductor layer having a small number of defects is formed. Further, the mask layer is directly formed on the substrate, whereby the number of growth steps for the nitride-based semiconductor layer is reduced. | 2008-10-09 |
20080248604 | Post-logic isolation of silicon regions for an integrated sensor - In producing an integrated sensor, regions of silicon between compensating electronics and a sensor are electrically isolated, while the sensor is delineating and released. The described process can be performed at the end of a fabrication process after electronics processing (i.e., CMOS processing) and compensating electronics are formed. In an aspect, the sensor and a conductive bridge are simultaneously developed from a silicon-on-insulator (SOI) substrate. In an aspect, the sensor is undercut from a silicon substrate utilizing a lateral etch. A cavity is concurrently defined by the same lateral etch in the silicon layer, forming the conductive bridge connecting the sensor to a logic component. An isolation trench is defined in the silicon layer between the sensor components and the logic component. A polymer masks vertical surfaces from the lateral etch, and an insulator layer and photosensitive film mask horizontal surfaces from the lateral etch. | 2008-10-09 |
20080248605 | METHOD OF FORMING A PRESSURE SWITCH THIN FILM DEVICE - This invention provides a method of forming at least one pressure switch thin film device. The method includes providing a substrate and depositing a plurality of thin film device layers as a stack upon the substrate. An imprinted 3D template structure is provided upon the plurality of thin film device layers. The plurality of thin film device layers and the 3D template structure are then etched and at least one thin film device layer is undercut to provide a plurality of aligned electrical contact pairs and adjacent spacer posts. A flexible membrane providing a plurality of separate electrical contacts is deposited upon the spacer posts, the separate electrical contacts overlapping the contact pairs. The spacer posts provide a gap between the electrical contacts and the contact pairs. | 2008-10-09 |
20080248606 | PHOTODETECTOR ARRAY USING ISOLATION DIFFUSIONS AS CROSSTALK INHIBITORS BETWEEN ADJACENT PHOTODIODES - A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate. | 2008-10-09 |
20080248607 | SOLID STATE IMAGE PICKUP DEVICE AND ITS MANUFACTURE METHOD - A solid state image pickup device is provided which includes: charge accumulation regions disposed in a semiconductor substrate in a matrix shape; a plurality of vertical transfer channels formed in the semiconductor substrate each in a close proximity to each column of the charge accumulation regions; vertical transfer electrodes formed above the vertical transfer channels; a channel protective impurity layer formed just under the vertical transfer channel and surrounding the charge accumulation region; one or more pixel separation impurity layers formed under the channel protective impurity layer and at a position facing the channel protective impurity layer; an overflow barrier region having a peak position of an impurity concentration at a position deeper than the pixel separation impurity layer, the peak position of the impurity concentration being at a depth of 3 μm or deeper from a surface of the semiconductor substrate; and a horizontal CCD for transferring signal charges transferred from the vertical transfer channels in a horizontal direction. | 2008-10-09 |
20080248608 | FRONT SIDE ELECTRICAL CONTACT FOR PHOTODETECTOR ARRAY AND METHOD OF MAKING SAME - A photodiode includes a semiconductor having front and backside surfaces and first and second active layers of opposite conductivity, separated by an intrinsic layer. A plurality of isolation trenches filled with conductive material extend into the first active layer, dividing the photodiode into a plurality of cells and forming a central trench region in electrical communication with the first active layer beneath each of the cells. Sidewall active diffusion regions extend the trench depth along each sidewall and are formed by doping at least a portion of the sidewalls with a dopant of first conductivity. A first contact electrically communicates with the first active layer beneath each of the cells via the central trench region. A plurality of second contacts each electrically communicate with the second active layer of one of the plurality of cells. The first and second contacts are formed on the front surface of the photodiode. | 2008-10-09 |
20080248609 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A constitution of the display device of the invention is shown in the following. The display device includes a pixel unit including TFTs of which the active layer contains an organic semiconductor material for forming channel portions in the opening portions in an insulating layer arranged to meet the gate electrodes. The pixel unit further includes a contrast media formed on the electrodes connected to the TFTs for changing the reflectivity upon the application of an electric field, or microcapsules containing electrically charged particles that change the reflectivity upon the application of an electric field. The pixel unit is sandwiched by plastic substrates, and barrier layers including an inorganic insulating material are provided between the plastic substrates and the pixel unit. The purpose of the present invention is to supply display devices which are excellent in productivity, light in weight and flexible. | 2008-10-09 |
20080248610 | THERMAL BONDING PROCESS FOR CHIP PACKAGING - The present invention provides a thermal bonding process for chip packaging. In accordance with an aspect of the invention, there is provided an approach to solve the problems caused by the different CTEs between the die and the substrate. It discloses an improved thermal bonding process for forming pillar-shaped interconnection, which controls the thermal expansion of the semiconductor die and the substrate by applying differential heating temperature to the two, thereby minimizing the misalignment between the die and the substrate, overcoming the stresses imposed on the interconnection and allowing more reliable and accurate packaging. | 2008-10-09 |
20080248611 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The quality and reliability of a semiconductor device can be improved by eliminating a warp of a chip and performing a chip-stack. A wiring substrate, the first semiconductor chip connected via the first gold bump on the wiring substrate, the second semiconductor chip stacked via the second gold bump on the first semiconductor chip, and a sealing body are comprised. A first gold bump is connected to the wiring substrate, heating, and injection by pressure welding of the first gold bump is done under normal temperature after that at the hole-like electrode of the first semiconductor chip. Since injection by pressure welding of the second gold bump of the second semiconductor chip is done under normal temperature into the hole-like electrode of the first semiconductor chip and the second semiconductor chip is stacked, the chip-stack can be performed under normal temperature. The chip after the second stage can be stacked in the state where there is no warp in the first stage chip, by this, and the quality and reliability of the semiconductor device (semiconductor package) can be improved. | 2008-10-09 |
20080248612 | ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE - An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die. | 2008-10-09 |
20080248613 | Method of Forming a Micromechanical Device with Microfluidic Lubricant Channel - A micromechanical device assembly includes a micromechanical device enclosed within a processing region and a lubricant channel formed through an interior wall of the processing region and in fluid communication with the processing region. Lubricant is injected into the lubricant channel via capillary forces and held therein via surface tension of the lubricant against the internal surfaces of the lubrication channel. The lubricant channel containing the lubricant provides a ready supply of fresh lubricant to prevent stiction from occurring between interacting components of the micromechanical device disposed within the processing region. | 2008-10-09 |
20080248614 | WAFER LEVEL PACKAGE WITH GOOD CTE PERFORMANCE - The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM. | 2008-10-09 |
20080248615 | CMOS STRUCTURE FOR BODY TIES IN ULTRA-THIN SOI (UTSOI) SUBSTRATES - The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region from the bulk-Si region; and at least one first device located in the UTSOI region and at least one second device located in the bulk-Si region. The UTSOI region has an SOI layer atop an insulating layer, wherein the SOI layer has a thickness of less than about 40 nm. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. | 2008-10-09 |
20080248616 | Integration of strained Ge into advanced CMOS technology - A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices. | 2008-10-09 |
20080248617 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a base substrate, a first metal pattern, a gate insulating layer, a second metal pattern, a channel layer and a pixel electrode. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode of a switching element. The gate insulating layer is formed on the base substrate including the first metal pattern. The second metal pattern is formed on the gate insulating layer, and includes a source electrode, a drain electrode and a source line. The channel layer is formed under the second metal pattern, and is patterned to have substantially a same side surface as a side surface of the second metal pattern. The pixel electrode is electrically connected to the drain electrode. Therefore, an afterimage on a display panel, thus improving display quality. | 2008-10-09 |
20080248618 | ATOMIC LAYER DEPOSITION OF CeO2/Al2O3 FILMS AS GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric layer of cerium oxide and aluminum oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memory, or as a dielectric in an NROM device, because the high dielectric constant (high-k) of the film provides the functionality of a much thinner silicon dioxide film. | 2008-10-09 |
20080248619 | PROCESS FOR FABRICATING DYNAMIC RANDOM ACCESS MEMORY - A process for fabricating a dynamic random access memory is provided. In this fabrication process, the steps of forming the silicon layer, and performing the ion implantation process and the removing process are repeated at least twice and the oxidation process is performed once to form an oxidation spacer that is larger than the landing area for a bit line contact in the prior art. Therefore, when defining a bit line contact opening, a larger process window is fabricated to prevent the occurrence of a short between the bit line contact and the gate of a transistor due to misalignment. | 2008-10-09 |
20080248620 | Gated semiconductor device and method of fabricating same - A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut. | 2008-10-09 |
20080248621 | Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication - Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array. | 2008-10-09 |
20080248622 | Methods Of Fabricating Non-Volatile Memory With Integrated Peripheral Circuitry And Pre-Isolation Memory Cell Formation - Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically form word lines. | 2008-10-09 |
20080248623 | Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach - A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region. | 2008-10-09 |
20080248624 | METHOD OF MAKING INTEGRATED CIRCUIT (IC) INCLUDING AT LEAST ONE STORAGE CELL - A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer. | 2008-10-09 |
20080248625 | METHODS FOR ENHANCING TRENCH CAPACITANCE AND TRENCH CAPACITOR - Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost. | 2008-10-09 |
20080248626 | SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY - A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes. | 2008-10-09 |
20080248627 | Method of Manufacturing Integrated Deep and Shallow Trench Isolation Structures - A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinting a first pattern into the hard mask to define an open end of a first trench, imprinting a second pattern into the hard mask to define an open end of a second trench, and etching into the film stack the first trench to a first depth and the second trench to a second depth such that the first trench and the second trench each define a blind aperture in the surface of the film stack. | 2008-10-09 |
20080248628 | Methods of Forming Integrated Circuit Devices Having Single Crystal Semiconductor FIN Structures that Function as Device Active Regions - Methods of forming integrated circuit devices include forming an electrically insulating layer having a semiconductor fin structure extending therethrough. This semiconductor fin structure may include at least one amorphous and/or polycrystalline semiconductor region therein. The at least one amorphous and/or polycrystalline semiconductor region within the semiconductor fin structure is then converted into a single crystalline semiconductor region. This semiconductor fin structure is then used as an active region of a semiconductor device. | 2008-10-09 |
20080248629 | Method for manufacturing semiconductor substrate - A method for manufacturing a semiconductor substrate is provided, which comprises a step of irradiating a single crystal semiconductor substrate with ions to form an embrittlement layer in the single crystal semiconductor substrate, a step of forming a silicon oxide film over the single crystal semiconductor substrate, a step of bonding the single crystal semiconductor substrate and a substrate having an insulating surface with the silicon oxide film interposed therebetween, a step of performing a thermal treatment, and a step of separating the single crystal semiconductor substrate with a single crystal semiconductor layer left over the substrate having the insulating surface. | 2008-10-09 |
20080248630 | METHOD OF MANUFACTURING BONDED WAFER - The present invention provides a method of manufacturing a bonded wafer. The method includes forming an oxygen ion implantation layer in an active layer wafer having a substrate resistivity of 1 to 100 mΩcm by implanting oxygen ions in the active layer wafer, bonding a base wafer and the active layer wafer directly or through an insulating layer to form a bonded wafer, heat treating the bonded wafer to strengthen the bond and convert the oxygen ion implantation layer into a stop layer, grinding, polishing, and/or etching, from the active layer wafer surface side, the bonded wafer in which the bond has been strengthened to expose the stop layer on a surface of the bonded wafer, removing the stop layer, and subjecting the bonded wafer from which the stop layer has been removed to a heat treatment under a reducing atmosphere to diffuse an electrically conductive component comprised in the active layer wafer. | 2008-10-09 |
20080248631 | WAFER AND METHOD OF PRODUCING A SUBSTRATE BY TRANSFER OF A LAYER THAT INCLUDES FOREIGN SPECIES - A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implantation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties. The preferred embodiment produces substrates with a thin InP layer rendered semi-insulating by iron diffusion. | 2008-10-09 |
20080248632 | Methods of Fabricating Multi-Bit Phase-Change Memory Devices and Devices Formed Thereby - Methods of forming integrated circuit devices include forming at least one non-volatile memory cell on a substrate. The memory cell includes a plurality of phase-changeable material regions therein that are electrically coupled in series. This plurality of phase-changeable material regions are collectively configured to support at least 2-bits of data when serially programmed using at least four serial program currents. Each of the plurality of phase-changeable material regions has different electrical resistance characteristics when programmed. | 2008-10-09 |
20080248633 | Method for Manufacturing Indium Gallium Aluminium Nitride Thin Film on Silicon Substrate - The method for manufacturing the indium gallium aluminium nitride (InGaAlN) thin film on silicon substrate, which comprises the following steps: introducing magnesium metal for processing online region mask film, that is, or forming one magnesium mask film layer or metal transition layer; then forming one metal transition layer or magnesium mask layer, finally forming one layer of indium gallium aluminium nitride semiconductor layer; or firstly forming one layer of metal transition layer on silicon substrate and then forming the first indium gallium aluminium nitride semiconductor layer, magnesium mask layer and second indium gallium aluminium nitride semiconductor layer in this order. This invention can reduce the dislocation density of indium gallium aluminium nitride materials and improve crystal quality. | 2008-10-09 |
20080248634 | ENHANCEMENT MODE III-NITRIDE FET - A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device. | 2008-10-09 |
20080248635 | Polycrystalline SiGe Junctions for Advanced Devices - A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions. | 2008-10-09 |
20080248636 | Boron Ion Implantation Using Alternative Fluorinated Boron Precursors, and Formation of Large Boron Hydrides for Implanation - Methods of implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. A method of manufacturing a semiconductor device including implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. Also disclosed are a system for supplying a boron hydride precursor, and methods of forming a boron hydride precursor and methods for supplying a boron hydride precursor. In one implementation of the invention, the boron hydride precursors are generated for cluster boron implantation, for manufacturing semiconductor products such as integrated circuitry. | 2008-10-09 |
20080248637 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A flash annealing process is performed on the ion-implanted semiconductor substrate. The metal layer, the conductive layer, and the gate insulating layer are patterned. | 2008-10-09 |
20080248638 | PROCESS FOR MANUFACTURING VOLTAGE-CONTROLLED TRANSISTOR - The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential. | 2008-10-09 |
20080248639 | Method for forming electrode for group III nitride based compound semiconductor and method for manufacturing p-type group III nitride based compound semiconductor - An undoped GaN layer having a thickness of 3 μm is formed by MOVPE on a sapphire substrate with a buffer layer composed of aluminum nitride (AlN) therebetween. A GaN layer doped with 5×10 | 2008-10-09 |
20080248640 | Method for reducing polysilicon gate defects in semiconductor devices - Semiconductor devices and fabrication methods are provided, in which gate defects associated with photoresist stress after plasma trim/etch are substantially reduced. The method comprises forming a gate dielectric layer above a semiconductor body substrate; coating the gate dielectric layer with a photoresist coating; exposing and developing the photoresist coating; performing a resist annealing; and trimming and etching the photoresist coating. | 2008-10-09 |
20080248641 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device according to this invention includes; forming a first region in which a first insulating film is formed on a semiconductor substrate surface and a second region on which the semiconductor substrate surface is exposed; cleaning the semiconductor substrate surface exposed in the second region with a cleaning fluid; removing a chemical oxide film formed on the semiconductor substrate surface in the second region with the cleaning fluid; forming a second insulating film having a film thickness different from that of the first insulating film on the semiconductor substrate surface in the second region; and forming a gate electrode film on the first insulating film and the second insulating film to form a pattern in the gate electrode film (and the first insulating film and the second insulating film formed under the gate electrode film). In removing the oxide film, the oxide film is removed by processing the semiconductor substrate in the presence of a hydrogen gas at a temperature of not less than 940° and not more than 990° and a pressure of not less than 30 Torr and not more than 150 Torr. | 2008-10-09 |
20080248642 | Nanowire transistor and method for forming same - A method is provided for removing reentrant stringers in the fabrication of a nanowire transistor (NWT). The method provides a cylindrical nanostructure with an outside surface axis overlying a substrate surface. The nanostructure includes an insulated semiconductor core. A conductive film is conformally deposited overlying the nanostructure, to function as a gate strap or a combination gate and gate strap. A hard mask insulator is deposited overlying the conductive film and selected regions of the hard mask are anisotropically plasma etched. As a result, a conductive film gate electrode is formed substantially surrounding a cylindrical section of nanostructure. Inadvertently, conductive film reentrant stringers may be formed adjacent the nanostructure outside surface axis, made from the conductive film. The method etches, and so removes the conductive film reentrant stringers. | 2008-10-09 |
20080248643 | SOLDER CONNECTOR STRUCTURE AND METHOD - Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well. | 2008-10-09 |
20080248644 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH A POROUS DIELECTRIC FILM - In the fabrication of a semiconductor device, an SiO | 2008-10-09 |
20080248645 | METHOD TO CREATE A METAL PATTERN USING A DAMASCENE-LIKE PROCESS - A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive, insulative material. A conformed metal layer is formed over the dielectric layer and into the at least one trench and a photoresist layer is formed over the metal layer. The photoresist layer may be deposited so that a photoresist material fills the at least one trench and forms a thinner coating on portions of the metal layer surrounding the at least one trench. At least a portion of the photoresist layer is selectively removed. For instance, portions of the photoresist layer surrounding the at least one trench may be removed while a portion of the photoresist layer remains therein. At least a portion of the metal layer is selectively removed, such as portions of the metal layer surrounding the at least one trench. The photoresist layer remaining in the trench may subsequently be removed. Intermediate semiconductor device structures are also disclosed. | 2008-10-09 |
20080248646 | METHOD OF FABRICATING A FLASH MEMORY DEVICE - In a method of fabricating a flash memory device, an interlayer dielectric layer is formed on a semiconductor substrate. The interlayer dielectric layer is etched to form first contact holes through which junction regions of a cell region are exposed. First contact plugs are formed within the first contact holes. A top surface of the interlayer dielectric layer is etched so that portions of the first contact plugs having the largest width are exposed. The interlayer dielectric layer is etched to form a second contact hole through which a junction region of a peri region is exposed. A second metal layer is formed over the first contact plugs and the interlayer dielectric layer so that the second contact hole is gap-filled. A second contact plug is formed within the second contact hole by removing the second metal layer and the exposed portions of the first contact plugs on the interlayer dielectric layer. | 2008-10-09 |
20080248647 | Method of depositing materials on a non-planar surface - A method of depositing materials on a non-planar surface is disclosed. The method is effectuated by rotating non-planar substrates as they travel down a translational path of a processing chamber. As the non-planar substrates simultaneously rotate and translate down a processing chamber, the rotation exposes the whole or any desired portion of the surface area of the non-planar substrates to the deposition process, allowing for uniform deposition as desired. Alternatively, any predetermined pattern is able to be exposed on the surface of the non-planar substrates. Such a method effectuates manufacture of non-planar semiconductor devices, including, but not limited to, non-planar light emitting diodes, non-planar photovoltaic cells, and the like. | 2008-10-09 |
20080248648 | DEPOSITION PRECURSORS FOR SEMICONDUCTOR APPLICATIONS - This invention relates to organometallic compounds comprising at least one metal or metalloid and at least one substituted anionic 6 electron donor ligand having sufficient substitution (i) to impart decreased carbon concentration in a film or coating produced by decomposing said compound, (ii) to impart decreased resistivity in a film or coating produced by decomposing said compound, or (iii) to impart increased crystallinity in a film or coating produced by decomposing said compound. The organometallic compounds are useful in semiconductor applications as chemical vapor or atomic layer deposition precursors for film depositions. | 2008-10-09 |
20080248649 | First inter-layer dielectric stack for non-volatile memory - A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer ( | 2008-10-09 |
20080248650 | Etching apparatus and method for semiconductor device - Disclosed is an etching method for a semiconductor device. The protecting layer, such as the hydrocarbon layer or the hydrocarbon layer containing phosphorous, is formed on the photoresist layer by using the precursor gas containing no fluorine. Therefore, the etching process enabling the thin photoresist to have a high selectivity can be performed, thereby improving the etching efficiency. The method includes the steps of placing a semiconductor substrate in a chamber, in which a material layer is formed on the semiconductor substrate and a photoresist layer is formed on the material layer, forming a hydrocarbon layer on the photoresist layer by introducing precursor gas containing no fluorine into the chamber and etching an etching target material by introducing etching gas into the chamber. | 2008-10-09 |
20080248651 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A first oxide film and a second oxide film 16 are formed in a first region | 2008-10-09 |
20080248652 | SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor manufacturing apparatus includes a chamber, a gas supplier, a vacuum pump, an electrode, a conductive knitted wire mesh and a radio frequency power supply. The electrode is placed outside of the chamber and fixed to the chamber. The gas supplier supplies gas into the chamber. The vacuum pump exhausts the chamber. The radio frequency power supply supplies radio frequency power to the electrode through the conductive knitted wire mesh. | 2008-10-09 |
20080248653 | Etchant gas and a method for removing material from a late transition metal structure - An etchant gas and a method for removing at least a portion of a late transition metal structure are disclosed. The etchant gas includes PF | 2008-10-09 |
20080248654 | METHOD OF FORMING A MICRO PATTERN OF A SEMICONDUCTOR DEVICE - A method of forming a micro pattern of a semiconductor device includes forming an etch target layer, a hard mask layer, a Bottom Anti-Reflective Coating (BARC) layer and a first photoresist pattern over a semiconductor substrate. An organic layer is formed on a surface of the first photoresist pattern. A second photoresist layer is formed over the BARC layer and the organic layer. An etch process is performed so that the second photoresist layer remains on the BARC layer between the first photoresist patterns and becomes a second photoresist pattern. The organic layer on the first photoresist pattern and between the first and second photoresist patterns is removed. The BARC layer formed below the organic layer is removed. The hard mask layer is etched using the first and second photoresist patterns as an etch mask. The etch target layer is etched using a hard mask pattern as an etch mask. | 2008-10-09 |
20080248655 | DEVELOPMENT OR REMOVAL OF BLOCK COPOLYMER OR PMMA-b-S-BASED RESIST USING POLAR SUPERCRITICAL SOLVENT - Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO | 2008-10-09 |
20080248656 | METHODS FOR STRIPPING PHOTORESIST AND/OR CLEANING METAL REGIONS - Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma. | 2008-10-09 |
20080248657 | Method and system for thermally processing a plurality of wafer-shaped objects - Process and system for processing wafer-shaped objects, such as semiconductor wafers is disclosed. In accordance with the present disclosure, a multiple of two wafers are processed in a thermal processing chamber. The thermal processing chamber is in communication with at least one heating device for heating the wafers. The wafers are placed in the thermal processing chamber in a face-to-face configuration or in a back-to-back configuration. | 2008-10-09 |
20080248658 | ELECTRICAL CONNECTOR LEAD FRAME - An electrical interconnection system with high speed, differential electrical connectors. The connector is assembled from wafers containing columns of conductive elements, some of which form differential pairs. Each column may include ground conductors adjacent pairs of signal conductors. The ground conductors may be wider than the signal conductors, with ground conductors between adjacent pairs of signal conductors being wider than ground conductors positioned at an end of at least some of the columns. Each of the conductive elements may end in a mating contact portion positioned to engage a complementary contact element in a mating connector. The mating contact portions of the signal conductors in some of the pairs may be rotated relative to the columns. The printed circuit board to which the differential signal connector is mounted may be constructed with elongated antipads around pairs of signal conductors. | 2008-10-09 |
20080248659 | ELECTRICAL CONNECTOR WITH COMPLEMENTARY CONDUCTIVE ELEMENTS - An electrical interconnection system with high speed, differential electrical connectors. The connectors are formed with columns of conductive elements, some of which carry signals some of which act as ground conductors. The conductive elements may contain projections to secure the conductive elements in a housing or to facilitate desirable current flow patterns. To avoid impedance discontinuities caused by the projections, adjacent conductive elements may be formed with complementary portions to provide a relatively uniform edge-to-edge spacing between signal and ground conductors along the length of the signal conductor. To manufacture such a connector in which both the signal and the ground conductive elements contain projections, the conductive elements carrying signals may be inserted into a housing from one side and the conductive elements acting as ground conductors may be inserted from an opposite side. | 2008-10-09 |
20080248660 | HIGH SPEED, HIGH DENSITY ELECTRICAL CONNECTOR WITH SELECTIVE POSITIONING OF LOSSY REGIONS - An electrical interconnection system with high speed, high density electrical connectors. The connectors incorporate electrically lossy material, selectively positioned to reduce crosstalk without undesirably attenuating signals. The lossy material may be molded through ground conductors that separate adjacent differential pairs within columns of conductive elements in the connector. However, regions of lossy material may be set back from the edges of the ground conductors to avoid undesired attenuation of signals. Also, the lossy material may be positioned in multiple regions along the length of signal conductors. The regions may be separated by holes, notches, gaps or other openings in the lossy material, which can be simply formed as part of a molding operation. | 2008-10-09 |
20080248661 | Circuit board assembly with light emitting element - A circuit board assembly includes a circuit board having opposing first and second surfaces each extending between at least one edge surface that intersects the first and second surfaces. A light emitting element is mounted directly over the edge surface of the circuit board. | 2008-10-09 |
20080248662 | TAMPER RESISTANT INTERRUPTER RECEPTACLE HAVING A DETACHABLE METAL SKIN - A tamper-resistant device including a housing having a first surface and a second surface; and one or more covers positioned on the first surface of the housing, wherein the first surface includes at least two angled surfaces for receiving the one or more covers to create a securedly fixed connection, and wherein the one or more covers are securedly fixed to the housing via a snapping device. | 2008-10-09 |
20080248663 | Methods and apparatus for flexible extension of electrical conductors beyond the edges of a substrate - A flexible extension wafer translator includes a wafer translator portion, one or more flexible connectors extending outwardly therefrom, and a connector tab coupled to the distal end of each outwardly extending flexible connector. The flexible connectors may take any suitable form, including but not limited to, draped and pleated. | 2008-10-09 |
20080248664 | LEVER-TYPE CONNECTOR AND CONNECTOR ASSEMBLY | 2008-10-09 |
20080248665 | Connector and Connector Assembly - A connector has a first housing ( | 2008-10-09 |
20080248666 | Connector Storing Apparatus and Electronic Device - A main frame supports a receiving-side connector to which a connecting-side connector is connected in movable manner toward inside. A holding unit holds the receiving-side connector that is moved to the inside. A connector biasing unit applies a biasing force toward outside to the receiving-side connector. A hold releasing unit releases a hold by the holding unit, and moves the receiving-side connector to the outside by the biasing force. A pressing-force applying unit applies, when the receiving-side connector is not moved by the biasing force, a pressing force for ejecting the receiving-side connector to the receiving-side connector. | 2008-10-09 |
20080248667 | POWER STRIP FOR COMPUTER AND RELATED COMPUTER PERIPHERALS - A power strip includes a plug having a hot line terminal and a neutral line terminal, at least one outlet having a hot line terminal and a neutral line terminal, and a power control apparatus having a connector and an electrical switch. The neutral line terminal of the at least one outlet is electrically connected to the neutral line terminal of the plug. The connector is connected to a controlling portion of the electrical switch. The hot line terminal of the plug is connected to the hot line terminal of the at least one outlet via a switching portion of the electrical switch. If the connector is electrified, the controlling portion controls the switching portion to turn on thereby controlling the hot line terminal of the plug to be electrically connected to the hot line terminal of the at least one outlet. | 2008-10-09 |
20080248668 | Plug - A plug for a socket of an airbag is disclosed. The plug has a position assurance member having a movable member and a static member and the position assurance member is movable between a transport position and an end position by moving the movable member in relation to the static member. The plug also has a shorting contact, a flow of current in the shorting contact being possible in the transport position while the flow of current is not possible in the end position. The end position is attainable only when the plug is inserted into the socket. | 2008-10-09 |
20080248669 | HIGH VOLTAGE ELECTRICAL CONNECTORS - The present invention is directed to a connector housing for high voltage wires, either single ended or double ended with an integrated connector. Other features of the present invention include integration of a deep recessed high voltage connector contact for an arc and leakage resistant high voltage connection point, use of a female socket pin embedded at the base of the connector. The socket pin is co-molded into the connection end of the body, or it is co-molded or press fitted into a hole at the end of the connector housing. | 2008-10-09 |
20080248670 | ELECTRICAL POWER CONTACTS AND CONNECTORS COMPRISING SAME - Electrical connectors and contacts for transmitting power are provided. One power contact embodiment includes a first plate that defines a first non-deflecting beam and a first deflectable beam, and a second plate that defines a second non-deflecting beam and a second deflectable beam. The first and second plates are positioned beside one another to form the power contact. | 2008-10-09 |
20080248671 | LOCKING HIGH DEFINATION MULTIMEDIA INTERFACE PLUG - A locking plug comprises a plug body having an opening and an actuator that moves between a first position where a locking tab is biased to protrude from the opening and a second position where the locking tab is positioned within the opening. | 2008-10-09 |
20080248672 | Dongle for accessing data storage cartridges - A dongle is provided for coupling a data storage cartridge with a host computing device. The data storage cartridge includes a data storage medium and an electrical connection providing access to the data storage medium. The dongle includes a first plug and a second plug. The first plug includes a first electrical data connector configured for insertion into a receptacle of the host computing device. The second plug includes a second electrical data connector and a clamp mechanism sized to grasp a portion of the data storage cartridge to maintain the second electrical data connector in a position to communicate with the electrical connection of the data storage cartridge. The second plug is in electrical communication with the first plug. As such, the dongle is configured to provide an electrical communication link between the host device and the data storage cartridge. | 2008-10-09 |
20080248673 | Detachable coupling for a remote inspection device - A remote inspection device is provided for inspecting visually obscured locations. The device is generally comprised of a imager housing and a display housing disposed on opposite ends of a modular, flexible cable. An imaging device and one or more light sources are embedded in the end of the cylindrical imager housing. A display housing is coupled to the other end of the flexible cable and configured to be grasped by a user of the device. A display device supported by the display housing receives a video signal from the imaging device and converts the video signal to a video image. The flexible cable can be removably attached to other components with a detachable coupling. | 2008-10-09 |
20080248674 | ELECTRICAL PLUG CONNECTOR PART - An electrical plug connector part with a locking nut that is rotatable relative to the plug body and can be screwed onto an associated matching plug part and that is secured against unintentional rotation relative to the plug body by matched latch elements, wherein first latch elements are rigid and are molded onto the locking nut, and corresponding second latch elements are mounted rotation-proof and with spring action on the plug body. The locking nut and the plug body of the plug connector part have an equal number N of first and second latch elements that are spaced from each other and are arranged in sequence in circumferential direction, with the first latch elements being located on an inner circumference of the locking nut, and the second latch elements being located on an outer circumference of the plug body. The spacing of the first latch elements is different than that of second latch elements. The N first and second latch elements do not follow each other directly, with the first latch elements specifically not forming a locking ring gear. | 2008-10-09 |
20080248675 | SHIELDED SURFACE MOUNT CONNECTOR - A shielded surface mount connector mounted to a PCB includes a housing, a plurality of terminals and a shelter enclosing the housing. The housing provides a first protruding portion and a second protruding portion. The first and second protruding portions extend downwards respectively to form a first pillar and a second pillar. The shelter provides a first shielding portion and a second shielding portion for covering the first and second protruding portions respectively. The edges of the shielding portions extend downwards respectively to form a first inserting portion and a second inserting portion. As mentioned above, by inserting the first and second pillars and the two inserting portions into the corresponding holes of a PCB, the shielded surface mount connector is mounted to the edge of the PCB, which makes the electronic products much thinner due to the present invention, and saves more space of the PCB for other designs. | 2008-10-09 |
20080248676 | NETWORK PLUG - The present invention relates to a technical field of high-speed network plug, and more particularly to an improved network plug. The network plug includes a short body, a one-piece holder, a core holder, a clip and a U-like metal housing. The core holder and the one-piece holder are disposed inside the short body. The lengths of the core holder and the one-piece holder are shortened to 4 mm and 3 mm respectively. The back portion of the clip is flexible and arc-like and has a rising and curved central portion. The rear end and the seat thereof are formed integrally. The front end of the clip is inserted in a slot located on a top side of the short body. The clip is fastened on the top side of the short body through a seat thereof. The network plug of the present invention is featured by simple structure, easy plug-out after plugging in a jack, low likelihood of damage to network plug and jack, good high-frequency property and support of demand for performance and speed. | 2008-10-09 |
20080248677 | Electrical Contact Holder Assembly - An electrical contact assembly holder includes a body having a cable interface. A contact holder is attached to the body on a side opposite from the cable interface and is provided with a plurality of contacts arranged in rows. Each of the contacts has a base that secures the contact to the contact holder. At least one electrically conductive plate is disposed inside the body and extends substantially parallel to the contacts from the cable interface to the base of the contacts. The electrically conductive plate is electrically connected to the contacts and has recesses that receive the contacts to separate the rows of the contacts. A resilient tab extends from the electrically conductive plate to an outside of the electrical contact assembly holder. The resilient tab is electrically conductive and is configured to engage a shielding shell of a connector that receives the electrical contact assembly holder. | 2008-10-09 |
20080248678 | Connector fastening arrangement for printed circuit boards - A connector fastening arrangement locks a connector housing to a printed circuit board, thereby to effect engagement between a resilient contact on the housing and a corresponding electrical element on the adjacent top surface of the printed circuit board. A rotary locking member carried by the connector housing extends within a locking bore contained in the adjacent surface of the printed circuit board, the locking member being rotatable between locked and unlocked positions relative to the connector housing. In a preferred embodiment, the locking bore is a through bore, and the locking member extends completely through the locking bore. When the locking member is rotated toward the locked position, an eccentric locking device carried by the extremity of the locking member extends in locking engagement beneath the bottom surface of the printed circuit board. In a second embodiment, the locking device comprises a bayonet fitting arrangement. | 2008-10-09 |
20080248679 | Circuit board fixing structure - The base has a plurality of elastic claws ( | 2008-10-09 |
20080248680 | POWER CABLE CONNECTOR - This invention relates to an improved power connector that has a housing comprising a plurality of slots that are each for receiving a receptacle contact. Preferably, the housing has a plurality of quick-disconnect contacts each disposed in one of the housing slots. Further, a cover, may be coupled to the housing, and the housing may comprise a top portion and a bottom portion. A strain relief member, may be disposed between the cover top and bottom portions. A plurality of cables extend through the channels disposed in the strain relief members and are attached to the housing quick disconnects. A latching spring assembly that may comprise two latching springs is coupled to the housing and attaches the power cable connector to a receptacle connector, such as a right-angle or straight board connector. | 2008-10-09 |
20080248681 | Electrical connector arrangement for knife contacts - An electrical connecting arrangement includes a locator device mounted on a photovoltaic panel for relatively positioning a connector housing such that a resilient contact on the connector housing is arranged for electrical connection with a stationary rigid contact on the photovoltaic panel that extends in space relation within a chamber contained in the locator device, connection being made via an access opening contained in the locator device. Preferably, the stationary contact is a knife contact having a rectangular configuration defining a pair of parallel end edges that are supported by a pair of support slots defined in the opposed walls of the access opening, thereby to support the stationary contact during the engagement thereof by the resilient contact. | 2008-10-09 |
20080248682 | Snagless plug and boot connection - A boot with a flexible actuator can be used to provide improved protection and ease of use for an electrical connector plug. The plug, such as an RJ45 plug connected to a data or communications cable, can have an extended latch member adapted to releasably engage a connection mechanism of a receptacle into which the plug is placed. A recess in a receiving portion of an actuator can capture the extended end of the latch member, whereby damage to the latch member due to snagging or catching on nearby objects is prevented. | 2008-10-09 |
20080248683 | OPTOELECTRONIC MODULE RETENTION MECHANISM - A retention mechanism for an electronic or optoelectronic module. In one example embodiment, an optoelectronic module retention clip includes a base, a pair of arms extending from the base, and a protrusion extending from each arm. Each protrusion is configured to engage a complementary structure defined in a de-latch slide and a complementary structure defined in an optoelectronic module shell so as to prevent motion of the de-latch slide relative to the shell when the optoelectronic module retention clip is attached to the optoelectronic module. | 2008-10-09 |
20080248684 | Jack Connector Assembly Having Circuity Components Integrated for Providing Poe-Functionality - The invention relates two a jack connector assembly having a circuitry components integrated providing power over LAN, functionality, in particular for use with regard to Ethernet-networks. An object of the present invention is to provide a jack connector assembly providing integrated power over LAN-functionality and especially avoiding any undesirable and destructive heat accumulation. The object is achieved by a modular jack connector assembly having at least one connector housing ( | 2008-10-09 |
20080248685 | Connector Systems for Electrosurgical Generator - A connector system for coupling electrosurgical instruments to electrosurgical generators is provided. The connector system includes a plug portion connectable to an electrosurgical instrument, the plug portion of the electrosurgical instrument having a shape specific to a particular manufacturer; and a plug receptacle portion supported on the electrosurgical generator; the plug receptacle portion being shaped to receive the plug portion of the electrosurgical instrument of the particular manufacturer and the plug portion of the electrosurgical instrument of any other manufacturer. | 2008-10-09 |
20080248686 | CONNECTOR STRUCTURE - A connector structure is constituted by a body, an illumination element, and a locking seat, wherein the body is extended with a cover, and an interior of the body is provided with a first tunnel having a contact terminal and conduction terminal, as well as a second tunnel having the illumination element and the locking seat. By installing the illumination element on the locking seat, and by transversal movement of the locking seat in a locking slot of the body, the illumination element can be conveniently assembled with the body, and the locking seat can be stably connected with the body without easily dropping out. | 2008-10-09 |
20080248687 | Internally Overlapped Conditioners - The application discloses novel internal structures of energy conditioners, assemblies of external structures of energy conditioners and mounting structure, and novel circuits including energy conditioners having A, B, and G master electrodes. | 2008-10-09 |
20080248688 | SURE-GRIP RCA-TYPE CONNECTOR AND METHOD OF USE THEREOF - A sure-grip RCA-type coaxial cable connector is provided, wherein the connector comprises a connector body having an external surface upon which at least two gripping rings are securely located. Friction-enhancing surface features are positioned upon at least a portion of the external surface of the connector body between at least two of the gripping rings. Sure-grip fastening of the connector to an interface port is provided by gripping the connector so as to engage the gripping rings and the friction-enhancing surface features while maneuvering the connector onto an interface port. | 2008-10-09 |
20080248689 | FLEXIBLE RF SEAL FOR COAXIAL CABLE CONNECTOR - The present invention incorporates a flexible seal into a typical coaxial cable connector. The seal comprises a flexible brim, a transition band, and a tubular insert with an insert chamber defined within the seal. In a first embodiment the flexible brim is angled away from the insert chamber, and in a second embodiment the flexible brim is angled inward toward the insert chamber. A flange end of the seal makes a compliant contact between the port and connector faces when the nut of a connector is partially tightened, and becomes sandwiched firmly between the ground surfaces when the nut is properly tightened. The present invention allows the connector to make a uniform RF seal on a port even with a range of tightening torques. | 2008-10-09 |
20080248690 | CONNECTOR AND CONTACT ASSEMBLIES FOR MEDICAL DEVICES - A contact assembly of a medical device includes a sidewall surrounding a bore that receives axial insertion of a medical electrical lead connector; the bore extends along a longitudinal axis of the contact assembly, and first and second contact clips are mounted on, or attached to the sidewall such that opposing first and second legs of each clip extend into the bore of the contact assembly. Each of the first and second clips include first and second terminal ends, which terminate the first and second legs, respectively. The first and second legs of each contact clip may bend into and out from the bore such that the first and second terminal ends of each clip are located outside the bore. | 2008-10-09 |
20080248691 | RELEASABLY ENGAGING HDMI PLUG - A releasably engaging plug comprises a plug body having an extension, the outer surface of the extension having at least one projection thereon. The projection is configured to releasably engage at least one spring biased tab of a mating receptacle upon insertion of the extension into the receptacle. Engagement of the spring biased tab with the projection increases the mechanical friction fit between the mating components. | 2008-10-09 |
20080248692 | Extended Memory Card and Manufacturing Method - An embodiment of the present invention includes an extended memory card comprising memory circuitry, extended memory controller circuitry, a plurality of first format connection fingers, and a plurality of second format connection fingers. The memory circuitry is operable to store data files therein. The extended memory controller circuitry is operable to control data file storage and retrieval to and from the memory circuitry. | 2008-10-09 |
20080248693 | SHIELDLESS, HIGH-SPEED ELECTRICAL CONNECTORS - A shieldless, high-speed electrical connector is disclosed. Such a connector may include a first column of electrical contacts comprising a first arrangement of differential signal pairs separated from one another by first ground contacts, and a second column of electrical contacts adjacent to the first column, the second column of electrical contacts comprising a second arrangement of differential signal pairs separated from one another by second ground contacts. The connector may be devoid of electrical shield plates between the first column of electrical contacts and the second column of electrical contacts. The connector may be capable of transferring differential signals at data transfer rates of at least ten gigabits per second through the connector while producing no more than an acceptable level of cross talk on any of the differential signal pairs. | 2008-10-09 |
20080248694 | TRANSCEIVER CONNECTOR WITH INTEGRATED MAGNETICS - In one example embodiment, a connector structure includes a housing that defines a chamber, a plurality of magnetic cores positioned within the chamber, and a means for positioning the plurality of magnetic cores so that a first magnetic core of the plurality of magnetic cores is not in physical contact with a second magnetic core of the plurality of magnetic cores. | 2008-10-09 |
20080248695 | Modular jack with improved grounding member - A modular jack ( | 2008-10-09 |
20080248696 | MEDICAL ELECTRICAL LEAD CONNECTION SYSTEMS AND METHODS - An electrical connection assembly of a medical device includes at least one conductive sidewall mounted in a fixed position to a module base; the sidewall may be electrically coupled to a feedthrough wire. The assembly further includes at least one resilient member to apply a spring force against a connector element of a lead connector when the connector element is positioned adjacent to the conductive sidewall. The spring force of the resilient member causes electrical coupling between the connector element and the conductive sidewall. | 2008-10-09 |
20080248697 | Slide lock panel-mount connector - An electrical connector for mounting to a panel includes a housing configured to be mounted to the panel, and a deflectable latch including a latch arm having a length extending in a longitudinal direction between a fixed end secured to the housing and a free end movable with respect to the housing. The free end has a locking finger extending therefrom. The latch arm is deflected laterally with respect to the length thereof to align the locking finger with an opening through the panel. The deflectable latch returns to a resting position once the housing is mounted to the panel, and the locking finger engages the panel when in the resting position. | 2008-10-09 |
20080248698 | Terminal block with jaw part for engagement with the flat pin of movable electric contacts - A terminal block for connecting electric wires using a removable contact, such as a fuse, with flat pins, includes an insulating body and two conducting elements housed inside the body. Associated with respective terminals for retaining the free end of a respective electric wire, the conducting elements including, at an end opposite to the end for retaining the wire, a resilient clamp which is open on one side for insertion, retention and electric contact with the respective flat pin of the movable contact. | 2008-10-09 |
20080248699 | Electric Terminal For Printed Circuit Boards - The invention relates to physical connections of a plurality of mutually insulated connecting elements, especially configured for printed circuit boards, the physical connection being a component of an electric connection between two or more conducting elements with direct contact using a spring. The electric terminal represents such a connection, and allows rapid and simple detachment of the conductor, similar to the plug‘n’play technology used for plugging in the conductors. A clamping system is provided which allows to simply and rapidly detach the conductor and which is accessible from several sides of the terminal. The advantageous accessibility of the clamping system makes it possible to always use the tools for operating the clamping system in a manner perpendicular to the surface of the printed circuit board. | 2008-10-09 |
20080248700 | Contact Arrangement - The invention relates to a contact arrangement in which an electrical contact of U-shaped construction is fixed in common by two contact holders, which surround it at the top and bottom, and selectably also upper and lower screening caps, by means of two pins which go through corresponding bores not only of the described components, but also of the insulating rod at which the fastening shall take place. | 2008-10-09 |
20080248701 | Sports board having stringers - A sports board includes a foam core, a top skin, a bottom skin, at least one stringer and at least one flexible foam tube. The top skin is connected to a top of the foam core. The bottom skin is connected to a bottom of the foam core. The stringer enclosed by the foam tube is secured in the foam core for strengthening the board. | 2008-10-09 |