41st week of 2008 patent applcation highlights part 14 |
Patent application number | Title | Published |
20080246099 | LOW TEMPERATURE POLY OXIDE PROCESSES FOR HIGH-K/METAL GATE FLOW - An integrated circuit device is disclosed as comprising a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. Various method can be used to form the poly-oxide coating include conversion of a ploy-silicon coating using UV O | 2008-10-09 |
20080246100 | HIGH-K DIELECTRIC FILM, METHOD OF FORMING THE SAME AND RELATED SEMICONDUCTOR DEVICE - A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content. | 2008-10-09 |
20080246101 | METHOD OF POLY-SILICON GRAIN STRUCTURE FORMATION - A method for forming a poly-crystalline silicon film on a substrate by positioning a substrate within a processing chamber, heating the processing chamber to a first temperature between about 640° C. and about 720° C., stabilizing a deposition pressure between about 200 Torr and about 350 Torr, introducing a silicon precursor into the processing chamber to deposit a silicon film comprising an amorphous or hemisphere grain film, and heating the processing chamber to a second temperature between about 700° C. and about 750 C.° to anneal the amorphous or hemisphere grain film into a poly-crystalline nano-crystalline grain film. | 2008-10-09 |
20080246102 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an Nch transistor having a first gate electrode and a Pch transistor having a second gate electrode. The first gate electrode and the second gate electrode are made of materials causing stresses of different magnitudes. | 2008-10-09 |
20080246103 | MR device with surfactant layer within the free layer - The dR/R ratios of TMR and GMR devices, having a FeCo/NiFe type of free layer, have been significantly increased by inserting a suitable surfactant layer within (as opposed to above or below) the free layer. Our preferred surfactant material has been oxygen but similar-acting materials could be substituted. The concept can be applied to GMR CPP, CIP, and CCP sensor designs. | 2008-10-09 |
20080246104 | High Capacity Low Cost Multi-State Magnetic Memory - One embodiment of the present invention includes multi-state current-switching magnetic memory element including a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states. | 2008-10-09 |
20080246105 | Detector System and Detector Subassembly - A detector system ( | 2008-10-09 |
20080246106 | Integrated circuits having photonic interconnect layers and methods for fabricating same - Various embodiments of the present invention are directed to integrated circuits having photonic interconnect layers and methods for fabricating the integrated circuits. In one embodiment of the present invention, an integrated circuit comprises an electronic device layer and one or more photonic interconnect layers. The electronic device layer includes one or more electronic devices, and the electronic device layer is attached to a surface of an intermediate layer. One of the photonic interconnect layers is attached to an opposing surface of the intermediate layer, and each of the photonic interconnect layers has at least one photonic device in communication with at least one of the electronic devices of the electronic device layer. | 2008-10-09 |
20080246107 | SOLID STATE IMAGING DEVICE AND FABRICATION METHOD OF SOLID STATE IMAGING DEVICE - A solid state imaging device comprises: photoelectric conversion portions on or above a substrate; and color filters on or above the respective photoelectric conversion portions. Each of the photoelectric conversion portions comprises: a lower electrode on or above the substrate; a photoelectric conversion film on or above the lower electrode; and an upper electrode on or above the photoelectric conversion film. The device further comprises: a first inorganic material film that protects each of the photoelectric conversion portions, is formed by a first method and is above the upper electrode and below the color filters; a second inorganic material film that prevents characteristic deterioration of the photoelectric conversion portion caused by the first method, is formed by a second method and is between the upper electrode and the first inorganic material film; and a polymeric material film that enhances a function of the first inorganic material film and is on or above the first inorganic material film. | 2008-10-09 |
20080246108 | Semiconductor device including power switch and power reinforcement cell - A semiconductor device according to one embodiment includes a cell disposition region in which plural basic cells are disposed and a basic power supply wiring. In the cell disposition region are disposed a primitive cell connected to the basic power supply wiring and a high current consumption cell connected to the basic power supply wiring. Furthermore, in the cell disposition region are disposed regularly plural ordinary power switch cells that supply a first current to the primitive cell respectively. The power reinforcement cell including a power switch cell configured so as to flow a predetermined current to the high current consumption cell is disposed near the high current consumption cell. | 2008-10-09 |
20080246109 | SOI substrate, method for manufacturing the same, and semiconductor device - An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side. | 2008-10-09 |
20080246110 | STRUCTURE FOR SPANNING GAP IN BODY-BIAS VOLTAGE ROUTING STRUCTURE - Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire. | 2008-10-09 |
20080246111 | Semiconductor device and method of fabricating the same - A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region beyond the boundary of the active region and the isolation structure, and a protruding part overlying the boundary of the active region and the isolation structure. | 2008-10-09 |
20080246112 | SEMICONDUCTOR STRUCTURE INCLUDING LAMINATED ISOLATION REGION - A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolation trench; (2) a U shaped dielectric liner layer located upon the lower lying dielectric plug layer and partially filling the recess; and (3) an upper lying dielectric plug layer located upon the U shaped dielectric liner layer and completely filling the recess. The isolation region provides for sidewall coverage of the isolation trench, thus eliminating some types of leakage paths. | 2008-10-09 |
20080246113 | SEMICONDUCTOR DEVICE INCLUDING REDISTRIBUTION LINE STRUCTURE AND METHOD OF FABRICATING THE SAME - The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided. | 2008-10-09 |
20080246114 | INTEGRATED PASSIVE DEVICE WITH A HIGH RESISTIVITY SUBSTRATE AND METHOD FOR FORMING THE SAME - According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) ( | 2008-10-09 |
20080246115 | ROBUST ESD CELL - An electric discharge device includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown. | 2008-10-09 |
20080246116 | Symmetrical programmable crossbar structure - A crossbar structure includes a first layer or layers including first p-type regions and first n-type regions, a second layer or layers including second p-type regions and second n-type regions, and a resistance programmable material formed between the first layer(s) and the second layer(s), wherein the first layer(s) and the second layer(s) include first and second intersecting wiring portions forming a crossbar array. | 2008-10-09 |
20080246117 | SURFACE PATTERNED TOPOGRAPHY FEATURE SUITABLE FOR PLANARIZATION - A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions. | 2008-10-09 |
20080246118 | METHOD FOR REALIZING A CONTACT OF AN INTEGRATED WELL IN A SEMICONDUCTOR SUBSTRATE, IN PARTICULAR FOR A BASE TERMINAL OF A BIPOLAR TRANSISTOR, WITH ENHANCEMENT OF THE TRANSISTOR PERFORMANCES - A method realizes a contact of a first well of a first type of dopant integrated in a semiconductor substrate next to a second well of a second type of dopant and forming with it a parasitic diode. The method comprises: formation of the first well; formation of the second well next to the first well; definition of an oxide layer above the first and second wells; and formation of an electric contact layer above the oxide layer in correspondence with the first well for realizing an electric contact with it. The definition step of the oxide layer further comprises a deposition step of this oxide layer above the whole first well and a removal step of at least one portion of the oxide layer in correspondence with a contact area of the first well so that the contact area has a shorter length than a length of the first well. | 2008-10-09 |
20080246119 | LARGE TUNING RANGE JUNCTION VARACTOR - Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias. | 2008-10-09 |
20080246120 | REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SiGe CONTAINING SUBSTRATES - A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided. | 2008-10-09 |
20080246121 | METHOD OF FABRICATING A DEVICE WITH A CONCENTRATION GRADIENT AND THE CORRESPONDING DEVICE - A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate. | 2008-10-09 |
20080246122 | POSITIVE-INTRINSIC-NEGATIVE (PIN)/NEGATIVE-INTRINSIC-POSITIVE (NIP) DIODE - A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity. | 2008-10-09 |
20080246123 | METHODS FOR CONTROLLING CATALYST NANOPARTICLE POSITIONING AND APPARATUS FOR GROWING A NANOWIRE - A method for controlling catalyst nanoparticle positioning includes establishing a mask layer on a post such that a portion of a vertical surface of the post remains exposed. The method further includes establishing a catalyst nanoparticle material on the mask layer and directly adjacent at least a portion of the exposed portion of the vertical surface. | 2008-10-09 |
20080246124 | PLASMA TREATMENT OF INSULATING MATERIAL - A method is disclosed which includes forming an opening in an insulating material, performing a plasma process to introduce nitrogen into a portion of the insulating material to thereby form a nitrogen-containing region at least on an inner surface of the opening, and, after forming the nitrogen-containing region, performing an etching process through the opening. A device is disclosed which includes an insulating material comprising a nitrogen-enhanced region that is proximate an opening that extends through the insulating material and a conductive structure positioned within the opening. | 2008-10-09 |
20080246125 | Semiconductor device and method for manufacturing semiconductor device - The present invention is a semiconductor device characterized by including a substrate, an insulating film consisting of a fluorine added carbon film formed on the substrate, a barrier layer consisting of a silicon nitride film and a film containing silicon, carbon, and nitride formed on the insulating film, and a hard mask layer having a film containing silicon and oxygen formed on the barrier layer, wherein the barrier layer consists of a silicon nitride film and a film containing silicon, carbon, and nitride that are laminated from the bottom in that order, and functions to prevent the fluorine in the fluorine added carbon film from moving to the hard mask layer. | 2008-10-09 |
20080246126 | STACKED AND SHIELDED DIE PACKAGES WITH INTERCONNECTS - According to an example embodiment, a stacked die package | 2008-10-09 |
20080246127 | Arrangement for high frequency application - A source mounted semiconductor device package is described which includes a semiconductor die having first and second opposing major surfaces, first and second major electrodes disposed on respective major surfaces and a control electrode disposed on the second major surface, and a thin metal clip electrically connected to the first major electrode of the die. The thin metal clip has a relatively large surface area, and package resistance which is caused by skin effect phenomenon is reduced thereby in high frequency applications. | 2008-10-09 |
20080246128 | Bent lead transistor - A metal backing tab supports the semiconductor device and has an extending portion extending from an edge. A top leg, a middle leg and a bottom leg are all coupled to the semiconductor device and each has a lead terminal portion extending beyond the boundary of said molded housing. The top leg has a first top leg section that protrudes directly away from the molded housing, a second top leg section that bends toward a direction of a face of the molded housing, and a third top leg section bending downward. The middle leg has a first middle leg section connected to the package that protrudes away from the molded housing, and a middle leg downward section that points downward. The bottom leg has a first bottom leg section that protrudes away from the molded housing face, a second bottom leg section that points away from the molded housing face, and third bottom leg section that points downward. | 2008-10-09 |
20080246129 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The present invention provides a method of manufacturing a semiconductor device in which a plurality of wires are connected to the same electrode on a semiconductor chip, the method making it possible to inhibit an increase in electrode area. First, ball bonding is performed to compressively bond a first ball to an electrode on a semiconductor chip to form a first connection portion. Wedge bonding is then performed on an inner lead. Subsequently, ball bonding is performed to compress a second ball against the first connection portion from immediately above to bond the second ball to form a second connection portion. Wedge bonding is then performed on the inner lead. | 2008-10-09 |
20080246130 | Semiconductor Package Structure Having Enhanced Thermal Dissipation Characteristics - In an exemplary embodiment, a packaged device having enhanced thermal dissipation characteristics includes a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of assembly. The packaged device further includes a conductive clip for coupling the major current carrying electrode to a next level of assembly, and a heat spreader device formed on or integral with the conductive clip. A portion of the heat spreader device may be optionally exposed. | 2008-10-09 |
20080246131 | CHIP PACKAGE STRUCTURE - A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components. | 2008-10-09 |
20080246132 | Semiconductor device and method of manufacturing semiconductor device - This semiconductor device includes a semiconductor chip, and a lead arranged around the semiconductor chip to extend in a direction intersecting with the side surface of the semiconductor chip, and having at least an end farther from the semiconductor chip bonded to a package board, wherein a joint surface to the package board and an end surface orthogonal to the joint surface are formed on the end of the lead farther from the semiconductor chip, and a metal plating layer made of a pure metal is formed on the end surface. | 2008-10-09 |
20080246133 | Flip-chip image sensor packages and methods of fabricating the same - There is provided an imager package including an image sensor die attached to a transparent substrate such that sensitive image sensing components on the sensor die face the transparent substrate. In accordance with an embodiment of the present technique, the imager package may be coupled to an external package via bond wires and other interconnect elements. The sensor die and bond wires may be protected by an encapsulant on which the interconnect elements may be disposed. The bond wires may enable placement of the interconnect elements partially or directly above the sensor die, as opposed to around an outer periphery of the sensor die. There is further provided a method of manufacturing an imager package wherein interconnect elements may be located partially or directly above the sensor die, enabling the manufacture of smaller imager packages than previously envisioned. | 2008-10-09 |
20080246134 | Package-Borne Selective Enablement Stacking - The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the plastic body of one or more leaded packaged ICs bear conductive traces that create circuitry to provide stacking related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs. | 2008-10-09 |
20080246135 | Stacked package module - A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting ends, a plurality of first conductive pads on the first surface, a plurality of conductive vias, and at least one circuit layer, therewith the electrode pads of the first chip electrically connecting to the electro-connecting ends and the first conductive pads directly through the conductive vias and the circuit layer; and a second package structure electrically connecting to the first package structure through a plurality of first solder balls to make a package on package. The stacked package module of this invention has characters of compact size, high performance, high flexibility, and detachability. | 2008-10-09 |
20080246136 | Chips having rear contacts connected by through vias to front contacts - A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias. | 2008-10-09 |
20080246137 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR THE PRODUCTION THEREOF - An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer. | 2008-10-09 |
20080246138 | Packed System of Semiconductor Chips Having a Semiconductor Interposer - A semiconductor system ( | 2008-10-09 |
20080246139 | Polar hybrid grid array package - A grid array package includes a rectangular pattern of electrical contacts around a perimeter of the package. The grid array package also includes a polar pattern of electrical contacts inside of, and concentric with, the rectangular pattern. The grid array package also includes additional electrical contacts arranged between the rectangular pattern and the polar pattern. | 2008-10-09 |
20080246140 | SEMICONDUCTOR DEVICE - A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. A relay post is provided on the dielectric plate. The first band-shaped conductor is connected to the circuit pattern by an interconnection via the relay post. | 2008-10-09 |
20080246141 | SEMICONDUCTOR DEVICE - A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, which is provided with a stepped surface positioned at lower level at a portion of the base plate than a main surface of the base plate. A first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed on the first and the second dielectric plate. An insulator is mounted on the stepped surface of the base plate, which forms a part of the sidewall. Power supply portions are provided including a band-shaped conductor. An interconnection is provided which connects the band-shaped conductor to the circuit pattern. | 2008-10-09 |
20080246142 | Heat dissipation unit and a semiconductor package that has the heat dissipation unit - A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process. | 2008-10-09 |
20080246143 | EMBEDDED METAL HEAT SINK FOR SEMICONDUCTOR - An embedded metal heat sink for a semiconductor device is described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a second surface on opposite sides, wherein at least one semiconductor device is embedded in the first surface of the metal thin layer, and the semiconductor device has two electrodes with different conductivity types. The metal heat sink is deposited on the second surface of the metal thin layer. The bonding pads are deposed on the first surface of the metal thin layer around the semiconductor device and are respectively corresponding to the electrodes, wherein the electrodes are electrically and respectively connected to the corresponding bonding pads by at least two wires, and the bonding pads are electrically connected to an outer circuit. | 2008-10-09 |
20080246144 | METHOD FOR FABRICATING CONTACT PADS - A method for fabricating a contact pad is disclosed. A first metal layer is disposed on a substrate for serving as a probing region. A second metal layer is disposed on the substrate thereafter to serve as an electrical connection region. Preferably, the first metal layer and the second metal layer are composed of different material and are electrically connected. The present invention uses two different metals to form a probing region and an electrical connection region of a contact pad. The probing region is used for providing a contacting surface for a test probe, whereas the electrical connection region is used for establishing an electrical connection in the later bumping or wire bonding process. By providing a contact pad having two different regions, the present invention is able to achieve probing process while prevent the surface of the contact pad from being damaged by the contact of test probes. | 2008-10-09 |
20080246145 | MOBILE BINDING IN AN ELECTRONIC CONNECTION - A method of creating an electrical contact involves locating a barrier material at a location for an electrical connection, providing an electrically conductive bonding metal on the barrier material, the electrically conductive bonding metal having a diffusive mobile component, the volume of barrier material and volume of diffusive mobile component being selected such that the barrier material volume is at least 20% of the volume of the combination of the barrier material volume and diffusive mobile component volume. An electrical connection has an electrically conductive bonding metal between two contacts, a barrier material to at least one side of the electrically conductive bonding metal, and an alloy, located at an interface between the barrier material and the electrically conductive bonding metal. The alloy includes at least some of the barrier material, at least some of the bonding metal, and a mobile material. | 2008-10-09 |
20080246146 | WIRING SUBSTRATE AND WIRING SUBSTRATE MANUFACTURING METHOD - A method of manufacturing a wiring substrate comprises: a first step of forming, on a support plate, an electrode pad made of metal; a second step of etching the support plate in such a manner that the support plate has a shape which includes a projection portion to be contacted with the electrode pad; a third step of forming, on the surface of the support plate, an insulating layer for covering the electrode pad; a fourth step of forming, on the surface of the insulating layer, a conductive pattern to be connected to the electrode pad; and, a fifth step of removing the support plate. | 2008-10-09 |
20080246147 | Novel substrate design for semiconductor device - A novel design and method of fabricating a semiconductor device. In a preferred embodiment, the present invention is a flip chip package including a BT substrate. On the side of the substrate facing the die, thin traces are formed of an enhanced conductive material. Conductive bumps such as eutectic solder balls are then mounted on the traces, and the die mounted to the bumps. The die then packaged and mounted to a printed circuit board using, for example, a ball grid array. | 2008-10-09 |
20080246148 | Electrical Interconnect Structures Having Carbon Nanotubes Therein and Methods of Forming Same - Integrated circuit devices include electrically conductive interconnects containing carbon nanotubes. An electrical interconnect includes a first metal region. A first electrically conductive barrier layer is provided on an upper surface of the first metal region and a second metal region is provided on the first electrically conductive barrier layer. The first electrically conductive barrier layer includes a material that inhibits out-diffusion of the first metal from the first metal region and the second metal region includes a catalytic metal therein. An electrically insulating layer having an opening therein is provided on the second metal region. A plurality of carbon nanotubes are provided as a vertical electrical interconnect in the opening. | 2008-10-09 |
20080246149 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises growing a carbon nano tube (CNT) in a contact hole to form a contact plug, thereby preventing diffusion of a tungsten layer. The method does not require forming a titanium nitride (TiN) film deposited to improve an adhesive strength. The CNT has an excellent electric conductivity and a high mechanical strength to improve characteristics of the device. | 2008-10-09 |
20080246150 | FORMATION OF A MASKING LAYER ON A DIELECTRIC REGION TO FACILITATE FORMATION OF A CAPPING LAYER ON ELECTRICALLY CONDUCTIVE REGIONS SEPARATED BY THE DIELECTRIC REGION - Devices are presented including: a substrate including a dielectric region and a conductive region; a molecular self-assembled layer selectively formed on the dielectric region; and a capping layer formed on the conductive region, where the capping layer is an electrically conductive material such as: an alloy of cobalt and boron material, an alloy of cobalt, tungsten, and phosphorous material, an alloy of nickel, molybdenum, and phosphorous. In some embodiments, devices are presented where the molecular self-assembled layer includes one or more of a polyelectrolyte, a dendrimer, a hyper-branched polymer, a polymer brush, a block co-polymer, and a silane-based material where the silane-based material includes one or more hydrolysable substituents of a general formula R | 2008-10-09 |
20080246151 | INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME - A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner. | 2008-10-09 |
20080246152 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is disposed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and the first substrate is exposed through an opening in the lowermost metal pattern. | 2008-10-09 |
20080246153 | ORGANIC SILICA-BASED FILM, METHOD OF FORMING THE SAME, COMPOSITION FOR FORMING INSULATING FILM FOR SEMICONDUCTOR DEVICE, INTERCONNECT STRUCTURE, AND SEMICONDUCTOR DEVICE - A method of forming an organic silica-based film, including: applying a composition for forming an insulating film for a semiconductor device, which is cured by using heat and ultraviolet radiation, to a substrate to form a coating; heating the coating; and applying heat and ultraviolet radiation to the coating to effect a curing treatment, wherein the composition includes organic silica sol having a carbon content of 11.8 to 16.7 mol %, and an organic solvent, the organic silica sol being a hydrolysis-condensation product produced by hydrolysis and condensation of a silane compound selected from compounds shown by the general formulae (1): R | 2008-10-09 |
20080246154 | Top layers of metal for high performance IC's - The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill. | 2008-10-09 |
20080246155 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to an embodiment includes: a semiconductor substrate having a semiconductor element formed on a surface thereof; an interwiring insulating film formed above the semiconductor substrate; a wiring formed in the interwiring insulating film; a first intervia insulating film formed under the interwiring insulating film; a first via formed in the first intervia insulating film and connected to a lower surface of the wiring; a second intervia insulating film formed on the interwiring insulating film; a second via formed in the second intervia insulating film and connected to an upper surface of the wiring; and a CuSiN film formed in at least one of a position between the interwiring insulating film and the first intervia insulating film, and a position between the interwiring insulating film and the second intervia insulating film. | 2008-10-09 |
20080246156 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads. | 2008-10-09 |
20080246157 | Surface mount devices with minimum lead inductance and methods of manufacturing the same - A device according to various aspects of the present invention generally includes a surface mount device having a top side, a bottom side, a plurality of sidewalls, and a circuit comprising one or more layers. The device includes a first conductive surface covering a portion of one of the sidewalls for providing an input to the circuit, a second conductive surface covering a portion of one of the sidewalls for providing an output from the circuit, and a third conductive surface covering a portion of one of the sidewalls for providing an electrical ground to the circuit. When the surface mount device is mounted to a provided mounting surface, at least one layer of the circuit is orthogonal to the provided mounting surface. | 2008-10-09 |
20080246158 | Method for Realizing a Nanometric Circuit Architecture Between Standard Electronic Components and Semiconductor Device Obtained with Said Method - A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area. | 2008-10-09 |
20080246159 | PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device. | 2008-10-09 |
20080246160 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 2008-10-09 |
20080246161 | Damascene conductive line for contacting an underlying memory element - A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element. | 2008-10-09 |
20080246162 | Stack package, a method of manufacturing the stack package, and a digital device having the stack package - A chip stack package may include a substrate, semiconductor chips, a molding member and a controller. The substrate may have a wiring pattern. The semiconductor chips may be stacked on a first surface of the substrate. Further, the semiconductor chips may be electrically connected to the wiring pattern. The molding member may be formed on the first substrate covering the semiconductor chips. The controller may be arranged on a second surface of the substrate. The controller may be electrically connected to the wiring pattern. The controller may have a selection function for selecting operable semiconductor chip(s) among the semiconductor chips. | 2008-10-09 |
20080246163 | Semiconductor Device - A semiconductor device ( | 2008-10-09 |
20080246164 | Soldering Method, Solder Pellet for Die Bonding, Method for Manufacturing a Solder Pellet for Die Bonding, and Electronic Component - A pellet for use in die bonding of an electronic chip and a substrate in an electronic component generates minimized voids in spite of the pellet being made of a lead-free solder. The pellet forms a colorless transparent protective film comprising Sn-(30-50 at % 0)-(5-15 at % P) or Sn-(10-30 at % In)-(40-60 at % O)-(5-15 at % P) when heated for soldering, has a thickness of 0.05-1 mm, and has generally the same shape as the semiconductor chip to be bonded to the substrate. | 2008-10-09 |
20080246165 | Novel interconnect for chip level power distribution - A semiconductor device ( | 2008-10-09 |
20080246166 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device that improves adhesion between a resin and a die pad and prevents cracking of the resin includes: a semiconductor chip; a die pad on which the semiconductor chip is mounted; a bonding agent for bonding the semiconductor chip to the die pad; a plurality of inner leads provided at the outer periphery of the die pad; outer leads extending from the inner leads; bonding wires connecting the inner leads to the semiconductor chip mounted on the die pad; and a resin for sealing the inner leads, the die pad, the semiconductor chip, the bonding agent and the bonding wires. The bonding agent is further disposed in all or part of a margin of the die pad at a peripheral portion where the semiconductor chip is mounted, and a plurality of dimples are formed in the surface of the bonding agent in the die pad margin. | 2008-10-09 |
20080246167 | Layout Structure for Chip Coupling - A layout structure disposed on the substrate of the liquid crystal display (LCD) for chip coupling is provided. The first and second orientations that are substantially perpendicular to the first orientation can be defined on the substrate. The layout structure includes a plurality of lines, which extend along the second orientation, and a plurality of conductive pads that are respectively disposed on the lines. The conductive pads are distributed along the first orientation and staggered along the second orientation. Each line can shift away from the adjacent conductive pad on the first orientation. Thus, the LCD chip has a better conductivity and a thinner dimension under the precision of the conventional machines. | 2008-10-09 |
20080246168 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction. | 2008-10-09 |
20080246169 | Filtering structure of a humidifier - A humidifier includes a water storage tank, and an air passage and a filtering device in the water storage tank; the filtering device has a hollow holding portion therein, and magnetic members held in the hollow holding portion, which will make metallic substances adhere to the hollow holding portion when water is flowing through the filtering device; the filtering device has an annular wall between the hollow holding portion and an outer wall thereof; the filtering device has a flow passage, which exists next to inner and outer sides of the annular wall, and which is stuffed with ion exchange resin for filtering out minerals; the filtering device having a water inlet on an outward edge of a lower end thereof, and a water outlet on an inward edge of the lower end; therefore, unfiltered water is prevented from flowing to the heater through the air passage. | 2008-10-09 |
20080246170 | CARBURETOR START-STOP MECHANISM - The present invention relates to a carburetor of an internal combustion engine having a manually activated start position. The carburetor comprises at least a choke valve and a throttle valve both located in the carburetor's main air passage which are able to move between an open and a closed position, each valve having at least one respective lever that cooperates during the manual activation to give at least one start position of the choke and throttle valves. The carburetor further usually comprises at least one thermally responsive member arranged to affect the start position. Further a handle is arranged to provide a two stage draw—lift motion to attain the start position. | 2008-10-09 |
20080246171 | CHILLED INJECTION MOLDING DURING OPHTHALMIC LENS MANUFACTURE - The present invention includes molds for forming ophthalmic lenses, such as contact lens. In particular, the present invention relates to apparatus, molds and methods for fashioning mold parts used to fashion an ophthalmic lens which includes cooling a mold structure used to fashion a mold part prior to depositing a molten material into the mold structure. | 2008-10-09 |
20080246172 | FINE CHANNEL DEVICE, FINE PARTICLE PRODUCING METHOD AND SOLVENT EXTRACTION METHOD - A fine channel device capable of producing fine particles in an industrial scale, hardening the fine particles immediately after the production and recovering the fine particles from a medium without collapsing the shape of the produced fine particles, a fine particle producing method using the fine channel device and a solvent extraction method using the fine channel, are presented. The fine channel device comprises a fine channel provided with an inlet port and an inlet channel which feed a dispersion phase, an inlet port and an inlet channel which feed a continuous phase, and an outlet channel and an outlet port which discharge fine particles produced by the dispersion phase and the continuous phase, wherein the inlet channel for feeding the dispersion phase and the inlet channel for feeding the continuous phase are joined at an arbitrary angle, and the two inlet channels are connected to the outlet channel at the arbitrary angle. | 2008-10-09 |
20080246173 | METHOD OF SEPARATING A POLY(ARYLENE ETHER) COMPOSITION FROM A SOLVENT, AND POLY(ARYLENE ETHER) COMPOSITION PREPARED THEREBY - A method of separating a poly(arylene ether) from a solvent includes treating a poly(arylene ether)-containing solution with a devolatilizing extruder to form an extruded composition, and cooling the extruded composition with a cooling device that does not immerse the extruded composition in water. The composition may be used to isolate a poly(arylene ether) from the solvent-containing reaction mixture in which it is prepared, or to remove solvent from a multi-component poly(arylene ether)-containing thermoplastic composition. | 2008-10-09 |
20080246174 | Permeable Cements - A permeable cement composition including an aqueous slurry of a hydraulic cement which is based upon a water-immiscible dispersed fluid phase and a hollow particulate material. The hollow particulate material breaks down in the presence of the cement so as to leave voids which together with the dispersed phase create a permeable structure in the cement. | 2008-10-09 |
20080246175 | Composite Barrel Sections for Aircraft Fuselages and Other Structures, and Methods for Systems for Manufacturing Such Barrel Sections - Composite sections for aircraft fuselages and methods and systems for manufacturing such sections are disclosed herein. A composite section configured in accordance with one embodiment of the invention includes a skin and at least first and second stiffeners. The skin can include a plurality of unidirectional fibers forming a continuous surface extending 360 degrees about an axis. The first stiffener can include a first flange portion bonded to an interior surface of the skin and a first raised portion projecting inwardly and away from the interior surface of the skin. The second stiffener can include a second flange portion bonded to the interior surface of the skin and a second raised portion projecting inwardly and away from the interior surface of the skin. A method for manufacturing a section of a fuselage in accordance with one embodiment of the invention includes positioning a plurality of uncured stiffeners on a mandrel assembly. The method can further include applying a plurality of fiber tows around the plurality of uncured stiffeners on the mandrel assembly. | 2008-10-09 |
20080246176 | PRODUCTION METHOD OF PREFABRICATED ELEMENTS MADE FROM POROUS BUILDING MATERIALS, ESPECIALLY FROM COMPOSITE MATERIALS - The invention is a method of manufacturing construction precast elements made of porous construction materials, especially composite materials with open structure of pores, cured under normal temperatures, such as concretes, where these construction materials are formed of a mixture of aggregate and bond. Unsorted plastic waste is added into the mixture of aggregate and bond. Such unsorted plastic waste is freed from dirt, crushed and shaped into granules. These granules of plastic waste are mixed into the mixture of construction material before curing. When cured, the resulting precast element is heated to a temperature causing at least part of the granules to melt into a fully liquid state. The resulting composite element is allowed to cool. The plastic waste becomes an additional bond in the precast elements. | 2008-10-09 |
20080246177 | Production of Moulded Bodies From Lignocellulose-Based Fine Particle Materials - The present invention relates to a process for the production of moldings from finely divided materials based on lignocellulose, and the moldings obtainable thereby. The invention also relates to the use of aqueous compositions which comprise at least one crosslinkable urea compound for the preparation of finely divided materials based on lignocellulose and treated with this composition for the production of moldings. | 2008-10-09 |
20080246178 | Method For Dividing Ceramic Cylindrical Body and Shape of Notched Portions Thereof - There are provided a method for dividing a ceramic cylindrical body, involving forming first and second notched portions in an inner periphery surface of the ceramic cylindrical body at positions confronting each other in the diametrical direction and subsequently applying a compressive load in the diametrical direction to divide the cylindrical body along the first and second notches, thereby making it possible to afford divided surfaces having such a concave and a convex as prevent axial displacement when re-joining divided sections, as well as a shape of the notched portions. Bisected cylindrical body portions can be joined together closely without axial displacement of the joined cylindrical body. | 2008-10-09 |
20080246179 | Composition and Method of Using the Same to Make a Simulated Rock Climbing Wall - A composition and method for making a simulated rock climbing, including the steps of making a mold for a basic shape for a rock climbing wall casting, filling the mold with cellular concrete; allowing the concrete to cure partially and inverting it in a bed of sand, removing the mold to expose the simulated rock climbing wall casting; sandblasting the simulated rock climbing wall casting into its general finished shape; and using concentrated sandblasting to form integral recesses and protrusions comprising various hand holds. | 2008-10-09 |
20080246180 | Methods for Manufacturing Three-Dimensional Devices and Devices Created Thereby - In certain exemplary embodiments of the present invention, three-dimensional micro-mechanical devices and/or micro-structures can be made using a production casting process. As part of this process, an intermediate mold can be made from or derived from a precision stack lamination and used to fabricate the devices and/or structures. Further, the micro-devices and/or micro-structures can be fabricated on planar or nonplanar surfaces through use of a series of production casting processes and intermediate molds. The use of precision stack lamination can allow the fabrication of high aspect ratio structures. Moreover, via certain molding and/or casting materials, molds having cavities with protruding undercuts also can be fabricated. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. This abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b). | 2008-10-09 |
20080246181 | Polymer Compositions, Method of Manufacture, and Articles Formed Therefrom - A composition comprises, based on the total weight of the composition: from 10 to 80 wt. % of a modified polybutylene terephthalate copolymer that (1) is derived from polyethylene terephthalate component selected from the group consisting of polyethylene terephthalate and polyethylene terephthalate copolymers and (2) has at least one residue derived from the polyethylene terephthalate component; from 10 to 80 wt. % of a polycarbonate; from 0 to 20 wt. % of an impact modifier; from 1 to less than 25 wt. % of a reinforcing filler; from 0.1 to less than 2.5 wt. % of a fibrillated fluoropolymer; from 0 to 5 wt. % of an additive selected from the group consisting of antioxidants, mold release agents, colorants, quenchers, stabilizers, and combinations thereof. The composition has a heat deflection temperature of at least 110° C., measured in accordance with to ASTM D648 on 3.2 mm thick molded bars at 0.455 MPa. | 2008-10-09 |
20080246182 | HIGH FLOW FLUID FILTRATION SYSTEMS AND METHODS FOR MANUFACTURING SAME - The present disclosure is directed to systems and methods of manufacturing filter cartridges are disclosed, the system including a tube of laminated and seamed filter media, a media unwind mechanism, a mandrel having a starting point operatively positioned proximate the media unwind mechanism, structure, operatively positioned proximate the mandrel, for feeding the tube of laminated and seamed filter media into the starting point of the mandrel, structure, operatively positioned in the mandrel, for pressurizing the tube of laminated and seamed filter media with a gas, structure, operatively positioned in the mandrel, for expanding the tube of laminated and seamed filter media into a substantially cylindrical shape as the tube of laminated and seamed filter media passes over the mandrel, a pleater mechanism, operatively positioned proximate the mandrel, a blade mechanism, operatively associated with the pleater mechanism, for alternately engaging the tube of laminated and seamed filter media with the blade mechanism, structure, operatively positioned proximate the pleater mechanism, for moving newly formed pleated filter media downstream; and structure for compressing the tube of laminated and seamed filter media radially toward the mandrel. Methods of manufacturing filter cartridges are also disclosed. | 2008-10-09 |
20080246183 | Method of manufacturing a golf ball - The invention provides a method of manufacturing a golf ball composed at least in part of a spherical elastomeric body. The method includes the steps of extruding a bar of an unvulcanized rubber compound for obtaining the elastomeric body, cutting the extruded bar into slugs of a given length, and coating the slug with a saturated or unsaturated carboxylic acid metal salt in powder form having a melting point at or below a vulcanizing temperature. This method prevents the slugs from clumping together and improves mold releasability. | 2008-10-09 |
20080246184 | Process and Mould For Moulding Structured Sheets - Process for moulding sheets possessing, locally, a three-dimensional projecting or recessed structure ( | 2008-10-09 |
20080246185 | COMPOSITION OF LED FRAME BODY AND MANUFACTURING METHOD THEREOF - A lamp body is an enclosing structure that encloses a blue light-emitting crystal to form a LED structure. In a method of manufacturing frame body of the LED, resin, titanium, and fluorescent powder are mixed uniformly to constitute a composition of frame body, then the composing materials being placed into a mould for processing a thermally pressing procedure to thus form a frame body. By the blue light emitted from the blue light-emitting crystal, the fluorescent powder of the frame body may be excited to emit uniform yellow light, which may be further mixed with the blue light to become white light. | 2008-10-09 |
20080246186 | COMPOSITION AND METHOD FOR MAKING POLYARYLENE ETHER COPOLYMERS - A method for making a polyarylene ether copolymer including mixing a polyarylene ether, a hydroxyaromatic terminated siloxane reagent and an oxidant, and melt compounding the mixture. A polyarylene ether copolymer including a polyarylene ether, a hydroxyaromatic terminated siloxane reagent, an oxidant and a filler is also presented. | 2008-10-09 |
20080246187 | Thermoplastic polyurethane lenses with a specified weight percentage of urethane repeating units - A method of forming thermoplastic polyurethane (TPU) into an optical lens. Suitable TPUs contain urethane (—NHCOO—) repeating units that are present in at least 23% by weight. This range of urethane weights is an indicator of a flexural modulus above 1,400 MPa. The TPUs have refractive indices above 1.54 and Abbe numbers above 27. They have glass transition temperatures above about 100 degrees C. The selected TPU can be injection molded to form ophthalmic lenses, that are well suited for use in rimless spectacles. The lenses are highly solvent resistant, while at the same time being readily tintable. The lenses made according the invention meet FDA 21 CFR 801.41 Impact Requirement, and ANSI Z87.1 high velocity impact (HVI) standard. | 2008-10-09 |
20080246188 | Method and apparatus for prediction of amount of deformation due to shrinkage of molded article - The method of predicting the amount of deformation due to shrinkage of a molded article of the present invention finds a support point P of the bending moment M from a distribution of shrinkage rates of a molding material forming a molded article | 2008-10-09 |
20080246189 | Cellulose Resin Film, Process for Producing Cellulose Resin Film, Antireflection Film, Polarizing Plate, and Liquid Crystal Display - A cellulosic resin film which is wide and, despite this, is extremely reduced in breakage during a stretching step; a process for producing the film; and an antireflection film, a polarizer, and a liquid-crystal display each comprising or employing the film. The process for cellulosic resin film production comprises casting a liquid cellulosic resin on a support to form a web, peeling the web from the support, subsequently drying the web in a first edge gripping step ( | 2008-10-09 |
20080246190 | FLEXIBLE MOLD AND METHOD OF MANUFACTURING MICROSTRUCTURE USING THE SAME - To provide a flexible mold useful for manufacturing a PDP rib having a lattice pattern and other microstructures, and capable of highly precisely manufacturing the microstructures without involving defects such as occurrence of bubbles and pattern deformation. | 2008-10-09 |
20080246191 | Polyester Compositions, Method Of Manufacture, And Uses Thereof - A polyester composition comprising a reaction product of 50 to 95 wt. % of a polyester having a number average molecular weight of greater than or equal to 42,450 g/mol, wherein the polyester is of the formula | 2008-10-09 |
20080246192 | Polyester Compositions, Method Of Manufacture, And Uses Thereof - A polyester composition comprising a reaction product of: 65-94.5 weight percent of a polyester having a weight average molecular weight of greater than or equal to 70,000 g/mol, of the formula | 2008-10-09 |
20080246193 | Bottles Prepared from Compositions of Polypropylene and Inorganic Nucleating Agents - This invention discloses bottles and pre-forms prepared by injection-stretch-blow-moulding (ISBM) from a composition comprising polypropylene and an inorganic non-sorbitol nucleating agent. | 2008-10-09 |
20080246194 | METHOD OF PRODUCING A CERAMIC SINTERED BODY - A method of producing a laminated body having a ceramic porous body having a thickness of 300 μm or larger and a ceramic dense body having a thickness of 25 μm or smaller. A green body for the porous body and a green body for the dense body are laminated to obtain a laminate, which is then subjected to pressure molding by cold isostatic pressing to obtain a pressure molded body. The pressure molded body is sintered to obtain a laminated sintered body. By reducing the leakage rate of helium gas of the laminated sintered body to 10 | 2008-10-09 |
20080246195 | Method and apparatus for testing the integrity of a shroud seal on a ladle for a continuous casting installation - Molten steel is conducted by a tubular shroud interconnecting a slide gate at a bottom tap hole of a ladle with the molten steel in an underlying tundish of a continuous caster. The flow path is confirmed to be isolated from contaminants in atmospheric air by applying a source of partial vacuum to the internal cavity of tubular shroud to allow prevailing atmospheric pressure acting on molten steel in a tundish to push molten steel upwardly in the internal cavity of the tubular shroud. A measure of the partial vacuum in the cavity of the shroud is used to assess the integrity of the gas tight seal. Before and after the integrity of the gas tight seal is determined, a three way valve is used to apply an inert gas to the volume in the cavity of the shroud. | 2008-10-09 |
20080246196 | Container | 2008-10-09 |
20080246197 | Slow Acting Pocketed Spring Core and Method of Manufacturing Same - Spring cushions ( | 2008-10-09 |
20080246198 | GAS SPRING ASSEMBLY AND METHOD - A gas spring assembly includes a first end member, a piston assembly and a flexible wall extending therebetween. The piston assembly includes a piston body receiving a portion of the flexible wall and a retainment ring for retaining the flexible wall on the piston body. A method of assembly is also included. | 2008-10-09 |