41st week of 2009 patent applcation highlights part 25 |
Patent application number | Title | Published |
20090251933 | METHOD FOR CONTROLLING INVERTERS - The invention relates to a method for controlling the voltage and power of several HF inverters ( | 2009-10-08 |
20090251934 | Apparatus, System and Method for Cascaded Power Conversion - An apparatus method and system are provided for power conversion, to supply power to a nonlinear load such as a plurality of light emitting diodes. An exemplary apparatus comprises a first power converter stage, a second power converter stage, a plurality of sensors such as first and second sensors, and a controller. The first power converter stage includes a power switch and a first inductor having a first inductance. The first and second sensors are both coupled to a common reference node, with the first sensor adapted to sense a first parameter of the first power converter stage, and the second sensor adapted to sense the output current level. The second power converter stage includes a second inductor having a second inductance, and is coupleable to provide an output current to the nonlinear load such as LEDs. The controller is coupled to the power switch, the first sensor and the second sensor, and the controller is adapted to turn the power switch into an on state for an on-time duration substantially proportional to a ratio of the second inductance to the first inductance. | 2009-10-08 |
20090251935 | Multi-Pulse Rectifier for AC Drive Systems having Separate DC Bus Per Output Phase and Multiple Isolation Transformers - An 18n-pulse rectifier for AC drive systems having a separate DC bus for each output phase is provided, where n=any positive integer. The rectifier uses three separate phase rectifiers, one for each output phase of a transformer, each comprised of 2n six-pulse diode bridges connected in series or parallel. Each phase rectifier may be supplied with n unique sets of phase inputs from a transformer secondary winding. In some configurations, the n sets of inputs provided to each rectifier are separated by 60/n degrees of phase (when n is greater than 1), while the corresponding inputs to neighboring rectifiers are separated by 20/n degrees of phase. In a 36-pulse example, the phase offsets for the inputs provided to the rectifiers may be −25° and +5° from the transformer primary winding (for the first rectifier), −15° and +15° from the primary winding (for the second rectifier) and −5° and +25° from the primary winding (for the third rectifier). Each set of inputs may include three lines of in-phase current, and may be coupled to one of the six-pulse diode bridges. In some configurations, two identically-wound transformers may be used to supply output voltages to the rectifiers. The transformers may each supply the same phase offsets to each rectifier, in accordance with the methodology above, which may support higher-capacity applications. | 2009-10-08 |
20090251936 | DISTRIBUTED MULTIPHASE CONVERTERS - A direct current to pulse amplitude modulated (“PAM”) current converter, denominated a “PAMCC”, is connected to an individual source of direct current. The PAMCC receives direct current and provides pulse amplitude modulated current at its output. The pulses are produced at a high frequency relative to the signal modulated on a sequence of pulses. The signal modulated onto a sequence of pulses may represent portions of a lower frequency sine wave or other lower frequency waveform, including DC. When the PAMCC's output is connected in parallel with the outputs of similar PAMCCs an array of PAMCCs is formed, wherein the output pulses of the PAMCCs are out of phase with respect to each other. An array of PAMCCs constructed in accordance with the present invention form a distributed multiphase inverter whose combined output is the demodulated sum of the current pulse amplitude modulated by each PAMCC. | 2009-10-08 |
20090251937 | CIRCUIT ARRANGEMENT HAVING A DUAL COIL FOR CONVERTING A DIRECT VOLTAGE INTO AN ALTERNATING VOLTAGE OR AN ALTERNATING CURRENT - The invention proposes a circuit arrangement for converting a DC voltage present at DC voltage terminals into an alternating current, which is supplied via AC voltage terminals, or an AC voltage, which circuit arrangement has a first series circuit, which is connected to the DC voltage terminals, comprises a first electronic switch (S | 2009-10-08 |
20090251938 | Inverter Circuit and Method for Operating the Inverter Circuit - An inverter circuit having a primary circuit with a first choke for periodically connecting a primary winding to a DC voltage present at an input of the inverter circuit, a secondary circuit with a secondary winding, the secondary winding arranged in series with a first capacitor and connected via a full bridge consisting of four switching elements to a AC voltage present at an output of the inverter circuit via a second choke, and a transformer, wherein the primary circuit and the secondary circuit are electrically isolated by the transformer. | 2009-10-08 |
20090251939 | PRIORITY ENCODER - A priority encoder encodes an (N+1)-bit thermometer code, where N indicates a natural number. A plurality of selectors are arranged in a matrix of M rows and (N+1) columns, where M indicates a natural number, and select one of signals at first and second input terminals (1,0) in accordance with the value of a signal input to the control terminal. An output signal from the selector in the i-th row and (j−1)th column is input to the first input terminal of the selector in the i-th row and j-th column (1≦i≦M, 2≦j≦N+1), a predetermined value of 1 or 0 is input to the second input terminal of the selector in the i-th row and j-th column, and the j-th significant bit of the thermometer code is input to the control terminal of the selector in the i-th row and j-th column. | 2009-10-08 |
20090251940 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE USING A VARIABLE RESISTANCE FILM AND METHOD OF MANUFACTURING THE SAME - A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes. | 2009-10-08 |
20090251941 | Semiconductor Device - A semiconductor device is provided, which includes a transistor, a memory element, a first control circuit and a second control circuit. A gate of the transistor is electrically connected to the first control circuit through a first word line, one of a source and a drain of the transistor is electrically connected to the second control circuit through a bit line, the other of the source and the drain of the transistor is electrically connected to a first terminal of the memory element, and a second terminal of the memory element is electrically connected to the first control circuit through a second word line. | 2009-10-08 |
20090251942 | METHOD OF PROGRAMMING A MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE AND INTEGRATED CIRCUIT INCORPORATING SUCH A MEMORY - A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device. | 2009-10-08 |
20090251943 | TEST CIRCUIT FOR AN UNPROGRAMMED OTP MEMORY ARRAY - Circuits for testing unprogrammed OTP memories to ensure that wordline and bitline connections, column decoders, wordline drivers, correctness of decoding, sensing and multiplexing operate properly. The OTP testing system includes one or both of column test circuitry and row test circuitry. The column test circuitry charges all the bitlines to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a test wordline. The bitline voltages can be sensed, thereby allowing for testing of the column decoding and sense amplifier circuits. The row test circuitry charges a test bitline to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a wordline of the OTP memory array. This test bitline voltage can be sensed, thereby allowing for testing of the row decoding and driver circuits. | 2009-10-08 |
20090251944 | MEMORY CELL HAVING IMPROVED MECHANICAL STABILITY - Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion and the base portion having respective outer surfaces and the pillar portion having a width less than that of the base portion. A memory element is on a top surface of the pillar portion of the bottom electrode, and a top electrode is on the memory element. A dielectric spacer contacts the outer surface of the pillar portion, the outer surface of the base portion of the bottom electrode self-aligned with an outer surface of the dielectric spacer. | 2009-10-08 |
20090251945 | SYSTEM AND METHOD OF OPERATION FOR RESISTIVE CHANGE MEMORY - The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes a data storage element which includes a variable resistance and an electrode, and a controller which selects a first mode that stores data by the resistance value of the variable resistance and a second mode that stores data by the amount of electrical charges stored in the electrode. By selectively using the data storage element in the first mode and the second mode, a plurality of storage modes can be implemented with a single data storage element. Thus, miniaturization and cost reduction of the semiconductor device can be achieved. | 2009-10-08 |
20090251946 | DATA CELLS WITH DRIVERS AND METHODS OF MAKING AND OPERATING THE SAME - Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate. | 2009-10-08 |
20090251947 | Semiconductor device having single-ended sensing amplifier - A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage. | 2009-10-08 |
20090251948 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes. | 2009-10-08 |
20090251949 | Array Structural Design of Magnetoresistive Random Access Memory (MRAM) Bit Cells - Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line. | 2009-10-08 |
20090251950 | Integrated Circuit, Memory Cell Arrangement, Thermal Select Magneto-Resistive Memory Cell, Method of Operating a Thermal Select Magneto-Resistive Memory Cell, and Method of Manufacturing a Thermal Select Magneto-Resistive Memory Cell - According to one embodiment of the present invention, an integrated circuit includes a thermal select magneto-resistive memory cell. The memory cell includes a stack of layers including a storage memory layer. The memory cell also includes a heating element which covers at least a part of the sidewalls of the stack of layers and which is electrically coupled to the stack of layers such that a heating current routed between the top end and the bottom end of the stack of layers is at least partly routed through the heating element. | 2009-10-08 |
20090251951 | MAGNETORESISTIVE ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetoresistive element includes a foundation layer, a first magnetic layer on the foundation layer, a tunnel barrier layer on the first magnetic layer, and a second magnetic layer on the tunnel barrier layer. The first magnetic layer is made of a ferromagnetic metal containing one or more elements selected from a first group consisting of Co, Fe, and Ni, and one or more elements selected from a second group consisting of Cu, Ag, Au, Pd, Pt, Ru, Rh, Ir, and Os. The foundation layer is made of a metal containing one or more elements selected from a third group consisting of Al, Ni, Co, Fe, Mn, Cr, and V. | 2009-10-08 |
20090251952 | STATE MACHINE SENSING OF MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating a first sensing reference according to a first output of a state machine. The method includes bifurcating a range of possible programmed levels to which a memory cell can be programmed with the first sensing reference. The method also includes generating a second sensing reference according to a second output of the state machine. The method further includes determining a programmed level of the memory cell with the second generated sensing reference. | 2009-10-08 |
20090251953 | Variable resistance memory device - A variable resistance memory device includes a variable resistance memory cell array including a plurality of variable resistance memory cells; a plurality of global word lines configured to drive the variable resistance memory cell array; and a plurality of local word line decoders. Each of the plurality of local word line decoders includes a first transistor having a gate connected to the global word line. A voltage greater than an operation voltage of one or more of the plurality of local word line decoders is applied to a selected one of the plurality of global word lines. | 2009-10-08 |
20090251954 | VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM - Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit. | 2009-10-08 |
20090251955 | MRAM AND DATA READ/WRITE METHOD FOR MRAM - An MRAM according to the present invention is provided with a magnetic recording layer being a ferromagnetic layer and a pinned layer connected to the magnetic recording layer through a nonmagnetic layer. The magnetic recording layer includes a magnetization switching region, a first magnetization fixed region and a second magnetization fixed region. The magnetization switching region has reversible magnetization and overlaps with the pinned layer. The first magnetization fixed region and the second magnetization fixed region are both connected to the same one end of the magnetization switching region. Also, the first magnetization fixed region and the second magnetization fixed region respectively have first fixed magnetization and second fixed magnetization whose directions are fixed. One of the first fixed magnetization and the second fixed magnetization is fixed in a direction toward the above-mentioned one end, and the other is fixed in a direction away from the above-mentioned one end. | 2009-10-08 |
20090251956 | Magnetic random access memory devices, methods of driving the same and data writing and reading methods for the same - A magnetic memory device includes a lower structure or an antiferromagnetic layer, a pinned layer, an information storage layer, and a free layer formed on the lower structure or the antiferromagnetic layer. In a method of operating a magnetic memory device, information from the storage information layer is read or stored after setting the magnetization of the free layer in a first magnetization direction. The information is stored when the first magnetization direction is opposite to a magnetization direction of the pinned layer, but is read when the first magnetization direction is the same as the magnetization direction of the pinned layer. | 2009-10-08 |
20090251957 | SYSTEM AND METHOD FOR WRITING DATA TO MAGNETORESISTIVE RANDOM ACCESS MEMORY CELLS - Magnetic random access memory (MRAM) cell with a thermally assisted switching writing procedure and methods for manufacturing and using same. The MRAM cell includes a magnetic tunnel junction that has at least a first magnetic layer, a second magnetic layer, and an insulating layer disposed between the first and a second magnetic layers. The MRAM cell further includes a select transistor and a current line electrically connected to the junction. The current line advantageously can support a plurality of MRAM operational functions. The current line can fulfill a first function for passing a first portion of current for heating the junction and a second function for passing a second portion of current in order to switch the magnetization of the first magnetic layer. | 2009-10-08 |
20090251958 | Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same - An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line. Sensing circuitry responsively couples the current regulation circuitry to the bit line during the portion of the read operation. | 2009-10-08 |
20090251959 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A memory includes: memory cells including floating bodies, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source and drain layer and lower than the other of the potentials of the source and drain layer so that electric charges flow in the body region, and a potential of the second gate electrode is set to be higher as an absolute value than those of potentials of the source layer, drain layer, and first gate electrode so that electric charges flow from the body region, and in the data holding state, the memory cell is kept in a stationary state that a first amount of the electric charges flowing in the body region per unit time is substantially the same as a second amount of the electric charges flowing from the body region per unit time. | 2009-10-08 |
20090251960 | HIGH TEMPERATURE MEMORY DEVICE - Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells disposed upon it. In other embodiments, a high temperature nonvolatile integrated device comprises a silicon on insulator substrate or a large bandgap semiconductor substrate having multiple ferroelectric or magnetic memory cells disposed on it. In yet other embodiments, a high temperature nonvolatile integrated device comprises a sapphire, silicon on insulator, or a large bandgap substrate having programmable read only memory (PROM) cells or electrically erasable PROM (EEPROM) cells disposed on it. | 2009-10-08 |
20090251961 | FLASH MEMORY DEVICE AND VOLTAGE GENERATING CIRCUIT FOR THE SAME - Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate at least one reference voltage to be supplied to the high voltage generating circuit. The reference voltage generating circuit includes a first reference voltage generator configured to generate a first reference voltage in response to a supply voltage, and a second reference voltage generator configured to generate a second reference voltage in response to the first reference voltage. The at least one reference voltage supplied to the high voltage generating circuit includes the second reference voltage. | 2009-10-08 |
20090251962 | Three-Dimensional Memory Device and Driving Method Thereof - A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage. | 2009-10-08 |
20090251963 | Non-volatile memory device and method of manufacturing the same - A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers. | 2009-10-08 |
20090251964 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to the present invention is a NAND-type flash memory which is electrically capable of programming/erasing. The nonvolatile semiconductor memory device has at least 3 or more memory cell columns in which a plurality of memory cells are connected in series, and these memory cell columns are adjacent to each other via a shallow trench isolation. And, a programming operation is performed individually to each of these memory cell columns. In this manner, a programming-prevent voltage is surely provided at on at least one side of both surfaces of the semiconductor substrate which are adjacent via a shallow trench isolation to the surface of the semiconductor substrate under the programming-prevented memory cell. Therefore, a miss-programming to an unselected memory cell can be largely reduced. | 2009-10-08 |
20090251965 | NONVOLATILE MEMORY DEVICE INCLUDING CIRCUIT FORMED OF THIN FILM TRANSISTORS - A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier. | 2009-10-08 |
20090251966 | SEMICONDUCTOR MEMORY HAVING VOLATILE AND MULTI-BIT, NON-VOLATILE FUNCTIONALITY AND METHODS OF OPERATING - A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer. | 2009-10-08 |
20090251967 | NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL - A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well. | 2009-10-08 |
20090251968 | Integrated circuit having a base structure and a nanostructure - In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure. | 2009-10-08 |
20090251969 | ANALOG READ AND WRITE PATHS IN A SOLID STATE MEMORY DEVICE - A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface is comprised of a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage. | 2009-10-08 |
20090251970 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - A semiconductor device in accordance with one embodiment of the invention can include a first data storage region including a non-volatile main data storage region. Additionally, the semiconductor device can include a second data storage region including a non-volatile reference region wherein an erasing operation and a writing operation are performed on both the first data storage region and the second data storage region. Moreover, the semiconductor device can also include a control unit coupled to the first and second data storage regions which determines a stress condition corresponding to the first data storage region based on a stress information related to the second data storage region. | 2009-10-08 |
20090251971 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - According to an aspect of the invention, a non-volatile semiconductor storage device includes: a memory cell array including memory strings, each of the memory strings having: a first end; a second end; and a plurality of memory cells connected in series between the first end and the second end, the memory cells being categorized into memory cell groups; a first end that is one end of the memory string; and a second end that is the other end of the memory string; first selection transistors connected to the respective first ends of the memory strings; a plurality of second selection transistors connected to the respective second ends of the memory strings; bit lines connected to the respective second selection transistors; word lines connected to the memory cells; and a control circuit configured to apply different control voltages to the respective word lines. | 2009-10-08 |
20090251972 | NONVOLATILE MEMORY ARRAYS WITH CHARGE TRAPPING DIELECTRIC AND WITH NON-DIELECTRIC NANODOTS - Charge-trapping dielectric ( | 2009-10-08 |
20090251973 | Trench monos memory cell and array - The MONOS vertical memory cell of the present invention allow miniaturization of the memory cell area. The two embodiments of split gate and single gate provide for efficient program and erase modes as well as preventing read disturb in the read mode. | 2009-10-08 |
20090251974 | MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FOR SAME - A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described. | 2009-10-08 |
20090251975 | Circuit and Method for a Sense Amplifier with Instantaneous Pull Up/Pull Down Sensing - A circuit and method for a sense amplifier for sensing the charge stored when a select signal couples a memory cell to the sense amplifier. A pull up voltage and a pull down voltage are instantaneously supplied to the sense amplifier to sense the small signal differential input on the complementary bit lines and to simultaneously restore the value stored in the memory cell. A differential output signal generator circuit is provided to instantaneously supply the pull up and pull down voltages. In another preferred embodiment the signal generator provides the pull up and pull down voltages at a first level and subsequently increases the pull up voltage to a voltage greater than the positive supply voltage and decreases the pull down voltage. A method of sensing is disclosed wherein the sense and restore actions are performed instantaneously to provide memory cell sensing with greater tolerance of device mismatches. | 2009-10-08 |
20090251976 | Method and apparatus for DQS postamble detection and drift compensation in a double data rate (DDR) physical interface - Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control logic, a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of the double data rate type memory, a gate coupled to the second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along the data strobe line in response to a data strobe masking gating signal and a data strobe masking gating signal modifier applying to the expected data receipt duration indicating signal a variable time delay such as to center the expected data receipt duration indicating signal about the midpoint of the duration of the data transmission. | 2009-10-08 |
20090251977 | DEVICE HAVING MALFUNCTION PREVENTING CIRCUIT - A fixing device fixes a toner image on a recording medium. The fixing device includes a heat source that converts electric power into heat and a fixing member that gives the heat generated by the heat source to the recording medium on which the toner image is formed. The fixing device includes a safety circuit that forcibly interrupts voltage supplied from a power supply to the heat source if the temperature in the device detected by a temperature detection sensor exceeds reference temperature. The fixing device has a malfunction preventing circuit that stops the operation of the safety circuit in order to prevent the voltage supplied to the heat source from being forcibly interrupted when the voltage of the power supply supplied to the heat source is unstable. | 2009-10-08 |
20090251978 | INTEGRATION OF LBIST INTO ARRAY BISR FLOW - A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality. | 2009-10-08 |
20090251979 | METHOD FOR SUPPRESSING CURRENT LEAKAGE IN MEMORY - A method for suppressing a current leakage of a memory is provided. The memory at least includes a memory cell, an equalizing circuit, a current limiter, a word line and a pair of complementary bit lines. The method includes: having the memory cell entering a pre-charging mode; having the equalizing circuit and the current limiter being normally operated, so as for pre-charging the pair of complementary bit lines; applying a periodic control signal to the current limiter for controlling the current limiter to be either conducting or non-conducting, in which when the current limiter is non-conducting, a standby current leakage of the memory is suppressed, in which the standby current leakage is caused by a short circuit between the word line and the pair of complementary bit lines. | 2009-10-08 |
20090251980 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a discharge circuit that discharges bit lines to a ground potential, a sense amplifier of a single-ended input configuration, and a charging transistor connected between a power supply and an input node of the sense amplifier. The charging transistor charges a bit line from a side of the input node of the sense amplifier via the selected column select transistor which is set to an on state. When a current path to the ground from the bit line to which a selected memory cell is connected is turned off during reading, the input node of the sense amplifier is charged by the charging transistor, and a potential at the input node of the sense amplifier is thereby raised. After the input node of the sense amplifier has been further charged with the one of the column select transistors turned off, the reading operation is performed. | 2009-10-08 |
20090251981 | MEMORY WITH A FAST STABLE SENSING AMPLIFIER - A memory includes a memory cell, a sensing amplifier, four N-type MOS transistors, a reference circuit, and a comparator. The sensing amplifier is used for sensing digital data stored in the memory cell of the memory and generating an output signal corresponding to the digital data when the memory cell is read. The sensing amplifier includes a current source, a voltage generator, an auxiliary transistor, and an operational amplifier. The auxiliary transistor is coupled in parallel to the current source so as to provide an additional current to the sensing amplifier initially. Thus, the sensing amplifier can output a stable signal in a short time so as to improve the performance of the memory. | 2009-10-08 |
20090251982 | Low Energy Memory Component - The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply voltage in replacement of a substantially invariant power supply voltage is used to power a sense amplifier in the DRAM circuit for amplifying a voltage difference between two bit lines coupled to the sense amplifier. As a result, the heat produced by the self-refresh operation is only a fraction of the heat produced by the conventional self-refresh powered by the substantially invariant power supply voltage. | 2009-10-08 |
20090251983 | SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF REDUCING GROUND NOISE - An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level. | 2009-10-08 |
20090251984 | Static memory device and static random access memory device - A static memory device includes a bit cell connected to an internal voltage line, and a power supply control circuit connected between the internal voltage line and a power supply voltage, wherein the power supply control circuit is configured to supply the power supply voltage level to the internal voltage line, and the power supply control circuit is configured to perform a write assist function that includes floating the internal voltage line during a write operation on the bit cell, the internal voltage line being floated in response to a signal of a mode control signal group. | 2009-10-08 |
20090251985 | SEMICONDUCTOR MEMORY APPARATUS - A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals. | 2009-10-08 |
20090251986 | FIFO PEEK ACCESS - Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read enable signal is asserted, the same data block can be accessed again on the next read enable signal. | 2009-10-08 |
20090251987 | Memory Data Transfer - In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals may have second and third frequencies, respectively, that are about equal to the first frequency. The second and third frequencies may be out of phase relative to each other. A controller may output a first data in response to a rising edge of the second clock signal and output a second data in response to another rising edge of the third clock signal. | 2009-10-08 |
20090251988 | SYSTEM AND METHOD FOR PROVIDING A NON-POWER-OF-TWO BURST LENGTH IN A MEMORY SYSTEM - A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices. | 2009-10-08 |
20090251989 | Streamlined flow mixer - A streamlined flow mixer is provided that includes a housing and a plurality of tubes having an upstream end and a downstream end. The tubes are flared at the downstream end. The mixer includes a header plate and the upstream end of each tube passes through the header plate in such as fashion as to be sealed therein. The housing may extend further downstream than the tubes and proved a mixing region. A second header plate may be added to provide for mixing more than two fluids. | 2009-10-08 |
20090251990 | Method for Functionally Testing an Ultrasonic Sensor - A method for functionally testing an ultrasonic sensor on a motor vehicle in which, in a test operating mode, an ultrasonic signal is emitted whose magnitude is large enough that under conventional conditions this ultrasonic signal is reflected by a ground surface in front of the vehicle and is received again. In this way, it can easily be determined that the ultrasonic sensor is functioning properly. | 2009-10-08 |
20090251991 | SYSTEM FOR ACQUIRING SEISMIC DATA IN A MARINE ENVIRONMENT, USING SEISMIC STREAMERS COUPLED TO MEANS FOR DETECTING AND/OR LOCATING MARINE MAMMALS - Discloses herein is a a system of acquiring seismic date in a marine environment, which includes: seismic streamers towed by a vessel; and means for detecting and/or locating marine mammals, characterised in that said marine mammal detection and/or location means are secured to said seismic streamers. | 2009-10-08 |
20090251992 | Method for deghosting marine seismic streamer data with irregular receiver positions - Seismic data are obtained for each seismic source activation in a marine streamer and for each frequency, after being transformed to a spectral domain. An iterative conjugate gradient scheme, using a physically-based preconditioner, is applied to the transformed seismic data, to provide a least squares solution to a normal set of equations for a deghosting system of equations. The solution is inverse-transformed back to a space-time domain to provide deghosted seismic data. | 2009-10-08 |
20090251993 | SHEAR WAVE TRANSDUCER AND METHOD OF USING THE SAME - A wave generating device and method of using the same wherein the device is for producing a shear wave in a ground layer wherein the generated wave emanates from a bore hole in the ground layer and passes through the ground layer toward a receiver spaced from the bore hole. This wave having a given waveform and the bore hole being defined by at least one bore wall that extends from a surface of the ground layer to a bottom extent of the bore hole. The device including a driver having an outer layer extending in a longitudinal direction along a longitudinal axis and having a radially outwardly facing surface generally parallel to the longitudinal axis which is configured to engage an associated bore wall of an associated bore hole. The driver further including a coil assembly fixed relative to the outer layer, an inner assembly configured to move relative to the coil assembly and the inner assembly having at least one magnetic field emitter producing an inner magnetic field and the coil assembly having at least one coil of wire wherein the at least one magnetic field passes through the at least one coil. The device further including an electrical connection between the at least one coil of the driver and an associated power source such that when the associated power source is in an on condition the outer layer vibrates longitudinally relative to the inner assembly thereby producing a wave in an associated ground layer extending outwardly from the device. | 2009-10-08 |
20090251994 | SEISMIC VIBRATOR ARRAY AND METHODS OF OPERATION - An arrangement for conducting a seismic survey and methods for operating a vibrator array in a seismic survey. A signal source coupled to an array of vibrators drives the vibrators with a set of signals to generate seismic signals into a survey area. Each of the signals of the set has an autocorrelation function and a cross correlation function with the other signals of the set that decays faster with time than reflections of the seismic signals from the survey area. One such set of signals includes a linear FM sweep phase-modulated by a maximal-length sequence code shifted a different number of chips for each signal. | 2009-10-08 |
20090251995 | FAST RESIDUAL MIGRATION OF SEISMIC DATA THROUGH PARSIMONIOUS IMAGE DECOMPOSITION - A technique for performing a fast residual migration of seismic data through parsimonious image decomposition is presented. In one aspect, the technique includes a software-implemented method for processing a set of seismic data includes through parsimonious image decomposition. Other aspects of the technique include a program storage medium encoded with instructions that, when executed by a processor, perform such a method or a computing apparatus programmed to perform such a method. | 2009-10-08 |
20090251996 | OBJECT POSITION ESTIMATION - A system for determining the position of an object (8) in a space (10) defined by surfaces (11, 12) comprises at least a first transducer (1), a second transducer (2) and a processing device. The transducers are arranged at a mutual spacing (D). The processing device is arranged for determining the times of arrival of both acoustic signals transmitted between the object and each of the transducers (1, 2) and their reflections. On the basis of the difference in the times of arrival of clusters of acoustic signals and the associated reflections the processing device can determine which surface (11, 12) the indirect acoustic signals were reflected by, thus providing additional position information. | 2009-10-08 |
20090251997 | RADIO WAVE RECEIVING DEVICE WITH MAGNETIC DRIVE UNIT AND ANTENNA STRUCTURE AND ELECTRONIC APPARATUS USING THE RADIO WAVE RECEIVING DEVICE - A radio wave receiving device includes at least one magnetic drive unit and an antenna structure having a narrow core formed of magnetic material and a coil wound around the central part of the core. The device further includes two external magnetic members, each having a connecting part connected magnetically to one end part of the core. One magnetic member has a magnetism collecting part expanded in one side of the antenna structure from the connecting part to exclude the antenna structure, and the other magnetic member has a magnetism collecting part expanded in the other side of the antenna structure from the connecting part to exclude the antenna structure. These external magnetic members cover the drive unit in the both sides and shut off magnetic flux of external magnetic field from the both sides and collect magnetic flux of radio wave on the one end part of the core. | 2009-10-08 |
20090251998 | GONG FOR THE STRIKING WORK OR ALARM OF A WATCH - The gong for the striking work or alarm of a watch is configured to produce a sound within the audible frequency range when it is struck by at least one hammer. This gong is made of a material, wherein the square root of the ratio between the elasticity module of the material divided by the volumic mass of the selected material is less than 3300 m/s, so as to allow the gong to produce a rich sound, comprising a large number of partials, within the audible frequency range. The selected material may be, for example, gold. | 2009-10-08 |
20090251999 | PUSH-BUTTON CONTROL DEVICE FOR A WATCH - The push-button control device for a watch includes a push-button stem ( | 2009-10-08 |
20090252000 | Adaptive High Fidelity Reproduction System - Audio is adaptively associated with speakers, depending on the speaker configuration that is present. Each speaker it receives an audio assignment based on its individual spectral characteristics. As more speakers are added, content is adaptively associated with that you speaker, and taken away from the previous. | 2009-10-08 |
20090252001 | Adaptive High Fidelity Reproduction System - Audio is adaptively associated with speakers, depending on the speaker configuration that is present. Each speaker it receives an audio assignment based on its individual spectral characteristics. As more speakers are added, content is adaptively associated with that you speaker, and taken away from the previous. | 2009-10-08 |
20090252002 | Near-field light-emitting element and optical head - A near-field light-emitting element includes a transparent medium having a plane of incidence into which a laser beam enters, and a light-condensing plane on which the laser beam having entered the plane of incidence is concentrated, and a metal body provided on the light-condensing plane of the transparent medium having a first surface contacting the light-condensing plane, a second surface opposing the first surface, and an aperture which is formed to penetrate through the first and second surfaces at a position where the laser beam is concentrated and which emits a near-field light obtained from the laser beam. The metal body is arranged apart from a center of the aperture by a predetermined distance to connect together the first and second surfaces, and has a plasmon reflection plane that reflects toward the aperture a surface plasmon excited on the first and second surfaces by the laser beam concentrated at the aperture. | 2009-10-08 |
20090252003 | OPTICAL RECORDING/REPRODUCING APPARATUS AND FOCUS SEARCH METHOD - Disclosed is an optical recording/reproducing apparatus capable of performing focus search with high reliability even when a wavefront aberration occurs due to a thickness of a protective layer of an optical disk. The optical recording/reproducing apparatus comprises: an optical system which focuses the beam spot into the recording medium; a spot moving section which moves the beam spot at least in a direction parallel to thickness of the protective layer; a surface detector which detects each of a surface of the protective layer and one or more signal recording surfaces based on a returning light; and a focus controller which starts focusing servo control with respect to the one or more signal recording surfaces when the surface detector detects the surface of the protective layer and thereafter detects the one or more signal recording surfaces. | 2009-10-08 |
20090252004 | LIGHT BEAM OUTPUT CONTROL DEVICE, LIGHT BEAM EMISSION CONTROL PROGRAM, AND RECORDING MEDIUM ON WHICH LIGHT BEAM EMISSION CONTROL PROGRAM IS RECORDED - A light beam output control device is provided, which can adequately perform a negative feedback control for different light beams. | 2009-10-08 |
20090252005 | Test writing method and information recording device - The object of the present invention is to provide a test writing method for seeking the optimum write power correctly and in a short time under a high speed recording condition in a test writing method and an information recording device for recording information by forming different marks from the unrecorded part by injecting energy onto the recording medium. To achieve the above object, even number length marks and odd number length marks are separately test written in the 2T strategy to seek the respective optimum write power. Due to the possibility of enhancing the precision of test writing, a good recording ability can be obtained. | 2009-10-08 |
20090252006 | OPTICAL DISC DEVICE AND CONTROL METHOD - According to one embodiment, an optical disc device includes a semiconductor laser which generates laser light to irradiate an optical disc, and an automatic power control circuit which detects an optical output of the semiconductor laser, sets driving current data equalized to reflect the detection result, and drives the semiconductor laser based on the driving current data. This optical disc device further includes a protection circuit which monitors the driving current data set in the automatic power control circuit to invalidate the driving current data in a case where the abnormality of the driving current data is detected. | 2009-10-08 |
20090252007 | Method and apparatus for recording management information on a recording medium and the recording medium - The write-once recording medium has a data structure for managing temporary defect management areas, TDMAs, of the recording medium, where each TDMA is for at least storing temporary defect management information. In one embodiment, the recording medium includes a TDMA access indicator, TAI, area for selectively storing data indicating which one of the TDMAs is currently in use. | 2009-10-08 |
20090252008 | ANALYSIS OF OPTICAL EFFECTS ON STORAGE MEDIUM - A method of analyzing the quality of optical effects on an optical recording medium as well as applications of the method in connection with optimizing a write strategy and analyzing the write quality for an optical recording medium are disclosed. The method comprising the steps of determining waveforms of a measured and a nominal optical signal, and calculating an amplitude-difference parameter from a difference in the measured and nominal waveforms. A quality measure of the optical effects can thereby be determined from the amplitude-difference parameter. The applications of the method include, but are not limited to: a device for reading optical effects from an optical storage medium with means for determining the an amplitude-difference parameter, an optical recording apparatus with means for adjusting the power level and/or level duration in a write strategy and an IC for controlling an optical storage apparatus. | 2009-10-08 |
20090252009 | POSITIONING CONTROL UNIT AND OPTICAL DISK DRIVE - A position-error-signal calculation circuit ( | 2009-10-08 |
20090252010 | OPTICAL DISK DRIVE WITH DISK TYPE DETERMINATION AND METHOD OF DETERMINING A DISK TYPE OF AN OPTICAL DISK WITH AN OPTICAL DISK DRIVE - An optical disk drive and a method for determining a disk type are described. The optical disk drive may be arranged to receive a radial error signal while an incident beam is focused onto the optical disk and before tracking the track, to analyze the radial error signal for detecting whether a wobble signal is present, indicating whether the track is wobbled, and to derive a disk type from the wobble signal, if present. The optical disk drive may additionally or alternatively be arranged to receive a central aperture signal while the incident beam is focused onto the optical disk and before tracking a track including a sequence of embossed pits, to analyze the signal amplitude of the central aperture signal, and to determine the disk type from at least a first variation of the signal amplitude of the central aperture signal as a function of time. | 2009-10-08 |
20090252011 | OPTICAL INFORMATION RECORDING/ REPRODUCING DEVICE AND OPTICAL INFORMATION RECORDING/ REPRODUCING METHOD - An optical information recording/reproducing device includes a liquid optical element containing a liquid crystal polymer layer in an optical head. A liquid crystal optical element drive unit drives a liquid crystal optical element having a first pattern electrode divided into a plurality of region at one side of the liquid crystal polymer layer in the optical axis direction. The first pattern electrode includes a first region arranged to surround the optical axis and second to ninth regions arranged outside the first regions in such a manner that the circumference is divided eight portions. The liquid crystal optical element drive unit applies a first effective voltage to the first region, a second effective voltage to the second and the sixth region, a third effective voltage to the third and the seventh region, a fourth effective voltage to the fourth and the eighth region, and a fifth effective voltage to the fifth and the ninth region. An average value of the second and the fourth effective voltage and an average value of the third and the fifth effective voltage are identical to the first effective voltage. The voltage applied to the respective regions of the pattern region of the liquid crystal optical element is decided in a short time so as to optimize the quality of the reproduction signal. | 2009-10-08 |
20090252012 | DEFECT INSPECTION METHOD AND DISK DRIVE USING SAME - Provided are a disk defect inspection method and apparatus. The defect inspection method includes; determining an independent recording density value for disk defect detection in relation to disk drive component factors excepting a disk of the disk drive, and performing a disk defect inspection using the independent recording density value for disk defect detection. | 2009-10-08 |
20090252013 | HYDRAZIDE CHELATE COMPLEX COMPOUND, OPTICAL RECORDING MEDIUM USING THE COMPOUND AND RECORDING METHOD THEREOF - Provided are a novel hydrazide chelate complex compound which is excellent in terms of both solubility in a coating solvent and light fastness, which can be used for blue laser recording, and which is useful as a dye for forming a recording layer of an optical recording medium, the hydrazide chelate complex compound being represented by general formula (1) below; and a dye for forming a recording layer of an optical recording medium, the dye containing the compound. | 2009-10-08 |
20090252014 | OPTICAL DRIVE CAPABLE OF REPLAYING OPTICAL CARRIERS WITH HIGH BIREFRINGENCE - The invention relates to an optical drive for reading information from an optical disk ( | 2009-10-08 |
20090252015 | BRUSHLESS MOTOR AND DISK DRIVE APPARATUS PROVIDED WITH THE SAME - A brushless motor includes a substantially flat attachment plate and a circuit board. The attachment plate includes a plurality of motor attachment portions and a base portion arranged to interconnect the motor attachment portions. The circuit board is arranged on an upper surface of the base portion and includes a first area to which electronic parts are attached. The upper surfaces of the motor attachment portions are arranged higher than the upper surface of the base portion. The height of the upper surface of the circuit board in the first area is substantially equal to or greater than the height of the upper surfaces of the motor attachment portions. | 2009-10-08 |
20090252016 | INFORMATION RECORDING APPARATUS AND METHOD, AND COMPUTER PROGRAM - An information recording apparatus forms a record mark corresponding to a recording signal by applying a laser beam to a recording medium, and includes: a light source for emitting the laser beam; a signal generating device for generating a recording pulse signal for driving the light source on the basis of the recording signal; a test-writing device for performing test-writing; and a determining device for determining at least one of a power and a pulse width of the recording pulse signal on the basis of a test-writing result, the test-writing device performs the test-writing by changing the power of the recording pulse signal, the determining device determines the power, by which waveform distortion is greater than or equal to an upper limit or is less than or equal to a lower limit of an amplitude limit value on a limit equalizer in the mark period corresponding to the long mark. | 2009-10-08 |
20090252017 | OPTICAL COMPENSATOR FOR USE IN AN OPTICAL SCANNING DEVICE - An optical compensator for use in an optical scanning device for scanning optical record carriers, there being at least two different information layer depths within two different ones of the carriers, the optical record carriers including a first optical record carrier ( | 2009-10-08 |
20090252018 | HOLOGRAM LENS MANUFACTURING APPARATUS, HOLOGRAM LENS, METHOD OF MANUFACTURING HOLOGRAM LENS, INFORMATION RECORDING APPARATUS, AND INFORMATION REPRODUCING APPARATUS - A hologram lens manufacturing apparatus includes: a separation unit that separates a light beam emitted from a light source into a reference light beam and an irradiation light beam; an irradiation light irradiating unit that collects the irradiation light beam so as to have a focal point at a predetermined focal position, and irradiates a hologram recording element located on the way to the focal point with the irradiation light beam; and a reference light irradiating unit that irradiates the hologram recording element with the reference light beam under a predetermined irradiation condition to record an interference pattern occurring between the irradiation light beam and the reference light beam as a hologram. | 2009-10-08 |
20090252019 | MICRO OPTICAL PICKUP APPARATUS - This invention discloses a micro optical pickup apparatus for providing an incident light to an optical recording medium, receiving a reflected light from the optical recording medium, and thereby accessing data of the optical recording medium. The micro optical pickup apparatus includes a light source generating element for producing the incident light, an axial light splitting element allowing the incident light to pass through and deflecting the reflected light according to polarization directions of the incident and reflected lights, a polarization element disposed between the axial light splitting element and the optical recording medium is capable of changing the polarization directions of the incident light and reflected light of the optical recording medium, an astigmatic mirror for receiving, astigmatism focusing and reflecting the reflected light from the axial light splitting element, and an optical sensing element for receiving the reflected light from the astigmatic mirror and converting the reflected light into a corresponding electric signal. | 2009-10-08 |
20090252020 | OPTICAL PICKUP - An optical pickup according to the present invention includes: an objective lens | 2009-10-08 |
20090252021 | MULTIFOCAL OBJECTIVE LENS AND OPTICAL INFORMATION RECORDING/REPRODUCING DEVICE - There is provided a multifocal objective lens used for two types of optical discs. The protective layer thicknesses of first and second optical discs t | 2009-10-08 |
20090252022 | Method of Manufacturing Synthetic Resin Lens, Method of Manufacturing Reformed Synthetic Resin Material and Optical Pickup Apparatus - A method of manufacturing a synthetic resin lens, comprising: adjusting a degree of change in transmittance of a lens member made of synthetic resin for a blue violet laser beam with accumulated application of the blue violet laser beam, by applying to the lens member an electromagnetic wave shorter in wavelength than the blue violet laser beam. | 2009-10-08 |
20090252023 | INTEGRATED OPTICAL SYSTEM AND METHOD OF MANUFACTURING THE SAME AND INFORMATION RECORDING AND/OR REPRODUCING APPARATUS USING THE INTEGRATED OPTICAL SYSTEM - An optical system and an information apparatus using the optical system are provided. The optical system includes an optical bench on which a light source and a photodetector including a main photodetector receiving the light are mounted. A lens unit is coupled to the optical bench, and an optical path separating member separates an optical path of light emitted from the light source and propagating toward the lens unit and an optical path of light incident from the lens unit. The optical system may include a monitor photodetector and/or an optical path forming unit coupled to the optical bench. The monitor photodetector receives a portion of the light emitted from the light source. The optical path forming unit includes a first mirror reflecting the light emitted from the light source and a second mirror reflecting the light incident from the lens unit and reflected by the first mirror. | 2009-10-08 |
20090252024 | Signal Processing Circuit and Reproducing Apparatus - A signal processing circuit is provided with a signal input layer having a plurality of signal input sections which receive signal input; a plurality of signal processing layers whereupon a plurality of signal processing sections, which are arranged corresponding to each of the signal input sections and processes in parallel signals from the signal input sections, are dispersed; and connecting lines for associating and connecting the signal input sections with the signal processing sections, respectively. The size of a region occupied by each of the signal processing sections on the signal processing layers is larger than the arrangement intervals between the signal input sections on the signal input layers. | 2009-10-08 |
20090252025 | METHOD AND APPARATUS OF OBTAINING DIRECTIVITY - A method of obtaining directivity in an optical waveguide includes the steps of falling incident light on surface of diffuse reflection members arranged at a center portion of the optical waveguide, generating a first table relative to an amount of emitted light that is acquired at a circumference of the optical waveguide by controlling at least one of an image control factor for changing an image of the incident light and a coordinate control factor for changing coordinates of the incident light with them being changed, and generating a second table relative to a pattern of the light which is incident to the diffuse reflection member by seeking for a combination of the image and the coordinates of the light based on the generated first table. | 2009-10-08 |
20090252026 | TIMING AND FREQUENCY ACQUISITION FOR MEDIAFLO SYSTEMS - An apparatus, logic, and method of performing timing and frequency estimation in a MediaFLO™ mobile multimedia multicast system comprising a receiver and a transmitter, wherein the method comprises receiving a wireless data stream comprising a MediaFLO™ mobile multimedia multicast system superframe comprising Orthogonal Frequency Division Multiplexing (OFDM) symbols; estimating a Fast Fourier Transform (FFT) trigger point for each of the received OFDM symbols; estimating a fine carrier frequency offset of each OFDM symbol; determining the start of the MediaFLO™ mobile multimedia multicast system superframe by locating a Time Division Multiplexed (TDM) pilot symbol in the superframe; estimating a coarse carrier frequency offset of each of the received OFDM symbols; and synchronizing the receiver to the start of the MediaFLO™ mobile multimedia multicast system superframe and the transmitted OFDM symbols based on the fine carrier frequency offset, the TDM pilot symbol, and the coarse carrier frequency offset. | 2009-10-08 |
20090252027 | WIC AND LIC ESTIMATION IN MEDIAFLO SYSTEMS - An apparatus and method for WIC/LIC estimation without channel mode construction in a MediaFLO™ system comprising a receiver, a transmitter and transmission channel, wherein the method comprises receiving a signal comprising a MediaFLO™ mobile multimedia multicast system superframe comprising WIC/LIC symbols; setting a first sparseness index value of the digital signal to zero; setting a local copy WIC/LIC number of the digital signal to one; generating a local copy of all possible values of the WIC/LIC symbols corresponding to a WID/LID value from zero to fifteen; dividing the received WIC/LIC symbol values by a local copy WIC/LIC value corresponding to WIC/LIC number one; performing an IFFT of all the possible values of the WIC and LIC symbols; calculating a second sparseness index value of the IFFT of sixteen possible values of the WIC/LIC symbols; and extracting a WIC/LIC symbol from the digital signal corresponding to the second sparseness index. | 2009-10-08 |
20090252028 | APPARATUS AND METHOD FOR CONTROLLING RANGING OF MOBILE TERMINALS IN WIRELESS COMMUNICATION SYSTEM - Disclosed are an apparatus and a method for controlling ranging in a wireless communication system. The apparatus according to the present invention comprises a Radio Frequency (RF) module converting RF band signals received via antenna to low-frequency band signal; a Fast Fourier Transform (FFT) module converting the low-frequency band signal of time-domain to frequency-domain signal; a derandomizer performing derandomizing the frequency-domain signals by using a random sequence being transmitted by the terminals; a depermutation module combining the frequency-domain signals output from the derandomizer by unit of burst and outputting the combined signal; and a ranging controller controlling periodic ranging of the terminal corresponding to the respective bursts by estimating phase change in the frequency-domain signals of burst unit. | 2009-10-08 |
20090252029 | Method, Detection Device and Server Device for Evaluation of an Incoming Communication to a Communication Device - A method, a detection device and a server device for evaluation of a communication arriving via a connecting line at the communication device are provided. Communication information which can be read or determined from the incoming communication is detected by the detection device which is coupled between the connecting line and the communication device, and is associated solely with the communication device. Furthermore, the detection device checks whether the detected communication information matches predeterminable data pattern information, and/or whether a response message to be initiated by the incoming communication from the communication device via the connecting line is absent. If the check result is positive, the detected communication information is stored, and is read out during the course of a central evaluation process carried out by the server device | 2009-10-08 |
20090252030 | REDUCING TRAFFIC LOSS IN AN EAPS SYSTEM - A ring network with an automatic protection switching domain includes a control VLAN and at least one data VLAN. A master node in the ring is connected to at least one transit node. Each node in the ring network is linked to an adjacent node by a primary port or a secondary port. The master node receives notification of a fault via the control VLAN, the fault indicating a failed link between adjacent nodes. In response, the master node unblocks its secondary port to traffic on the data VLAN(s). The forwarding database entries on the master node and on the transit node(s) are flushed. Data traffic is flooded to the ring network until forwarding database entries on the master node and on the transit node(s) have been reestablished. | 2009-10-08 |
20090252031 | METHODS AND APPARATUS FOR PERFORMING PROTOCOL DATA UNIT HEADER RE-SYNCHRONIZATION IN A COMMUNICATION SYSTEM - A method for performing protocol data unit (PDU) header re-synchronization in a communication system includes: when a header check sequence (HCS) fail occurs, detecting whether there exists a valid HCS in a first portion of first data by utilizing at least one detection window, where the first data is derived from an input signal received by the communication system; and when a valid HCS is detected in the first portion of the first data, detecting whether at least a second portion of the first data matches a connection identifier (CID) to determine whether the PDU header re-synchronization is completed. | 2009-10-08 |
20090252032 | Wireless sensor network gateway unit with failed link auto-redirecting capability - A wireless sensor network gateway unit is proposed, which is designed for integration to a wireless sensor network (WSN) for providing a gateway function with a failed link auto-redirecting capability for the wireless sensor network. The proposed WSN gateway unit is characterized by the provision of an failed link auto-redirecting capability, which can respond to the failure of any sensor node in the WSN system by performing a failed link auto-redirecting operation for redirecting the down-linked good sensor nodes for linking to a nearby good sensor node to thereby allow the down-linked good sensor nodes to be nevertheless able to transfer data to the WSN gateway unit of the invention. This feature allows the WSN gateway unit of the invention to maintain good operational reliability for the WSN system. | 2009-10-08 |